Data sheet acquired from Harris Semiconductor SCHS152

CD74HC154, CD74HCT154

High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer

Description

The Harris CD74HC154 and CD74HCT154 are 4-to-16 line decoders/demultiplexers with two enable inputs, E1 and E2. A High on either enable input forces the output into the High state. The demultiplexing function is performed by using the four input lines, A0 to A3, to select the output lines Y0 to Y15, and using one enable as the data input while holding the other enable low.

September 1997

Features
Two Enable Inputs to Facilitate Demultiplexing and Cascading Functions Fanout (Over Temperature Range) - Standard Outputs. 10 LSTTL Loads - Bus Driver Outputs. 15 LSTTL Loads Wide Operating Temperature Range. -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs
[ /Title (CD74 HC154 , CD74 HCT15 4) /Subject (High Speed CMOS Logic 4-to-16 Line Decod er/Dem

Ordering Information

PART NUMBER TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 24 Ld PDIP 24 Ld PDIP 24 Ld PDIP 24 Ld PDIP 24 Ld SOIC 24 Ld SOIC PKG. NO. E24.6 E24.6 E24.3 E24.3 M24.3 M24.3
HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH
CD74HC154E CD74HCT154E CD74HC154EN CD74HC154EN CD74HC154M CD74HCT154M NOTES:
1. When ordering, use the entire part number. Add the sufx 96 to obtain the variant in the tape and reel. 2. Wafer or d ie for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.

Pinout

CD74HC154, CD74HCT154 (PDIP, SOIC) TOP VIEW
YYYYYYYYYYYGND VCC 23 AAAAEEYYYYY11
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

Harris Corporation 1997

File Number

1657.1

CD74HC154, CD74HCT154 Functional Diagram
7 AAA2 AE1 E17 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 GND = 12 VCC = 24
TRUTH TABLE INPUTS E1 L L L L L L L L L L L L L L L L L H H E2 L L L L L L L L L L L L L L L L H L H A3 L L L L L L L L H L H H H H H H X X X A2 L L L L H H H H L H L L H H H H X X X A1 L L H H L L H H L L H H L L H H X X X A0 L H L H L H L H L H L H L H L H X X X Y0 L H H H H H H H H H H H H H H H H H H Y1 H L H H H H H H H H H H H H H H H H H Y2 H H L H H H H H H H H H H H H H H H H Y3 H H H L H H H H H H H H H H H H H H H Y4 H H H H L H H H H H H H H H H H H H H Y5 H H H H H L H H H H H H H H H H H H H Y6 H H H H H H L H H H H H H H H H H H H OUTPUTS Y7 H H H H H H H L H H H H H H H H H H H Y8 H H H H H H H H L H H H H H H H H H H Y9 H H H H H H H H H L H H H H H H H H H Y10 H H H H H H H H H H L H H H H H H H H Y11 H H H H H H H H H H H L H H H H H H H Y12 H H H H H H H H H H H H L H H H H H H Y13 H H H H H H H H H H H H H L H H H H H Y14 H H H H H H H H H H H H H H L H H H H Y15 H H H H H H H H H H H H H H H L H H H

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Dont Care

Absolute Maximum Ratings

DC Supply Voltage, VCC. -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V.20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V.20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V.25mA DC VCC or Ground Current, ICC or IGND.50mA

Thermal Information

Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package (.300). 75 PDIP Package (.600). 60 SOIC Package. 75 Maximum Junction Temperature. 150oC Maximum Storage Temperature Range.-65oC to 150oC Maximum Lead Temperature (Soldering 10s). 300oC (SOIC - Lead Tips Only)

Operating Conditions

Temperature Range (TA). -55oC to 125oC Supply Voltage Range, VCC HC Types.2V to 6V HCT Types.4.5V to 5.5V DC Input or Output Voltage, VI, VO. 0V to VCC Input Rise and Fall Time 2V. 1000ns (Max) 4.5V. 500ns (Max) 6V. 400ns (Max)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.Low Level Input Voltage VIL 2 4.High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.5.2 4.4.2 4.4.1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.160 V V V V V V V V V V V V V V V V V V A A SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
DC Electrical Specications (Continued)
TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II ICC ICC VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.4.4 0.4.4 0.4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS

5.5 5.5 4.5 to 5.5

NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specication is 1.8mA.

HCT Input Loading Table

INPUT A0 - A3 E1, E2 UNIT LOADS 1.4 1.3
NOTE: Unit Load is ICC limit specied in DC Electrical Table, e.g., 360A max at 25oC.
Switching Specications Input tr, tf = 6ns
TEST CONDITIONS 25oC VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
PARAMETER HC TYPES Propagation Delay (Figure 1) Address to Output

SYMBOL

tPLH, tPHL CL = 50pF

ns ns ns ns ns ns ns ns

CL =15pF CL = 50pF E1 to Output tPLH, tPHL CL = 50pF

CL =15pF CL = 50pF

Switching Specications Input tr, tf = 6ns (Continued)
TEST CONDITIONS 25oC VCC (V) 2 4.5 CL =15pF CL = 50pF Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF 2 4.Input Capacitance Power Dissipation Capacitance (Notes 4, 5) HCT TYPES Propagation Delay (Figure 2) Address to Output tPLH, tPHL CL = 50pF CL =15pF E1 to Output tPLH, tPHL CL = 50pF CL =15pF E2 to Output tPLH, tPHL CL = 50pF CL =15pF Output Transition Time Input Capacitance Power Dissipation Capacitance (Notes 4, 5) NOTES: 4. CPD is used to determine the dynamic power consumption, per gate. 5. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. tTLH, tTHL CL = 50pF CIN CPD 4.4.4.4.10 ns ns ns ns ns ns ns pF pF CIN CPD 5 MIN TYP MAX 10 -40oC TO 85oC MIN MAX 10 -55oC TO 125oC MIN MAX 10 UNITS ns ns ns ns ns ns ns pF pF

PARAMETER E2 to Output

Test Circuits and Waveforms
tf = 6ns 2.7V 1.3V 0.3V tTLH 90% INVERTING OUTPUT tPHL tPLH 1.3V 10% 3V
tr = 6ns INPUT 90% 50% 10%

tf = 6ns VCC

tr = 6ns INPUT GND
tTLH 90% 50% 10% tPHL tPLH

INVERTING OUTPUT

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
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