Perform post-simulation analysis of the results This means you can plot additional information
derived from the waveforms. What you can plot depends on the types of analyses you run. Bode plots, phase margin, derivatives for small-signal characteristics, waveform families, and histograms are only a few of the possibilities. You can also plot other waveform characteristics such as rise time versus temperature, or percent overshoot versus component value.
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Using PSpice with other OrCAD programs
Using Capture to prepare for simulation
Capture is a design entry program you need to prepare your circuit for simulation. This means:
placing and connecting part symbols, defining component values and other attributes, defining input waveforms, enabling one or more analyses, and marking the points in the circuit where you want to see results.
Capture is also the control point for running other programs used in the simulation design flow.
What is the Stimulus Editor?
The Stimulus Editor is a graphical input waveform editor that lets you define the shape of time-based signals used to test your circuits response during simulation. Using the Stimulus Editor, you can define:
analog stimuli with sine wave, pulse, piecewise linear, exponential pulse, single-frequency FM shapes
The Stimulus Editor lets you draw analog piecewise linear stimuli by clicking at the points along the timeline that correspond to the input values that you want at transitions.
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What is the Model Editor?
The Model Editor is a model extractor that generates model definitions for PSpice to use during simulation. All the Model Editor needs is information about the device found in standard data sheets. As you enter the data sheet information, the Model Editor displays device characteristic curves so you can verify the model-based behavior of the device. When you are finished, the Model Editor automatically creates a part for the model so you can use the modeled part in your design immediately.

Files needed for simulation
To simulate your design, PSpice needs to know about:
the parts in your circuit and how they are connected, what analyses to run, the simulation models that correspond to the parts in your circuit, and the stimulus definitions to test with.
This information is provided in various data files. Some of these are generated by Capture, others come from libraries (which can also be generated by other programs like the Stimulus Editor and the Model Editor), and still others are user-defined.
Files that Capture generates
When you begin the simulation process, Capture first generates files describing the parts and connections in your circuit. These files are the netlist file and the circuit file that PSpice reads before doing anything else.
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Netlist file

The netlist file contains a list of device names, values, and how they are connected with other devices. The name that Capture generates for this file is DESIGN_NAME.NET. Refer to the online OrCA D PSpice Reference Manual for the syntax of the statements in the netlist file and the circuit file.

Circuit file

The circuit file contains commands describing how to run the simulation. This file also refers to other files that contain netlist, model, stimulus, and any other user-defined information that apply to the simulation. The name that Capture generates for this file is DESIGN_NAME.CIR.
Other files that you can configure for simulation
OrCAD Stimulus Editor global model libraries OrCAD Model Editor

MODEL + BF =

model definitions
input waveforms stimulus file simulation primitives
local model libraries OrCAD PSpice

custom include file

Figure 1 User-configurable data files that PSpice reads Before starting simulation, PSpice needs to read other files that contain simulation information for your circuit. These are model files, and if required, stimulus files and include files. The circuit file (.CIR) that Capture generates contains references to the other user-configurable files that PSpice needs to read. 11
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You can create these files using OrCAD programs like the Stimulus Editor and the Model Editor. These programs automate file generation and provide graphical ways to verify the data. You can also use the Model Text view in the Model Editor (or another text editor like Notepad) to enter the data manually.

Model library

A model library is a file that contains the electrical definition of one or more parts. PSpice uses this information to determine how a part will respond to different electrical inputs. These definitions take the form of either a:
model parameter set, which defines the behavior of a part by fine-tuning the underlying model built into PSpice, or subcircuit netlist, which describes the structure and function of the part by interconnecting other parts and primitives.

To create a new PSpice project
1 From the Windows Start menu, choose the OrCAD Release 9 program folder and then the Capture shortcut to start Capture. In the Project Manager, from the File menu, point to New and choose Project. Select Analog Circuit Wizard. In the Name text box, enter the name of the project (CLIPPER). Click OK, then click Finish. No special libraries need to be configured at this time. A new page will be displayed in Capture and the new project will be configured in the Project Manager.
To place the voltage sources
In Capture, switch to the schematic page editor.
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From the Place menu, choose Part to display the Place Part dialog box. Add the library for the parts you need to place: a b Click the Add Library button. Select SOURCE.OLB (from the PSpice library) and click Open.
In the Part text box, type VDC. Click OK. Move the pointer to the correct position on the schematic page (see Figure 2) and click to place the first part. Move the cursor and click again to place the second part. Right-click and choose End Mode to stop placing parts.
Note There are two sets of library files supplied with Capture and PSpice. The standard schematic part libraries are found in the directory Capture\Library. The part libraries that are designed for simulation with PSpice are found in the sub-directory Capture\Library\PSpice. In order to have access to specific parts, you must first configure the library in Capture using the Add Library function.

To place the diodes

From the Place menu, choose Part to display the Place Part dialog box. Add the library for the parts you need to place: a b 7 Click the Add Library button. Select DIODE.OLB (from the PSpice library) and click Open. or
In the Part text box, type D1N39 to display a list of diodes. Select D1N3940 and click OK. Press r to rotate the diode to the correct orientation. Click to place the first diode (D1), then click to place the second diode (D2). Right-click and choose End Mode to stop placing parts.

When placing parts:

Leave space to connect the parts with

wires.

You will change part names and values
that do not match those shown in Figure 2 later in this section.
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To move the text associated with the diodes (or any other object)
1 Click the text to select it, then drag the text to a new location.

To place the other parts

pre From the Place menu, choose Part to display the Place Part dialog box. Add the library for the parts you need to place: a b 3 Click the Add Library button. Select ANALOG.OLB (from the PSpice library) and click Open.

This operator class. arithmetic

logical*

~ | ^ &

relational*

== != > >= < <=
* Logical and relational operators are used within the IF() function.
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Table 10

Functions in arithmetic expressions

Means this. |x| x1/2 ex

This function. ABS(x) SQRT(x) EXP(x) LOG(x) LOG10(x) PWR(x,y) PWRS(x,y) SIN(x) ASIN(x) SINH(x) COS(x) ACOS(x) COSH(x) TAN(x) ATAN(x) ARCTAN(x) ATAN2(y,x) TANH(x) M(x) P(x) R(x) IMG(x)

ln (x) log (x)

|x|y +|x|y (if x > 0) -|x|y (if x < 0)
which is log base e which is log base 10
sin(x) sin-1 (x) sinh (x) cos (x) cos-1 (x) cosh (x) tan (x) tan-1 (x) tan-1 (y/x) tanh (x)
magnitude of x* phase of x* real part of x* imaginary part of x*
where x is in radians where the result is in radians where x is in radians where x is in radians where the result is in radians where x is in radians where x is in radians where the result is in radians where the result is in radians where x is in radians which is the same as ABS(x) in degrees; returns 0.0 for real numbers
which is applicable to AC analysis only
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Functions in arithmetic expressions (continued)
Means this. time derivative of x which is applicable to transient analysis only

This function.

Note In waveform analysis, this function is D(x). Note In waveform analysis, this function is S(x).

DDT(x)

SDT(x)
time integral of x which is applicable to transient analysis only y value as a function of x where xn,yn point pairs are plotted and connected by straight lines

TABLE(x,x1,y1,.)

MIN(x,y) MAX(x,y)
minimum of x and y maximum of x and y
LIMIT(x,min,max) min if x < min max if x > max else x SGN(x) +1 if x > if x = 0 -1 if x < if x > otherwise which is used to suppress a value until a given amount of time has passed where t is a relational expression using the relational operators shown in Table 9

Running the Model Editor from the schematic page editor

If you want to:

test behavior variations on a part, or refine a model before making it available to all designs,
Once you have started the Model Editor , you can proceed with entering data sheet information and model fitting as described in How to fit models on page 4-97.
then run the Model Editor from the schematic page editor in Capture. This means editing models for part instances on your schematic page. When you select a part instance and edit its model, the schematic page editor automatically creates an instance model that you can then change.
For more information on instance models, see Reusing instance models on page 4-118.
What is an instance model?
An instance model is a copy of the parts original model. The copied model is local to the design. You can customize the instance model without impacting any other design that uses the original part from the library. When the schematic editor creates the copy, it assigns a unique name that is by default: original_model_name-Xn where n is <blank 1 | 2 |. > depending on the number of different instance models derived from the original model for the current design.
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Starting the Model Editor To start editing an instance model
To find out how Capture searches the library, see Changing model library search order on page 4-124. In Capture, select one part on your schematic page. From the Edit menu, choose PSpice Model. The schematic page editor searches the model libraries for the instance model.
If found, the schematic page editor starts the Model Editor, which opens the model library that contains the instance model and loads the instance model. If not found, the schematic page editor assumes that this is a new instance model and does the following: makes a copy of the original model definition, names it original_model_name-Xn, and starts the Model Editor with the new model loaded.

Saving design models

When you save your edits, the Model Editor saves the model definition to DESIGN_NAME.LIB, which is already configured for local use (see What happens if you dont save the instance model on page 4-103).

To save instance models

1 From the File menu, choose Save to update DESIGN_NAME.LIB and save it to disk.
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What happens if you dont save the instance model
Before the schematic page editor starts the Model Editor, it does these things:
Makes a copy of the original model and saves it as an instance model in SCHEMATIC_NAME.LIB. Configures SCHEMATIC_NAME.LIB for design use, if not already done. Attaches the new instance model name to the Implementation property for the selected part instance. quit the Model Editor, or return to Capture to simulate the design

In these cases you must adjust the value of the parts PSPICETEMPLATE property to reflect these changes. To find out how, see Pin callout in subcircuit templates on page 5-144. 136
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Pins must be placed on the grid at integer multiples of the grid spacing. Because the default grid spacing for the Schematic Page Grid is set at 0.10", OrCAD recommends setting pin spacing in the Part and Symbol Grid at 0.10" intervals from the origin of the part and at least 0.10" from any adjacent pins. The part editor considers pins that are not placed at integer multiples of the grid spacing from the origin as off-grid, and a warning appears when you try to save the part. Here are two guidelines:
For more information about grid spacing and pin placement, refer to the OrCA D Capture Users Guide.
Make sure Pointer Snap to Grid is enabled when editing part pins and editing schematic pages so you can easily make connections. Make sure the Part and Symbol Grid spacing matches the Schematic Page Grid spacing.
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Attaching models to parts
If you create parts and want to simulate them, you need to attach model implementations to them. If you created your parts using any of the methods discussed in this chapter, then your part will have a model implementation already attached to it.
The Implementation property defines the name of the model that PSpice must use for simulation. When attaching this implementation, this rule applies:
The Implementation name should match the name of the.MODEL or.SUBCKT definition of the simulation model as it appears in the model library (*.LIB).
Example: If your design includes a 2N2222 bipolar transistor with a.MODEL name of Q2N2222, then the Implementation name for that part should be Q2N2222.
Make sure that the model library containing the definition for the attached model is configured in the list of libraries for your project. See Configuring model libraries on page 4-120 for more information.
For more information on model editing in general, see Chapter 4, Creating and editing models. For specific information on changing model references, see Changing the model reference to an existing model definition on page 4-117. You do not need to enter an Implementation Path because PSpice searches for the model in the list of model libraries you configure for this project.
To attach a model implementation
In the schematic page editor, double-click a part to display the Parts spreadsheet of the Property Editor. From the Implementation list, select PSpice Model. In the Implementation column, type the name of the model to attach to the part. Click Apply to update the design, then close the Parts spreadsheet.
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ELOWPASS CHEBYSHEV {V(10)} = LP 800 1.2K.1dB 50dB

HIPASS

The HIPASS part is characterized by two cutoff frequencies that delineate the boundaries of the filter pass band and stop band. The attenuation values, RIPPLE and STOP, define the maximum allowable attenuation in the pass band, and the minimum required attenuation in the stop band, respectively. The HIPASS part provides one input and one output. Figure 36 shows an example of a HIPASS filter device. This is a high pass filter with the pass band above 1.2 kHz and the stop band below 800 Hz. Again, the pass band ripple is 0.1 dB and the minimum stop band attenuation is 50 dB. This will produce a PSpice netlist declaration like this:
EHIGHPASS CHEBYSHEV {V(10)} = HP 1.2K 800.1dB 50dB
Figure 36 HIPASS filter part example.

BANDPASS

RIPPLE STOP F0, F1, F2, F3 pass band ripple in dB stop band attenuation in dB cutoff frequencies
The BANDPASS part is characterized by four cutoff frequencies. The attenuation values, RIPPLE and STOP, define the maximum allowable attenuation in the pass band, and the minimum required attenuation in the stop
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band, respectively. The BANDPASS part provides one input and one output. Figure 37 shows an example of a BANDPASS filter device. This is a band pass filter with the pass band between 1.2 kHz and 2 kHz, and stop bands below 800 Hz and above 3 kHz. The pass band ripple is 0.1 dB and the minimum stop band attenuation is 50 dB. This will produce a PSpice netlist declaration like this:
EBANDPASS CHEBYSHEV + {V(10)} = BP 800 1.2K 2K 3K.1dB 50dB
Figure 37 BANDPASS filter part example.

BANDREJ

RIPPLE STOP F0, F1, F2, F3 is the pass band ripple in dB is the stop band attenuation in dB are the cutoff frequencies
The BANDREJ part is characterized by four cutoff frequencies. The attenuation values, RIPPLE and STOP, define the maximum allowable attenuation in the pass band, and the minimum required attenuation in the stop band, respectively. The BANDREJ part provides one input and one output. Figure 38 shows an example of a BANDREJ filter device. This is a band reject (or notch) filter with the stop band between 1.2 kHz and 2 kHz, and pass bands below 800 Hz and above 3 kHz. The pass band ripple is 0.1 dB and the minimum stop band attenuation is 50 dB. This will produce a PSpice netlist declaration like this:

Do not set RELTOL to a value above 0.01. This can seriously compromise the accuracy of your simulation.
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Basic controlled sources

As with basic SPICE, PSpice has basic controlled sources derived from the standard SPICE E, F, G, and H devices. Table 1 summarizes the linear controlled source types provided in the standard part library. Table 1 Basic controlled sources in ANALOG.OLB

Part name E F G H

Device type Controlled Voltage Source (PSpice E device) Current-Controlled Current Source (PSpice F device) Controlled Current Source (PSpice G device) Current-Controlled Voltage Source (PSpice H device)
Creating custom ABM parts
Refer to your OrCA D Capture Users Guide for a description of how to create a custom part. Create a custom part when you need a controlled source that is not provided in the special purpose set or that is more elaborate than you can build with the general purpose parts (with multiple controlling inputs, for example). The transfer function can be built into the part two different ways:
directly in the PSPICETEMPLATE definition. by defining the parts EXPR and related properties (if any).
Refer to the online OrCA D PSpice A /D Reference Manual for more information about E and G devices.
The PSpice syntax for declaring E and G devices can help you form a PSPICETEMPLATE definition.
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Part three

Setting Up and Running Analyses
Part Three describes how to set up and run analyses and provides setup information specific to each analysis type.
Chapter 7, Setting up analyses and starting simulation, explains the procedures general to all analysis types to set up and start the simulation. Chapter 8, DC analyses, describes how to set up DC analyses, including DC sweep, bias point detail, smallsignal DC transfer, and DC sensitivity. Chapter 9, AC analyses, describes how to set up AC sweep and noise analyses. Chapter 10, Transient analysis, describes how to set up transient analysis and optionally Fourier components. This chapter also explains how to use the Stimulus Editor to create time-based input. Chapter 11, Parametric and temperature analysis, describes how to set up parametric and temperature analyses, and how to run post-simulation performance analysis in Probe on the results of these analyses.
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Chapter 12, Monte Carlo and sensitivity/worst-case analyses, describes how to set up Monte Carlo and sensitivity/worst-case analyses for statistical interpretation of your circuits behavior.
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Once a trace is removed, it is no longer retrievable. Delete traces with caution.
Manual stimulus configuration
Stimuli can be characterized by manually starting the Stimulus Editor and saving their specifications to a file. These stimulus specifications can then be associated to stimulus instances in your schematic or to stimulus symbols in the symbol library.
To manually configure a stimulus
Start the Stimulus Editor by double-clicking on the Stimulus Editor icon in the OrCAD program group. Open a stimulus file by selecting Open from the File menu. If the file is not found in your current library search path, you are prompted for a new file name. Create one or more stimuli to be used in your schematic. For each stimulus: a Name it whatever you want. This name will be used to associate the stimulus specification to the stimulus instance in your schematic, or to the symbol in the symbol library. Provide the transient specification. From the File menu, choose Save.
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In the schematic page editor, configure the Stimulus Editors output file into your schematic: a a b c From the Pspice menu, choose Edit Simulation Settings. In the Simulation Settings dialog box, select the Include Files tab. Enter the file name specified in step 2. If the stimulus specifications are for local use in the current design, click the Add to design button. For global use by any design, use Add as global instead. Click OK.
Modify either the stimulus instances in the schematic or symbols in the symbol library to reference the new stimulus specification. Associate the transient stimulus specification to a stimulus instance: a b c d e Place a stimulus part in your schematic from the part set: VSTIM, ISTIM, and DIGSTIMn. Click the VSTIM, ISTIM, or DIGSTIMn instance. From the Edit menu, choose Properties. Click the Implementation cell, type in the name of the stimulus, and click Apply. Complete specification of any VSTIM or ISTIM instances by selecting Properties from the Edit menu and editing their DC and AC attributes. Click the DC cell and type its value. Click the AC cell, type its value, and then click Apply. f Close the property editor spreadsheet. Select the part you want to edit. From the Edit menu, choose Part to start the part editor.

Worst-case analysis

This section discusses the analog worst-case analysis feature of PSpice. The information provided in this section explains how to use worst-case analysis properly and with realistic expectations.
Overview of worst-case analysis
Worst-case analysis is used to find the worst probable output of a circuit or system given the restricted variance of its parameters. For instance, if the values of R1, R2, and R3 can vary by +10%, then the worst-case analysis attempts to find the combination of possible resistor values which result in the worst simulated output. As with any other analysis, there are three important parts: inputs, procedure, and outputs.
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Inputs

In addition to the circuit description, you need to provide two pieces of information:
the parameter tolerances a definition of what worst means You can define models for nearly all primitive analog circuit parts, such as resistors, capacitors, inductors, and semiconductor devices. PSpice reads the standard model parameter tolerance syntax specified in the.MODEL statement. For each model parameter, PSpice uses the nominal, minimum, and maximum probable values, and the DEV and/or LOT specifiers; the probability distribution type (such as UNIFORM or GAUSS) is ignored.
You can set tolerances on any number of the parameters that characterize a model. The criterion for determining the worst values for the relevant model parameters is defined in the.WC statement as a function of any standard output variable in a specified range of the sweep. In a given range, reduce the measurement to a single value by one of these five collating functions: MAX MIN YMAX Maximum output variable value Minimum output variable value Output variable value at the point where it differs the most with the nominal run Sweep value where the output variable value crosses above a given threshold value Sweep value where the output variable value crosses below a given threshold value
RISE_EDGE (value) FALL_EDGE (value)
Y ou can define W orst as the highest (HI) or lowest (LO) possible collating function relative to the nominal run.
You can use analog behavioral models to measure waveform characteristics other than those detected by the available collating functions, such as rise time or slope. You can also use analog behavioral models to incorporate several voltages and currents into one output variable to which a collating function may be applied. See Chapter 6, Analog behavioral modeling, for more information. This procedure saves time by performing the minimum number of simulations required to make an educated guess at the parameter values that produce the worst results. It also has some limitations, which are described in the following sections.

To start the simulation

From Captures File menu, point to Open and choose Project. Open the following project in your OrCAD program installation directory:
Note When you run a Fourier analysis using PSpice as specified in this example, PSpice writes the results to the PSpice output file (*.OUT). You can also use Probe windows to display the Fourier transform of any trace expression by using the FFT capability in PSpice. To find out more, refer to PSpice A/D online Help.
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\PSPICE\SAMPLES\ANASIM\EXAMPLE\ EXAMPLE.OPJ If PSpice is set to show traces for all markers on startup, you will see the V(OUT1) and V(OUT2) traces when the Probe window displays. To clear these traces from the plot, from the Trace menu, choose Delete All Traces. 3 From the PSpice menu, choose Run to start the simulation.
PSpice generates a binary waveform data file containing the results of the simulation. A new Probe window appears with the waveform data file EXAMPLE.DAT already loaded (Figure 96).
Figure 96 Waveform display for EXAMPLE.DAT. Because this sample project was set up as a transient analysis type, the data currently loaded are the results of the transient analysis.
In this sample, the voltage markers for OUT1 and OUT2 are already placed in the design. If the markers are not placed prior to simulating, you can display the waveforms later, as explained below in Displaying voltages on nets.
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Displaying voltages on nets
After selected an analysis, voltages on nets and currents into device pins can be displayed in the Probe windows using either schematic markers or output variables (as will be demonstrated in this example).
To display the voltages at the OUT1 and OUT2 nets using output variables
1 From the Trace menu, choose Add Trace to display the Add Traces dialog box. The Simulation Output Variables frame displays a list of valid output variables. 2 Click V(OUT1) and V(OUT2), then click OK. The Probe window should look similar to Figure 96. press UI
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User interface features for waveform analysis
PSpice provides direct manipulation techniques and shortcuts for analyzing waveform data. These techniques are described below.

Shortcut keys

Many of the menu commands in PSpice have equivalent keyboard shortcuts. For instance, after placing a selection rectangle in the analog portion of the plot, you can type C+A instead of choosing Area from the View menu. For a list of shortcut keys, search on Keyboard Shortcuts in PSpice Help. or

Introduction

In order to calculate the bias point, DC sweep and transient analysis for analog devices PSpice must solve a set of nonlinear equations which describe the circuit's behavior. This is accomplished by using an iterative techniquethe Newton-Raphson algorithmwhich starts by having an initial approximation to the solution and iteratively improves it until successive voltages and currents converge to the same result. In a few cases PSpice cannot find a solution to the nonlinear circuit equations. This is generally called a convergence problem because the symptom is that the Newton-Raphson repeating series cannot converge onto a consistent set of voltages and currents. The following discussion gives some background on the algorithms in PSpice and some guidelines for avoiding convergence problems. The AC and noise analyses are linear and do not use an iterative algorithm, so the following discussion does not apply to them. The transient analysis has the additional possibility of being unable to continue because the time step required becomes too small from something in the circuit moving too fast. This is also discussed below.
Newton-Raphson requirements
The Newton-Raphson algorithm is guaranteed to converge to a solution. However, this guarantee has some conditions: The nonlinear equations must have a solution. The equations must be continuous. The algorithm needs the equations' derivatives. The initial approximation must be close enough to the solution.
Each of these can be taken in order. Remember that the PSpice algorithms are used in computer hardware that 380
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has finite precision and finite dynamic range that produce these limits:
Voltages and currents in PSpice are limited to +/-1e10 volts and amps. Derivatives in PSpice are limited to 1e14. The arithmetic used in PSpice is double precision and has 15 digits of accuracy.

Is there a solution?

Yes, for any physically realistic circuit. However, it is not difficult to set up a circuit that has no solution within the limits of PSpice numerics. Consider, for example, a voltage source of one megavolt connected to a resistor of one micro-ohm. This circuit does not have a solution within the dynamic range of currents (+/- 1e10 amps). Here is another example:
V1 1, D1 1,.MODEL 0 5v 0 DMOD DMOD(IS=1e-16)
The problem here is that the diode model has no series resistance. It can be shown that the current through a diode is: I = IS*eV/(N*k*T) N defaults to one and k*T at room temperature is about.025 volts. So, in this example the current through the diode would be: I = 1e-16*e200 = 7.22e70 amps This circuit also does not have a solution within the limits of the dynamic range of PSpice. In general, be careful of components without limits built into them. Extra care is needed when using the expressions for controlled sources (such as for behavioral modeling). It is easy to write expressions with very large values.

Inductors and transformers
While the impedance of capacitors gets lower at high frequencies (and small time steps) the impedance of inductors gets higher.
The inductors in PSpice have an infinite bandwidth.
Real inductors have a finite bandwidth due to eddy current losses and/or skin effect. At high frequencies the effective inductance drops. Another way to say this is that physical inductors have a frequency at which their Q begins to roll off. The inductors in PSpice have no such limit. This can lead to very fast spikes as transistors (and diodes) connected to inductors turn on and off. The fast spikes, in turn, can force PSpice to take unrealistically small time steps.
OrCAD recommends that all inductors have a parallel resistor (series resistance is good for modeling DC effects but does not limit the inductor's bandwidth).
The parallel resistor gives a good model for eddy current loss and limits the bandwidth of the inductor. The size of 391
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resistor should be set to be equal to the inductor's impedance at the frequency at which its Q begins to roll off. Example: A common one millihenry iron core inductor begins to roll off at no less than 100KHz. A good resistor value to use in parallel is then R = 2**100e3*.001 = 628 ohms. Below the roll-off frequency the inductor dominates; above it the resistor does. This keeps the width of spikes from becoming unreasonably narrow.
Bipolar transistors substrate junction
The UC Berkeley SPICE contains an unfortunate convention for the substrate node of bipolar transistors. The collector-substrate p-n junction has no DC component. If the capacitance model parameters are specified (e.g., CJS) then the junction has (voltage-dependent) capacitance but no DC current. This can lead to a sneaky problem: if the junction is inadvertently forward-biased it can create a very large capacitance. The capacitance goes as a power of the junction voltage. Normal junctions cannot sustain much forward voltage because a large current flows. The collector-substrate junction is an exception because it has no DC current. If this happens it usually shows up at the first time step. It can be spotted turning on the detailed operating point information (.TRAN/OP) and looking at the calculated value of CJS for bipolar transistors. The whole problem can be prevented by using the PSpice model parameter ISS. This parameter turns on DC current for the substrate junction.

-c makeplot.cmd -p newamp.prb -cmakeplot.cmd-pnewamp.prb
are equivalent. The order of the options does not matter. The command line options that use <file name> assume default extensions. These command line options can be used without specifying the extension to <file name>. For example:
-c makeplot -p newamp -c makeplot.cmd -p newamp.prb
are equivalent. However, PSpice searches first for the exact <file name> specified for these command line options, and if that <file name> exists, PSpice uses it. If the exact <file name>
does not exist, PSpice adds default extensions to <file name> and searches for those. The following default extensions are used: <file name[.dat]> waveform data file -c<file name[.cmd]> -l<file name[.log]> -p<file name[.prb]> command file log file displays, goal functions, and macros file
You can learn more about PSpice macros by consulting PSpice Help.

xxviii

standard analyses
.AC (AC analysis).DC (DC analysis).FOUR (Fourier analysis).NOISE (noise analysis).OP (bias point).SENS (sensitivity analysis).TF (transfer).TRAN (transient analysis)

output control

.PLOT (plot).PRINT (print).PROBE (Probe).VECTOR (digital output).WATCH (watch analysis results)
simple multi-run analyses
.STEP (parametric analysis).TEMP (temperature)

circuit file processing

.END (end of circuit).FUNC (function).INC (include file).LIB (library file).PARAM (parameter)

statistical analyses

.MC (Monte Carlo analysis).WCASE (sensitivity/ worst-case analysis)

device modeling

.ENDS (end subcircuit).DISTRIBUTION (user-defined distribution).MODEL (model definition).SUBCKT (subcircuit)

initial conditions

.IC (initial bias point condition).LOADBIAS (load bias point file).NODESET (set approximate node voltage for bias point).SAVEBIAS (save bias point to file)

miscellaneous

.ALIASES,.ENDALIASES (aliases and endaliases).EXTERNAL (external port).OPTIONS (analysis options).STIMLIB (stimulus library file).STIMULUS (stimulus).TEXT (text parameter) * (comment) ; (in-line comment) + (line continuation)

Analog devices

Digital devices Device equations
Command reference for PSpice and PSpice A/D
Schematics users enter analysis specifications through the Analysis Setup dialog box (from the Analysis menu, select Setup).

Function

PSpice command
.AC (AC analysis).DC (DC analysis).FOUR (Fourier analysis).NOISE (noise analysis).OP (bias point).SENS (sensitivity analysis).TF (transfer).TRAN (transient analysis).STEP (parametric analysis).TEMP (temperature).MC (Monte Carlo analysis).WCASE (sensitivity/worst-case analysis).IC (initial bias point condition).LOADBIAS (load bias point file).NODESET (set approximate node voltage for bias point).SAVEBIAS (save bias point to file).ENDS (end subcircuit).DISTRIBUTION (user-defined distrib ution).MODEL (model definition).SUBCKT (subcircuit).PLOT (plot).PRINT (print).PROBE (Probe).VECTOR (digital output).WATCH (watch analysis results)

Creating a file of frequently used.FUNC definitions and accessing them using an.INC command near the beginning of the circuit file can be helpful.FUNC commands can also be defined in subcircuits. In those cases they only have local scope.
.IC (initial bias point condition)
The.IC command sets initial conditions for both small-signal and transient bias points. Initial conditions can be given for some or all of the circuits nodes.IC sets the initial conditions for the bias point only. It does not affect a.DC (DC analysis) sweep.
.IC < V(<node> [,<node>])=<value> >*.IC <I(<inductor>)=<value>>*.IC V(2)=3.4 V(102)=0 V(3)=-1V I(L1)=2uAmp.IC V(InPlus,InMinus)=1e-3 V(100,133)=5.0V
<value> A voltage assigned to <node> (or a current assigned to an inductor) for the duration of the bias point calculation.
The voltage between two nodes and the current through an inductor can be specified. During bias calculations, PSpice clamps the voltages to specified values by attaching a voltage source with a 0.0002 ohm series resistor between the specified nodes. After the bias point has been calculated and the transient analysis started, the node is released. If the circuit contains both the.IC command and.NODESET (set approximate node voltage for bias point) command for the same node or inductor, the.NODESET command is ignored (.IC overrides.NODESET). Refer to your PSpice users guide for more information on setting initial conditions.
An.IC command that imposes nonzero voltages on inductors cannot work properly, since inductors are assumed to be short circuits for bias point calculations. However, inductor currents can be initialized.

.INC (include file)

The.INC command inserts the contents of another file.
.INC <file name>.INC "SETUP.CIR".INC "C:\LIB\VCO.CIR"
<file name> Any character string that is a valid file name for your computer system.
Including a file is the same as bringing the files text into the circuit file. Everything in the included file is actually read in. The comments of the included file are then treated just as if they were found in the parent file. Included files can contain any valid PSpice statements, with the following conditions: The included files should not contain title lines unless they are commented. Included files can be nested up to 4 levels.

The equations in this section use the following variables: Vd Vt k q T Tnom
= voltage across the intrinsic diode only = kT/q (thermal voltage) = Boltzmanns constant = electron charge = analysis temperature (K) = nominal temperature (set using TNOM option)
Other variables are listed in Diode model parameters.
Diode equations for DC current
Id = area(Ifwd - Irev) Ifwd = forward current = InrmKinj + IrecKgen Inrm = normal current = IS(eVd/(NVt)-1) if: IKF > 0 1/2 then: Kinj = high-injection factor = (IKF/(IKF+Inrm)) else: Kinj = 1 Irec = recombination current = ISR(eVd/(NRVt)-1) Kgen = generation factor = ((1-Vd/VJ)2+0.005)M/2 Irev = reverse current = Irevhigh + Irevlow Irevhigh = IBVe-(Vd+BV)/(NBVVt) Irevlow = IBVLe-(Vd+BV)/(NBVLVt)
Diode equations for capacitance
Cd = Ct + areaCj Ct = transit time capacitance = TTGd
d ( Inrm Kinj + Irec Kgen ) Gd = DC conductance = area ----------------------------------------------------------------------dVd
Kinj = high-injection factor Cj = CJO(1-Vd/VJ)-M IF: Vd < FCVJ
Cj = CJO(1-FC)-(1+M)(1-FC(1+M)+MVd/VJ) IF: Vd > FCVJ Cj = junction capacitance
Diode equations for temperature effects
= ISe(T/Tnom-1)EG/(NVt)(T/Tnom)XTI/N = ISRe(T/Tnom-1)EG/(NRVt)(T/Tnom)XTI/NR = IKF(1 + TIKF(T-Tnom)) = BV(1 + TBV1(T-Tnom) + TBV2(T-Tnom)2) = RS(1 + TRS1(T-Tnom) + TRS2(T-Tnom)2) = VJT/Tnom - 3Vtln(T/Tnom) - Eg(Tnom)T/Tnom + Eg(T)
ISR(T) IKF(T) BV(T) RS(T) VJ(T)
Eg(T) = silicon bandgap energy = 1.16 -.000702T 2/(T+1108)

CJO(T)

= CJO(1 + M(.0004(T-Tnom)+(1-VJ(T)/VJ)) )
Diode equations for noise

In2 = 4kT/(RS/area)

intrinsic diode shot and flicker noise
In2 = 2qId + KFIdAF/FREQUENCY
For a detailed description of p-n junction physics, refer to: [1] A. S. Grove, Physics and Technology of Semiconductor Devices, John Wiley and Sons, Inc., 1967. Also, for a generally detailed discussion of the U.C. Berkeley SPICE models, including the diode device, refer to: [2] P. Antognetti and G. Massobrio, Semiconductor Device Modeling with SPICE, McGraw-Hill, 1988.
Voltage-controlled voltage source Voltage-controlled current source
E<name> <(+) node> <(-) node> <(+) controlling node> <(-) controlling node> <gain> E<name> <(+) node> <(-) node> POLY(<value>) + < <(+) controlling node> <(-) controlling node> >* + < <polynomial coefficient value> >* E<name> <(+) <node> <(-) node> VALUE = { <expression> } E<name> <(+) <node> <(-) node> TABLE { <expression> } = + < <input value>,<output value> >* E<name> <(+) node> <(-) node> LAPLACE { <expression> } = + { <transform> } E<name> <(+) node> <(-) node> FREQ { <expression> } = [KEYWORD] + < <frequency value>,<magnitude value>,<phase value> >* + [DELAY = <delay value>] E<name> <(+) node> <(-) node> CHEBYSHEV { <expression> } = + <[LP] [HP] [BP] [BR]>,<cutoff frequencies>*,<attenuation>*

Model level 7 (BSIM3 version 3.1)
The BSIM3 version 3.1 model was developed by the University of California, Berkeley, as a deep submicron MOSFET model with the same physical basis as the BSIM3 version 2 model, but with a number of major enhancements, such as a single I-V expression to describe current and output conductance in all regions of device operation, better modeling of narrow width devices, a reformulated capacitance model to improve short and narrow geometry models, a
new relaxation time model to improve transient modeling, and improved model fitting of various W/L ratios using one parameter set. BSIM3 version 3.1 retains the extensive built-in dependencies of dimensional and processing parameters of BSIM3 version 2. For additional, detailed model information, see Reference [8] of References.
Additional notes Note 1 If any of the following BSIM3 version 3.1 model parameters are not explicitly specified, they are calculated using the following equations:
If VTHO is not specified, then:

VTHO = VFB + s K1 s

VFB=-1.0
If VTHO is specified, then:

VFB = VTHO s + K1 s

q NCH XT 2 VBX = s ---------------------------------2
2 ox 7 CF = ---------- ln 1 + ------------------- TOX
where ( 7.4 T 2 ) Eg(T)=the energy bandgap at temperature T= 1.16 ----------------------------------------( T + 1108 )

equations:

If K1 AND K2 are not specified, they are calculated using the following

K1 = GAMMAK2 s VBM

( GAMMA1 GAMMA2 ) ( S VBX s ) K2 = ------------------------------------------------------------------------------------------------------------2 s ( s VBM s ) + VBM
NCH s = 2Vt ln ----------- n

---------Vt = k T q

1.5 T n i = 1.10 --------------- 300.15
Eg ( T ) exp 21.5565981 -------------- 2Vt
If NCH is not given and GAMMA1 is given, then:

2q si

GAMMA( Cox ) 2 NCH = --------------------------------------------------
If neither GAMMA1 nor NCH is given, then NCH has a default value of 1.7e23 1/m3 and GAMMA1 is calculated from NCH:
2q si NCH GAMMA1 = ------------------------------------Cox
If GAMMA2 is not given, then:
2q si NSUB GAMMA2 = ----------------------------------------Cox
If CGSO is not given and DLC>0, then:

CGSO = ( DLC Cox ) CGSL

If the previously calculated CGSO<0, then:

CGSO=0

CGSO=0.6 XJ

2.2 0.0 0.53 -0.032 5.3E6 -0.032 0.0 0.0 0.08 -0.07 1.0E-4 0.0 0.5 see page 182 0.0 see page 182 80.0

DWG ETA0 ETAB

JSW K1

K3B KETA LINT

body effect coefficient of K3 body-bias coefficient of bulk charge effect length offset fitting parameter from I-V without bias subthreshold swing factor poly gate doping concentration lateral non-uniform doping parameter channel length modulation parameter first output resistance DIBL effect correction parameter second output resistance DIBL effect correction parameter body effect coefficient of DIBL correction parameter body effect coefficient of RDSW gate-bias effect coefficient of RDSW first substrate current body effect parameter second substrate current body effect parameter gate dependence of Early voltage parasitic resistance per unit width source-drain sheet resistance mobility at Temp=TNOM NMOS PMOS first-order mobility degradation coefficient second-order mobility degradation coefficient body effect of mobility degradation coefficient
1/V 1/V m none cm-3 m none none none 1/V 1/V1/2 1/V V/m V/m none -mWR /square 670.0 250.0 m/V (m/V)2 m/V2 1/V
0.0 -0.047 0.0 1.0 0.0 1.74E-7 1.3 0.39 0.0086 0.0 0.0 0.0 4.24E8 1.0E-5 0.0 0.0 0.0 cm2/(Vsec) 2.25E-9 5.87E-19 -4.65E-11 when MOBMOD=1 or 2 -0.046 when MOBMOD=3 -3.0 -0.08
NFACTOR NGATE NLX PCLM PDIBLC1

PDIBLC2

PDIBLCB
PRWB PRWG PSCBE1 PSCBE2 PVAG RDSW RSH U0

UA UB UC

maximum applied body-bias in threshold voltage calculation offset voltage in the subthreshold region at large W and L

VSAT VTH0

saturation velocity at Temp=TNOM threshold voltage@Vbs=0 for large L

m/sec V

8.0E 4 0.7 (NMOS) -0.7 (PMOS) see page 181 2.5E-6 0.0 1.0

W0 WINT

narrow-width parameter width-offset fitting parameter from I-V without bias width-offset from Weff for Rds calculation

m m none

Level 7: flicker noise parameters

Bipolar transistor

General form Examples Model form
Q<name> < collector node> <base node> <emitter node> + [substrate node] <model name> [area value] QPNPNOM Q1 NPNSTRONG 1.5 Q7 VC [SUB] LATPNP.MODEL <model name> NPN [model parameters].MODEL <model name> PNP [model parameters].MODEL <model name> LPNP [model parameters]
[substrate node] is optional, and if not specified, the default is the ground. Because the simulator allows alphanumeric names for nodes, and because there is no easy way to distinguish these from the model names, the name (not a number) used for the substrate node needs to be enclosed with square brackets [ ]. Otherwise, nodes would be interpreted as model names. See the third example. [area value] is the relative device area and has a default value of 1.
The bipolar transistor is modeled as an intrinsic transistor using ohmic resistances in series with the collector (RC/area), with the base (value varies with current, see Bipolar transistor equations), and with the emitter (RE/area). Collector
Qw Qo Cjc Base Rb Cje Ibc2 Ibe2 Ibe1/BF Substrate (LPNP only) (Ibe - Ibc1)/Kqb RE Emitter Ibc1/BR Iepi (if RCO > 0) Cjs Substrate (LPNP only)
Positive current is current flowing into a terminal.
For model parameters with alternate names, such as VAF and VA (the alternate name is shown by using parentheses), either name can be used. For model types NPN and PNP, the isolation junction capacitance is connected between the intrinsic-collector and substrate nodes. This is the same as in SPICE2, or SPICE3, and works well for vertical IC transistor structures. For lateral IC transistor structures there is a third model, LPNP, where the isolation junction capacitance is connected between the intrinsic-base and substrate nodes.
The following table lists the set of bipolar transistor breakout parts designed for customizing model parameters for simulation. These are useful for setting up Monte Carlo and worst-case analyses with device and/or lot tolerances specified for individual model parameters.
QBREAKL QBREAKN QBREAKN3 QBREAKN4 QBREAKP QBREAKP3 QBREAKP4

LPNP NPN

AREA MODEL AREA MODEL AREA MODEL

degree coulomb

0.0 0.0 0
RB RBM RC RCO RE TF TR TRB1 TRB2 TRC1 TRC2 TRE1 TRE2 TRM1 TRM2 T_ABS T_MEASURED T_REL_GLOBAL T_REL_LOCAL VAF (VA) VAR (VB) VG VJC (PC) VJE (PE)
ohm ohm ohm ohm ohm sec sec C-1 C-2 C-1 C-2 C-1 C-2 C-1 C-2 C C C C volt volt V volt volt
0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
infinite infinite 1.206 0.75 0.75
VJS (PS) VO VTF XCJC XCJC2 XCJS XTB XTF XTI (PT)
substrate p-n built-in potential carrier mobility knee voltage transit time dependency on Vbc fraction of CJC connected internally to Rb fraction of CJC connected internally to Rb fraction of CJS connected internally to Rc forward and reverse beta temperature coefficient transit time bias dependence coefficient IS temperature effect exponent

volt volt volt

0.75 10.0 infinite 1.0 1.0
0.0 0.0 3.0 (model definition).
The parameters ISE (C2) and ISC (C4) can be set to be greater than one. In this case, they are interpreted as multipliers of IS instead of absolute currents: that is, if ISE is greater than one, then it is replaced by ISEIS. Likewise for ISC. If the model parameter RCO is specified, then quasi-saturation effects are included.
Distribution of the CJC capacitance
The distribution of the CJC capacitance is specified by XCJC and XCJC2. The model parameter XCJC2 is used like XCJC. The differences between the two parameters are as follows.

Branch

intrinsic base to intrinsic collector extrinsic base to intrinsic collector extrinsic base to extrinsic collector

XCJC*CJC (1.0 XCJC)*CJC

XCJC2*CJC

not applicable

(1.0 XCJC2)*CJC
When XCJC2 is specified in the range 0 < XCJC2 < 1.0, XCJC is ignored. Also, the extrinsic base to extrinsic collector capacitance (Cbx2) and the gain-bandwidth product (Ft2) are included in the operating point information (in the output listing generated during a Bias Point Detail analysis,.OP (bias point)). For backward compatibility, the parameter XCJC and the associated calculation of Cbx and Ft remain unchanged. Cbx and Ft appears in the output listing only when XCJC is specified. The use of XCJC2 produces more accurate results because Cbx2 (the fraction of CJC associated with the intrinsic collector node) now equals the ratio of the devices emitter area-to-base area. This results in a better correlation between the measured data and the gain bandwidth product (Ft2) calculated by PSpice. which is valid in the range 0 XCJS 1.0, specifies a portion of the CJS capacitance to be between the external substrate and external collector nodes instead of between the external substrate and internal collector nodes. When XJCS is 1, CJS is applied totally between the external substrate and internal collector nodes. When XCJS is 0, CJS is applied totally between the external substrate and external collector codes.

subckt 74393 A CLR QA QB QC QD + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UINV inv DPWR DGND + CLR CLRBAR + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + $D_HI CLRBAR A $D_HI $D_HI QA_BUF $D_NC + D_393_1 IO_STD MNTYMXDLY={MNTYMXDLY}= + IO_LEVEL={IO_LEVEL} U2 jkff(1) DPWR DGND + $D_HI CLRBAR QA_BUF $D_HI $D_HI QB_BUF $D_NC + D_393_2 IO_STD MNTYMXDLY={MNTYMXDLY} U3 jkff(1) DPWR DGND + $D_HI CLRBAR QB_BUF $D_HI $D_HI QC_BUF $D_NC + D_393_2 IO_STD MNTYMXDLY={MNTYMXDLY} U4 jkff(1) DPWR DGND + $D_HI CLRBAR QC_BUF $D_HI $D_HI QD_BUF $D_NC + D_393_3 IO_STD MNTYMXDLY={MNTYMXDLY} UBUFF bufa(4) DPWR DGND + QA_BUF QB_BUF QC_BUF QD_BUF QA QB QC QD + D_393_4 IO_STD MNTYMXDLY={MNTYMXDLY}IO_LEVEL={IO_LEVEL}.ends
When adding digital parts to a part library, you can create corresponding digital device models by connecting U devices in a subcircuit definition similar to the one shown above. OrCAD recommends that these be saved in a custom model file. The model files can then be configured into the model library or specified for use in a given design.
General digital primitive format
The format of digital primitives is similar to that of analog devices. One difference is that most digital primitives use two models instead of one. One of the models is the timing model, which specifies propagation delays and timing constraints, such as setup and hold times. The other model is the I/O model, which specifies information specific to the devices input/output characteristics. The reason for having two models is that, while timing information is specific to a device, the input/output characteristics apply to a whole device family. Thus, many devices in the same family reference the same I/O model, but each device has its own timing model. If wanted, the timing models can be selected among primitives of the same class. The general digital primitive format is shown below. Each statement can span one or more lines by using the + (line continuation) character in the first column position. Comments can be added to each line by using the ; (in-line comment). For specific information on each primitive type, see the sections that follow.
U<name> <primitive type> [(<parameter value>*)] + <digital power node> <digital ground node> + <node>* + <timing model name> <I/O model name> + [MNTYMXDLY=<delay select value>] + [IO_LEVEL=<interface subckt select value>].MODEL <model name> UIO ( <model parameters>* )
See Input/output model parameters for a list of the UIO model parameters.

Timing model format

.MODEL <model name> <model type> ( <model parameters>* )
U1 NAND(2) $G_DPWR $G_DGND 10 D0_GATE IO_DFT U2 JKFF(1) $G_DPWR $G_DGND 2 D_293ASTD IO_STD U3 INV $G_DPWR $G_DGND IN OUT D_INV IO_INV MNTYMXDLY=3 IO_LEVEL=2
<primitive type> [(<parameter value>*)] The type of digital device, such as NAND, JKFF, or INV. It is followed by zero or more parameters specific to the primitive type, such as number of inputs. The number and meaning of the parameters depends on the primitive type. See the sections that follow for a complete description of each primitive type and its parameters. <digital power node> <digital ground node> These nodes are used by the interface subcircuits which connect analog nodes to digital nodes or vice versa. Refer to your PSpice users guide for more information. <node>* One or more input and output nodes. The number of nodes depends on the primitive type and its parameters. Analog devices, digital devices, or both can be connected to a node. If a node has both analog and digital connections, then the simulator automatically inserts an interface subcircuit to translate between logic levels and voltages. Refer to your PSpice users guide for more information.

X1 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 + IN13 IN14 + OUT1 OUT2 OUT3 OUT4 + PAL14H4 + TEXT: JEDEC_FILE = "myprog.jed"
This example creates a 14H4 PAL which is programmed by the JEDEC file myprog.jed.
U<name> <pld type> (<no. of inputs>, <no. of outputs>) + <digital power node> <digital ground node> + <input_node>* <output_node>* + <timing model name> <I/O model name> + [FILE=<(file name) text value>] + [DATA=<radix flag>$<program data>$] + [MNTYMXDLY=<delay select value>] + [IO_LEVEL=<interface subckt select value>]
.MODEL <timing model name> UPLD [model parameters]
UDECODE PLANDC(3, 8) ; 3 inputs, 8 outputs + $G_DPWR $G_DGND ; digital power supply and ground + IN1 IN2 IN3 ; the inputs + OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 ; the outputs + PLD_MDL ; the timing model name + IO_STD ; the I/O model name + DATA=B$ ; the programming data * IN1 IN2 IN3 * TF TF TF + 01 ; OUT0 + 10 ; OUT1 + 01 ; OUT2 + 10 ; OUT3 + 01 ; OUT4 + 10 ; OUT5 + 01 ; OUT6 + 10 $ ; OUT7.MODEL PLD_MDL UPLD(.) ; PLD timing model definition
<pld type> One of the following:

PLD type

PLAND PLANDC PLNAND PLNANDC PLNOR PLNORC PLNXOR PLNXORC PLOR PLORC PLXOR PLXORC
AND array AND array using true and complement columns for each input NAND array NAND array using true and complement columns for each input NOR array NOR array using true and complement columns for each input Exclusive NOR array Exclusive NOR array using true and complement columns for each input OR array OR array using true and complement columns for each input Exclusive OR array Exclusive OR array using true and complement columns for each input
<file name text value> The name of a JEDEC format file which specifies the programming data for the array. The file name can be specified as a text constant (enclosed in double quotes ), or as a text expression (enclosed in vertical bars |). If a FILE is specified, any programming data specified by a DATA section is ignored. The mapping of addresses in the JEDEC file to locations in the array is controlled by model parameters specified in the timing model. <radix flag> One of the following: B O X binary data follows octal data follows (most significant bit has the lowest address) hexadecimal data follows (most significant bit has lowest address)
<program data> A string of data values used to program the logic array. The values start at address zero, which programs the array for the connection of the first input pin to the gate which drives the first output. A 0 (zero) specifies that the input is not connected to the gate, and a 1 specifies that the input is connected to the gate. (Initially, all inputs are not connected to any gates.) The next value programs the array for the connection of the complement of the first input to the gate which drives the first output (if this is a programmable gate having true and complement inputs) or, the second input connection to the gate which drives the first output. Each additional 1 or 0 programs the connection of the next input or its complement to the gate which drives the first output, until the connection of all inputs (and their complements) to that gate have been programmed. Data values after that, program the connection of inputs to the gate driving the second output, and so on. The data values must be enclosed in dollar signs ($), but can be separated by spaces or continuation lines.

.MODEL <timing model name> UADC [model parameters]
U5 ADC(4) $G_DPWR $G_DGND ; 4-bit ADC + Sig Ref 0 Conv Stat OvrRng Out3 Out2 Out1 Out0 + ADCModel IO_STD.MODEL ADCModel UADC(.) ; Timing Model
Multi-bit A/D converter timing model parameters

TPCSMN

propagation delay: rising edge of convert to rising edge of status, min propagation delay: rising edge of convert to rising edge of status, typ propagation delay: rising edge of convert to rising edge of status, max

TPCSTY

TPCSMX

TPDSMN

propagation delay: data valid to falling edge of status, sec min propagation delay: data valid to falling edge of status, sec typ propagation delay: data valid to falling edge of status, sec max propagation delay: rising edge of status to data valid, sec min propagation delay: rising edge of status to data valid, sec typ propagation delay: rising edge of status to data valid, sec max (model definition).

TPDSTY

TPDSMX

TPSDMN

TPSDTY

TPSDMX

ADC primitive device timing

Convert Status

Old Valid

Unknown

New Valid
DATA refers to both the data and over-range signals. The Convert pulse can be any width, including zero. If the propagation delay between the rising edge of the Convert signal and the Status signal (tpsd) is zero, the data and over-range do not go to unknown but directly to the new value. There is a resistive load from <ref node> to <gnd node>, and from <in node> to <gnd node>, of 1/GMIN. The voltage at <in node> and <ref node> with respect to <gnd node> is sampled starting at the rising edge of the Convert signal, and ending when the Status signal becomes high. This gives a sample aperture time of tpcs plus any rising time for Convert. If, during the sample aperture, the output calculated having the minimum <ref node> voltage and maximum <in node> voltage is different from the output calculated having the maximum <ref node> voltage and minimum <in node> voltage, the appropriate output bits are set to the unknown state and a warning message is printed in the output file. The output is the binary value of the nearest integer to
V ( in, gnd ) ---------------------------- 2 nbits V ( ref, gnd )
If this value is greater than 2nbits-1, then all data bits are 1, and over-range is 1. If this value is less than zero, then all data bits are zero, and over-range is 1.

<time>

Each value corresponds to a single binary signal (the default) or the entire group of signals inside the OCT or HEX radix functions. The number of values listed must equal the total number of binary signals and radix functions which are specified in the header. Valid <values> are:
Binary Logic/Numeric Unknown Hi-impedance Rising Falling

0,1 X Z R F

0-7 X Z R F

0-F X Z

When the <value> in a HEX or OCT column is a number, the simulator converts the number to binary and assigns the appropriate logic value of each bit (either zero or one) to the signals inside the radix function. The bits are assigned msb to lsb. When the <value> is X, Z, R, or F, all signals in the radix function take on that value. Note that there can be no falling value in a HEX column because F is used as a numeric value. The following example shows the use of TIMESCALE and relative <time> values.
TIMESCALE=10ns ; must appear on separate line Clock, Reset, In1, In2 HEX(Addr7 Addr6 Addr5 Addr4) HEX(Addr3 Addr2 Addr1 Addr0) ReadWrite 2 + 0 110R 4E 4E 1111 4E 1 011F C11X0 C; transition occurs at 10ns ; transition occurs at 50ns ; transition occurs at 70ns

File stimulus device

The file stimulus device, FSTIM, is used to access one or more signals inside a stimulus file. More than one FSTIM device can access the same file. An FSTIM device can even refer to the same signal as another FSTIM device. Any number of stimulus files can be used during a simulation.
U<name> FSTIM(<# outputs>) + <digital power node> <digital ground node> + <node>* + <I/O model name> + FILE=<stimulus file name> + [IO_LEVEL=<interface subckt select value>] + [SIGNAMES=<stimulus file signal name>*] U1 FSTIM(1) $G_DPWR $G_DGND + IN1 IO_STM FILE=DIG1.STM U2 FSTIM(4) $G_DPWR $G_DGND + ADDR3 ADDR2 ADDR1 ADDR0 + IO_STM + FILE = DIG_2.STM + SIGNAMES = AD3 AD2 AD1 AD0 U3 FSTIM(4) $G_DPWR $G_DGND + CLK PRE J K + IO_STM + FILE = FLIPFLOP.STM + SIGNAMES = CLOCK PRESET
<# outputs>Specifies the number of nodes driven by this device.
<digital power node> <digital ground node> These nodes are used by the interface devices which connect analog nodes to digital nodes or vice versa. Refer to your PSpice users guide for more information. <node>* One or more node names which are output by the file stimulus. The number of nodes specified must be the same as <# outputs>. <I/O model name> The name of an I/O model, which describes the driving characteristics of the stimulus device. I/O models also contain the names of up to four DtoA interface subcircuits, which are automatically called by the simulator to handle interface nodes. In most cases, the I/O model named IO_STM can be used from the library dig_io.lib. Refer to your PSpice users guide for a more detailed description of I/O models. FILE The name of the stimulus file to be accessed by this device. The <stimulus file name> can be specified as a quoted string or as a text expression; see.TEXT (text parameter). Note that the FILE device parameter is not optional. IO_LEVEL An optional device parameter which selects one of the four AtoD or DtoA interface subcircuits from the devices I/O model. The simulator calls the selected subcircuit automatically in the event a node connecting to the primitive also connects to an analog device. If not specified, IO_LEVEL defaults to 0. Valid values are: 0 = the current value of.OPTIONS DIGIOLVL (default=1) 1 = AtoD1/DtoA= AtoD2/DtoA= AtoD3/DtoA= AtoD4/DtoA4 Refer to your PSpice users guide for more information. SIGNAMES Used to specify the names of the signals inside the stimulus file which are to be referenced by the FSTIM device. The signal names correspond, in order, to the <nodes> connected to the device. If any or all SIGNAMES are unspecified, The simulator looks in the stimulus file for the names of the <nodes> given. Because the number of signal names can vary, the SIGNAMES parameter must be specified last. SIGNAMES can be a list of names or text expressions (see.TEXT), or a mixture of the two.

This consists of locating and binding the device instance and its model, initializing any local variables, and obtaining appropriate values for the device branch voltages. The branch voltages (e.g., vds, vgs) are set differently depending upon whether there are user-specified initial conditions (using IC= or.IC), and on whether the present Newton Raphson cycle has finished or not. This is needed to monitor progress towards a Newton Raphson solution.
Computing new nonlinear branch voltage:
Test if the solution has If there is not significant change bypass the rest of the computation. Otherwise, continue. changed: Limit any nonlinear branch voltages: Compute currents and conductances: Charge calculations: Check convergence: This code uses the macro PNJLIM() to insure that the branch voltages are in the appropriate operating region. This is the meat of the Device Equations code, and involves obtaining all the branch currents (e.g., ibs, ibd) as well as all the derivatives to be used in the conductance matrix. Internal charges are calculated and updated. Check to see if the nonlinear device branches now have values that are within a small tolerance range of those obtained in the last repeat cycle, and set a return flag to signal whether the device converged.
Load the current vector The macro Y_MATRIX () is used to obtain handles to the proper and conductance matrix elements, and the elements are assigned their values based matrix: on the present evaluation of the device equations and derivatives. SPICE2G is written in FORTRAN, whereas PSpice is in C. For the device subroutines, as much correspondence as possible has been maintained between the two. Because of FORTRAN, SPICE kept integer and real numbers in different tables: NODPLC (indexed by LOC) and VALUE (indexed by LOCV or LOCM). In PSpice, these have been combined into one structure (e.g., struct m_). The state vector information is constructed somewhat differently, though the overall pattern is similar. In SPICE the state vector information is kept in a set of vectors in VALUE. There is one vector for each time point remembered (from 4 to 7, depending on the order of the integration method). Each devices LOC table contains an offset, LX, to its portion of the information in each state vector. In PSpice the number of state vectors is fixed, and each devices state information is kept in its own device structure (e.g., struct m_). For example, for MOSFETs the state vectors are an array, struct msv_def m_sv[MSTVCT] in struct m_. MSTVCT is the number of state vectors and is defined in TRAN.H to be equal to 4. The definition of msv_def (also in M.H) lists the various currents, conductances, charges, and capacitances that are in the state vector. Finally, M.H contains a set of #defines, which allows accessing of the entries to the state vectors by name. It is these (uppercase) names

object operator OUTPUT ALL

package page

parameter part part definition part instance pin

pin current POLY port

run SCBE schematic

setpoint

Glossary SIMLIBPATH simulation skipbp statement
A variable that defines the environment that the simulator is working in (path to the directory that the library is in). The use of a mathematical model to represent a physical device or process. (skip bias point) The smallest executable entity within a programming language. In general, each line of a program is an individual statement and is considered an individual instruction. (Examples: command statements, option statements, control statements, assignment statements, comment statements.) A GaAsFET model A small collection of components working together to perform a task. A symbol consists of the graphical representation of a logical or physical electronic part on the schematic page, and its definition. Symbols can be created either for a specific schematic or extracted from a library file, and may contain schematic pages nested within them. The grammar of a particular computer language, with rules that govern the structure and content of the statement. A function which returns a text string which is the integer value closest to the value of the <value or expression>; (<value or expression> is a floating-point value) The number generated from a regular recurring signal emitted by a clocking circuit, or from the interrupt generated by this signal. a GaAsFET device The default option is VARY BOTH. When VARY BOTH is used, sensitivity to parameters using both DEV and LOT specifications is checked only with respect to LOT variations. The parameter is then maximized or minimized using both DEV and LOT tolerances for the worst-case. All devices referencing the model have the same parameter values for the worst-case simulation. See VARY BOTH See VARY BOTH The temperature of the JFET or MOSFET device when there is zero-bias threshold (pinchoff) voltage. An area on the screen in a graphical computer interface that contains instructional documentation or a message.
Statz model subcircuit symbol

syntax TEXTINT

tick number TOM model VARY BOTH
VARY DEV VARY LOT VTO temperature window
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z * (comment), 99 ; (in-line comment), 100 resistors, 216 semiconductor parts, 132, 177 analog-to-digital converter, 51 analyses AC, 32 bias point, 58 DC, 34 Fourier, 41 Monte Carlo, 47 noise, 56 parametric, 79 sensitivity, 78 sensitivity/worst-case, 95 temperature, 87 transient, 90 analysis options flag options, 59 AND, 256 AND3, 259 anhysteric, 165 annotation defined, 347 annotation symbol defined, 347 AO, 256 arc tangent (ATAN and ARCTAN), xix arccosine function, xix ARCOS(x), xix arcsine, xix arctangent, xix argument, 85, 86, 236, 347 arithmetic expressions, xx ASIN(x), xix ATAN2, xix attributes definition, 53, 60, 347