2004 Allied Telesyn, Inc.

Central Office Practices

5/10/04 - Rev. A
In the design of a production video over ADSL delivery network, each piece of the end to end system must be considered in order to maximize bandwidth, minimize error rates, and enhance robustness. This white paper describes a set of proven Central Office practices field tested by Allied Telesyn and proven to increase subscriber coverage, service consistency, and ultimately ADSL success. ---------------------------------------------------------------------------------------------------------------------
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Technology Brief

Optimized ADSL performance enhances service provider revenue by increasing the number of eligible subscribers and maintaining the highest possible service quality and reliability. This is especially true for those deploying video services over ADSL. Current video delivery technologies, i.e., MPEG2, demand high ADSL data rates and error-free performance. ADSL technology is pushed to its limits to deliver the bandwidth needed to support multiple set top boxes per subscriber. Careful engineering of the end to end system maximizes the number of subscribers that can be reached, thus increases service provider revenue. Optimized ADSL performance also implies constant bandwidth and error performance that is consistent over time. Customer satisfaction is easily lost over the slightest degradations in video quality. Worse yet is the case where a customer is initially offered a specific service class and over a period of time is forced to downgrade or even lose their entire service because of performance degradation. Performance is influenced by all components of the ADSL delivery system; DSLAM, splitters, wiring, loop plant, and customer premise conditions. Simply following existing ANSI or ITU-T standards for ADSL equipment does not guarantee
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optimized performance. The weakest link in this chain controls the performance of the entire system.
Before reviewing the system components that affect ADSL performance, it is useful to have a basic understanding of ADSL technology. ADSL operates in the frequency spectrum that is above the POTS frequency band of 0 to 4KHz. The ADSL spectrum is shown in Figure 1, below.

power spectrum

upstream

downstream

1.1 MHz

2.2MHz.

frequency
Figure 1 Above the POTS frequencies, the ADSL spectrum is divided into two major bands- the upstream band and the downstream band. Upstream frequencies are used to carry data from the ADSL modem at the customer premise to the DSLAM. Downstream bands carry data from the DSLAM to the ADSL modem. The downstream spectrum is much wider than the upstream, giving more capacity downstream compared to upstream- thus the Asymmetric in Asymmetric Digital Subscriber Line. Figure 1 shows both the 1.1MHz spectrum used for 10Mbps ADSL, and the 2.2MHz spectrum used for 24Mbps ADSL2+. Also notice that the downstream
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band is shown to overlap into the upstream band. This overlap reflects the optional echo cancellation feature that boosts downstream user rates to 12Mbps for ADSL and 26Mbps for ADSL2+. ADSL subdivides its spectrum into frequency sub-channels called bins. Each orthogonal sub-channel is spaced at 4.3125KHz. The bins are numbered starting at 1 which is the frequency range reserved for POTS. Bins 2 through 5 are a guard band that separates POTS and ADSL. Bins 6 through 32 are used for upstream transmission. For ADSL, downstream data uses bins 33 through 255, while for ADSL2+ the downstream spectrum extends to bin 512.
DOWNSTREAM (ADSL2+) UPSTREAM DOWNSTREAM (ADSL)

Energy / tone

255 256

511 512

Figure 2: ADSL Bins
Each of these bins can be thought of as separate and independent communication channels. In other words, one can view an ADSL downstream link as 223 (255-32) individual modems. User data is transmitted by modulating each of the bin frequencies with a technique known as quadrature amplitude modulation (QAM). The process is referred to as bin loading reflecting the fact that each of bins is carrying a certain number of payload data bits. In theory, each bin is capable of carrying up to 15 bits of information.

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Since each bin operates independently from all other bins, the number of bits that are loaded in each bin can vary. ADSL link data rates are computed by aggregating the capacity in each bin over the frame rate of the ADSL link. Assuming a uniform bin loading of 15 bits per bin, and 223 available bins (ADSL with no echo cancellation), the corresponding aggregate link data rate would be 4000*15*223 = 13.4Mbps. The amount of that 13.4Mbps bandwidth available for user data is somewhat smaller due to the ADSL framing overhead, ADSL OAM overhead, error correction overhead, and ATM layer overhead that is used to map user data into an ADSL frame. At any given moment, the number of bits that can be carried in a given bin is limited by amount of noise present relative to the signal strength of that bin, typically referred to as the signal to noise ratio (SNR). ADSL requires approximately 15dB of SNR for the first bit to be loaded in a bin and an additional 3dB for every additional bit. Therefore, 15 bits per bin requires 57dB of SNR. SNR degradation is directly proportional to loss in the ADSL data rate. The loss of a single bit per bin results in a loss of (1bit * 223bins * 4000Hz) 892Kbps in ADSL link data rate. Obviously, control and reduction of noise is important for maximum ADSL performance. Noise that impacts ADSL performance can be divided into three groups; 1. Internally Generated, examples of which include: a. Quantization & thermal noise representative of the discrete nature of sampled signals and physical background levels respectively. b. Clocking noise components induced by phase noise and digital PLL operations result in some induced scatter in recovered bin constellations. Particularly at high bin loadings like 14 or 15 bits this can be a major noise source since the spacing between the OAM constellation points is so small.
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c. Algorithm residue caused by design, precision, and performance limits. Examples include phase effects in shaping filters, limits of dispersion correction in TEQ, limits of frequency equalization in FEQ, and accuracy of noise level estimation in finite time periods. d. Power supply noise in the ADSL spectrum or alias region, thermal time constants between high power dissipation components and low noise receiver components, self echo of transmitted signal into the receiver or trans-hybrid loss, Internal noise limits must be controlled at the physical chip, system on chip, and integrated modem design or build levels. These noise sources are influenced by the design of the DSLAM and cannot be mitigated with central office deployment practices. 2. External Stationary a. Interference from other services and that are carried in the office such as T1, HDSL, and other types of DSL, and electromagnetic interference (AM radio stations) b. Interference generated by adjacent ADSL circuits. This is commonly referred to as self crosstalk. External stationary noise limits must be accounted for in network design. The network design must include CO, outdoor loop plant, and CPE criteria. 3. External Non-Stationary a. Impulse noise and electromagnetic interference (HAM radio) b. POTS signaling (on / off hook transitions, dial pulse, ringing, ring trip) c. xDSL or other services moving in and out of operation External non-stationary noise limits must be accounted for in network design. The network design must include CO, outdoor loop plant, and CPE criteria.

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ADSL standards define a range of downstream bin transmit levels from -52dBm/Hz to -40dBm/Hz. This range is needed to limit transceiver dynamic range and must accommodate both short and long subscriber loops. At the shortest loop lengths, the downstream ADSL transmit power is cut-back by 12dB so that the subscribers modem is not over-driven. Transmit power increases with loop length. This variation in transmit power affects the allowable noise floor of the system required to support a given bin loading. 14bits per bin is a practical bin loading objective that can deliver 10Mbps and still leave headroom for noise. The self crosstalk noise analysis is shown in Figure 3. 14bits per bin requires an SNR of 54dB. From the figure it can be seen that for a long loop (transmit level = -40dBm per Hz), noise levels must be kept below -94dBm per Hz. Additionally, for a short loop (transmit level = -52dBm per Hz), noise levels must be kept below -106dBm per Hz.

pow er s p e c tru m

Range of ADSL transmit power

MAX MIN

-40 dBm/Hz -52 dBm/Hz

d o w n s tre a m

SNR required for 14 bits/bin = 54dB

-94 dBm/Hz -106 dBm/Hz

4 kHz 1.1 MHz 2.2 M H z.

fre q u e ncy

Figure 3: Noise Levels required for 14bits/bin
Now that the basics of ADSL transmission have been covered, we will look at the central office components involved in ADSL delivery.
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All elements of the ADSL delivery system must be considered to maximize performance. Knowledge of the limiting criteria in each, as well as the optimal location for enhancement must be considered for any commercially successful design. The three major parts of this system include the Central Office, the outside loop plant, and the Customer Premise. Of these, the Central Office offers the greatest opportunity to optimize performance. A high level block diagram of a typical CO is shown in Figure 4.

MDF DSLAM MAP TERMINAL PROTECTOR BLOCK OUT
Subscriber Appearance Equipment Appearance
ADSL IN POTS IN POTS-ADSL OUT POTS-ADSL OUT
OUTSIDE PLANT CABLE BINDER

DSLAM-SPLITTER CABLE

POTS CABLE

CO POTS SPLITTER

POTS - ADSL CABLE

TERMINAL BLOCK IN

Figure 4: ADSL Components in Central Office
From the illustration, the components that must be considered for optimizing performance are: 1. the DSLAM, or Multiservice Access Platform (MAP) 2. the cable connecting the DSLAM/MAP to the POTS splitter (DSLAM-SPLITTER CABLE), 3. the CO POTS Splitter, 4. the cable connecting the combined ADSL and POTS to the MDF (POTS-ADSL CABLE), 5. the terminal block that brings the equipment side of the ADSL service onto the MDF (TERMINAL BLOCK IN), 6. the connections from the TERMINAL BLOCK IN to the TERMINAL BLOCK OUT, and, 7. the terminal block that connects the service to the TIP/RING pair going out to the subscriber (TERMINAL BLOCK OUT)
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Perhaps the most important factor to consider regarding the MAP, is the tradeoff between data rates and error performance. With no imposed constraints, an ADSL link will train to its maximum data rate by loading as many bits per bin as the SNR will support. While this approach offers the highest nominal bandwidth, it leaves little headroom to accommodate fluctuations in noise and loop attenuation. Loop attenuation can vary by 2 -4 dB depending on the loop plant makeup and temperature. Similarly, crosstalk conditions can vary significantly during peak demand times such as after school or evening hours. If the noise level increases to the point where the SNR will no longer support the specific bin loading, the ADSL link will retrain with a new bin loading. During retrain, the link does not carry data and this will cause a noticeable disturbance in the video. Also, the link will retrain at a data rate that could be lower than the minimum required to provide appropriate service.
RECOMMENDATION 1: ADSL Min/Max Train Rates
It is STRONGLY recommended that ADSL ports be configured so that the maximum downstream train rate is limited to no more than the bandwidth required to support service delivery. For example, consider the example of a video and internet data service shown in Table 1. Accounting for multicast and uni-cast traffic, the analysis shows that the two set top box service will demand 7.8Mbps of channel capacity. If left unconstrained, the ADSL link could train up to 10Mbps. This assumes that the port is configured for G.DMT mode with S=1/2 and the loop length is of sufficient length. The excess channel capacity (10Mbps 7.8Mbps) will be subject to increased link errors that will result in degraded video quality. Configuring the ADSL port for a maximum downstream rate of 8.2M will result in a lower bit error rate and consistent high quality video delivery. (Note 8.2Mbps was chosen instead of 7.8Mbps. This allows a 5% margin added to the total downstream requirement.)

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Table 1: Downstream Data Rates
Multicast Contribution Encoder Video Rate Encoder Audio Rate Encoder Overhead Rate Video Burst Factor Electronic program guide Number of Set Top Boxes Allowed 3Mbps 200Kbps 300Kbps 5% 40Kbps 2
Total Multicast Contribution = ((3M + 200K) *(1.05) + 40K) * 2 = 6.8Mbps Unicast Contribution Maximum Internet Downstream Data Rate 1Mbps
Total Downstream Required = 7.8M
RECOMMENDATION 2: ADSL Target SNR=8
Higher values of SNR improve the ADSL links ability to sustain higher amplitude bursts of noise without effect on video quality. It is recommended to configure all ADSL ports for a target SNR of 8dB. Lower values of SNR, which raise train rates and increase reach, can be used for some subscribers but will make the service more susceptible to intermittent errors and periods of poor video quality. The service may appear error free when it is first installed, but over time customers with lower target SNR values may experience service degradation and interruption. Never use a target SNR lower than 6dB. The final consideration for the DSLAM is the cabling used for connecting to the POTS splitter. It is important to minimizing crosstalk in this connection. Depending on the type of ADSL line card used, anywhere from 8 to 24 circuits can be carried in the DSLAMSPLITTER CABLE. Minimizing the coupling between ADSL circuits within this cable is very important.
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RECOMMENDATION 3: Use a high performance DSLAM-SPLITTER CABLE
DSLAM-SPLITTER CABLEs should only be constructed with 25 pair
cable that is rated at CAT5 or higher. At the point where the individual twisted pairs terminate on RJ-21 (Telco style) connector, be sure to maintain the twist as close as possible to where the wires attach to the connector. Figure 5 shows examples of incorrectly and correctly terminated cables.

Incorrect Twist not maintained close to connector.
Correct Twist maintained very close to connector.
Figure 5: RJ-21 Terminations
Allied Telesyn offers precision engineered DSLAM-SPLITTER CABLEs in a variety of lengths. These cables are manufactured to stringent engineering guidelines that maximize isolation between ADSL circuits.
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RECOMMENDATION 4: Minimize the Number of RJ-21 connectors
It is important to know that an RJ-21 connector has a significant amount of crosstalk. For this reason, installations should eliminate unnecessary RJ-21 connectors in the ADSL path, including the connections from the DSLAM to the splitter and the connections from the splitter to the MDF. Port to port isolation measurements on a sample RJ-21 connector are shown in Figure Figure 6. As you can see, isolation worsens as frequencies increase. Therefore, for ADSL (maximum frequency = 1.1MHz) the worse case isolation between adjacent pairs is approximately -64dB. For ADSL2+ (maximum frequency = 1.1MHz), the worse case isolation between adjacent pairs is around -58dB.
RJ-21 Port to Port Isolation

995500

-63 Isolation [dB] Adjacent One Away Two Away

-75 Frequency [Hz}

Figure 6: RJ-21 Port to Port Isolation Figure 6 shows that, in addition to noise coupling from adjacent pairs, there is decreasing crosstalk from neighboring pairs as they move apart. As an example, Figure 7 shows mathematically how the crosstalk from adjacent ports on an RJ-21 connector, contributes to the net noise level on port 7.
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Port 10 Port 9 -70 dB

-76 dB

Port 8

-64 dB Port 7

Port 6

-64 dB

Port 5

-70 dB Port 4 -76 dB
Figure 7: Power Summing Effect of Crosstalk (Net Isolation) With all ports shown transmitting at maximum power, port 7 will have a power sum noise level of -59.8 dB from the transmitted level. Since the coupling is bilateral the choice of the term source and victim is arbitrary. For the total summing effect the contribution of all ports must be included.
S7V4:= 76 S7V5:= 70 S7V6:= 64 S7V8:= 64 S7V9:= 70 S7V10:= 76
S7V4 S7V5 S7V6 S7V8 S7V9 S7V10
Source Port # Victim Port #

A1 := 10

A1 = 1.046 10
Coupling := 10 log ( A1) Coupling = 59.803

Table 2

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CO POTS Splitters are often designed for the highest port densities. Typical chassis based splitters carry 24 ADSL/POTS circuits per line card. As with 24 pair cable, splitters must be designed to minimize port to port crosstalk. ADSL train rates on four sequential ADSL ports were measured using splitters from 3 different manufacturers. The net port to port isolation at (net isolation considers the noise contributions of all ports) at 1104 Khz for the splitters was measured at: BRAND 1 net isolation = -53.3dB BRAND 2 net isolation = -49.0dB BRAND 3 net isolation = -45.6dB The train rates achieved on the 4 ports measured with each splitter are shown in Figure 8.

Splitter Brand 1

Splitter Brand 2

Splitter Brand 3

Average Train Rate

Port #

Figure 8: Splitter Effect on ADSL Data Rates
The train achieved on the 4 ports. Ports measured with each splitter are shown in Figure 8. As you can see, all CO POTS splitters are not alike. The splitter with the greatest isolation at 1104 KHz (highest frequency utilized for this ADSL mode) yielded the highest train rates.
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RECOMMENDATION 5: Use CO POTS splitters with the highest ratings of net self crosstalk isolation
In order to keep the POTS splitter from affecting service delivery when the distribution loops travel the same distance and carry 14 bits per bin, the splitter must have a net isolation of greater than -54dB at the highest ADSL frequency. Allied Telesyn offers CO POTS splitters that are engineered for maximum isolation to account for SNR and downstream power cutback impact. Accounting for these parameters prevents CO interaction between long distance and short distance services. Different service distances and mixes may require more or less isolation depending on the actual conditions. Allied Telesyn can assist to help determine the exact requirements of specific deployment conditions.
RECOMMENDATION 6: Use a high performance POTSADSL CABLE
Cabling from the POTS splitter to the MDF carries similar requirements to those that apply to the DSLAM-SPLITTER CABLE. CATpair should always be used, and for the end of the cable that attaches to the splitter, the twisted pair must maintain the twist as close to the RJ-21 connector as possible. Refer to Figure 5.

"

The main distribution frame (MDF) in a central office is typically divided into two sections; the equipment side and the subscriber (or outside plant) side. Facilities equipment is cabled to a terminal block, labeled in Figure 4 as TERMINAL BLOCK IN. Usually the terminal block provides appearances of the TIP/RING pairs from office equipment; PSTN switch, POTS-ADSL output from a POTS splitter, etc. Service is installed to a subscribers loop by connecting the equipment appearance to the subscribers appearance on the terminal block labeled in Figure 4 as TERMINAL BLOCK OUT.
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Allied Telesyn has evaluated several styles of terminal blocks for crosstalk performance. Figure 9 shows the measurements taken from a terminal block that is commonly found in North American COs. This terminal block is constructed with an RJ-21 connector that terminates the 25 pair cable from the POTS splitter and provides wirewrap pins for equipment appearances. From the graph it can be seen that this type of terminal block offers approximately 50dB of isolation from adjacent ports at 1.1MHz. The net isolation will be somewhat lower. Recall from the discussion of the POTS splitter, that the engineering objective is for at least 54dB net isolation. Obviously this style of terminal block is unsuitable for optimized ADSL, not to mention ADSL2+. This terminal block will degrade ADSL data rates and will also cause significant degradation on short loops when long loops are provision adjacent to short loops.
-45 -50 Isolation [dB] -55 -60 -65 -70 -75 Frequency [Hz] Two Away One Away Adjacent Three Away
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Fr eq u 2. en 18 cy E 4. +5 E 6. +5 E 8. +5 E 1. +5 E 1. +6 E 1. +6 E 1. +6 E 1. +6 E 2. +6 E+ 06
Figure 9: Terminal Block Crosstalk (Standard: Wirewrap with RJ-21 Connector)
RECOMMENDATION 7: Use Ethernet quality punchdown blocks for MDF connections
The highest performing terminal blocks are those used for interconnecting 100Mbps and 1Gbps Ethernet services. These blocks use an insulation displacement technology that requires the twisted pair to be punched-down into the connector block. The S210 punchdown block from the Siemon company (www.siemon.com) is an example of a high performance terminal block. Crosstalk measurements made on this block are shown in Figure 10. Note that the crosstalk isolation of this block approaches 100dB. This block will easily support ADSL2+ rates.

NEXT (Com m on Mode) vs. Frequency (forw ard orientation) -30 -40 -50 NEXT (dB) -60 -70 -80 -90 -Frequency (Mhz) 1000 Pair 1-2 Pair 1-3 Pair 1-4 Pair 2-3 Pair 2-4 Pair 3-4 Limit
Figure 10: Terminal Block Crosstalk (CAT6 Punchdown)
Punchdown blocks do have two disadvantages. One, their dimensions are larger than traditional wirewrap styled blocks and therefore do not easily mount on most MDFs. Two, punchdowns are not commonly used in North America COs and carry an operational stigma.
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RECOMMENDATION 8: (Alternate) Use connector-less terminal blocks for MDF connections
A more Telco-friendly alternative has been identified that provides a higher level of crosstalk isolation than the traditional terminal block, but does not have the operational issues associated with punchdown technologies. The alternative terminal block is connector-less with wirewrap pins that terminate the cables from the POTS splitter and wirewrap pins that provide the equipment appearance for connecting to subscribers. While it does not have level of isolation provided by the punchdown technologies, the Telect 485-0000-041 (www.telect.com) , has been found to have acceptable levels of isolation. Crosstalk measurements for this connector-less block are shown in Figure 11. From the graph, it can be seen that this style of terminal block provides over 75dB of port to port isolation at 1.1MHz. This level of isolation is sufficient for ADSL service.
2.00E+04 1.62E+05 3.03E+05 4.45E+05 5.87E+05 7.29E+05 8.70E+05 1.01E+06 1.15E+06 1.30E+06 1.44E+06 1.58E+06 1.72E+06 1.86E+06 2.00E+06 2.15E+06
-6.50E+01 -7.00E+01 -7.50E+01 Crosstalk [dB] -8.00E+01 -8.50E+01 -9.00E+01 -9.50E+01 -1.00E+02 -1.05E+02 -1.10E+02 -1.15E+02 Frequency [Hz} One Away Adjacent Two Away
Figure 11: Terminal Block Crosstalk (Standard with Wirewrap Only) For ADSL2+, additional loop treatment is required to minimize port to port crosstalk. The impact of the increased terminal block near end crosstalk of long loops transmitting at maximum power on short loops can be reduced by decreasing the relative transmit power differences between them.
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This is possible by placing enough attenuation at the subscriber premise in the ADSL plant to force the short loop to transmit the downstream power at the same level as the long loop services. Allied Telesyn provides attenuation components and installation guidelines on how to recover service rate lost to this effect.

# "

ADSL standards do not specify all the technical criteria required for a high performance video distribution network. This white paper identifies CO system level design criteria which requires careful consideration in order to maximize performance for a production video over ADSL delivery network. Following the installation and operational recommendations within ensures that the network performance will be limited by the outdoor loop plant rather than CO practices. Allied Telesyn offers the knowledge and components required to ensure delivery of high quality triple play services.
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% &

A global company with more than two decades of continuous profitability
Founded in 1987 with the goal of producing feature-rich, reliable, standards-based networking products, Allied Telesyn has a proven track record in bridging the gap left by other Ethernet networking manufacturers, whose solutions are often limited in scope or cost-prohibitive. By taking cues directly from our customers and leveraging our global manufacturing competencies, weve evolved a marketfocused approach to system development that is geared entirely to applications, rather than individual components. And by concentrating on battle-tested, end-to-end solutions for vertical market applications we avoid the scattershot, company-focused approach common in the industry. Our tagline: Its Our Network, Too is a testament to our highlevel of accountability and to our investment in our customers bottom line success. Allied Telesyn focuses entirely on end-to-end, purpose-built Ethernet and IP applications; with a complete line of networking products that includes Layer 2 switches, Layer 3 switches, carrier class fiber/copper Multiservice Access Platforms, and residential gateways. No other networking vendor can match Allied Telesyns breadth and depth of Ethernet productswe are the leading manufacturer of media converters, unmanaged Fast Ethernet switches and hubs, fiber optic network adapters and other feature-rich interconnectivity products, worldwide. Additionally, Allied Telesyn has developed a world class systems engineering and support organization that ensures networks are designed and implemented to handle the stress of providing voice, video and data services.

Our tagline: Its Our Network, Too, is a testament to our investment in our customers bottom line success
Allied Telesyn focuses entirely on end-toend, purpose-built Ethernet applications
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2003 Allied Telesyn, Inc.
A world-class engineering and support organization spanning five continents and more than 30 countries
With engineering, manufacturing, sales, and distribution divisions strategically located throughout the Americas, Europe, Asia and Japan, Allied Telesyn is able to deploy solutions anywhere in the world, quickly and efficiently. And by rigorously testing products in design and support centers and leveraging our design and manufacturing competencies, Allied Telesyn is able to offer reliable solutions for the access edge. This ideal combination helps our customers keep costs low, speed network deployment and maximize network uptime. Our customer-driven approachcombined with a pragmatic, value-based pricing scheme and a superlative service organizationhas made Allied Telesyn a global networking leader, with more than 17 years of continuous profitability and products deployed in more than 50,000 companies in 30 countries and five continents. Allied Telesyn: the ideal choice for cost-conscious IT professionals who are looking for highquality, feature-rich network solutions at a lower price
The ideal choice for cost- conscious IT professionals who are looking for highquality, feature-rich network solutions at a lower price.
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Freescale Semiconductor Users Guide
PTKITBASEUG Rev. 1, 9/2005
Packet Telephony Development Kit Baseboard Hardware
The baseboard subsystem in the Packet Telephony Development Kit is the motherboard for the kit. It supports both the fast Ethernet interface to the packet network and the UTOPIA level-2 interface to the ATM network. The heart of the baseboard subsystem is the PowerQUICC II MSC8260 controller, which runs all the application-specific protocols to support the target application and also controls the daughter cards.
CONTENTS 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 4
Packet Telephony Development Kit..3 Getting Started With the Baseboard.4 Components of the Baseboard Subsystem.5 MPC8260...5 Clock Generator..7 Jumper Settings..8 External Power Supply..8 Power Supply Regulators..10 60x SDRAM..10 Local SDRAM..12 Flash Memory..13 DSP Farm Card Interface..14 PSTN Card Interface..20 COP/JTAG Support...24 Signals for General-Purpose Lines..26 Serial Port Interface...30 LEDs...31 TDM Bus...31 Board Initialization..33
Freescale Semiconductor, Inc., 2005. All rights reserved.

Serial Port

Baseboard Ethernet

DSP Card Ethernet

H.100 TDM

PSTN Card Slot

DSP Card Slot

ATM Card Slot

Power Connector Figure 1. Baseboard Interfaces
The features of the baseboard subsystem are as follows (see Figure 2): 480-pin PowerQUICC II MPC8260 control processor. 4 MB unbuffered SDRAM on the 32-bit MPC8260 local bus. 128 MB unbuffered 144-pin small outline DIMM SDRAM on the MPC8260 64-bit system bus. 8 MB buffered Flash memory on the MPC8260 system bus. Dual 10/100 Ethernet transceiver using MPC8260 FCC1 and FCC2 signals. Dual 10/100 Ethernet transceiver using DSP daughter cards. RS-232 connector for UART applications using the MPC8260 SCC1 signals. High density (Mictor logic) logic analyzer connectors for fast logic analyzer connections. H.100 connector for TDM traffic.
Packet Telephony Development Kit Baseboard Hardware, Rev. Freescale Semiconductor
Packet Telephony Development Kit

RS-232

Dual 10/100 PHY
DSP Card Only Ethernet Dual 10/100 PHY

60x Bus SoDIMM Local Bus

MPC8260
SCC1 FCC1 FCC2 TDMA Switch DSP Card MII Connector
SDRAM DSP Card Bus Connector Buffer

Buffer

ATM Card UTOPIA Connector

Buffer Flash

DSP Card UTOPIA Connector

ATM Card Bus Connector

TDM Card Bus Connector

TDM Card TDM Connector

H.100 Connector

DSP Card TDM Connector

Figure 2. Baseboard Block Diagram
The Packet Telephony Development kit (PDK) is a platform for evaluating and developing voiceover packet applications. The PDK has an MPC8260 host network processor that runs Linus, StarCore DSP resource cards that run DSP code, and a Public Switched Telephone Network (PSTN) card with interfaces such as E1/T1 and analog telephone lines (see Figure 3).
Packet Telephony Development Kit Baseboard Hardware, Rev. 1 Freescale Semiconductor 3
Getting Started With the Baseboard

Managed Packet Network

Telephone Network
MPC8260 Control Processor

Ethernet

StarCore DSP Resource Daughtercard
Baseboard Figure 3. Components of the Packet Telephony Development Kit (PTK)
The documentation for the kit components is as listed in Table 1.
Table 1. PTK Components and Their Associated Documents
Component Baseboard MPC8260 Control Processor PSTN Card StarCore DSP Resource Daughtercard Document Packet Development Kit Baseboard Hardware Users Guide MPC8260 PowerQUICC II Family Reference Manual (Available at the website listed on the back page of this users guide.) Packet Development Kit PSTN Card Users Guide MSC8102 Packet Telephony Farm Card (MSC8102PFC) Users Guide MSC8101 Packet Telephony Farm Card (MSC8101PFC) Users Guide Reference manuals and other documentation for the MSC81xx products are located at the website listed on the back page of this users guide. Packet Telephony Development Kit Software Users Guide PTKITSOFTUG Document ID PTKITBASEUG MPC8260UM PTKITPSTNUG PTKIT8101UG PTKIT8102UG
StarCore DSP Resource Software

CAUTION:

Optional PSTN Card Power

Power Card +3.3 V 5V Basecard Power
Standard ATX Power Connector

ATX PC Power Supply

110 or 220 AC Figure 7. External Power Set-up
Table 4 shows the outputs of the power supply card.
Table 4. Power Supply Outputs
Pin Purpose PSTN card ring PSTN card ring Voltage +48 V +24 V Maximum Output Current 63 mA 378 mA Notes Minimum load of 7 mA means that measured voltage without a load is much higher. Pins 2 and 3 are shared. Total power from these pins does not exceed 9 W. A minimum load of 4.2 means that measured voltage without a load is much higher. Pins 2 and 3 are shared. Total power from these pins does not exceed 9 W. A minimum load of 2.1 mA means that measured voltage without a load is much higher.
PSTN card battery PSTN card ground Baseboard ground Baseboard Baseboard Switch power ON Switch ground

189 mA

GND GND +5V + 3.3 V N/A GND
Limited by external supply Limited by external supply Grounding this pin turns on the external ATX power supply.
Packet Telephony Development Kit Baseboard Hardware, Rev. 1 Freescale Semiconductor 9
3.5 Power Supply Regulators
The Austin MicroLynx DC-DC (Tyco) SMT 5A and Linear technology (LT1963ES8-25) modules are included to meet voltage requirements for baseboard and high-performance MSC810x DSP cards (see Table 5).
Table 5. Power Supply Regulators
Voltage DSP voltage Setting The 5 volt and 3.3 volt power supplies are fed as inputs into the Austin Micro Lynx DC-DC (Tyco) SMT 5A power regulators. Austin Micro Lynx DCDC has a Pot resistor (VR2) that users can adjust to meet the appropriate DSP voltage. Connecting Jand 2 disables this supply. The 5 volt and 3.3 volt power supplies are fed as inputs into the Austin Micro Lynx DC-DC (Tyco) SMT 5A power regulators. Austin Micro Lynx DCDC has built in a Pot resistor (VR1) that users can adjust to meet the appropriate PQ2 voltage. The 3.3 volts inputs are fed into a linear technology power regulator (LT1963ES8-25) that produces an output voltage for the Ethernet transceiver I/O voltages. Source (power supply). Source (power supply). Ground. Output 1.6-2.0 volts Voltage Locations in Baseboard J20

Figure 15. JTAG With MPC8260 Only
Packet Telephony Development Kit Baseboard Hardware, Rev. 1 Freescale Semiconductor 25
Figure 16. JTAG With DSP and PSTN Card
3.12 Signals for General-Purpose Lines
Table 19 lists the MPC8260 general-purpose input/output (GPIO) lines. The signals marked by * are shared between the Ethernet and ATM. These signals cannot be used via both Ethernet and ATM at the same time, so a switch from Pericom (PI3B16233) allows you to select between ATM or Ethernet. The switch is controlled via J17. When J17 is open, ATM is used. When J17 is closed, Ethernet is used. Figure 17 illustrates the ATM/Ethernet switch.
Ir) U@urrvurihrihqhrqrqvphrqurHQ8'!%Q@urrA88!v
uhrqvu6UH@urr A88 vvqrrqrsurrvtsurQrvpvpu Srsr@urrA88 vUhiyr (
Table 19. MPC8260 GPIO and CPM Signals
MPC8260 Pin (Source) PA0 PA1 PA2 PA3 PA4 PA5 PA6 (GPIO) PA7 (GPIO) PA8 (GPIO) PA9 PA10 PA11

Function UTOPIA FCC2

Destination 1 UTP_TXADR2 UTP_TXADR1 UTP_TXADR0 UTP_RXADR0 UTP_RXADR1 UTP_RXADR2 CT_FRAME_A CT_D5 CT_D4

Destination 2

O O O I I I I/O I/O I/O
Table 19. MPC8260 GPIO and CPM Signals (Continued)
MPC8260 Pin (Source) PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB4 PB5 PB6 PB7 PB8 PB9 PB10 (GPIO) PB11 (GPIO) PB12 (GPIO) PB13 (GPIO) PB14 (GPIO) PB15 (GPIO) PB16 PB17 UTOPIA using FCC2 Ethernet using FCC1 PQ2_PHY1_RERR PQ2_PHY1_RDV PQ2_PHY1_TXEN PQ2_PHY1_TERR PQ2_PHY1_CRS PQ2_PHY1_COL UTP_RXD0 UTP_RXD1 UTP_RXD2 UTP_RXD3 UTP_TXD3 UTP_TXD2 TDM_GPIO5 TDM_GPIO4 TDM_GPIO3 TDM_GPIO2 TDM_GPIO1 TDM_GPIO0 Ethernet using FCC1 PQ2_PHY1_RD3 PQ2_PHY1_RD2 PQ2_PHY1_RD1 PQ2_PHY1_RD0 PQ2_PHY1_TD0 PQ2_PHY1_TD1 PQ2_PHY1_TD2 PQ2_PHY1_TD3 Function Destination 1 I/O Destination 2 I/O

I I I I O O O O

I I O O I I I I I I O O I/O I/O I/O I/O I/O I/O
Packet Telephony Development Kit Baseboard Hardware, Rev. 1 Freescale Semiconductor 27
MPC8260 Pin (Source) PB18* PB19* PB20* PB21* PB22* PB23* PB24* PB25* PB26* PB27* PB28* PB29* PB30* PB31* PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 (GPIO) PC10 (GPIO) PC11 (GPIO) PC12 (GPIO) PC13 (GPIO) PC14 (GPIO) PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PQ2_PHY5_RCLK PQ2_PHY5_TCLK PQ2_PHY2_RCLK PQ2_PHY2_TCLK PQ2_PHY1_TCLK PQ2_PHY1_RCLK PQ2_IDMA1_DONE Ethernet using FCC2 PQ2_PHY2_MDIO PQ2_PHY2_MDC PQ2_TO_DSP_INT 1 PQ2_TO_DSP_INT 2 DSP_GPIO PQ2_RS232_RS_C D Ethernet using FCC2 FCC2_RXENB FCC2_TXCLAV Ethernet and UTOPIA using FCC2 Function Ethernet and UTOPIA using FCC2 Destination 1 PQ2_PHY2_RD3 PQ2_PHY2_RD2 PQ2_PHY2_RD1 PQ2_PHY2_RD0 PQ2_PHY2_TD0 PQ2_PHY2_TD1 PQ2_PHY2_TD2 PQ2_PHY2_TD3 PQ2_PHY2_CRS PQ2_PHY2_COL PQ2_PHY2_RERR PQ2_PHY1_RDV PQ2_PHY2_TXEN PQ2_PHY2_TERR PQ2_IDMA2_DREQ PQ2_IDMA2_DREQ PQ2_IDMA2_DONE I/O Destination 2 UTP_RXD4 UTP_RXD5 UTP_RXD6 UTP_RXD7 UTP_TXD7 UTP_TXD6 UTP_TXD5 UTP_TXD4 UTP_TXD1 UTP_TXD0 UTX_IF_UTP UTX_IF_RXCLAV UTP_TXSOC UTP_TXENB I/O

I I I I O O O O I I O O I I I I O I O

O 1/O 1/O 1/O 1/O 1/O

I I I I I I O
MPC8260 Pin (Source) PC23 PC24 PC25 PC26 (GPIO) PC27 PC28 PC29 PC30 (GPIO) PC31 (GPIO) PD4 (GPIO) PD5 (GPIO) PD6 (GPIO) PD7 (GPIO) PD8 PD9 PD10 (GPIO) PD11 (GPIO) PD12 (GPIO) PD13 (GPIO) PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 (GPIO) PD23 (GPIO) PD24 (GPIO) PD25 (GPIO) PD26 (GPIO) PD27 (GPIO) PD28 (GPIO) PD29 (GPIO) PD30 (GPIO) PD31 (GPIO) Serial and UTOPIA using SCC FPGA_CCLK FPGA_DONE FPGA_DIN FPGA_PROGRAM ATM_RESET DSP_RESET TDM_RESET PQ2_RS232_RS_C TS PQ2_PD30 PQ2_RS232_RXD ETH1_RST ETH2_RST PQ2_PHY1_MDIO PQ2_PHY1_MDC PQ2_PHY3_MDIO PQ2_PHY3_MDC UTP_TXPRTY UTP_RXPRTY PQ2_PHY4_MDIO PQ2_PHY4_MDC PQ2_PHY5_MDIO PQ2_PHY5_MDC PQ2_I2CSCL PQ2_I2C_SDA PQ2_SPIMISO PQ2_SPIMOSI PQ2_SPICLK TDM_SPI_CS0 TDM_SPI_CS1 ATM_GPIO1 Function Destination 1 I/O Destination 2 I/O
O O O I/O O I/O O I O I/O O I/O O O I O O O O O O I O O O O O O I

UTX_IF_UTP

Packet Telephony Development Kit Baseboard Hardware, Rev. 1 Freescale Semiconductor 29

MPC8260 Common Signals

Figure 17. ATM and Ethernet Switch
3.13 Serial Port Interface
The Intersil ICL3241 device is a 3.0V to 5.5V powered RS-232 transmitter/receiver that meets ElA/TIA-232 and V.28/V.24 specifications (see Figure 18). Table 20 lists the relevant signals between MPC8260 and the ICL3241. These signals ensure a reliable channel for data to travel between the MPC8260 processor and the ICL3241.

Table 20. RS-232 Signals

Signals RTS TXD RXD CD PD29 PD30 PD31 PC14 SCC1 Description PQ2_RS232_RS_CTS PQ2_RS232_TXD PQ2_RS232_RXD PQ2_RS232_RS_CD O O I I I/O
Baseboard ICL3241 RS-232 Serial Connector RTS TXD RXD CD MPC8260 PD29 PD30 PD31 PC14
Figure 18. Serial Port Interface

3.14 LEDs

Table 21 outlines all the LEDs in the baseboard.

Table 21. Baseboard LEDs

LED D7 D8 D9 D10 D11 D12 D1 D2 D3 D4 D5 D6 D26 D27 3.3 V supply 5 V supply MPC8260 Ethernet PHY Device DSP Ethernet PHY Port 0 Tx Port 0 Rx Port 0 link Port 1 Tx Port 1 Rx Port 1 link Port 0 Tx Port 0 Rx Port 0 link Port 1 Tx Port 1 Rx Port 1 link Indicates whether there is an adequate 3.3 V supply Indicates whether there is an adequate 5 V supply Description

3.15 TDM Bus

H.100 is a non-proprietary switching fabric implementation developed by the Enterprise Computer Telephony Forum (ECTF). The standards are implemented in computer telephony (CT) systems. CT systems integrate voice, fax, and data networking. The 20 CT bus lines can support 1280 calls if the bus runs at a rate of 8MBps. The AMP 1-557100-7 is numbered differently than the H.100 specification connector. The AMP 1-557100-7 numbering is as follows:
This numbering should be translated to the H.100 specification numbering when you are referring to the H.100 specifications, as follows:

2. 3. 4.

Program the Flash memory (OR0 and BR0 registers) while referring to Table 9, Flash Memory Br0 and OR0 Registers, on page 14. Program the 60x SDRAM (PSDMR, OR1 and OR2, and BR1 and BR2 registers) following the procedures described in Section 3.6, 60x SDRAM, on page 10. Program the local SDRAM (LSDRAM, OR4, and BR4) following the procedures described in Section 3.7, Local SDRAM, on page 12.

Appendix A

Schematics
The following pages show the baseboard schematics.
Packet Telephony Development Kit Baseboard Version 3.1

Revision History

1.94 2.65 3.0 3.1 Added T3 card support, power sequencing, GPCM pull-up. Flash buffer fix. Second Revision Sent to Fab Initial Prototypes

Table of Contents

Description

This Page

Block Diagram

CPM Switch

Clocks

DSP Ethernet

PQ2 Ethernet

H.100 TDM interface

ATM/Ethernet card PMC connectors

DSP card PMC connectors

TDM card PMC connectors

Power and Reset

System bus buffers

PowerQUICC CPM

PowerQUICC CPU

Flash and System SDRAM

Memory Controller and Local SDRAM

PowerQUICC Power

THESE SCHEMATICS ARE PROVIDED "AS IS". MOTOROLA ASSUMES NO RESPONSIBILITY FOR THE ACCURACY OR COMPLETENESS OF THESE SCHEMATICS AND EXPRESSLY DISCLAIMS ALL REPRESENTATIONS AND WARRANTIES OF ANY KIND REGARDING THE CONTENTS OR USE OF THEM INCLUDING, BUT NOT LIMITED TO, EXPRESS AND IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE, OR NON-INFRINGEMENT. IN NO EVENT WILL MOTOROLA BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, LOST BUSINESS OR LOST DATA, RESULTING FROM THE USE OF OR RELIANCE UPON THESE SCHEMATICS, WHETHER OR NOT MOTOROLA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Packet telelphony

Motorola Copyright 2002 2

Title Name Date:

PTDK BASEBOARD Rich Cutler Tuesday, November 04, 2003
Block Cover Page 3.1 Sheet

R ev 18

Guide to Schematics
Power supplies input 5V, 3.3V: Produce on-board 1.8-1.0V (for DSP), 2.5 (for phy & DSP FPGA), 2.6-1.7V (for 82xx)

Dual 10/100 Phy

33ohm +3.3V 1 10K 3 4

33ohm 1 U31 TP4

2 GND REF CLK2 CLK1 GND

ICS9112-16-G C64 0.01uF C192Place caps close to 0.1uF clock buffer.
2 RR229 CLKOUT CLK4 VCC CLK3
J5 JTAG_TDO ATM_TDO TDM_TDI DSP_TDO JTAG_TDO
Header can be used to put the JTAG in various configurations. To have the PQ2 only, just connect 1 and 2. To connect everything, connect 1-3, 4-6, 7-9, and 8-10. To connect only PQ2 and DSP, connect 1-3 and 4-2. Other combinations possible. ATM_TDI

JTAG_TDO 4 2

TDM_TDO
DSP_TDI PQ2_TDO HEADER5x2

R90 R91 R92 R93 J6

R94 R95

JTAG_TDO RR99

1 0ohm

4K7 4K7 4K7 4K7

R96 10K JTAG_TRST

RR100 2

1 0ohm 1 0ohm 1
PQ2_TDI PQ2_QREQ JTAG_TCK JTAG_TMS PQ2_SRESET PQ2_HRESET

HEADER8x2

On-board COP for MPC8260 MECHANICAL KEY NEEDED.

Block Clocks 3.1 Sheet

R159 R160 R161 330ohm 330ohm 330ohm 330ohm +3.3V D 11 Yellow Green C100 0.1uF C107 C101 0.001uF C102 0.1uF C103 0.001uF C 104 0.1uF C105 0.001uF C106 0.1uF D 12 D7 Yellow Yellow Green Yellow D8 D9 D 10 330ohm 330ohm
Default LED Mode Port 0 Port 1 ----------------------------D7 - Tx D10 - Tx D8 - Rx D11 - Rx D9 - Link D12 - Link

0.001uF 2KV C82

U 18 SGND 1 FB L+ C109 10uF C110 0.1uF C111 0.001uF C112 0.1uF +2.5V C113 0.001uF GNDR GNDR GNDT GNDT LED0_3 LED0_2 LED0_1 LED1_3 LED1_2 LED1_+2.5V 0.001uF 2KV
Ferrite bead seperates the analog and digital supply planes.
DSP_MII1_TXD[0:3] +2.5V + C 114 10uF + C 115 0.01uF C116 0.1uF C117 0.001uF C 118 0.1uF C119 0.001uF 90
Per Port LED and Configuration Signals
DSP_MII1_RXD[0:3] VCCD VCCD GNDD GNDD GNDD
DSP_MII1_TXD0 DSP_MII1_TXD1 DSP_MII1_TXD2 DSP_MII1_TXD3 TXD0_0 TXD0_1 Port0_transmit_data TXD0_2 TXD0_3 VCCR VCCR VCCT VCCT
DSP_M II1_RXD3 DSP_M II1_RXD2 DSP_M II1_RXD1 DSP_M II1_RXD0 RXD0_3 RXD0_2 Port0_recieve_data RXD0_1 RXD0_0 Power Supply Signals Port 0 signals This Port uses FCC2 channel signals +3.3V
R N11A R N11B R N 11C R N 11D

47ohm 47ohm 47ohm 47ohm

R N12A R165

47ohm 43ohm

+3.3V CRS0 COL0 MDC0 VCCPECL GNDPECL Rohm Rohm PQ2_PORESET ETH1_RST LTXD1_0 TXD1_1 Port1_transmit_data TXD1_2 TXD1_3 R R R R 2 RXD1_3 RXD1_2 Port1_recieve_data RXD1_1 RXD1_0 ETH_PHY2_CLK 2 1K 2 1K 2 1K 2 1K DPBP_3 D PBN_3 DPAP_3 D PAN_74 MDIO0 Do Not Populate R287 The default is for Ethernet Reset to be controlled via PORESET. The option exists to give the host PQII reset control
DSP_MII1_TCLK DSP_MII1_RCLK DSP_MII1_TXEN DSP_MII1_RXDV DSP_MII1_TXER DSP_MII1_RXER TXCLK0 RXCLK0 TXEN0 RXDV0 TXER0 RXER0 GNDIO GNDIO GNDIO GNDIO VCCIO VCCIO VCCIO VCCIO 84 96

R N 12B

47ohm 46 47ohm 45
DSP_MII1_CRS DSP_MII1_COL MDC_FROM_DSP PQ2_PHY3_MDC MDIO_FROM_DSP

PQ2_PHY3_MDIO

DSP_MII2_TXD[0:3]
R N 12C R N 12D 1 R0 ohm 1 R0 ohm
DSP_MII2_TXD0 DSP_MII2_TXD1 DSP_MII2_TXD2 DSP_MII2_TXD3

C120 0.001uF 2KV

0.001uF 2KV C121 C122 0.001uF 2KV

DSP_MII2_RXD[0:3]

DSP_M II2_RXD3 DSP_M II2_RXD2 DSP_M II2_RXD1 DSP_M II2_RXD0
R N13A R N13B R N 1 3C R N 1 3D
R N14A R170 Port 1 signals This Port uses FCC1 channel signals
RESET ADDR1 ADDR2 ADDR3 ADDR4 TEST_0 TEST_1 REFCLK
P8 NC NC B1 B2 B3 C123 0.01uF NC NC NC NC NC NC 50ohm R171 50ohm 50ohm R172 R173 A4 A5 B6 50ohm R 174 50ohm R175 50ohm R176 A7 A8 AGRAY_B1 BROWN__B2 YELLOW_B3 GREEN_A4 RED_A5 BLACK_B6 ORANGE_A7 BLUE_A8 GRAY_A1
+3.3V COL1 CRS1 MDC1 MDIO1 DPBN_1 DPBN_64 D PBN_3 D PBN_2 DPBP_0 DPBP_67 DPBP_2 DPBP_3
DSP_MII2_TCLK DSP_MII2_RCLK DSP_MII2_TXEN DSP_MII2_RXDV DSP_MII2_TXER DSP_MII2_RXER TXCLK1 RXCLK1 TXEN1 RXDV1 TXER1 RXER1

R N 14B

DSP_MII2_COL DSP_MII2_CRS
R N 14C 47ohm R N 1 4D 47ohm
PQ2_PHY4_MDC MDC_FROM_DSP

PQ2_PHY4_MDIO

MDIO_FROM_DSP

1 R0 ohm 1 R0 ohm 2 R177

SD0 SD1 LXT973 1K 1
L6 50ohm 2 R180 DPBP_2 D PBN_2 +3.3V 50ohm 50ohm R181 R184

A2 A3 B4 B5 A6

BROWN_A2 YELLOW_A3 GREEN_B4 RED_B5 BLACK_A6

DPAN_0 DPAN_1

D PAN_2 D PAN_3

DPAP_0 DPAP_1

DPAP_2 DPAP_3 R 1K 2 10K 2 10K 2 RRRRRRR R 1K 2 1K 2 1K 1K 1K 1K 10K 2 10K 2 10K 2 10K 2 10K 2 Do Not Populate R238, R239
DPAP_2 D PAN_2 C124 0.01uF

B7 B8 NC NC H1200 NC NC

ORANGE_B7 BLUE_B8

R179 1

21 U 19 50ohm 2 +3.3V RR195 C125 0.001uF 2KV 1 R R 2 1K 2 1K RR10K 2 10K 2 C126 0.001uF 2KV ohm 0ohm C127 0.001uF 2KV R R R R 197 1
LED_CGF1 LED_CGF0 DUPLEX1 DUPLEX0 SD_2P5V/SPEED0 SD_2P5V/SPEED1 AUTO_NEG1 AUTO_NEG0
TxSLEW0 TxSLEW1 MDDIS0 MDDIS1 FIBER_TP1 FIBER_TP0 PWRDWN1 PWRDWN0

C1 C2 C3 C4 C5 C6

NC1 NC2 NC3 NC4 CHASSIS CHASSIS
Motorola Copyright 2002 B C D

Title N a me Date:

Block DSP Card Ethernet 3.1 Sheet 5 of R ev 18

CT_D3 CT_D2 CT_D1 CT_D0

CT_D[0:19]
CT_FRAME_A CT_C8_A CT_FRAME_B CT_C8_B FST3245 RN25 10ohm
RN24 22ohm 4 CONN_CT_D3 3CONN_CT_D2 2CONN_CT_D1 1CONN_CT_D0 CONN_CT_FRAME_A 4 CONN_CT_C8_A 3 CONN_CT_FRAME_B 2 CONN_CT_C8_B 1
37 38. Should be translated to the H.100 specification numbering

J28 JUMPER

J29 J30 J31 JUMPER JUMPER JUMPER
Close jumpers when the R222 R223 R224 R225 100ohm 100ohm 100ohm 100ohm CT bus is terminated at the PDTK.
C170 100pF 100pF 100pF 100pF
when referring to the H.100 specification.
Block H.100 Connector 3.1 Sheet
Baseboard component side.

PTMC J2

PTMC J4
+5V J15 +3.3V JTAG_TRST ATM_TDO UTP_TXSOC UTP_RXADR4 UTP_TXADR4 CONN_AD23 CONN_AD24 CONN_AD25 +3.3V UTP_RXADR2 UTP_TXADR1 UTP_RXADR1 UTP_RXADR0 UTP_RXPRTY UTP_RXD7 UTP_RXD6 UTP_RXD5 UTP_RXD4 UTP_RXD3 UTP_RXD2 UTP_RXD1 UTP_RXD0 UTP_RxSOC UTP_TXENB UTP_RXENB UTP_RXCLAV CONN_AD26 CONN_AD27 CONN_AD28 CONN_AD29 CONN_AD30 CONN_AD31 ATM_TO_PQ2_INT1 BUF_BCTL0_N PQ2_CS_ATM2 TDM_GPL2 BUFF_GPL1 PQ2_CS_ATM BUF_WE0 ATM_GPIO1 PQ2_PHY5_RCLK PQ2_PHY5_TCLK PQ2_PHY5_MDC JTAG_TCK +5V UTP_TXCLAV J16

PQ2_PHY5_MDIO

JTAG_TMS ATM_TDI

CO NN_D0 CO NN_D1

ATM_RESET

CO NN_D2 CO NN_D3

CO NN_D4 CO NN_D5

CO NN_D6 CO NN_D7

CO NN_D8

CO NN_D9

C ONN_D10 C ONN_D11

C ONN_D12 C ONN_D13

C ONN_D14 C ONN_D15

CONN_AD22

5 UTP_RXADRUTP_TXADRUTP_TXADR25 UTP_TXCLK 27 UTP_TXADR31 UTP_TXPRTY 33 UTP_TXDUTP_TXD43 UTP_RXCLK 45 UTP_TXDUTP_TXD51 UTP_TXDUTP_TXD57 UTP_TXDUTP_TXD63
HEADER32x2 Note: Since ATM card is not yet designed, extra bus control and GPIO signals have been added to the interface.

HEADER32x2

UTP_TXD7 UTP_TXD6 UTP_TXD5 UTP_TXD4 UTP_TXD3 UTP_TXD2 UTP_TXD1 UTP_TXD0
UTP_RXD7 UTP_RXD6 UTP_RXD5 UTP_RXD4 UTP_RXD3 UTP_RXD2 UTP_RXD1 UTP_RXD0

CONN_D[0:15]

CO NN_D0 CO NN_D1 CO NN_D2 CO NN_D3 CO NN_D4 CO NN_D5 CO NN_D6 CO NN_D7 CO NN_D8 CO NN_D9 C ONN_D10 C ONN_D11 C ONN_D12 C ONN_D13 C ONN_D14 C ONN_D15 CONN_AD[15:31] CONN_AD22 CONN_AD23 CONN_AD24 CONN_AD25 CONN_AD26 CONN_AD27 CONN_AD28 CONN_AD29 CONN_AD30 CONN_AD31 UTP_TXADR[0:4]
UTP_TXADR4 UTP_TXADR3 UTP_TXADR2 UTP_TXADR1 UTP_TXADR0

UTP_RXADR[0:4]

UTP_RXADR4 UTP_RXADR3 UTP_RXADR2 UTP_RXADR1 UTP_RXADR0
Block ATM PTMC Connectors Sheet

+3.3V T1

5mm_Link FPGA_CCLK FPGA_DONE FPGA_DIN

PTMC J1

FPGA_PROGRAM

PTMC J5

PTMC J3

J11 +5V J12 J13

PQ2_HRESET JTAG_TMS DSP_TDI MDIO_FROM_DSP MDC_FROM_DSP UTP_TXCLAV UTP_RXADR4 UTP_TXADR4 UTP_TXSOC

JTAG_TRST DSP_TDO

PMC_HA1

JTAG_TCK

J14 HEADER32x2
PMC_HA2 PMC_HA3 UTP_RXENB UTP_RXCLAV UTP_RXADR2 UTP_TXADR1 UTP_RXADR1 UTP_RXADR0 UTP_RXPRTY UTP_RXD7 UTP_RXD6 UTP_RXD5 UTP_RXD4 UTP_RXD3 UTP_RXD2 UTP_RXD1 UTP_RXD0 UTP_RxSOC UTP_TXENB

+1.6V +1.6V

LGPL5 LSDCAS CT_FRAME_A CT_FRAME_B CT_C8_A CT_D18 CT_D16 CT_D14 CT_D12 DSP_GPIO CT_C8_B CT_D10 CT_D8 0ohm 0ohm 0ohm 0ohm HEADER32x2 CT_D19 CT_D17
PQ2_IDMA1_DREQ PQ2_IDMA2_DREQ
PQ2_TO_DSP_INT1 PQ2_CS_DSP

PQ2_TO_DSP_INT2

DSP_MII2_TCLK DSP_MII2_TXD0 DSP_MII2_TXD1 DSP_MII2_TXD2 DSP_MII2_TXD3 DSP_MII2_RXDV DSP_MII2_RXD0 DSP_MII2_RXD1 DSP_MII2_RXD2 DSP_MII2_RXD3 DSP_MII2_TXEN DSP_MII2_TXER DSP_MII2_COL

DSP_TO_PQ2_INT1

DSP_TO_PQ2_INT2 PMC_HA_DSP0

PMC_HA_DSP1 PMC_HA_DSP2

PQ2_IDMA1_DONE CT_D2 CT_D0 CT_D1 CT_D5 CT_D3

CT_D6 CT_D4

CT_D15 CT_D13 CT_D11 CT_D9 CT_D7
DSP_MII2_RXER DSP_MII2_CRS DSP_MII2_RCLK DSP_MII1_TXD0 DSP_MII1_TXD1 DSP_MII1_TXD2 DSP_MII1_TXD3 DSP_MII1_RXDV DSP_MII1_RXD0 DSP_MII1_RXD1 DSP_MII1_RXD2 DSP_MII1_RXD3
+3.3V LDLD13 DSP_RESET 15 LDLD21 LDLD27 LDLD33 LD37 LD41 LDLD47 LDLD53 LDLD59 PMC_HA1

PQ2_IDMA2_DONE

UTP_RXADR9 PQ2_I2CSCL 15 UTP_TXADRUTP_TXADR25 UTP_TXCLK 27 UTP_TXADR31 UTP_TXPRTY 33 UTP_TXDUTP_TXD43 UTP_RXCLK 45 UTP_TXDUTP_TXD51 UTP_TXDUTP_TXD57 PQ2_I2C_SDA UTP_TXDUTP_TXD64
PQ2_BUS_CLK Do not populate R306 and R307

2 RRRR308

DSP_MII1_TXEN DSP_MII1_TXER DSP_MII1_COL
NOTE: To use the HPAC MPC8260 CPM microcode, add R227 and R228 and depopulate R104 and R105. HPAC also requires R306 and R307 to be populated and R305 and 308 to be depopulated.

LA14 LA15 LA16 LA17 LA18

RRRRR105 2
0ohm 1 PMC_HA_DSP0 0ohm 1 PMC_HA_DSP1 0ohm 1 PMC_HA_DSP2 0ohm PMC_HA0ohm PMC_HA1 1
UTP_TXD7 UTP_TXD6 UTP_TXD5 UTP_TXD4 UTP_TXD3 UTP_TXD2 UTP_TXD1 UTP_TXD0 UTP_TXADR4 UTP_TXADR3 UTP_TXADR2 UTP_TXADR1 UTP_TXADR0
UTP_RXD7 UTP_RXD6 UTP_RXD5 UTP_RXD4 UTP_RXD3 UTP_RXD2 UTP_RXD1 UTP_RXD0 UTP_RXADR4 UTP_RXADR3 UTP_RXADR2 UTP_RXADR1 UTP_RXADR0
DSP_MII1_RXER DSP_MII1_CRS DSP_MII1_RCLK DSP_MII1_TCLK
HEADER32x2 DSP_MII2_TXD3 DSP_MII2_TXD2 DSP_MII2_TXD1 DSP_MII2_TXD0 DSP_MII1_TXD[0:3]
DSP_MII1_TXD3 DSP_MII1_TXD2 DSP_MII1_TXD1 DSP_MII1_TXD0 DSP_MII1_RXD3 DSP_MII1_RXD2 DSP_MII1_RXD1 DSP_MII1_RXD0

LD[0:31]

LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 RRTP5 TP6 0ohm 1 PMC_HA2 0ohm 1 PMC_HA3 Do not 0ohm populate R0ohm and R228. 1 RRCT_D[0:19]

LA[14:30]

LA25 LA26 LA27 LA28 LA29 LA30
CT_D0 CT_D1 CT_D2 CT_D3 CT_D4 CT_D5 CT_D6 CT_D7 CT_D8 CT_D9 CT_D10 CT_D11 CT_D12 CT_D13 CT_D14 CT_D15 CT_D16 CT_D17 CT_D18 CT_D19 UTP_TXADR[0:4]
DSP_MII2_RXD3 DSP_MII2_RXD2 DSP_MII2_RXD1 DSP_MII2_RXD0 DSP_MII1_RXD[0:3]

Motorola Copyright 2

Block DSP PTMC Connectors 3.1 Sheet

PTMC J2 PTMC J1

CS1, INT1 go to QuadFALCC on TDM card. CS2, INT2 go to TSI.
REMEMBER: D0 is LSB on QuadFALC D0 is MSB on Motorola!! +3.3V
REMEMBER: A0 is LSB on QuadFALC A31 is LSB on Motorola!!

+5V J9 +5V

TDM_SPI_CS1 JTAG_TMS TDM_TDI JTAG_TCK +5V

JTAG_TRST TDM_TDO

CONN_AD23
PQ2_UPMWAIT PQ2_GPL5 PQ2_CS_TDM3 CONN_AD21 CONN_AD20 CONN_AD19 CONN_AD18 CONN_AD17 CONN_AD16 CONN_AD15
CONN_AD24 CONN_AD25 +3.3V CT_C8_A CT_D18 CT_D16 CT_D14 CT_D12 CT_D19 CT_D17 CT_FRAME_A CT_FRAME_B

CONN_AD26 CONN_AD27

CONN_AD28 CONN_AD29

CONN_AD30 CONN_AD31

CS_TDM1 = QuadFALCC CS_TDM2 = TSI

CT_C8_B

TDM_TO_PQ2_INT1
PQ2_CS_TDM1 TDM_GPL2 TDM_GPL1 CT_D6 CT_D4 CT_D2 CT_D0 CT_D5 CT_D3 CT_D1 CT_D10 CT_D8

GPL2 = DS GPL1= RW

PQ2_CS_TDM2 TDM_SPI_CS0
TDM_SIGCLK TDM_GPIO5 TDM_GPIO4 TDM_GPIO3 TDM_GPIO2 TDM_GPIO1 TDM_GPIO0
CO NN_DCO NN_D+5V 13 TDM_RESET 15 CO NN_DCO NN_D+3.3V 21 CO NN_DCO NN_D27 CO NN_DCO NN_D33 CO NN_D37 CO NN_D41 C ONN_DC ONN_D47 C ONN_DC ONN_D53 C ONN_DC ONN_D59 CONN_AD63

TDM_SPIMOSO TDM_SPIMOSI

TDM_SPICLK
TDM_TO_PQ2_INT2 TDM_TO_PQ2_INT3 TDM_TO_PQ2_INT4
HEADER32x2 HEADER32x2 TDM_GPIO5 TDM_GPIO4 TDM_GPIO3 TDM_GPIO2 TDM_GPIO1 TDM_GPIO0 TDM_GPIO[0:5]
CT_D0 - Receive from DSP (TDM0) CT_D1- Transmit to DSP (TDM0) CT_D2 - Receive from DSP (TDM1) CT_D3 - Transmit to DSP (TDM1) CT_D4 - Receive from MPC8260 CT_D5 - Transmit to MPC8260
CO NN_D0 CO NN_D1 CO NN_D2 CO NN_D3 CO NN_D4 CO NN_D5 CO NN_D6 CO NN_D7 CO NN_D8 CO NN_D9 C ONN_D10 C ONN_D11 C ONN_D12 C ONN_D13 C ONN_D14 C ONN_D15

CONN_AD[15:31]

CONN_AD15 CONN_AD16 CONN_AD17 CONN_AD18 CONN_AD19 CONN_AD20 CONN_AD21 CONN_AD22 CONN_AD23 CONN_AD24 CONN_AD25 CONN_AD26 CONN_AD27 CONN_AD28 CONN_AD29 CONN_AD30 CONN_AD31
CT_D0 CT_D1 CT_D2 CT_D3 CT_D4 CT_D5 CT_D6 CT_D7 CT_D8 CT_D9 CT_D10 CT_D11 CT_D12 CT_D13 CT_D14 CT_D15 CT_D16 CT_D17 CT_D18 CT_D19 CT_D[0:19]
Block TDM PTMC Connectors 3.1 Sheet
+5V +3.3V +5V R265 330ohm

F1 FUSE 10A + C137

1uF Tant 2 0V
D33 D31 C198 0.1uF 1SMC5.0AT3 330ohm MBR620CT VPQ2 +1.6v +3.3V C199 0.01uF

+ C136 100uF

Test_Wire_Bridge J20 J21

Test_Wire_Bridge

AC28 AD27 AF29 AF28 AG25 AH26 AJ27 AJ23 AG23 AJ22 AE20 AJ20 AG18 AG17 AF16 AH15 AJ14 AH13 AJ12 AE12 AF10 AG9 AH8 AG7 AE4 AG1 AD4 AD2
PQ2_RS232_RS_CTS PQ2_PD30 R59 R60 R61 PQ2_RS232_RXD

Parallel I/O

PQ2_PB18 PQ2_PB19 PQ2_PB20 PQ2_PB21 PQ2_PB22 PQ2_PB23 PQ2_PB24 PQ2_PB25 PQ2_PB26 PQ2_PB27 PQ2_PB28 PQ2_PB29 PQ2_PB30 PQ2_PB31
AD28 AD26 AD25 AE26 AH27 AG24 AH24 AJ24 AG22 AH21 AG20 AF19 AJ18 AJ17 AE14 AF13 AG12 AH11 AH16 AE15 AJ9 AE9 AJ7 AH6 AE3 AE2 AC5 AC4
ATM_RESET DSP_RESET TDM_RESET
UTP_RXADR4 UTP_RXADR3 UTP_RXADR2 UTP_RXADR1 UTP_RXADR0 UTP_RXADR[0:4]
UTP_TXADR4 UTP_TXADR3 UTP_TXADR2 UTP_TXADR1 UTP_TXADR0 1K 1K

UTP_TXADR[0:4]

Block PQ2 CPM 3.1 Sheet
Do not populate R62, R63, R64, R65

R432 10ohm

C45 0.1uF

PQ2_D[0:63] PQ2_QREQ

R442 10ohm
PQ2_D0 PQ2_D1 PQ2_D2 PQ2_D3 PQ2_D4 PQ2_D5 PQ2_D6 PQ2_D7 PQ2_D8 PQ2_D9 PQ2_D10 PQ2_D11 PQ2_D12 PQ2_D13 PQ2_D14 PQ2_D15 PQ2_D16 PQ2_D17 PQ2_D18 PQ2_D19 PQ2_D20 PQ2_D21 PQ2_D22 PQ2_D23 PQ2_D24 PQ2_D25 PQ2_D26 PQ2_D27 PQ2_D28 PQ2_D29 PQ2_D30 PQ2_D31
1 AA3 B9 AB3 B20 A18 A16 A13 E12 D9 A6 B5 A20 E17 B15 B13 A11 E9 B7 B4 D19 D17 D15 C13 B11 A8 A5 C5 C19 C17 C15 D13 C11 B8 A4 E6

U 1C PQ2_BUS_CLK

EVEN ODD

+ C48 C49

C47 0.1uF

+3.3V PQ2_CLK

AB2 XFC GNDSYN CLKIN AB1 AH4

PQ2_CLK

VCCSYN1 VCCSYN
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31

2.2nF 5%

1500pF 5%
TA TEA ART RY PSDVAL PQ2_BADD30 PQ2_BADD29 PQ2_BADD28 PQ2_BADD27 DSP_TO_PQ2_INT1 DSP_TO_PQ2_INT2 TDM_TO_PQ2_INT1 ATM_TO_PQ2_INT1 PQ2_ALE TBST
W5 F4 E2 V1 V2 BR BG ABB/IRQ2 DBG DBB/IRQ3
RRTT4 TT3 TT2 TT1 TT0 TSIZ0

1K 2 1K 2

TT0 TSIZ0
BR BG ABB DBG D BB TS AACK
VDC SCL GND SDA CLK CLK2 D15 D16 D14 D17 D13 D18 D12 D19 D11 D20 D10 D21 D9 D22 D8 D23 D7 D24 D6 D25 D5 D26 D4 D27 D3 D28 D2 D29 D1 D30 D0 D31

LA_MICTOR38

BR BG ABB DBG D BB TS AACK TT4 TT3 TT2 TT1 TT0 TSIZ0 TSIZ1 TSIZ2 TSIZ3

MODCK1 MODCK2

Processor
TSIZ1 TSIZ2 TSIZ3 TBST PQ2_BADD29 PQ2_BADD30 IRQ1 TA TEA ART RY
E3 F3 F2 G2 G3 G4 F1 C1 E4 D2 F5 D3 U2 U3 W1 C22 V5 E1 TS AACK TT4 TT3 TT2 TT1 TT0 TSIZ0 TSIZ1 TSIZ2 TSIZ3 TBST CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 GBL/IRQ1 TA TEA ARTRY
U4 Y3 R2 AB4 CPUBG/BADDR31/IRQ5 CPUBR CPU_DBG TRIS
PQ2_PORESET R50 0ohm PQ2_SRESET RRR22ohm W22ohm W22ohm W4 2

PSDVAL

D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63

Vss Vss Vss Vss

VssQ VssQ VssQ VssQ VssQ VssQ VssQ VssQ
F25 C29 E27 E28 F26 F27 F28 G25 D29 E29 F29 G28

R25 R27 R28 R29

22ohm 1 22ohm 1 22ohm 1 22ohm 1

R19 R22 R23 RR24 R302 2

22ohm PQ2_CS_FLASH PQ2_CS_FLASH 22ohm PQ2_CS_SDRAM1 PQ2_CS_SDRAM1 22ohm PQ2_CS_SDRAM2 PQ2_CS_SDRAM2 22ohm 1 PQ2_CS_ATM2 22ohm L SDCS 22ohm 1 PQ2_CS_TDM3 PQ2_CS_ATM PQ2_CS_ATM PQ2_CS_DSP PQ2_CS_DSP PQ2_CS_TDM1 PQ2_CS_TDM1 PQ2_CS_TDM2 PQ2_CS_TDM2 PQ2_BCTL1_N PQ2_BCTL1_N

PQ2_PSDDQM[0:7]

C25 E24 D24 C24 B26 A26 B25 A25
R30 R226 R32 R33 R34 R35 R36 R37
22ohm 1 22ohm 1 22ohm 1 22ohm 1 22ohm 1 22ohm 1 22ohm 1 22ohm 1
PQ2_PSDDQM0 PQ2_PSDDQM1 PQ2_PSDDQM2 PQ2_PSDDQM3 PQ2_PSDDQM4 PQ2_PSDDQM5 PQ2_PSDDQM6 PQ2_PSDDQM7

C41 0.01uF LD[0:31]

C42 0.1uF

C43 0.1uF

+ C40 10uF

R300 10K

Place caps close to SDRAM
PQ2_PSDA10 PQ2_PSDA10 PQ2_PSDWE_GPL1 PQ2_PSDWE_GPL1 PQ2_PSDRAS_GPL2 PQ2_PSDRAS_GPL2 PQ2_PSDCAS PQ2_PSDCAS

PQ2_UPMWAIT

PQ2_BCTL0_N TP1 TP2
E23 B24 A24 B23 A23 D22 A27

PQ2_GPL5 PQ2_BCTL0_N

R38 R39 10K 10K
+3.3V 2 R2 R41 10K R42 10K 1 10K

Y4 T1 D1

LA14/PAR LCL_DP0/C/BE0 LA15/FRAME/SMI LCL_DP1/C/BE1 LA16/TRDY LCL_DP2/C/BE2 LA17/IDY/CKSTP_OUT LCL_DP3/C/BE3 LA18/STOP LA19/DEVSEL LWR LA20/IDSEL LSDA10/LGPL0 LA21/PERR LSDWE/LGPL1 LA22/SERR LOE/LSDRAS/LGPL2 LA23/REQ0 LSDCAS/LGPL3 LA24/REQ1 LGTA/LUPWAIT/LGPL4/LPBS LA25/GNT0 LGPL5 LA26/GNT1 LA27/PCLK LWE0/LSDDQM0/LBS0 LA28/RST/CORE_SRESET LWE1/LSDDQM1/LBS1 LA29/INTA LWE2/LSDDQM2/LBS2 LA30/LOCK LWE3/LSDDQM3/LBS3 LA31 CS0 LCL_D/AD0 CS1 LCL_D/AD1 CS2 LCL_D/AD2 CS3 LCL_D/AD3 CS4 LCL_D/AD4 CS5 LCL_D/AD5 CS6 LCL_D/AD6 CS7 LCL_D/AD7 CS8 LCL_D/AD8 CS9 LCL_D/AD9 CS10/BCTL1/DBG_DIS LCL_D/AD10 CS11/AP0 LCL_D/AD11 LCL_D/AD12 PWE0/PSDDQM0/PBS0 LCL_D/AD13 PWE1/PSDDQM1/PBS1 LCL_D/AD14 PWE2/PSDDQM2/PBS2 LCL_D/AD15 PWE3/PSDDQM3/PBS3 LCL_D/AD16 PWE4/PSDDQM4/PBS4 LCL_D/AD17 PWE5/PSDDQM5/PBS5 LCL_D/AD18 PWE6/PSDDQM6/PBS6 LCL_D/AD19 PWE7/PSDDQM7/PBS7 LCL_D/AD20 LCL_D/AD21 PSDA10/PGPL0 LCL_D/AD22 PSDWE/PGPL1 LCL_D/AD23 POE/PSDRAS/PGPL2 LCL_D/AD24 PSDCAS/PGPL3 LCL_D/AD25 PGTA/PUPMWAIT/PGPL4/PPBS LCL_D/AD26 PSDAMUX/PGPL5 LCL_D/AD27 BCTL0 LCL_D/AD28 LCL_D/AD29 THERM0 LCL_D/AD30 THERM1 LCL_D/AD31 SPARE4 SPARE6 CLKIN2 L2_HIT/IRQ4 PCI_MODE. IRQ0/NMI_OUT IRQ7/INT_OUT/APE
LD0 H29 LD1 J29 LD2 J28 LD3 J27 LD4 J26 LD5 J25 LD6 K25 LD7 L29 LD8 L27 LD9 L26 LD10 L25 LD11 M29 LD12 M28 LD13 M27 LD14 M26 LD15 N29 LD16 T25 LD17 U27 LD18 U26 LD19 U25 LD20 V29 LD21 V28 LD22 V27 LD23 V26 LD24 W27 LD25 W26 LD26 W25 LD27 Y29 LD28 Y28 LD29 Y25 LD30 AA29 LD31 AA28

AA1 AG4 U5 V4 AE11 AF25

Thermal Resistance Measurement

Memory

Block PQ2 Local & Mem controller 3.1 Sheet

VPQ2 U 1A

+ C9 0.1uF 10uF C 10 0.1uF C 11 0.1uF C 12 0.1uF C 13 0.1uF C 14 0.1uF C 15 0.1uF C 16 0.1uF C 17 0.1uF C 18 0.1uF

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