Figure 1-13

Jumpers and Connectors (Top View)

Table 1-4

CPU Voltage (S1) Settings 2.35V

Off Off On Off

CPU Voltage Switch 1 Switch 2 Switch 3 Switch 4 Table 1-5 CPU Speed Switch 1 Switch 2 Switch 3 Switch 4 Table 1-6

Off On Off Off

Off Off Off Off

Off Off Off On

CPU Speed (SW3) Settings 120MHz

Off On Off On

133MHz

On Off Off On

150MHz

Off On On On

Multi-Function Switch (SW2) Settings Switch ON
88-key (Japan keyboard) Bypass No
84/85-key (U.S. keyboard) Check Yes
Keyboard Type (Default OFF) Keyboard Type Password Generic boot-up screen show on screen in POST

Table 1-7

Hardware Configuration and Specification

Memory Address Map

Memory Address Map Definition
640 KB memory 128 KB video RAM Video BIOS 128 KB system BIOS Base memory Reserved for graphics display buffer Video BIOS System BIOS System BIOS Extended memory 256 KB system ROM Onboard Memory SIMM memory Duplicate of code assignment at 0E0000-0FFFFF

Address Range

000000 - 09FFFF 0A0000 - 0BFFFF 0C0000 - 0CBFFF 0E0000 - 0EFFFF 0F0000 - 0FFFFF 10000 - 7FFFF 80000 - 27FFF FE0000 - FFFFFF

Function

Table 1-8 Priority

Interrupt Channel Map

Interrupt Channel Map Interrupt Number
SMI NMI IRQ 0 IRQ 1 IRQ 2 IRQ 8 IRQ 9 IRQ 10 IRQ 11 IRQ 12 IRQ 13 IRQ 14 IRQ 15 IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7

Interrupt Source

Power management unit Parity error detected, I/O channel error Interval timer, counter 0 output Keyboard Interrupt from controller 2 (cascade) Real-time clock Cascaded to INT 0AH (IRQ 2) Audio (option) / PCMCIA Audio (option) / PCMCIA PS/2 mouse INT from coprocessor Hard disk controller CD-ROM controller Serial communication port 2 Serial communication port 1 Parallel port (option) / Audio Diskette controller Parallel port (option)
A PCMCIA card can use IRQ 3, 4, 5, 7, 9 and 11 as long as it does not conflict with the interrupt address of any other device.

Battery Low Voltage Battery Low 1 level (V) Battery Low 2 level (V) Battery Low 3 level (V) Charge Current Fast charge (charge when system is still operative, A) Quick charge (charge while system is not operative, A) Charging Protection Safety timer for Fast Charge mode while notebook is operating (minute) Safety timer for Quick Charge mode while notebook is not operating (minute) Maximum temperature protection (C) Maximum voltage protection (V) Over voltage protection

1.4.23

DC-DC Converter
DC-DC converter generates multiple DC voltage level for whole system unit use. Table 1-31 DC-DC Converter Specifications
Vendor & model name Input voltage (Vdc) Output Rating Current (w/ load, A) Voltage ripple (max., mV) Voltage noise (max., mV) OVP (Over Voltage Protection, V) Ambit T62.061.C.00 8~21 5V 0~3.100 6.5~8.2 3.3V 0~3.100 4.5~6.2
2.9V (2.35/2.45/2.9/3.1V) 0~3.100 3.3~5.0 for 2.9/3.1/2.35V/2.45V

+12V 0~0.200 14~20

+6V 0~0.500 7~9

5VSB 0.100 -

1.4.24

DC-AC Inverter

DC-AC inverter is used to generate very high AC voltage, then supply to LCD CCFT backlight use, and is also responsible for the control of LCD brightness. Avoid touching the DC-AC inverter area while the system unit is turned on. Table 1-32 DC-AC Inverter Specifications Item
Vendor & model name Input voltage (V) Input current (mA) Output voltage (Vrms, no load) Output voltage frequency (kHz) Output current (mArms) 7.3 (min.) 1000 (min.) 25 (min.) 1.5~5.5 (min.)
Ambit T62.066.C.00 / Ambit T62.064.C.(typ.) 42 (typ.) 2.0~6.0 (typ.) 20 (max.) 550 (max.) 1500 (max.) 60 (max.) 2.5~6.5 (max.)

1.4.25

Table 1-33
LCD Specifications Item Specification
HITACHI LMG9900ZWCC 11.3 STN SVGA (800x600) -30 (typ.)
Vendor & model name Mechanical Specifications LCD display area (diagonal, inch) Display technology Resolution Supported colors Optical Specification Contrast ratio Brightness (cd/m ) Brightness control Contrast control Electrical Specification Supply voltage for LCD display Supply voltage for LCD backlight (Vrms)
TORiSAN LM-FH53-22NAW 11.3 STN VGA (800x600) -30 (typ.) 70 (typ.) keyboard hotkey using keyboard hotkey 3.3 (typ.) 590 (typ.)

to 75% after the AC power is off-line.
2. If the original brightness is below 75%, the brightness maintains the same level even if the AC power is

off-line.

3. If the brightness is already changed by the hotkey under DC power, it will not be changed after the AC

power is plugged in.

4. If the brightness is not changed by the hotkey under DC power, the brightness will be changed back to
the old setting the previous brightness parameter under AC power.
5. If the previous brightness parameter does not exist, the brightness will not be changed in process 4.
Drivers, Applications and Utilities
The notebook comes preloaded with the following software:
Windows 952 System utilities and application software3 Sleeper manager utility Touchpad driver Display drivers Audio drivers PC Card slot drivers and applications
Other third-party application software Table 1-40 Location of Drivers in the System Utility CD Device Category
Sound, video and game controllers Mouse Display adapters PCMCIA Audio Mouse Video Zoomed Video Port

Location

ENGLISH\WIN95\AUDIO\ ENGLISH\WIN95\MOUSE\ ENGLISH\WIN95\VGA\ English\Win95\PCMCIA\
To re-install applications under Windows 95, click on Start, then Run. Based on the location of the application, run the setup program to install the application. The following table lists the applications and their locations: Table 1-41 Location of Applications in the System Utility CD Name
Sleep Manager Y-Station SafeOFF
0V Suspend utility Audio application Protect if user accidentally press the power switch
ENGLISH\WIN95\SLEEPMGR\ ENGLISH\WIN95\Ystation ENGLISH\WIN95\SAFEOFF
Drivers for Windows 3.x and Windows NT are also found in the System Utility CD if you should need them.
2 In some areas, a different operating system may be pre-loaded instead of Windows 95. 3 The system utilities and application software list may vary.

System Block Diagram

Figure 1-15

Table 1-42

Environmental Requirements
Environmental Requirements Item Specification
+5C ~ +35C -20C ~ +60C 20% ~ 80% 20% ~ 80% 5 - 25.6Hz, 0.38mm; 25.6 - 250Hz, 0.5G > 1 minute / octave 2 / axis (X,Y,Z) 5 - 27.1Hz, 0.6G; 27.1 - 50Hz, 0.41mm; 50~500Hz, 2G > 2 minutes / octave 4 / axis (X,Y,Z) 40G peak, 111ms, half-sine 50G peak, 111ms, half-sine 10,000 feet 40,000 feet 8kV (no error) 12.5kV (no restart error) 15kV (no damage) 4kV (no error) 6kV (no restart error) 8kV (no damage)

PCI interface : (42) PCICLK 89 I PCI Clock. This is the PCI Bus interface CLK input signal. This clock frequency should not be more than 33 Mhz. It is used by internal PCI interface. PCI Address and Data bus. These lines are connected to PCI Bus AD[31:0]. These lines contain Address and Data bus information for PCI transaction.

AD[31:0]

91-98,29, 2025, 27, 28, 3037 99,10, 17,29

CBEJ[3:0]

PCI Bus Command and Byte enable. These are PCI bus commands at address phase and byte enable signals at data phase. Since M7101 is PCI slave only, it will not drive CBEJ[3:0]. They are inputs only. Cycle FRAME for PCI bus. This signal indicates the beginning and duration of a PCI access. Device select. When M7101 has decoded the address as its own cycle, it will assert DEVSELJ. Initiator Device Ready. This signal indicates the initiator is ready to complete the current data phase of transaction. Target Device Ready. This signal indicates that M7101 is ready to complete the current data phase of transaction. Parity bit of PCI bus. It is the even parity bit across AD[31:0] and CBEJ[3:0]
FRAMEJ DEVSELJ IRDYJ TRDYJ PAR

I O I O O

CLK & RESET interface : (3) CLK32 PWGD I I 32KHz clock. This is 32KHz clock input, used by internal timers and relative PMU circuit. POWER GOOD. When PWGD low means the VDD5&VDD3 power supply is turned off. When high, it means the power is available and stable. This signal will be sent to suspend circuit to disable the suspend protected circuit when PWGD is high. It will also be sent to reset the circuit supplied by VDD5&VDD3 power. SUSPEND RESET. SUSPEND circuit RESET signal. When low, the suspend circuit will be reset. The suspend circuit is supplied by the VDDS power.

SUSRSTJ

PMU Input event interface : (11) ACPWR 49 I AC power. When plugged in or out, the AC adapter status will be reflected at this signal. Both low to high or high to low transition will generate SMIJ. An internal debounce is built-in to avoid the input bouncing problem. Both rising & falling will be detected. This is a smith-trigger input signal.
M7101 Pin Descriptions (Continued)
PMU Input event interface : (11) LBJ 47 I Low Battery. First stage battery low indication. If low is detected and Low Battery Timer is timeout, then battery low 1 SMIJ will be generated every programmed interval time until battery low 2 SMIJ is asserted or LB timer is reset. No debounce circuit is built in. Only low level is detected. Low Low Battery. Second stage battery low indication. If low is detected and Low Low Battery Timer is timeout, then battery low 2 SMIJ will be generated every programmed interval time until both LB and LLB timer are reset. No debounce circuit is built in. Only low level is detected. LLBJ LBJ H H H L Normal condition Low Battery SMIJ will generate every interval. Low Low Battery SMIJ will not happen. L X Low Battery SMIJ will not happen. Low Low Battery SMIJ will generate every interval. COVSW /SUSTATI/O Cover switch (when 0F8h, D7=1). Cover switch status input. When COVER is closed, the cover switch is also pressed and a COVSW SMIJ will be generated. When COVER is opened, the cover switch will be released, a COVSW SMIJ will be generated, too. Moreover, both close and open will generate a doze-to-on or sleep-to-on SMIJ to wake the system up if the system is in Doze or Sleep state, respectively. Debounce circuit is built in. It detects both rising and falling edge. Suspend status 2 (when 0F8h, D7=0, it is default value). It is suspend status 2 signal during 0/5V suspend system. It will be low in normal. When writing to port 0FAh, it will go high to close the charger. Any event of RI, RTC or HOTKEYJ will wake it up, and let this pin go low again. RI 42 I Modem Ring. Modem ring input. A programmable ring counter will count the ring pulse. If the ring pulse reaches the counters setting value, a doze-to-on SMIJ or sleep-to-on SMIJ will be generated to wakeup the system. If the system is already at on state, there will be no new event or action. No debounce circuit is built in. It only detects rising edge. RTC Alarm wakeup. A low to high transition of this signal will generate a doze-to-on or sleep-to-on SMIJ to wakeup the system. If the system is already at on state, there will be no new event or action. No debounce circuit is built in. It only detects rising edge. Floppy DMA Request. A low to high transition of this signal will generate a doze-to-on or sleep-to-on SMIJ to wakeup the system. If the system is at on state already, there will be no new event or action. No debounce circuit is built in. It only detects rising edge.

GPIOA4 /GPIORBJ

GPIOA3 /CONTRAST2 /SLOWDOW N GPIOA2 /CONTRAST1 GPIOA1 /GPIOWA
General purpose I/O interface(24) General purpose I/O group A GPIOA0 /GPIORAJ (64) O External General Purpose I/O A read. When SPKCTL is pull low 4.7K, the GPIOA0 will become GPIORAJ. External General purpose A Read control pulse, When Read index 0E1h with a byte or a word. A 74245 OEJ pulse will be generated at this pin. The 74245 output should be connected to PCI AD[23:16] if a byte command. If a word command, two 74245s will be used and outputs are connected to PCI AD[31:16]. When read index 0E1h, M7101 will send DEVSELJ, TRDYJ but float the AD[31:0] because the data will be sent by 74245. The write action has no meaning and nothing will be done.
General purpose I/O interface(24) General purpose I/O group B GPIOB[7 :0] 88,85, 87,86, 84-81 I/O General Purpose I/O group B. These signals can be programmed to be input or output. Offset 0DBh D[7:0] control the I/O attribute. When programmed to be output, Offset 0DAh D[7:0] will set to corresponding signal. When programmed to be input, the signal can be read from the Offset 0DAh D[7:0] corresponding bits. Offset 0DBh D[n] = 0 : GPIOB[n]=input GPIOB[n] value can be read from Offset 0DAh D[n] 1 : GPIOB[n]=Output Offset 0DAh D[n] value will send to GPIOB[n] "n" value is from 7 to 0 GPIOB7 /STPCLKJ (88) O Stop clock signal. When DISPLAY is pulled low or offset 0F6h D14=1, this pin will become stop clock signal output. It may be connected to CPU to force it into STPGNT or STPCLK mode. Write port 0EFh will assert this function. APM State. When DISPLAY is pulled low, this pin will be APM state. It may be connected to clock generator to slow down clock. It is asserted when HALT or STPGNT cycle is detected and recovers when IN_SMIJ, IN_INTR or IN_INIT is asserted. System can use this signal to know the APM status, and slow down the speed or turn off some peripheral power to decrease the power consumption. This signal will be synchronized with PCICLKs rising or falling edge. INIT Output. When DISPLAY is pulled low, this pin will be INIT output. It will be disabled when IN_INIT is detected and AMSTATJ is asserted. Then, it will be sent as a 16 PCICLK wide pulse after AMSTATJ is deasserted. Otherwise, it will be the same with IN_INIT. It may be connected to CPU. INTR Output. When DISPLAY is pulled low, this pin will become INTR output. It may be connected to CPU. When AMSTATJ is asserted, IN_INTR will be masked until AMSTATJ is de-asserted.

REQ 169 SERR 200
PCI Interface Control Terminals TRDY 196 I/O Target ready. Indicates the PCI 1131 ability to complete the current data phase of the transaction. TRDY is used in conjunction with IRDY. A data phase is completed on any clock where both TRDY I/O are sampled asserted. During a read, TRDY indicates that valid data is present on AD31-0. During a write, TRDY indicates the PCI1131 is prepared to accept data. Wait cycles are inserted until both TIRDY and TRDY are asserted together. This signal is an output when the PCI 1131 is the PCI target. and an input when it is the PCI bus master. Interrupt Request 10 and 12. This terminal is software configurable and is used by the PCI 1131 to support the PCI Clock Run protocol. When configured as CLKRUN, by setting bit 0 in the System Control Register at offset 80h, this terminal is an open drain output. To select between IRQ10 and IRQ12 as the output use bit 7 of Register 80h.
IRQ10/CLKRUN 159 IRQ12/CLKRUN 161
TERMINAL Name Slot Slot A+ B
A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A67

I/O TYPE

FUNCTION
1 6-bit PC Card Address and Data (Slots A and B) O PC Card Address. 16-bit PC Card address lines. A25 is the most significant bit.
+ Terminal name is preceded with A_. As an example, the full name for terminal 121 is A_A25. Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.
D15 D14 D13 D12 D11 D10 D9 D8 D6 D5 D4 D3 D2 D1 D76
1 6-bit PC Card Address and Data (Slots A and B) I/O PC Card Data. 16-bit PC Card data lines. D15 is the most significant bit.
1 6-bit PC Card Interface Control Signals (Slots A and B) CD1 CD74 I PC Card Detect 1 and Card Detect 2. CD1 and CD2 are connected to ground internally on the PC Card. When a PC Card is inserted into a socket, these signals are pulled low. The signal status is available by reading the Interface Status Register Battery Voltage Detect 1. Generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See the Card Status Change Interrupt Configuration Register for enable bits (Section 8.6). See the Card Status Change Register and the Interface Status Register for the status bits for this signal. Status Change. STSCHG is used to alert the system to a change in the READY, Write Protect, or Battery Voltage Dead condition of a 16-bit I/O PC Card. Ring Indicate. RI is used by 1 6-bit modem cards to indicate ring detection. + Terminal name is preceded with A_. As an example, the full name for terminal 121 is A_A25. Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.

CBLOCK 107 42

CardBus PC Card Interface Control Signals (Slots A and B) I/O CardBus Lock. This is an optional signal used to lock a particular address, ensuring a bus initiator exclusive access. NOTE: This signal is not supported on the PCI 1131. CardBus Device Select. When actively driven, this signal indicates that the PCI 1131 has decoded its address as the target of the current access. As an input, CDEVSEL indicates whether any device on the bus has been selected. CDEVSEL CSTSCHG I/O I CardBus Stop. This signal indicates the current target is requesting the initiator to stop the current transaction. CardBus Status Change. CSTSCHG is used to alert the system to a change in the READY, WP, or BVD condition of the l/O CardBus PC Card. CardBus Audio. This signal is an optional digital input signal from a PC Card to the system's speaker. CardBus cards support two types of audio: single amplitude, binary waveform, and/or Pulse Width Modulation (PWM) encoded signal. The PCI1131 supports the Binary Audio Mode, and may output a binary audio signal from the PC Card to the SPKROUT signal. CIRDY I/O CardBus Initiator Ready. This signal indicates that the PCI1131 is initiating the bus initiator ability to complete a current data phase of the transaction. It is used in conjunction with CTRDY. When both of these signals are sampled asserted, a data phase is completed on any clock. During a write, CIRDY indicates that valid data is present on CAD31-0, and during a read, it indicates the PCI 1131, as an initiator, is prepared to accept the data. Wait cycles are inserted until both CTRDY and CFRDY are both low (asserted). CardBusTargetReady. This signal indicates that the PCI 1131, as a selected targets has the ability to complete a current data phase of the transaction. It is used in conjunction with CIRDY. When both of these signals are sampled asserted, a data phase is completed on any clock. During a read, CTRDY indicates that valid data is present on CAD31-0, and during a write, it indicates the PCI 1131, as a target, is prepared to accept the data. Wait cycles are inserted until both CIRDY and CTRDY are both low (asserted). CardBus Cycle Frame. This signal is driven by the PCI 1131 when it is acting as an initiator to indicate the beginning and duration of a transaction. CFRAME is asserted to indicated a bus transaction is beginning, and while it is asserted, data transfer is continuous. When CFRAME is high (deasserted), the transaction is in its final data phase.

CDEVSEL 111 47

CAUDIO 137 71

CTRDY 114

CFRAME 116

CREQ CGNT 61 46

CardBus PC Card Interface Control Signals (Slots A and B) I O CardBus Request. This signal ir1dicates to the arbiter that the CardBus PC Card desires use the CardBus bus. CardBus Grant. This signal is driven by the PCI 1131 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has completed CardBus Parity Error. This signal reports errors during all CardBus PC Card transactions except during special cycles. This signal is sustained in a high-impedance state and must be driven active by the agent receiving data, two clocks following the data, when a data parity error is detected. This signal must be driven active for a minimum duration is one clock for each data phase. CPERR must be driven high for one clock before it is returned to the high-impedance state. An agent cannot report a CPERR until it has claimed the access by asserting CDSVSEL and completed a data phase. CardBus System Error. This signal reports address parity error, data errors on the Special Cycle command, or any other system error where the result could be catastrophic, such that the CardBus card may no longer operate correctly. CSERR is open drain and is actively driven for a single CardBus PC Card clock by the agent reporting the error. The assertion of this signal is synchronous to the Cock and meets the setup and hold times of all bussed signals. Restoring of the CSERR to the deasserted states is accomplished by a weak pull-up which is provided by the system designer. This pull-up may take two to three clock periods to fully restore ~R The PCI1131 reports CSERR to the operating system anytime it is sampled low (asserted) CardBus Voltage Sense 1 and Voltage Sense 2. CVS1 and CVS2, are used in conjunction with each other, along with CCD1 and CCD2, to determine the operating voltage of the CardBus PC Card. CardBus Interrupt. This signal is asserted low by a CardBus PC Card to request interrupt servicing from the host.

86, 84

44, 41

/MTR1 (PMM Mode)

92-89, 87-84 81
/RD /RDATA (Normal Mode) /RDATA (PPM Mode)
FDD Read Data. This pin supports an additional Read Data signal in PPM Mode when PNF = 0.

/RI1 /RI2

68, 60 I
UARTs Ring Indicator. When low, this indicates that a telephone ring signal has been received by the modem. The /RI signal is a modem status input whose condition is tested by the CPU by reading bit 6 (RI) of the Modem Status Register (MSR) for the appropriate serial channel. Bit 6 is the complement of the RI signal. Bit 2 ( TERI) of the MSR indicates whether the RI input has changed from low to high since the previous reading of the MSR. NOTE: When the TERI bit of the MSR is set and Modem Status interrupts are enabled, an interrupt is generated.

/RTS1 /RTS2

UARTs Request to Send. When low, this output indicates to the modem or data set that the UART is ready to exchange data. The RTS signal can be set to an active low by programming bit 1 (RTS) of the Modem Control Register to a high level. A Master Reset operation sets this signal to its inactive (high) state. Loop mode operation holds this signal to its inactive state. UARTs Serial Input. This input receives composite serial data from the communications link (peripheral device, modem, or data set). System interrupt 1, 2, and 3. This input can be routed to one of the following output pins: IRQ3-IRQ7, IRQ9-IRQ12. SIRQ12 and SIRQ13 can be also routed to IRQ15. Software configuration determines to which output pin the input pin is routed to. SIRQ1 is multiplexed with IRQ15, SRIQ12 is multiplexed with DRATE1/MSEN1/CS0, and SIRQ3 is multiplexed with DRV2/PNF/DR23.
SIN1 SIN2 SIRQ1 SIRQ2 SIRQ4

73, 65 58, 49, 47

Parallel Port Select. This input is set high by the printer when it is selected. This pin has a nominal 25 K pull-down resistor attached to it. Parallel Port Select Input. When this signal is low, it selects the printer. This pin is in a tristate condition 10 ns after a 0 is loaded into the corresponding Control Register bit. The system should pull this pin high using a 4.7 K resistor. UARTs Serial Output. This output sends composite serial data to the communications link (peripheral device, modem, or data set). The SOUT signal is set to a marking state (logic 1) after a Master Reset operation. Parallel Port Data Strobe. This output indicates to the printer that a valid data is available at the printer port. This pin is in a tristate condition 10 ns after a 0 is loaded into the corresponding Control Register bit. The system should pull high using a 4.7 K. FDC Step. This output signal issues pulses to the disk drive at a software programmable rate to move the head during a seek operation. FDC Step. This pin gives an additional step signal in PPM Mode when PNF = 0.

2.10.1

Figure 2-19

T62.061.C Pin Diagram

2.10.2

Table 2-19

Pin Assignment
T62.061.C Pin Descriptions Pin No.
1,14,15 16,17 GND DC-IN P.G.Vcc +5.0V GND +6V +12V GND +3.3V 5VSB ON/OFF P.G. Vcpu GND

2.10.3

Input:

Specifications

DC BATT_IN:7V-8V DC
Output: +5V +12V :Load :Load :0~2A :0~0.12A
The other conditions same as 2.2.1
Input: DCBATT_IN :8V-21V DC
Output: +5V: Load : 0A-3.2A Ripple: Noise: OVP: 50mV (max) 100mV (max) 6.5-8.2V Regulation: +5%, -5%
Short-circuit protection Fuse protection *Ripple(max)=75mV when regulate in IDLE mode Regulation: +5%, -5%
+3.3V: Load : 0A-3.3A Ripple: Noise: OVP: 50mV (max) 100mV (max) 4.5-6.2V
Short-circuit protection Fuse protection *Ripple(max)=75mV when regulate in IDLE mode Regulation: +5%, -4%
+2.9V:(3.1V) Load : 0A-3.0A Ripple: Noise: OVP: 50mA (max) 100mV (max) 3.3-5.0V
Short-circuit protection Fuse protection *Ripple(max)=75mV when regulate in IDLE mode
+2.35V:(2.45V) Load Ripple: Noise: OVP:

: 0A-4.2A

Regulation: +5%, -4%
50mA (max) 100mV (max) 3.3-5.0V
Short-circuit protection Fuse protection *Ripple(max)=75mV when regulate in IDLE mode : Load : 0A-0.15A 100mV (max) 200mV (max) 14-20V Regulation: +/-5%

+12V

Ripple: Noise: OVP:
*The +12V max load condition is available only when the +5V output load is greater than 0.5A. : Load : 0A~0.1A Ripple: Noise: OVP: 300mV (max) 500mV (max) 7-9 V Regulation: 5.5V~7.5V
*The +6V max load condition is available only when the +5V output load is greater than 0.5A. : 5mA Regulation:+/-10% Noise: 250mV(max)

5VSB:Load

Ripple: 75mV(max)
P.G. :Active high within 100ms to 500ms after systems +5V, 3.3V and Vcpu are all in regulation. Driving capability:12uA(source) 200uA(sink)

2.10.4

Control switch can switch Vcpu output voltage to 2.35V2.45V2.9 or 3.1V.

VCPU Control:

ON/OFF: A logic low will turn off +5V,+3.3V, 2.35V/2.45V/2.9V/3.1V,+12V and +6V main o/p. The DC/DC converter draws about 30uA when the notebook computer is in shutdown mode.

Figure 4-15

Removing the Bottom Screws
Remove three screws near the display hinge screw holes and one screw near the PC card slots. Before you detached the top cover make sure that you unplug the cable for the CN19 (touch pad). Unsnap the top cover from the base assembly and set aside.

Figure 4-16

Detaching the Top Cover from the Base Assembly
Removing the Base Assembly
Remove four screws that secure the inside frame assembly to the base assembly. Then detach the inside frame assembly from the base assembly.

Figure 4-17

Detaching the Base Assembly

Removing the Motherboard

Remove the fan by (3) removing the sticker and (4) unplugging the fan cable (CN9).

Figure 4-18

Removing the Fan When installing the fan, the fan hole should face the rear of the unit to draw thermal air out of the system.
Remove the audio board by (1) unplugging the audio board connector (CN5), and then (2) pulling up the audio board.

Figure 4-19

Removing the Audio Board
Unplug the battery connector board cable (CN18).

Figure 4-20 4.

Removing the Battery Connector Board
Unplug the (a) LCD cover switch cable (CN8) and (b) speaker cables (CN7 and CN10).

CN7 CN8 CN10

Figure 4-21
Unplugging the LCD Cover Switch and Speaker Cables
Turn the unit over and remove the two screws that secure the Charger Board to the inside of the assembly frame. Then remove the board.

Figure 4-22 6.

Removing the Charger Board
Remove seven screws that secure the motherboard to the inside assembly frame. Then release the latch and pull up the motherboard to detach it from the inside assembly frame.

Figure 4-23

Detaching the Motherboard from the Inside Assembly Frame
Disassembling the Motherboard
REMOVING THE PC CARD SLOT UNIT
The PC Card Connector Module is normally part of the motherboard spare part. The following removal procedure is for reference only.

Figure 4-24

Removing the PC Card Slot Unit
REMOVING THE KEYBOARD CONNECTION BOARD
Pull up the keyboard connection board to remove it.

Figure 4-25 4-20

Removing the Keyboard Connection Board Service Guide

Removing the Touchpad

Follow these steps to remove the touchpad

$BWE# $GWE#

S32K32-07

$CPUD[0.63]
3.3V R0R3 $CPUA5 $CPUA6 $CPUA7 $CPUA8 $CPUA9 $CPUA10 $CPUA11 $CPUA12 $CPUA17 $CPUA13 $CPUA14 $CPUA16 $CPUA21 U50 VCC A14 D7 A13 D6 A0 A1 D5 D4 A2 D3 A3 D2 A4 A5 D1 A6 D0 A7 A12 A8 CS1* A9 OE* A11 WE* A10 GND S32K8-$TAG[0.7] 2

3.3V 1

R10KR3 CS2
$TAG7 $TAG6 $TAG5 $TAG4 $TAG3 $TAG2 $TAG1 $TAG0 $AMSTATE# $TWE# 2
R100KR3 $C_MODE MODIFICATION: $C_MODE PULLED UP TO 100K PULL UP: PENTIUM BURST MODE PULL LOW: CYRIX LINEAR BURST MODE
R100 $H_ZZ DUMMY-R3 ACER 3.3V 1 10KR3 Size A3 Date: Document Number 96149 February 12, 1997 Sheet 5 of 25 RFTNC Title 370P/J (256KB CACHE) REV SC TAIPEI TAIWAN R.O.C $AMSTATE# $AMSTATE# 8
3.3V 3.3V CN3.3V C271 SC4D7U16V6ZY C268 SC4D7U16V6ZY 3 MA[2.11] 3 MD[0.63] MA[2.11] MD[0.63] 3.3V C225 SCD1U C224 SCD1U C234 SCD1U C244 SCD1U MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 CAS#0 CAS#1 CNMD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 CAS#0 CAS#MAAMAA1 MAA0 MAA1 MA2 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD60 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 CAS#4 CAS#5 MA3 MA4 MA5 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MA6 MA8 MA9 MA10 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MA7 MA11 CAS#2 CAS#3 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MDMWE#RAS#RAS#3 MWE#0 C261 SC4D7U16V6ZY C186 SCD1U C107 SCD1U C241 SCD1U 3 MABMAB1 MAB0 MAB1 MA2 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD60 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 CAS#4 CAS#5 MA3 MA4 MA5 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47

CX25 SCD1U

CX26 SCD1U

CX27 SCD1U

CX28 SCD1U

## ADD NEW COMPONENT

MWE#RAS#RAS#1
MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MA6 MA8 MA9 MA10 CAS#2 CAS#3 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

141 143

146 SDIMM144
MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MA7 MA11
CAS#6 CAS#7 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63

C260 SC4D7U16V6ZY

C257 SCD1U

C270 SCD1U

C272 SCD1U

C130 SC10U16V

C259 SCD1U

C264 SCD1U

C269 SCD1U

3 CAS#[0.7]

CAS#[0.7] ACER TAIPEI TAIWAN R.O.C Title 370P/J (DIMM SOCKET) Size A3 Date: Document Number 96149 February 12, 1997 Sheet 6 of 25 REV SC

3.3V 1 R180 22KR3.3V 1 SW4 KHS5 2
3.3V 1 R179 22KRR105 10KR3.3V 1 R106 10KR3 FS1 FS0 $BF1 $BF0 FOR CY2263 S0 S1 CLOCK 50MHZ 60MHZ 66.6MHZ 33MHZ $BF0 $BF0 1.5X 2X 3X 2.5X +5V +5V KBD14M VCC D CLK GND C L 1 Q P R 4 Q U47A R1 33R7 SSHCTCLK7M VCC D CLK GND C L +5V Q P R +5V +5V Q U47B R1 33RSSHCT## CLK4M 8
3.3V L2 MLB321611 C87 SC10U16V C101 SC100P C99 SCD1U C85 SCD1U C86 SCD1U C100 SCD1U
+5V INVAPMSEL7 U41D 8 SSHCT04 SC10P C84 SC10P FSU34A 3 3.3V SSLVC125 FS4 U34B 1 SSLVCRX8 22KR$AMSTATE $AMSTATE
1 R59 0R3 C2 X2 XTAL4P-14.318MHZ U39 VDD VDD VDD VDD VDD XIN XOUT CPUEN1 CPU-PCIEN SEL S1 S0 VSS VSS VSS VSS VSS CY2263 R92 CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 PCI0 PCI1 PCI2 PCI3 PCI4 EPCI USB-CLK IOCLK REF0 REFR33R3 R87 R61 R33R3 R33R1 33R3 RRX9 22KR3.3V 1 33R3 RC105 SC47P R96 33R33R3 RKBD14M $G14.318M $ALA14M 2 33R3 R33R3 R$P24M $AUDIO14M 2 R60 33R33R33R3 $21CLK $P21CLK $P23CLK $VGACLK $CARDCLK $P7101CLK 33R1 33R3 R$CPUCLK $L2CLK1 $L2CLK5 5

1 2MR5

2 +5V U19C SSHC4 U19A 2 SSHC14

X3 CAN4

C223 SCD1U
## REMOVE R65,R178,R182,R181,R66 PAD
+5V U19D 8 SSHC14 +5V U19B 4 SSHC14 32K2 32K2 3,17 ACER TAIPEI TAIWAN R.O.C Title Size A3 Date: 370P/J (CY2263 CLOCK GENERATOR) Document Number 96149 February 12, 1997 REV SC Sheet 7 of 25 32K1 32K1 8
+5V $7101STP# +5V LED# 16 STANDBY# TH_DQ_VGA PWR_SW# TH_COM EXCACD# TH_DQ_VGA 23 PWR_SW# 2 TH_COM 24 EXCACD# 9,13 XSA17 9,13 XSASA16 U3.3V 4 $23STP# 9 10
+5V U26B 7 SSHC$CPUSMI# U43C 9
3.3V U13C SOLCX125M +5V DISPLED# LLED# U26C RSSHC125 +5V 1 470RPLED# CLOSE TO U34 R2 47R3 SSHCT08 $STPCLK# 1
LLED# VR_U/D# BLVR# TPX1 TP-1 TPX2 TP-19
7 $P7101CLK 6 V V D D D D 3 3
## REMOVE U15 PAD, CIRUIT MODIFY P C I C L K
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD[0.31] 92 91

S M I J

V VV D DD D DD 5
1 V V V V V S S S S S S S S S S G P I O C 7 ( V C S J )
G P I O C 6 ( S E T U P ) GG P P I I OO C C ( ( E E X J T E S C WT ) J ) G P I O C 3 ( D O C K J ) G P I O C 2 G P I O C 1 G P I O C 0
AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 GPIOWF1
U36 D0 D1 D2 D3 D4 D5 D6 D7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

ID_CLK FLASH_ON 3_MODE TH_CLK TH_RST# DISABLELED ENAUDIO

RGBGND

VGAPWR C57 SC10U16V C55 SCD1U C56 SC1000P50V3KX LCD_3/5V# ENAVDD S0

LCDPWR SVMAD[0.15]

VRAMVCC VGAPWR 3.3V 3.3V Close 105(MGNDC),108(MVCCC) PIN G2 GAP-CLOSE C211 SC1U16V5JX C226 SC10U16V C221 SC1U16V5JX VMAD0 VMAD1 VMAD2 VMAD3 VMAD4 VMAD5 VMAD6 VMAD7 C80 SCD1U C81 SCD1U C193 SC10U16V MOAT 2 HF70ACB C200 SC10U16V RGBGND C192 SCD1U C191 SCD01U VRAMVCC VRAMVCC C222 SCD1U VMBD0 VMBD1 VMBD2 VMBD3 3.3V LCD+5V 17 ENAVDD SSHC00 CX24 SCD1U ## CIRCUIT MODIFY , CHANGE COMPONENT 1 100KR3 U17B RXUX3 GND OUT IN OUT IN OUT EN# OUT TPS2013D VMBD4 VMBD5 VMBD6 VMBD22 C96 SCD1U 17 VMBD[0.15] U40 VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C N.C N.C N.C WE RAS N.C A0 A1 A2 A3 VCC S256K16-60 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C N.C N.C LCAS UCAS OE A8 A7 A6 A5 A4 VSS VMBD15 VMBD14 VMBD13 VMBD12 VMBD11 VMBD10 VMBD9 VMBD8 C196 SCD1U C199 SCD01U AVCC 17 VAA[0.8] U42 VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C N.C N.C N.C WE RAS N.C A0 A1 A2 A3 VCC S256K16-60 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C N.C N.C LCAS UCAS OE A8 A7 A6 A5 A4 VSS VMAD15 VMAD14 VMAD13 VMAD12 VMAD11 VMAD10 VMAD9 VMAD8
Close 66(DVCC)PIN & 63,89(GND)PIN CVCC1 DCBATOUT CCFTPWR U3 R22KR3 +5V Q1 RN1 R22 10KR4 C24 SCD1U SI4435DY R127 10KR3 C205 33R3 SCD1U VGAPWR 1 C19 33R3 SCD1U RC18 SC10U16V MOAT RC32 SCD1U C31 SCD01U CVCCVWEA# 17 VRASA# VAA0 VAA1 VAA2 VAA3
VCASAL# VCASAH# VRAMOE# VAA8 VAA7 VAA6 VAA5 VAA4

VCASAL# VCASAH#

C82 SCD1U
C97 SC10U16V GZ2 GAP-CLOSE +5V
VWEA# VRASA# VAA0 VAA1 VAA2 VAA3
VCASBL# VCASBH# VRAMOE# VAA8 VAA7 VAA6 VAA5 VAA4

VCASBL# VCASBH# VRAMOE#

ACER TAIPEI TAIWAN R.O.C Title Size A3 Date: 370P/J (VRAM & VGA BYPASS CAPACITOR) Document Number 96149 January 27, 1997 REV SC Sheet 18 of 25
17 +5V 17 R[0.7] SUD[0.7] 1 L13 ELKE101FA 20 PLP R1 R2 R5 R6 SUD2 SUD1 SUD6 SUDUDUDLD2 +5V +5V 1 R15 330R16 BBT_QCHG CCFTPWR 20 CCFT_ON 1 C4 SCD1U C3 SC1U25V5MY CID_DATA SCD1U 8 PLED# 1 470R3 LMLBID_CLK 8 BLVR# CN40 JAE-CONN80C TPX4 TP-1 THIS CONN. IS LCD INTERFACE CONN. 17 VSW100RCRT_VS 20 CRT_B 20 CRT_HS 20 CRT_G DDC_DATA 20 CRT_R CRT_VS CRT_B CRT_HS CRT_G 1 CRT_R 33R3 RR1KR3 RPLFS R0 R3 R4 R7 SUD3 SUD0 SUD7 SUD4 UD3 UD0 LD3 LD1 LD0 LCDVEE 17 PMOD LCD_DISPLAY LCD+5V C1 SCD1U ENAVEE 8 C171 SC1U25V5MY 17 A_A18 A_A19 A_A13 Y4 Y1 C72 SCD1U R4K7R3 Y7 A_A20 A_A14 Y6 Y12 DPRLL4001 15,21,22 17

Y[0.7] UV[0.7]

A_A[0.25]

20 PSHFCLK

U9 VCC B9 B0 A9 A0 A8 B8 A1 B1 B7 B2 A7 A2 A6 A3 B6 B3 B5 B4 A5 A4 OEA OEB GND QQST3384
UV2 A_A16 A_A21 UV0 Y2 A_A8 A_A17 Y1 Y0 A_A9
UV4 A_A15 A_A12 UV6 UV1 A_A22 A_A23 UV3 UV5 A_A24
U14 VCC B9 B0 A9 A0 A8 A1 B8 B1 B7 B2 A7 A2 A6 A3 B6 B3 B5 B4 A5 A4 OEA OEB GND QQST3384