HR-16/HR-16B Drum Machines Service Manual V1.00 7/27/95
HR-16/HR16B Service Manual 1.00

03/31/06

PREFACE
This document is intended to assist the service technician in the operation, maintenance and repair of the HR16 and HR-16B Drum Machines. Together with the HR-16/B Reference Manual, this document provides a complete description of the functionality and serviceability of these machines. Any comments or suggestions you may have pertaining to the document are welcome and encouraged.

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Only Service Centers authorized by Alesis in writing are authorized to perform service and repairs covered by an Alesis warranty (if any), and transfer of the Manual to you does not authorize you to be an authorized Service Center. Therefore, if you perform, or if the Manual is used to perform, any service or repairs on any Alesis product or part thereof, any and all warranties of Alesis as to that product and any service contract with Alesis for that product shall be voided and shall no longer apply for such product, even if your services or repairs were done in accordance with the Manual. All service or repairs done by you or with reference to the Manual shall be solely your responsibility, and Alesis shall have no liability for any such repairs or service work. All such service or repairs are performed at the sole risk of the person performing the service or repairs. You agree that all such work will be performed in a competent, professional and safe manner at all times and to indemnify and fully hold Alesis and its successors and assigns harmless in the event of any failure to so perform. Your purchase of the Manual shall be for your own ultimate use and shall not be for purposes of resale or other transfer. As the owner of the copyright to the Manual, Alesis does not give you the right to copy the Manual, and you agree not to copy the Manual without the written authorization of Alesis. Alesis has no obligation to provide to you any correction of, or supplement to, the Manual, or any new or superseding version thereof. Alesis shall have the right to refuse to sell or otherwise transfer repair parts or materials to you in its sole discretion. You shall not use, sell or otherwise transfer spare or replacement parts supplied by Alesis to you (i) to repair or be used in products manufactured for or by third parties or (ii) to any third parties for any purpose. You shall not make any warranties or guarantees with respect to the products of Alesis or the use thereof on behalf of Alesis or in your own name. The foregoing describes the entire understanding related to sale or transfer of the Manual to you, and no other terms shall apply unless in a writing signed by an authorized representative of Alesis.

CAUTION:Danger of explosion if battery is
incorrectly replaced. Replace only with the same type or equivalent type recommended by the equipment manufacturer. Battery Manufacturer: Tadiran Type: TL-5101 Rating 3.6V 2.2 PUP Circuit The PUP (quiet Power UP) circuit is designed to prevent the unit from making noise during power up. Note that this circuit will not be present on the Diagram 2 earliest main PC boards. The circuit utilizes the RESET line (section 3.1) to control the power supply lines to U20, which is the final active stage before the output jacks. Since both rails operate similarly, we'll only take the time to explain the operation of the + rail. During power up, the RESET line is held low until the regulators are fully functioning. At this point, Q11 is turned off by RESET via R104. This has the affect of turning off Q10 by allowing the base of Q10 to pull high via R101. As soon as the reset line goes low, Q11 will turn on, pulling the base of Q10 lower. Q10 is now biased into saturation, allowing roughly +12V to be fed to the opamps. C65 is provided for extra filtering. The - rail consists of R99, R100, R105, Q12-Q13, and C64. HR-16/HR16B Service Manual 1.00 2
C62 was added to the analog rails of the op-amp to prevent oscillation during power up, and may need to be added to some older units (see section 7.20).

3.0 The 8031

The 8031 MPU is the heart of the HR-16's control section. It handles everything from keypad input and MIDI I/O, to sequencing. Note that the 8031 data buss serves a dual purpose. This buss multiplexes between low order addresses (1st 8 bits), and data. Latch U7 is used to hold the low order address half, during 8031 read and write cycles. The EPROM (U11) is used to hold 8031 program information. The SRAM (U12) holds system variables, as well as user sequence data. Z1 provides the 12MHz 8031 clock. MIDI I/O is handled through the 8031's built in RXD (Read Serial Data), and TXD (Transmit Serial Data) ports. Tape I/O and piezo input is handled through the built in 8031 I/O ports. DM3AG ASIC control, and LCD output are handled through memory mapped I/O (see section 3.2). Keypad decoding uses both forms of I/O (see section 3.3). 3.1 Reset The 8031 reset circuit is perhaps the single most important circuit in the HR-16. When this circuit is functioning incorrectly, problems ranging from loss of battery backup to a complete lock-up of the machine can occur. A thorough knowledge of the operation of this circuit will greatly facilitate troubleshooting this unit. This circuit uses the differential between raw +10V and regulated +5V to generate the required signals for system RESET. This is necessary due to fact that the system MUST be in a reset state while powering down, otherwise random noise on the 8031 data and address busses could corrupt SRAM data, and destroy any hope that the battery backup will work. R28, R29, and the 5.1V zener diode (D15) work together as a voltage divider to the base of Q4, and is designed so that transistor Q4 will turn on when the raw +10V supply is roughly 7V. This is to ensure that RESET does not occur until after the +5V regulator is fully functioning (i.e. +5V rail is solid). If RESET occurs too early, noise on the +5V rail can cause data corruption. Before the Q4 turn on threshold, Q5 remains turned on (the base of the transistor being pulled up by R30). This in turn holds the voltage across C20 at.3 volts. This is below the threshold (set by R25 and R96) necessary to turn on the comparator U1 (pins 10, 11 and 13), leaving the reset line high (pulled up by R10). Once the raw supply has reached a sufficient level to turn on Q4 (roughly 7V), Q4 will pull the base of Q5 low, turning it off. This allows C20 to begin charging through R24. Once C20 has charged to roughly 2.5V, the comparator will switch states and hold it low (due to the hysteresis established by R27). This completes the reset cycle during power up. During power down, the opposite occurs, ensuring that the 8031 is held in a reset state during power down as well. This is necessary in order to prevent random data from being written into the SRAM during shutdown. Be aware that this can cause unusual unit lockups to occur if the circumstances are just right. For example, if an HR-16 was shut off while in record mode, it's possible the 8031 was put into reset in the middle of writing a two byte pointer into memory. If only one of those bytes is written before reset, then it may point to an incorrect location in memory (battery backup holds the incorrect data). When the unit is powered back up, the incorrect pointer may send the software into "never never land" where the only way to recover is to reinitialize the unit.

3.2 Memory Mapped I/O In order to easily control the vast number of hardware functions that the 8031 needs to access, a system of memory mapped I/O is used. The basic idea is to make hardware functions appear to the 8031 as unused memory locations. That way all that the software has to do is write to a memory location in order to send that information to a specific device such as the LCD, or ASIC. 74HC138 (U13) performs the majority of the work in this circuit. Two things are required before U13 becomes active. 1> A15 must be low (i.e. the 8031 is accessing the lower 32K of address space). 2> The 8031 WRite line must be active (the 8031 is performing a memory write). A15 is used to directly control which function (memory or I/O) is active. Once U13 is enabled, addresses A8-A10 are decoded by it, and the latch corresponding to the value of the decoded address is strobed. At this point, data on the 8031 data buss is "written" into the latch. 3.3 Keypad I/O Keypad I/O is handled through a simple polling process Each row of the keypad matrix is pulled low one at a time (via U14 which is memory mapped). If any button along the row is pressed, the corresponding column input (U22) will appear high. If no buttons are pressed, all column inputs will appear as a low. D9D15 and R42-R47 provide protection for the outputs of U14. Use diagram 3 to localize individual button failures. 3.4 MIDI I/O The MIDI hardware is a standard implementation. MIDI out begins at the 8031's TXD port (pin 11) and travels via R6 to the darlington pair Q1/Q2. Note that the 8031's internal pullup is not very strong, and Diagram 3 older units (revision A) may require the addition of an external pullup resistor for the MIDI out to function correctly (see section 7.7). MIDI in consists mostly of the opto isolator (U4), protection diode D6, pullup R7, and threshold resistor R5. Note that the threshold resistor may need to be changed in order to eliminate false MIDI triggers (see section 7.6).

4.0 DM3AG ASIC

The DM3AG ASIC is a complex LSI device, specifically designed for the purpose of playing percussion samples. Obviously, the internal workings of such a device are beyond the scope of this manual. However, a brief description of some of the important pins follows.

NAME MD0-MD7 CLOCK DAC0-DAC16 A0-A19 D0-D7 SNH0 SNH1 SNHIN STRES STB PIN#(s) 27-42-51, 53-60 3-17, 19-23 61-Function 8031 Data Buss Input. Asic Clock Input (6MHz in HR-16). Output to DAC. Mask Address Buss Mask Rom Data Buss Output Sample and Hold Control " " " " " Output Sample and Hold Inhibit. Instruction reset strobe. Instruction latch strobe.
Diagram 4 4.1 Mask ROMs Diagram 5
The mask ROMs contain the all of the sample information. The 18 bit address buss allows for 2 megabytes per mask ROM. Address line A19 from the ASIC is actually used in conjunction with Q15 to switch the Mask ROM CE lines (pin 22) such that only one device is enabled at any given time.

5.0 Analog Signal Paths

5.1 Drum Signal Output The output of the DM3AG ASIC is an 18 bit value. This may seem a little strange at first, since we are using a 16 bit DAC. R63 and R73-R75 provide the binary weighted resistor network necessary to achieve a full 18 bit output. The PCM-54 DAC adjust circuit consists of R52, R53, R54, C34, and trimpot R90 (see section 6.3 regarding adjustment). The output of the DAC is sent via R68 to the 4052 analog switch (U19), where the ASIC controls to which output (out1 left/right or out2 left/right) the final signal will be sent. (Note that stereo panning is achieved by sending the same signal to the left and right sides separately.) Each output section (consisting of 1/4 of U20, 1/4 of U21, and misc. resistors and capacitors) serves the dual purposes of filtering and buffering (with a little gain added in). In the case of output 1, the signal is fed through the volume slider (via J11)(see section 7.19 regarding differences in wiring) before final output to the 1/4 inch jacks. 5.2 Piezo/Data Slider Input Successive approximation is the method used to determine the value of the keypad piezo crystals (keypad velocity), and the data slider. It is a heuristic approach to the process of analog to digital conversion. The idea is to divide the process into short, manageable sections. Each significant binary weight (starting with the Most Significant Bit) is taken in turn, thus requiring only 8 comparisons to achieve a final value. 74HC04s U2 and U3 (replaced by a single 74HC540 [U2] in revision AQ PC boards) combine with the binary weighted resistor network (R16-R20, and SIP R22) to form a simple 8 bit digital to analog converter. The 8031 sends values to the DAC via it's internal I/O ports. The analog equivalent of these values is compared to the actual input signals via comparators U1 (pins 2, 4, and 5 for the data slider) and U1 (pins 8, 9, and 14 for the piezos). The 8031 reads the result of the comparison through I/O port P3.4 (pin 14) or port P3.5 (pin 15) and proceeds according to that result. The data slider is read directly via R23 (with C16 acting as a filter to reduce "jitter"). However the piezos require a little bit of wave shaping and translation before they can be read. First, the signal is A.C. coupled by C50, and rectified by D19. Q3 is then used to translate the signal into a 0V to 5V range (the piezos can produce up to about 50V). The signal is now ready for conversion. 5.3 Tape I/O Tape output is very simple, while tape input is somewhat more complicated. This is due to the fact that tape backup and tape sync have different requirements. Data transfers need data integrity which implies guaranteed highs and lows, while tape sync needs tight timing and fast transistions. It's important to remember that not all tape decks are created equal. Probably the largest factor involved is the decks input and output capacitances. These can greatly affect the signals sent to and from the deck, and may cause some decks to be incompatible with the tape I/O needs of the HR-16. However, these cases should be rare, as the components chosen for the HR16 are based on the industry "standards" that most manufacturers adhere to. While we have heard many complaints regarding tape back up, we have actually found very few actual tape failures. Most of the complaints arise from user error, so below is a list of successful backup and tape sync strategies. 1. When attempting to save to a stereo cassette deck, use only the 1 channel (using both channels may result in odd phase cancellations during playback). 2. Avoid using any noise reduction systems (i.e. Dolby, or DBX) as these can distort the timing of the pulse train that contains the data. HR-16/HR16B Service Manual 1.00 6

3. Avoid using adapters for two reasons. 1> Some adapters contain built in attenuators that can result in extremely reduced levels, both to and from the tape. 2> Oxidation and "wear and tear" can cause adapters to become intermittent. 4. Always make several copies of each "save". It's especially smart to make copies on at least 2 different tapes as well. This reduces the chances that tape dropouts will cause loss of data. 5. Always use normal bias tapes, as high bias tapes actually end up recording noise, which could make it past the wave shaping circuitry and cause false triggers. 6. Always verify tapes after saving them. This helps reduce the chances of bad saves. Note however that the HR-16 does not compare the tape to the contents of memory. It simply verifies that the information on the tape is valid HR-16 data. 7. Experimentation with record and playback levels usually lead to better results. Trouble shooting tape problems should begin with listening to the data tape audibly. This can help the technician determine if the problem occurs during tape save or load. If unusual dropouts are heard then the problem is either just a bad tape, bad cable, or the tape save circuit. Normal sounding tapes usually indicate a tape load problem. Only practice will help you determine what is "normal". 5.4 Tape Output The tape output hardware is simply the 8031 output port P3.2 (pin 12), a pullup resistor (R40), and a voltage divider (R39 and R39) for achieving a line level output. The output during tape save or type sync out applications will appear as a.5V pulse train, but only if the tape out is NOT connected to a deck (the decks A.C. coupling will distort the output). 5.5 Tape Input In it's simplest form the tape input consists of an integrator (under software control of the 8031) and a threshold detector (U1C). Input from J5 is passed through a current limiting resistor (R112) and on to the integrator (C11, C23, R86). The software controls the integration characteristics through Q16 via memory mapped I/O latch U14 (see section 3.2). While the unit is in 'TAPE SYNC IN' mode, U14/P12 is held high, turning on Q16 and sinking the majority of current through the integrator to ground. This provides for faster operation of the detection circuitry. D17 is used to prevent leakage of the integrator signals through the control circuitry during 'TAPE LOAD/VERIFY' operations (when U14/P12 is low). The threshold detection circuitry surround U1C is relatively straight forward. R14 and R15 establish the threshold level with R12 and C9 acting as a filter to stabilize the threshold level and prevent oscillation. R21 establishes some hysteresis and R13 is a pullup for the open collector output of the LM339. The output of the '339 is sent directly to the 8031 in the form of an interrupt line. Forcing the 8031 to respond immediately to tape input is necessary due to the timing constraints required for I/O (especially in tape sync situations).

7.15 Tape Capacitors Revision A & CA The blue monolithic block RAM capacitors used throughout the board were found to be unreliable when used in timing critical applications due to excess leakage current. Here, the capacitors reside in the tape input path (C11 and C23), and may cause the distortion of incoming tape signals. Such distortions can cause the loss of tape loading capabilities. These capacitors should be replaced with either a ceramic disk or film (WIMA) type of capacitor if tape loading failures occur. 7.16 RF chokes Revision CA & AQ Occasionally the R.F. chokes on these board revisions (located near the power input jacks) will bust a lead during shipping. When this occurs, it may not be possible to repair the choke. In this case it is O.K. to remove the choke and add jumpers across its old location. In most cases this shouldn't be necessary as the units should have had their chokes hot glued to the board at the factory. Any units that have loose chokes need to be glued (hot glue recommended) to prevent future damage. 7.17 AQ reset threshold Revision AQ During the development of the AQ main PC board, one of the prime considerations was to reduce R.F. emissions to virtually 0. Towards this end, a 100 ohm resistor (R133) was introduced between the raw supply voltage and the rest of the circuitry to reduce power supply noise. This had the effect of increasing the threshold of the RESET circuit, and was found to cause some units to reset repeatedly in low power situations (i.e. use of lots of lights in a club could cause fluctuation in the local power by 15V to 20V, causing the unit to reset over and over again). R28 is part of the threshold circuit for the RESET line. Originally valued at 3K, the new value is 1.5K (easily obtained by adding an additional 3K in parallel). This will bring the threshold into a more reasonable range. 7.18 AQ R116 Revision AQ Again an attempt to reduce power supply noise, this resistor was found to sometimes reduce the power supply level to the 8031 (and surrounding circuitry) to below the required 4.75V. It is recommended that a jumper be soldered across this resistor (located between the 8031 and U6). 7.19 Volume Slider Wiring Note that the wiring of the volume slider changed between Revisions CA and AQ. Diagram 16 shows the correct wiring for each board style. Diagram 16
7.20 PUP Capacitor Revision CA When the PUP circuit first appeared, it was found that the circuit would occasionally oscillate on power up, causing noise. This was eliminated by adding a bypass capacitor (later incorporated as C62) across the power supply pins of U20 (pins 4 and 11).

8.0 Common Solutions

A thorough knowledge of the software history can help solve a great many situations quickly. Also be aware that with devices as full of options as the HR-16(B), there are even more possibilities for user error (i.e. the user claims that MIDI out isn't working, but on checking the settings, the tech finds that both MIDI clock, and DRUM NOTES OUT are turned off). Understanding how the user has the unit in his (her) setup is an important tool in troubleshooting units that act like there is nothing wrong with them. While it is simply beyond the scope of this manual to present every possibility, the chart below offers a majority of solutions to common situations.

Complaint

Unit is truly "dead". (No lights, or sound)

Possible Cause

Blown power supply. +5V rectifier blown (D5). (Note that 1N4001s were used originally, but some were found to be unreliable. We have since switched to using 1N4004s exclusively.) Blown DM3AG ASIC. (occasionally these devices will "short" and pull down the 5V supply rail) Blown +5V filter capacitor (C5) Usually blown capacitors will "distended" appearance. Faulty or broken power jack. Faulty or broken power switch. Broken lead on power choke.

Solutions

Replace and retest. Troubleshoot and repair as necessary.
Remove ASIC and attempt power up. Also note that this type of ASIC failure usually causes the ASIC to become extremely hot to the touch. Troubleshoot and repair as necessary.

display

a Troubleshoot and repair as necessary. Troubleshoot and repair as necessary. Troubleshoot and repair as necessary. (see section 7.16) Troubleshoot and repair as necessary. Note that when these capacitors fail, they often turn brown from overheating, and some will occasionally just burn up. Reinitialize memory and test.
Unit powers up, but does not function. (No LCD display, all LEDs on, buttons don't work, etc.)
Blown monolithic filter capacitor. (Any of the small blue RAM capacitors used as bypass capacitors can become shorted and pull the rail low. We are currently using ceramic disk capacitors as replacements exclusively) Unit is simply "crashed".
C-20 leaking excessively. Faulty 8031, EPROM, or SRAM. Faulty DM3AG ASIC. (Pulling down the 8031 data buss.) Faulty I/O latch pulling down lines on data buss. Other faulty reset component. Open or short in 8031 data buss. Open or short in 8031 address buss. Faulty LCD pulling down lines on data buss. Faulty LCD. Faulty LCD cable. Faulty 74HC138 (U13), or open between U13 and LCD header. C-20 leaking excessively. Faulty 8031, EPROM, or SRAM. D15 is glass package type (Revision A or CA only). R116 is pulling 8031 Vcc too low (revision AQ only).

Troubleshoot and repair as necessary. (see section 7.13) Troubleshoot and repair as necessary. (see section 3.X) Troubleshoot and repair as necessary. Troubleshoot and repair section 3.2) Troubleshoot and repair section 3.1) Troubleshoot and repair section 3.X) Troubleshoot and repair section 3.X) Test with new LCD. Test with new LCD. as necessary. (see as necessary. (see as necessary. (see as necessary. (see
LCD shows no, or scrambled display (the rest of the unit seems to function normally).
Replace and retest. Troubleshoot and repair as necessary. Troubleshoot and repair as necessary. (see section 7.13) Troubleshoot and repair as necessary. (see section 3.X) Replace with metal package type (see section 7.2). Add jumper across resistor.

Intermittent reset.

Intermittent reset. (cont.)

No sound at all.

No sound from a particular drum.

Intermittent buttons.

R28 (reset threshold) is wrong value. (Revision AQ only). Other faulty component is 8031 reset circuit. Faulty DM3AG ASIC, PCM-54 DAC, 4052 analog switch, or op-amp. Faulty volume slider. User error (i.e. drum pads set to wrong outputs, volumes set to )etc.). User error (i.e. drum pads set to wrong outputs, volumes set to )etc.). This is particularly noticeable on drums that panned hard left or right (TOM 1 and TOM 3 of the default drum kit). Dirty, or broken cliff (1/4") jack. This is particularly noticeable on drums that panned hard left or right (TOM 1 and TOM 3 of the default drum kit). Faulty Analog switch. Faulty op-amp (U20, U21) or component in surrounding circuitry. Component failure in keypad circuitry. (This is actually fairly rare, but it can happen). Old keypad PC Board. Dirty rubber keypad. Faulty ribbon cable. Needs MIDI pullup resistor. Faulty Transistor (Q1 or Q2). Faulty 8031. Faulty opto-isolator (U4). Threshold resistor (R5) wrong value. Faulty 8031. Broken 1/8" jack (J6). User error. Faulty 8031. Broken 1/8" jack (J5). User error. Faulty 8031. Faulty integrator capacitor (C11 or C23). Faulty comparator (U1). Faulty slide potentiometer. Broken wire between slider and keypad PC board. Faulty ADC circuit. (Usually if this is the case, the keypad velocity will not work either.) Faulty 8031. Faulty ADC circuit. (most likely a short or open in the binary weighted resistor network). Broken cliff (1/4") jack. Faulty 8031. Faulty SRAM bypass capacitor (blue monoblock type). Faulty or incorrect SRAM. SRAM not in standby mode while power off (CE pin 20 not held high). Faulty battery. Faulty reset circuit (not going into reset during power down). Faulty SRAM. Broken Piezo lead. Faulty cable. Faulty ADC circuit. Faulty reset circuit. Faulty 8031, EPROM, or SRAM. Open or short in address or data busses. Faulty DM3AG ASIC pulling down data buss.

7/3/90

3/10/92

1) Fixed bug which caused a wrong amount of silence at the beginning of a pattern if its length was changed to a shorter value from the top and there was no drum event on the old or new downbeat. For example, if no events existed on beats 1 and 2, and the length from top was changed to be shorter by one beat, the amount of silence before the first event would be wrong. 2) Fixed bug which caused sysex loading to be garbled if any real-time MIDI information was received during the sysex dump. This seemed to only be a problem with IBM MPU-401 interfaces. 3) All individuals names have been removed from the software.

11.0 MIDI Implementation

ALESIS HR-16/HR-16B MIDI SYSTEM EXCLUSIVE FORMAT
The following information is provided as a guide for programmers wishing to modify the data received via MIDI from the HR-16 for the purpose of interchanging patterns from separate block dumps, modification of drum setups, MIDI channel assignments, etc. Great care must be taken to insure that all modified addresses are valid, since one incorrect value (the length of a pattern, for example) could result in all data being lost in the HR-16. These errors may not show up immediately, since the incorrect values may not be accessed by the HR-16 until a particular pattern or song is selected. Therefore, it is recommended that any data manipulation programs be thoroughly tested after loading into the HR-16 by selecting and recording on many patterns and songs before assuming that the data is valid. For any of the sysex commands to be transmitted or received, the SYSEX ENABLE function (MIDI/UTIL page 15) must be turned on. All 11 possible commands will be transmitted in the following format: HEX F0H 00H 00H 0EH 01H 00H-0AH. F7H COMMENTS SYSTEM EXCLUSIVE STATUS BYTE
ALESIS I.D. NUMBER HR-16 I.D. NUMBER SYSEX COMMAND DATA EOX
The following sysex commands are transmitted and received by the HR-16:

COMPLETE MEMORY DUMP

A system exclusive MIDI data dump from the HR-16 is initiated by holding the TAPE button down, pressing (and releasing) the left arrow button once, and then pressing the RECORD button. This command is followed by a block of data representing the contents of the HR-16's memory. In order to optimize the data transfer, 8 MIDI bytes are used to transmit each block of 7 HR-16 data bytes. If the 7 data bytes are looked at as one 56bit word, the format for transmission is eight 7-bit words beginning with the most significant bit of the first byte, as follows: SEVEN HR-16 BYTES: A6 A5 A4 A3 A2 A1 B6 B5 B4 B3 B2 B1 C6 C5 C4 C3 C2 C1 D6 D5 D4 D3 D2 D1 E6 E5 E4 E3 E2 E1 F6 F5 F4 F3 F2 F1 G6 G5 G4 G3 G2 G1

0: 1: 2: 3: 4: 5: 6:

A7 B7 C7 D7 E7 F7 G7

A0 B0 C0 D0 E0 F0 G0

0: 1: 2: 3: 4: 5: 6: 7:
TRANSMITTED AS: A7 A6 A5 A4 A3 A2 A0 B7 B6 B5 B4 B3 B1 B0 C7 C6 C5 C4 C2 C1 C0 D7 D6 D5 D3 D2 D1 D0 E7 E6 E4 E3 E2 E1 E0 F7 F5 F4 F3 F2 F1 F0 G6 G5 G4 G3 G2 G1

A1 B2 C3 D4 E5 F6 G7 G0

In order to use the data properly, it must be decoded properly into HR-16 byte format. The following list gives the data locations within the "unpacked" (decoded) block of data, starting with the first byte of the block being 000. NOTE: All absolute addresses must have an offset of 8200H added to them (e.g., an absolute pointer to a pattern that starts at 35AH should have the pointer value 855AH). 000H-0C7H 0C8H 0C9H 0CAH 0CBH 0CCH 0CDH 0CEH 0CFH 0D0H 0D1H 0D2H 0D3H 0D4H 0D5H 0D6H 0D7H 0D8H 0D9H 0DAH 0DBH 0DCH 0DDH 0DEH 0DFH 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0E7H-0EBH 0ECH-F3H 0F4H 0F5H-FDH DON'T CARE MIDI channel Receive MIDI drum triggers (0=off, 1=on) Transmit MIDI drum triggers (0=off, 1=on) MIDI note assignment of CLICK (0-127) MIDI note assignment of KICK (0-127) MIDI note assignment of SNARE (0-127) MIDI note assignment of CLS HAT (0-127) MIDI note assignment of MID HAT (0-127) MIDI note assignment of OPEN HAT (0-127) MIDI note assignment of CLAPS (0-127) MIDI note assignment of PERC 3 (0-127) MIDI note assignment of PERC 4 (0-127) MIDI note assignment of TOM 1 (0-127) MIDI note assignment of TOM 2 (0-127) MIDI note assignment of TOM 3 (0-127) MIDI note assignment of TOM 4 (0-127) MIDI note assignment of RIDE (0-127) MIDI note assignment of CRASH (0-127) MIDI note assignment of PERC 1 (0-127) MIDI note assignment of PERC 2 (0-127) MIDI echo (0=off, 1=on) MIDI program select (0=off, 1=on) Clock mode (0=MIDI & internal, 1=internal only, 2=tape) MIDI clock out (0=off, 1=on) Auto start (0=off, 1=on) Click value Click in play (0=off, 1=on) Manual voice/tune/mix (0=off, 1=on) Pad dynamics (0-0AH) Song loop (0=off, 1=on) Sysex enable (0=off, 1=on) Software version: 5 ascii bytes, starting with a space (20H) if an HR-16, or a "B" (42H) if an HR-16B, followed by a 4 digit version number (e.g., "2.00", or 32H, 2EH, 30H, 30H) DON'T CARE 0 DON'T CARE 24
0FEH 0FFH 100H-187H 188H-191H 192H-1A1H 1A2H-1FFH 200H 201H 202H 203H 204H 205H " 2C6H 2C7H 2C8H-2CCH 2CDH 2CEH 2CFH-2D0H 2D1H 2D2H 2D3H-2D4H 2D5H 2D6H-2D7H 2D8H 2D9H 2DAH 2DBH-2FFH 300H-301H 302H 303H 304H 305H 306H 307H " 3C8H 3C9H 3CAH-3CCH 3CDH-3D2H 3D3H-3D6H 3D7H-3FFH 400H-?
27H 0B5H DON'T ALTER(this can be DON'T CARE if manual voice/tune/mix is off) DON'T CARE 0 DON'T CARE MSB of absolute pointer to pattern 00 LSB of absolute pointer to pattern 00 MSB of absolute pointer to pattern 01 LSB of absolute pointer to pattern 01 MSB of absolute pointer to pattern 02 LSB of absolute pointer to pattern 02 " " " " MSB of absolute pointer to pattern 99 LSB of absolute pointer to pattern 99 DON'T ALTER LSB of absolute pointer to first byte past SONG 99 data MSB of absolute pointer to first byte past SONG 99 data DON'T ALTER LSB of FF00H minus data in 0CDH & 0CEH MSB of FF00H minus data in 0CDH & 0CEH DON'T ALTER Shuffle amount (0-24, 0=50%) DON'T ALTER Tempo (20-255) Quant clock count (must correspond to Quant value 0-9: 96, 64, 48, 32, 24, 16, 12, 8, 6, 1) Quant value (0-9) DON'T CARE DON'T ALTER MSB of absolute pointer to song 00 LSB of absolute pointer to song 00 MSB of absolute pointer to song 01 LSB of absolute pointer to song 01 MSB of absolute pointer to song 02 LSB of absolute pointer to song 02 " " " " MSB of absolute pointer to song 99 LSB of absolute pointer to song 99 DON'T ALTER DON'T CARE DON'T ALTER DON'T CARE PATTERN 00 DATA

22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H-?? ??
TOM 3 sound number (0-30H) TOM 3 output assign (bit 7) and volume (bits 0-6: 0-63H) TOM 3 panning (bits 5-7: 0=L, 6=R) & pitch (bits 0-4:0=-16, 1FH=+15) TOM 4 sound number (0-30H) TOM 4 output assign (bit 7) and volume (bits 0-6: 0-63H) TOM 4 panning (bits 5-7: 0=L, 6=R) & pitch (bits 0-4:0=-16, 1FH=+15) RIDE sound number (0-30H) RIDE output assign (bit 7) and volume (bits 0-6: 0-63H) RIDE panning (bits 5-7: 0=L, 6=R) & pitch (bits 0-4:0=-16, 1FH=+15) CRASH sound number (0-30H) CRASH output assign (bit 7) and volume (bits 0-6: 0-63H) CRASH panning (bits 5-7: 0=L, 6=R) & pitch (bits 0-4:0=-16, 1FH=+15) PERC 1 sound number (0-30H) PERC 1 output assign (bit 7) and volume (bits 0-6: 0-63H) PERC 1 panning (bits 5-7: 0=L, 6=R) & pitch (bits 0-4:0=-16, 1FH=+15) PERC 2 sound number (0-30H) PERC 2 output assign (bit 7) and volume (bits 0-6: 0-63H) PERC 2 panning (bits 5-7: 0=L, 6=R) & pitch (bits 0-4:0=-16, 1FH=+15) PATTERN DATA 0FFH (End of pattern)
Pattern data must follow these rules: 1) Each byte of the pattern data (from 34H on) is either a drum event, or a count of clocks to wait, or 0FFH, which indicates the end of the pattern. If the event is a drum event, bit 7 will be 0, bits 4-6 will contain the dynamics of the note (0-7), and bits 0-3 will contain the drum to be played (0-15, in the same order as above). If the event is a count of clocks, bit 7 will be high, and bits 0-6 will indicate the number of clocks to wait (0-126). A wait of 0 clocks is legal, and will cause the pointer to immediately advance to the next event. An empty 8 beat pattern would consist of the following pattern data: 0FEH, 0FEH, 0FEH, 0FEH, 0FEH, 0FEH, 08CH, 0FFH. This data will count clocks for 126*6+12 clocks (768 clocks, divided by 96 clocks per beat = 8 beats), after which it will loop around since it has reached the end of the pattern. 2) Adding the number of bytes in a pattern to the absolute pointer of a pattern should point to 1 byte past the last byte of the pattern.
SONG DATA FORMAT The following is the format of each song, starting with the address pointed to by the absolute pointer to the pattern (offset by 8200H): 00H 01H 02H 03H 04H 05H 06H xxH LSB of number of bytes in song, including header. MSB of number of bytes in song, including header. Step 1 Step 2 Step 3 Step 4 etc. Pattern number 0FFH (end of song)
Song data must follow these rules: HR-16/HR16B Service Manual 1.00 27
1) Step data 0-99 indicate pattern steps. Step data 100-250 indicate tempo change of 50% to 200%, respectively. Step data of 251-254 are not accessible from the front panel, but would correspond to tempos of 201% through 204%. 2) There cannot be more than 255 steps in a song. 3) Adding the number of bytes in a song to the absolute pointer of a song should point to 1 byte past the last byte of the song.

STEP EDIT MODE This command is used to enter or exit step edit mode, as well as for stepping through the edited pattern. If it is received while in song mode, it will be ignored. If a step command is given while not in step mode, it will also be ignored. The HR-16 will always transmit the current quantize and swing settings before sending an enter step command. When receiving a step to next beat, any additional drums on the existing beat will be skipped. When receiving a step to next drum command when currently on the last drum of a beat, the command will be ignored. 000000xxB F7H x: 0=enter step mode, 1=exit step mode, 2=step to next beat, 3=step to next drum EOX
REQUEST SYSEX DUMP This command is used to request a complete sysex memory dump from the HR-16. After receiving this command (if not in PLAY mode), the HR-16 will send out its complete memory via MIDI. F7H EOX
CHANGE VOICE, TUNE, MIX SETTINGS This command is receive only, and is used to change the voice settings of the current pattern. It can function while the pattern is playing, and will update the display if the settings being displayed are
changed. It will be ignored if in song mode. The format is packed as 8 MIDI bytes per 7 data bytes as described in the MIDI bulk dump explanation. The data is identical to bytes 4 through 33H in the pattern data format. data F7H 48 data bytes, transmitted as 55 MIDI bytes EOX
MIDI COMMUNICATIONS TEST This command is used to insure that bi-directional MIDI communication is functioning. If an HR-16 receives the inquiry command (F0H, 00H, 00H, 0EH, 01H, 09H, 00H, F7H), it will respond with the response command (F0H, 00H, 00H, 0EH, 01H, 09H, 01H, F7H) only if MIDI ECHO is turned off. If MIDI ECHO is on, the transmitting device will see the inquiry message returned to it if bi-directional communication is functioning. This function is useful in determining that the HR-16 is ready to receive additional MIDI information. For example, selecting a pattern, or copying a pattern can cause a delay in which the HR-16 will ignore incoming MIDI information if its input buffer overflows. By sending this command after a copy pattern command (command 5), and then waiting for the response before sending any additional commands, it can be insured that the HR-16 will not miss any information. 0000000xB F7H x=0=MIDI inquiry, x=1=MIDI response EOX
ERASE PATTERN OR SONG This command is used to erase the currently selected pattern or song. It will be ignored if in play mode. F7H EOX
12.0 Service Manual History
7/27/95 V1.00 1st release.
+ +12V, 1, 2 +5V, 1, 3, 15 -12V, 1/4 inch jacks, 6 1/8 inch cable, 8 12MHz, 3 1N5231B, 9, 4052, 6, 16, 5.1V zener, 6MHz, 74HC04, 10, 18 74HC04s, 6 74HC138, 4, 15, 18 74HC540, 6, 18 7805, 1, 18 7812, 1, 18 7912, 1, 8031, 3, 4, 5, 6, 7, 8, 10, 11, 13, 15, 16, 18 A A, 1, 4, 6, 7, 9, 10, 11, 12, 13, 15, 23, 27 A0-A19, 5 A15, 4 A8-A10, 4 adapter, 1 adapters, 7 ADC, 16 Address Buss, 5, 8, 15 adjustment, 6, 8, 9, 17 Analog switch, 6, 16 analog to digital, 6 AQ, 1, 6, 9, 10, 11, 13, 15, 16, 18 ASIC, 3, 4, 5, 6, 10, 15, 16, 17, 18, 19 audio test, 8 Auto start, 24 B Battery backup, 2, 3, 8, 12, 16 battery drain, 2, 12 binary weighted resistor network, 6, 16 button failures, 4 buzz, 8 bypass, 1, 14, 15, 16 C C1, 1, 18 C11, 13, 16, 18 C16, 6, 18 C2, 1 C20, 3, 12 C23, 13, 16 C3, 1 C34, 6, 18 C4, 1, 18 C47, 12 C5, 1, 15, 18 C50, 6 C59, 2 C6, 1, 18 C62, 3, 14 C64, 3 C65, 3 C7, 1 CA, 1, 9, 10, 11, 12, 13, 14, 15 cassette, 6, 20 CE, 5, 10, 16 ceramic disk, 12, 13, 15 chokes, 13 Click value, 24 cliff jack, 10 CLOCK, 3, 5, 10, 15, 21, 24, 25 comparators, 6 contacts, 10, 12, 16 COPY, 29, 30 crashes, 10, 16, 17 D D1, 1, 18 D15, 3, 4, 15, 18 D19, 6 D2, 1, 18 D21, 11 D3, 1 D4, 1 D5, 1, 15 D6, 4, 18 D7, 2, 5 D8, 9 DAC, 5, 6, 8, 11, 16, 17, 18, 21 DAC0-DAC16, 5 data buss, 2, 3, 4, 5, 10, 15, 16, 17 data corruption, 2, 3, 9 data slider, 6, 16, 17 DataDisk, 7 distortion, 13 DM3AG, 3, 5, 6, 15, 16, 17 drift, 12 dropouts, 7 E EPROM, 3, 8, 10, 15, 16, 17 H hot glue, 13 HR-16, 3, 5, 6, 7, 8, 11, 12, 15, 17, 18, 20, 21, 22, 23, 24, 28, 29, 30 HR-16B, 17, 18, 23, 24 I I/O, 3, 4, 6, 8, 15, 17 Instruction latch strobe, 5 Instruction reset strobe, 5 internal diagnostics, 8 J J1, 1, 18 J11, 6, 18 J12, 11, 18 J5, 16, 18 J6, 16 jitter, 6 jumper, 10, 11, 13, 15 K keypad, 3, 4, 6, 12, 16, 18, 19, 20 L LCD, 3, 4, 11, 15, 18, 20 LED Test, 8 Lithium, 2, 18 lock-up, 3 low order address, 3 low power, 2, 13 LSI, 5 M Manual voice/tune/mix, 24, 25 Mask Rom, 5, 17, 18 mask ROMs, 5 MD0-MD7, 5 MEM PWR, 2 MEMORY DUMP, 23, 29 memory mapped I/O, 3, 4 microprocessor, 1 MIDI, 3, 4, 8, 11, 15, 16, 20, 21, 22, 23, 24, 28, 29, 30 mono, 10, 18 monolithic block ram capacitors, 12, 13 Most Significant Bit, 6, 23 N noise, 2, 3, 7, 8, 11, 12, 13, 14 normaling, 10 O OE, 10 op-amp, 3, 16, 17 opto isolator, 4, 11 oscillation, 3 Output Sample and Hold, 5 output section, 6 Oxidation, 7, 10 oxidize, 12 P PATTERN DATA, 26, 27, 30 PCM-54, 6, 8, 12, 16, 17 piezo, 3, 6, 16, 18 power supply, 1, 13, 14, 15, 17 program, 3, 20, 24 program change, 21 pullup resistor, 4, 7, 16