FPGA_Top.SchDoc

FPGAproject
ThetoplevelFPGAschematicdocument mustcontainportsatthepointwhere signalsareconnectedtophysicalpinson theFPGAdevice.Thenameoftheportsis importantastheywillbeusedinthe constraintsfile. FPGA.Constraint FPGAproject
TheConstraintfiledefinesthephysicalpin numberthatportsdefinedinthetoplevel FPGAschematicwillbeconnectedto.This isreferredtoasaportnametoFPGApin numbermapping.Portnamesdeclaredin theconstraintfilemust matchthose includedinthetoplevelFPGAschematic document. FPGA_Auto.SchDoc PCBproject
Theautogeneratedschematicsheetis createdfrominformationcontainedinthe FPGAconstraintfile.Essentiallythe autosheetisaschematicrepresentationof theporttopinmappingsmadebythe constraintfile.Porttopinconnectivityon theautosheetisaccomplishedthroughthe useofnetlabelsi.e.anetlabelis attachedtowiresconnectedtotheportson thesheetandacorrespondingnetlabelis alsoattachedtothedevicepin. FPGA_Manual.SchDoc PCBproject
Anoptionalmanualsheetisgeneratedas partoftheFPGAtoPCBprojectwizard. Thismanualsheetcontainsasheetsymbol oftheautosheettheportsonthe autosheetareconnectedtocorresponding portsonthesheetsymbol.Connectingto thissheetsymbolratherthandirectlytothe FPGAsymbolintroducesanimportant abstractionlayer.Thislayerfacilitateseasy (automated)updatestotheprojectifthe deviceorpinallocationsshouldchangeas theprojectdevelops. TargetPCB.PCBDoc PCBproject TheFPGAdepictedintheautosheetand abstractedonthemanualsheetwill eventuateintoaphysicaldeviceonthefinal PCB.Thephysicalpinsofthisdevicewill beconnectedtoportsasdescribedinthe autosheet.
Figure2.Theroleofthevariousdocumentsintheprojectstack
UsingtheFPGAtoPCBprojectwizard
WithaschematicdocumentintheFPGAprojectopenastheactiveviewinthemaindesignwindow, simplychoosetheToolsFPGAToPCBProjectWizardentryfromthemenu.Thewizardwill appear,asshowninFigure:
Figure3.TheFPGAToPCBprojectwizard.
ChoosingtheFPGAconfiguration
Thesecondpageofthewizardallowsyoutochoosetheconfigurationthatwillbeusedfortargeting theFPGAdesigntothePCB.TheconfigurationusesaconstraintfilethatdefinestheFPGAdevice tobeusedanditsassociatedpinmappings. TheconfigurationcaneitherbeanexistingonethatyouhavealreadydefinedaspartoftheFPGA project,oranewone,generatedbythewizard.Inthecaseofthelatter,thewizardwillgeneratea configurationandaddtoitanewconstraintfile.Thesewillhavedefaultnames(PCB ConfigurationandPCBConstraints.Constraintrespectively)andtheconstraintfilewillbe storedinthesamelocationastheFPGAprojectfile(*.PrjFPG),unlessotherwisespecified.

Figure4.Wizardbasedconfigurationgeneration.
Theconstraintfilethatisaddedtotheconfigurationwillcontainatargetdevicedefinitionforthe FPGAproject,accordingtothedeviceyouselectintheSelectedDevice field.Youcanbrowsefora devicebyclickingthebutton,totherightofthefield.ThiswillopentheChoosePhysicalDevice dialog,fromwhereyoucanperusefromanumberofdevicesavailableacrossaspectrumofFPGA vendordevicefamilies.
Figure5.BrowsingfortherequiredFPGAdevice.
InitialFPGApinassignments
ThesecondpageoftheFPGAtoPCBProjectwizardgivesyouthechoiceofwhattodowith unconstrainedportsi.e.portsthathavenotbeentiedtoaspecificpinonthetargetdevice.The decisionastohowthesepinsareassignedissomewhatarbitraryandsothereareanumberofways ofdoingthis:
Importingpinfilefromvendorplaceandroutetools
Clearlyforthisoptiontobeavailablethedesignmusthavepreviouslybeenbuiltforthecurrent deviceandaconstraintfileandconfigurationmustalreadyexist.Fortotallynewdesignsthisisthe preferreddesignpath.Itensuresthatthevendortoolsaregiventhemostopportunitytooptimizethe designwithoutbeingundulyconstrainedanditensuresthattheselecteddeviceiscapableof supportingthedesign.Inthiscase,thepinassignmentsshouldbemadepriortorunningtheFPGA toPCBprojectwizard.Withaconstraintfileopeninthemainwindow,selectDesignImportPin File fromthemenutoimportthevendorpinfile.Thefollowingdialogboxwillappear:
Figure6.Selectingconstraintstobeimportedfromthevendortools
AssigningpinsduringtheFPGAtoPCBwizard
ProbablythequickestandsimplestwaytoallocatepinsiswhilstexecutingtheFPGAtoPCBproject wizard.SelecttheAssignUnconstrainedPortsonthesecondpageofthewizard.Asthewizard executesitwillautomaticallyallocatepinnumberstounallocatedportsupdatingtheconstraintfile andautogeneratedsheetasitgoes.
Figure7.AssigningunconstrainedportsaspartoftheFPGAtoPCBprojectwizard
AssigningunconstrainedsignalsfromtheFPGAsignalmanager
ItisalsopossibletoallocateunconstrainedsignalsbyselectingtheAssignUnconstrainedSignals buttonintheFPGASignalManagerdialog(Figure8).
Figure8.UsingtheFPGAsignalmanagertoassignunconstrainedsignals
Performingpinassignmentsviathismethodisprobablylessadvisableasitdoesnotgivetheuser thechoicewhichconstraintfile(projectortarget)recordsthepinallocations.Furthermore,an additionalstepisrequiredafterthisonetoresynchronizethenetlabelsintheautogeneratedsheet.
Assigningsignalsmanuallyintheautogeneratedsheet
Thisisthemostlaboriousmethodandgenerallynotadvisable.Usingthismethodrequiresthe designertomanuallyenterthenetnamesforallportsontotheautogeneratedsheet.Asecond synchronizationstepisalsorequiredtopropagatethepinassignmentsintotheconstraintsfile.
ChoosingthetargetPCBproject
AfterchoosingtheFPGAconfiguration,theactualtargetPCBprojectmustnowbedefined.Simply accepttheWizard'sgenerationofanewproject(PCBProject1.PrjPCB),orbrowsetoandselect anexistingproject.InthecaseofanewPCBproject,thefilewillbestoredinthesamelocationas theFPGAproject.

ConfiguringtheFPGAcomponentschematicsheet
WhetherthePCBprojectalreadyexistsorisbeingnewlycreated,therelationshipbetweenthe FPGAprojectanditscorrespondingcomponentinthePCBprojecthastobemanagedinsomeway. Thisisachievedusingadedicated,autogeneratedschematicsheet,referredtoasthe'MainSheet' intheWizard.
Figure2.TheautogeneratedFPGAcomponentschematicsheet.
ThisschematicsheetwillbecreatedwiththecomponentsymbolplacedfortheFPGAdevice targetedintheconstraintfile.TheWizardallowsyoutodeterminewhereandbywhatname,the schematiciscreated.Bydefault,theschematicwillbenamedusingthechosendesignatorforthe FPGAcomponent(e.g.FPGA_U1_Auto.SchDoc)andwillbestoredinthesamelocationasthe FPGAproject.Eachusedpinonthecomponentsymbolislinkedtoaportentryintheconstraintfile bysignal(netlabel/port)name.ThenamesfornetsinthePCBprojectarethereforerequiredtobe thesameasthoseintheFPGAproject.Oncelinked,anychangesmadetothesourcedocumentsof eitherPCBorFPGAprojectcanbepassedon,ensuringthatthetwoprojectsremainsynchronized. 37
ConfiguringunallocatedI/O
TheWizardalsoallowsyoutodeterminehowanyunusedI/Opinsonthecomponentarehandled. YouhavetheabilitytocontrolthetreatmentofvariouscategoriesofpintypesindividuallyInput onlypins,VREFpins,SpecialFunctionpinsandallotherunusedpins. Foreachcategory,thepinscanbehandledinoneofthefollowingways: Tietosingleport Tieallunusedpinsinthecategorytoasingleport(whichwillalso appearontheparentsheetsymbol(ifapplicable)onthesheetabove)
Tietoindividualports Tieallunusedpinsinthecategorytotheirown,individualports (whichwillalsoappearontheparentsheetsymbol(ifapplicable)on thesheetabove) TietoportsbyIO bank(VREFonly) AddNoERCdirective Ignore TieallunusedVREFpinstoaportonabankbybankbasis(which willalsoappearontheparentsheetsymbol(ifapplicable)onthe sheetabove). AddaNoERCdirectivetoanunusedpin,sothatitisnotincludedas partoferrorcheckingwhenthedesigniscompiled Donothingwithanunusedpin
Figure3.SelectinghowunusedI/Oistobehandled
Note:ForVREFpins,whentheTietosingleportor TietoportsbyIObankoptionsareselected, youaregiventheadditionaloptionofwhetherornottoconnectviaPowerPorts.
Configuringthesheetsymbolschematicsheet
AspartofthePCBproject,youhavetheoptionofdefiningthe'owner'oftheFPGAComponent sheet(holdingthecomponentsymbolfortheFPGAdevice).ThefinalpageoftheWizardallowsyou todefinetheownerasasheetsymbol,which,ifenabled,willbecreatedonanadditionalschematic sheet,thenameandlocationofwhichyoucanfreelychoose.Bydefault,theschematicwillbe namedusingthechosendesignatorfortheFPGAcomponentonthepreviouspageoftheWizard (e.g.FPGA_U1_Manual.SchDoc)andwillbestoredinthesamelocationastheFPGAproject. Insummary,afteralloftheoptionsintheWizardhavebeensetasrequired,thefollowingwillbe generated: AnewPCBproject(ifspecified) Anewschematicsheet,addedtotheneworexistingPCBproject,whichcontainstheschematic representationoftheFPGAcomponent Anewschematicsheetwithparentsheetsymbol(ifspecified).Ifanexistingsheetistargeted, theparentsheetsymbolfortheFPGAComponentschematicwillbeadded/updatedas necessary Anewconfiguration(ifspecified),whichwillbeaddedtotheFPGAprojectfileandwhich containsanewconstraintfile Theconstraintfileeithernewforanewconfigurationoranexistingonecontainedinachosen configurationcontaining: apartconstraint aPCBboardconstraint alistofconstraintsforallportsonthetoplevelsourcefileoftheFPGAproject.Eachof theseportconstraintsismatched(andthereforelinked),bynetname,totheequivalentpin ontheFPGAcomponentinthePCBproject'sautogeneratedschematicsheet.

Exercise1RunningtheFPGAtoPCBprojectwizard
InthisexercisewewillutilizethedesigntargetedtotheSpartan2Edeviceandwewillrunthrough theFPGAtoPCBProjectWizard. 1. OpenthedesignSpiritLevel.PRJFPGinthefolder\Module3\Exercise1\ 2. OpentheconfigurationmanagerandmakesuretheNB1_6_XC2S300E6PQ208.Constraintis includedintheconfiguration.ClickOKtoclosetheconfigurationmanager. 3. OpentheFPGAschematicdocumentSL_FPGA_Complete.SchDoc. 4. Select ToolsFPGAtoPCBProjectWizard. 5. AttheSelecttheFPGAConfigurationstep,checktheUseExistingConfigurationoptionand specifyNB_Xilinx_Spartan2configuration.MakesureAssignUnconstrainedPortsisnot checked.
Figure4.UseanexistingconfigurationintheFPGAtoPCBProjectWizard
6. AttheConfigurethePCBProjectstep,specifythePCBProjectFileNameas SpiritLevel_2E.PrjPCB.
Figure5.SpecifythePCBprojectfilename.
7. AttheConfiguretheMainSheetstep,specifytheMainSheetFileNameas Auto_2E.SchDocandanyfurtheroptionsasdepictedinFigure6.ClickNexttocontinue.
Figure6.Mainsheetoptions.
8. AttheConfiguretheSheetSymbolSheetstep,checktheCreateSheetSymbolboxand specifytheSheetSymbolFileNameasSL_Top.SchDoc.ClickFinishtocompletethewizard.
Figure7.Symbolsheetoptions.
9. UseFileSaveAstosavethetwo,newlyautogeneratedschematicsheets 10. UseFileSaveProjectAstosavethenewlycreatedPCBprojectintothisdirectoryaswell. 11. Thebasicschematicfileshavenowbeencreatedandarereadyformodificationaccordingtothe specificprojectrequirements.Atthispoint,however,theFPGAprojectmaynotappearvisibly linkedtothePCBproject.RightclickonthePCBprojectintheprojectspanelandcompilethe design.Thedesigncompilerwillautomaticallychangetheprojectstructure.
Figure8.ProjectPanelaftercompiling.
12. Observethenewstructureofthecreatedschematicsheets. 13. Saveyourwork.
Modifyingtheautogeneratedsheet
Occasionallyitmaybenecessarytoperformmodificationstotheautogeneratedsheet.Thiswill causethePCBprojecttolosesynchronizationwiththeFPGAprojectandthedesignswillneedtobe resynchronizedthroughtheFPGAWorkspaceMap.Managingprojectsynchronizationisan automatedbutnotautomaticprocessandprojectsynchronizationcanonlybeperformedinone directionatonetimeie.designrevisionscanbepropagatedfromthePCBtotheFPGAorvice versabutnotbothwaysatthesametime.ExtremecautionshouldbeexercisedifboththePCBand FPGAprojectsarebeingworkedoninparallel. Situationsmightalsooccurinwhichadesignnevertotallysynchronizes.Thisiscommonlycaused whendifferencesexistinthenetnamingbetweenthePCBandFPGAschematics,or,when additionalcomponentsareconnectedtotheFPGAforpossiblefutureexpansion.Thelatter scenariomightincludetheadditionofaconnectorattheboardlevelthatisnotyetusedintheFPGA, andthusnotrepresentedintheFPGAdesign.IfthisoccursthePCBandFPGAdesignswillnot matchandthoughthismaycausethedesignstoappearoutofsync,thiswillnotaffecttheexisting functionalportionsofthedesign.
AwordaboutspecialfunctionFPGApins
SpecialFunctionPinsarehandledinaspecialwaywhencreatingtheautogeneratedsheet. Extremecaremustbeobservedtoensuretheirconnectivityismaintained.Asaruleofthumbitis besttoselecttheTietoindividualportsforSpecialFunctionPinsevenifyoudontintendtouse theminthefinaldesign.IfyouneedtouseanI/Opinthathasaspecialfunctionnetlabelattached toit,justremovethespecialfunctionnetlabelandreplaceitwiththenetlabelforthenetthatyoudo wishtobeconnected.Resynchronizethedesignasnecessary.

SelectinganyotheroptionotherthantheTietoindividualportswillcausespecialfunctionnet labelstoberippeduporrenamed.Beware!
Recreatingtheautogeneratedsheet
TheSynchronizedialogprovidesabuttontoRecreateAutogeneratedSheet.Thisfeatureshould beusedunderextremecare.IfthereareanyPCBdesignchangesthatareyettohavebeen propagatedbacktotheFPGAprojectthentheycanbedestroyedoncetheautogeneratedsheetis recreated.
Figure9.Recreatingtheautogeneratedsheetfromthesynchronizedialog.
Recallourpreviouswarningaboutthenatureofspecialfunctionpinsselectinganyotheroption otherthantheTietoindividualportswillcausespecialfunctionnetlabelstoberippedupor renamed.Beware!
2.Maintainingprojectsynchronization
MaintainingsynchronizationbetweenanFPGAprojectanditsparentPCBprojectisgreatly improvedthroughtheinternalsynchronizationmechanismsthatoperatewithinAltiumDesigner.Itis important,however,thatusersunderstandhowthissynchronizationprocessworkssothattheydont inadvertentlymakedesignchangesthatwilldefeatprojectsynchronization.

TheFPGAworkspacemap

Atanygiventimeduringthedesignprocess,thestatusofthelinkingbetweenFPGAandPCB projectscanbereadilycheckedbylaunchingtheFPGAWorkspaceMapdialog.Accesstothis dialogisprovidedbychoosingthecommandofthesamenamefromtheProjectsmenu,orby pressingthe buttonontheProjectspanel. IntheexamplebelowtheFPGAWorkspaceMapdisplaystherelationships(links)betweenvarious elementsofFPGAandPCBprojectsandthestatusoftheselinkswhetherthetwosidesofalink aresynchronizedanduptodateorwhethersomeactionisrequiredtoresynchronizethem.
Figure10.TheFPGAworkspacemapdialog.
Thevariouselementsinthetwoprojecttypesarelinkedinalogicalflowfromasoftcore microcontrollerplacedwithinanFPGAproject,toaPCBdesigndocumentwithinalinkedPCB project.Eachofthelinksaresummarizedbelow:

FPGAprojectsoftprocessor

TheSoftProcessorsregionofthedialogispurelyaddedforcompletenessandoffersataglance informationonthecoremicrocontroller(s)thatarebeingusedinaparticularFPGAproject.Thelink, assuch,isthereforecosmetic.Itwillalwaysbedisplayedassynchronized. 313
Schematicdocument(PCBproject)FPGAproject
ThislinkreflectsthesynchronizedstatusbetweentheFPGAcomponentinthePCBprojectandthe appropriateconfigurationintheFPGAproject.Whendeterminingthestatus,thesoftwareislooking foranynetrelatedchanges.
PCBdocumentschematicdocument(PCBproject)
ThislinkreflectsthesynchronizedstatusbetweentheFPGAComponentfootprintonthePCB documentandtheFPGAComponentsymbolontheschematicsheet,bothwithinthePCBproject.

Linkstatus

Alinkcanappearinoneoftwocolorsandhoveringoveralinkwillproduceatextualdescriptionofits status: Thegreenlinksignifiesuptodate(i.e.bothsidesare synchronized).Noactionisrequired. Theredlinksignifiesthatthetwosidesofthelinkarenot fullysynchronized(i.e.adesignchangehasbeenmadeon onesidebuthasyettobepassedtotheother).Clickingon aschematicFPGAprojectlinkwiththisstatuswillopenthe Synchronizedialog,fromwhereyoucanbrowseand matchanyunmatchedportsandpins.

Figure11.Determiningthelinkstatus
Whentwoelementsofthemapareshowntobeunsynchronized(i.e.thelinkbetweenthemisred), clickingonthelinkoritsassociatediconswillgiveaccesstoanumberofsynchronizationoptions. Thehintthatappearswhenhoveringoverthelinkwill,wherepossible,provideinformationonwhich directionsupdatesshouldbemadeinordertoachievesynchronization. Again,itmaybepossibleforadesigntonevertotallysynchronize. Thoughthismayoccur,itisnota signofafaileddesignitismerelythemethodwithwhichthesynchronizerevaluatesdifferences betweentheFPGAandPCBprojects.

Thesynchronizedialog

IftheFPGAWorkspaceMapdeterminesthattheprojectisnotsynchronized,aredlinkwillbe displayedbetweenthecorrespondingprojects.ClickingonthatlinkwillrevealtheSynchronize dialog.ThisdialogprovidesanautomatedmeansformaintainingsynchronizationbetweenFPGA andPCBprojects.Itisimportantatthispointthatthereaderunderstandthattheprocessis automatedbutnotautomaticandsomecareisrequiredtoensurethatrecentdesignchangesarenot overwritten.
Figure12.Thesynchronizedialogbox
TheSynchronizedialoghastwoprimaryregions.TheupperregioncontainsalistofPCBproject signalnamesthatcorrespondwithFPGAportnames.Thesesignalsarereferredtoasthematched signals.Informationconcerningthematchedsignalsisfurthersubdividedsothatsettingsrelatingto thePinnumberandElectricalTypecaneasilybecomparedbetweentheFPGAandPCBprojects. Thelowerregioncontainssignalsthatcantbe matchedbasedontheirsignalnamesotherwise knownasunmatchedsignals.TheSynchronizedialoghasnooptionbuttorequestuser interventioninknowinghowtomatchand/orhandlethesesignals. Projectsynchronizationcanonlybeperformedinonedirectionatonetimethatisdesignrevisions canbepropagatedfromthePCBtotheFPGAorviceversabutnotbothwaysatthesametime. WhereitisnecessarytoworkonboththeFPGAandPCBprojectsinparallel,astubprojectmay needtobecreatedtomanagesynchronizationbetweenthem.Moreinformationconcerningstub projectscanbefoundindocumentAP0102LinkinganFPGAProjecttoaPCBProject.pdf.
Determiningsynchronizationstatus
HowthedialogispopulateddependsontheextentofnetnamingintheFPGAcomponent schematic.Thefollowingisasummaryofthepossibilities: Anetlabelhasbeenassignedtoapinwiththesamenameasthatusedforthecorresponding portintheFPGAproject.Thepinnumberisdifferenttothat(ifspecified)intheassociated constraintfileand/ortheelectricaltypeforthepinisdifferenttothatoftheport.Astheportand pinhavethesamesignalname,theywillappearintheMatchedSignalslist.Theentrywillbe highlightedinredasthepinnumberand/orelectricaltypeisdifferent Anetlabelhasbeenassignedtoapinwiththesamenameasthatusedforthecorresponding portintheFPGAproject.Thepinnumberisidenticaltothatintheassociatedconstraintfileand theelectricaltypeforthepinisidenticaltothatoftheport.Astheportandpinhavethesame signalname,theywillappearintheMatchedSignalslist.Theentrywillbehighlightedingreen asthepinnumberandelectricaltypearealsothesame AnetlabelhasbeenassignedtoapinwithadifferentnametoanyoftheportsintheFPGA project.AnentryforthesignalnamewillappearintheUnmatchedPCBSignalslist. AllportsthathavenotbeenmatchedtopinswiththesamenamewillappearintheUnmatched FPGASignalslist. 315

Figure23.FPGASignalManager
Note:thelistofavailableI/Ostandardsiscontextsensitiveonlystandardsthatareapplicablefor thatparticularFPGAwillbeavailable.
FPGAsignalscanberapidlyupdatedingroupsbyusingthestandardshift/ctrlselecttechniqueand rightclickingoneoftheselectedrowstoaccessthepopupmenu.Additionalcolumnscanalsobe enabledfromthismenu. Afterdefiningthecharacteristicsfortheappropriatepinsofthedeviceasrequired,clickOKtoclose thedialog.TheEngineeringChangeOrderdialogwillappear,withthesettingsyoudefinelistedas aseriesofparameterstobeaddedtotheaffectedportconstraintentriesinthelinkedconstraintfile.
Figure23.Updatingtheconstraintfilewithsignalmanagerchanges
Thesechangesaretosignalcharacteristicsonlynotpinspecificchanges.Assuch,theyaffectonly therelevantentriesintheassociatedconstraintfile.TheschematicrepresentationoftheFPGA componentisnotaffectedandlaunchingtheFPGAWorkspaceMapdialogwillshowthelink betweentheschematiccomponentandtheFPGAprojectstillgreen,highlightingthefactthatthetwo sidesarefullysynchronized. Thechangeswillbestoredasconstraintsontheportsintheconstraintfile.Eachrequiredchange willbeperformedviaanECOandbyexecutingthechanges,thenewI/Ostandardswillbesavedin theconstraintfile.Anyfuturesynthesis/buildprocesswillthenusetheseconstraintsforprogramming theFPGA.(TheseconstraintswouldalsobeusedwhenperformingaSignalIntegrityanalysisonthe PCBproject).
Exercise2UsingtheFPGAsignalmanager
1. WiththeAuto_2E.SCHDOCdocumentopen,selectToolsFPGASignalManagerfromthe menu. 2. Modifythefollowingsignalsasdescribed: a. CLK_BRD: SlewRate=FAST b. JTAG_NEXUS_TCK:SlewRate=FAST c. JTAG_NEXUS_TDI:SlewRate=FAST d. JTAG_NEXUS_TDO:SlewRate=FAST,DriveStrength=24mA e. JTAG_NEXUS_TMS:SlewRate=FAST f. LCD_DB[0.7]:DriveStrength=24mA.
Figure234.Updatedsignalsinsignalmanager
3. SelectOKtoimplementthechangesandopentheEngineeringChangeOrderdialog.
Figure25.CommittingchangesmadeviatheFPGAsignalmanager
4. ValidateChangesandExecuteChangesandthenselectClose. 5. ChecktheFPGAWorkspaceMaptoensureyourprojectisstillsynchronised. 6. Saveyourwork.

4.ManuallylinkingFPGAandPCBprojects
InsomecircumstancestheFPGAdesignwillbedevelopedinparallelwith,butseparatefrom,the PCBdesign.InthesesituationsitmaybenecessarytomanuallylinktheFPGAandPCBdesigns togethertoensuresynchronization.
Figure24.ManuallylinkingFPGAandPCBprojectsthathavebeendevelopedseparately
IntheeventofanunlinkedPCBandFPGAproject,theFPGAWorkspaceMapmaylooksomething likethis:
Figure25.FPGAworkspacemapwithnolinkbetweenthePCBandFPGAprojects
Figure25showsthattheschematicandPCBdocumentsarecorrectlylinkedandsynchronized, howevernolinkcurrentlyexistsbetweentheFPGAprojectandthePCBproject.Thisisapparentby 323
thelackofconnectinglinesbetweentheSL1XilinxSpartanIIEPQ208Rev1.01.PRJPCB andtheFPGAprojectsandalsobythecommentNolinkedconfigurationbelowthe FPGA_51_Spirit_Level.PRJFPGicon.

Supporteddevices

InorderforAltiumDesignertoestablishalinkbetweenanFPGAprojectandaPCBproject,the FPGAcomponentinusebyeachprojectmustberecognizedandsupported.Alldevicespresentin thevendorlibrariesaresupportedforlinking. Thecomponentplacedontheschematicsheethastobeverifiedagainstthelistofsupported devicesinsomeway,beforeitisrecognizedanddisplayedintheFPGAWorkspaceMapdialog. ThisisachievedusingtheDesignItemIDfieldintheComponentPropertiesdialogfortheFPGA componentsymbolonthePCBschematic.Tobearecognizeddevice,theentryinthisfieldmustbe identicaltothatintheDevicefieldforthecorrespondingdeviceintheChoosePhysicalDevice dialog.ThisisdemonstratedinFigure26:
Figure26.Verificationthatdeviceissupported.

Creatingthelink

OncetheFPGAdeviceshavebeenrecognizedassupported,itispossibletocreatethemanuallink betweenthePCBandFPGAprojects.ThisisdoneusingtheStructureEditorintheProjectspanel inmuchthesamewayaswepreviouslylinkedanembeddedprojecttoanFPGAproject. ThelowerregionoftheProjectspanelcontainsallthevalidsubprojectsthatareopeninthe workspace.ThisincludesFPGA,embeddedandcoreprojects.ForFPGAprojects,theirdefined configurationswillalsobelistedalongwithconstraintfilesassociatedtoeach.Withinthisregionof thepanel,constraintfilescanbemovedfromoneconfigurationtoanother,simplybyperforminga draganddrop.Theconstraintfilewillbedisassociatedfromthesourceconfigurationandnewly associatedtothetargetconfiguration.Tocopyaconstraintfiletoanotherconfiguration,simplyhold downtheCTRLkeywhilstperformingthedraganddrop. Topurelydisassociateaconstraintfilefromaconfiguration,simplydragtheentryfortheconstraint intofreespacewithinthelowerregionofthepanel. DoubleclickingonaconfigurationentrywilllaunchtheConfigurationManagerdialogfortheparent FPGAproject. Linkingofthetwoprojectsisachievedinoneofthefollowingways: DraggingaconfigurationdefinedfortheFPGAprojectfromthelowerregionoftheProjects panelanddroppingitontotheentryfortheFPGAcomponentinthePCBproject DraggingtheFPGAproject fromeithertheupperorlowerregionsofthepanelanddropping itontotheFPGAcomponententryinthePCBproject

RightclickingontheentryfortheFPGAcomponentinthePCBprojectandchoosingtheSet SubProjectcommandfromthepopupmenuthatappears.ThiswillopentheSelectSub Projectdialog,fromwhereyoucanbrowsetoandopenthedesiredFPGAsubproject.This methodisparticularlyusefulifthedesiredsubprojectisnotcurrentlyopenintheProjectspanel.
Figure27.Linkingtwoprojectsviadraganddropinthestructureeditor
Ineachcase,asyoustarttodrag,thepossibleFPGAcomponententries(thatresideonaschematic sheet(s)withinoneormorePCBprojects)thatyoucanvalidlydropontoarehighlightedinpaleblue. Asthecursorpassesontoavalid'dropzone'itwillchangefromanoentrysymboltoadocument symbolasshownabove. IfyouchoosetodragtheentireFPGAprojectentryontothetargetschematicFPGAcomponentand morethanonevalidconfigurationexistsforthatprojecti.e.morethanoneconfigurationcontains anassociatedconstraintfiletargetingtheFPGAdevicetheSelectConfigurationdialogwill appearfromwhereyoucanchoosewhichspecificconfigurationtouse.
Figure28.Selectingaconfigurationtobelinked.
Whentherequiredconfigurationhasbeenassigned,theparentFPGAprojectwillbecomelinkedto thePCBprojectandisshowninthestructurehierarchyasasubdesignoftheschematicFPGA component.
Figure29.StructuralviewofaFPGAprojectlinkedtoaPCBproject.
Tobreakthelinkbetweenthetwoprojects,simplyclickanddragtheFPGAprojectentryintofree spacewithinthepanel(belowthelastentry). Nowthataconfigurationhasbeenlinked,theFPGAandPCBprojectsbecomelinkedandtheFPGA WorkspaceMapdialogwilldisplayalinkbetweentheschematiccomponentinthePCBprojectand theFPGAproject.
Figure30.FPGAworkspacemapshowingthesynchronizationstatusoflinkedprojects.
Theprojectsarenowlinked,buttheyareyettobesynchronized.
LinkinganautogeneratedsheettoanexistingPCBproject
IfyouselecttheoptiontoCreateSheetSymbol inthelaststageoftheFPGAtoPCBProject WizardasheetcontainingasheetsymboloftheFPGAprojectwillbecreated.Thiscanbeusedas thebasisforbuildingacompleteschematictodescribethetargetPCBhardware. Alternatively,ifyouareworkingwithaPCBprojectthatalreadyexists,youwillprobablyalreadyhave asheetwithmanysheetsymbolsleadingtovariousothersubsheets.Inthiscaseyoumaysimply wishtoconnectanexistingsheetsymboltotheautogeneratedsheet.Thisscenariowouldlikely occurwhereithasbeendecidedtochangetheFPGAdeviceonanexistingPCBdesign.Inthis case,youwouldopentheSheetSymboldialogfortheexistingsheetsymbolandmanuallyeditthe Filenamefieldtopointtotheautogeneratedsheet.
Figure31.Manuallylinkinganautogeneratedsheettoasheetsymbol.
Exercise3ManuallylinkingaPCBandFPGAproject
1. OpentheSLRev1.01.PrjPCBandtheFPGA_U1\SpiritLevel.PRJFPGprojectsatthe sametime. 2. OpentheFPGAWorkspaceMapandverifythatthereisnolinkbetweentheFPGAandPCB projects. 3. ChangetotheStructureEditorandestablishalinkbetweenthePCBandFPGAprojects. 4. ReopentheFPGAWorkspaceMapandverifythatalinknowexists. 5. ClickontheredlinkbetweentheFPGAandPCBprojectstoresolvetheunsynchronisedsignals. 6. Saveyourwork.

5.Pinswapping

5.1 PinswappinginthePCBdocument
ManypeoplemaywonderwhyseparateAutoandManualschematicfilesarecreatedintheFPGA toPCBProjectWizardprocess.TheAutofilecreatestheactualFPGAschematicsymbolandlinks therelevantpinstoports.TheManualfilecontainsasheetsymbolthatcontainsalloftheports definedintheAutofile.TheportlinkagebetweentheAutoandManualfilesisalogicalonerather thanphysical.ThisabstractionmakesitpossibleforthetooltoperformpinswappingontheAuto schematicwithoutaffectingconnectivityontheManualfile. TheporttophysicalpinassignmentsforanFPGAdevicearedefinedinaconstraintfile.Youcan manuallydefinetheassignments,orlettheplaceandroutetoolsassignthemandthenimportthe assignmentsbackintotheconstraintfile.However,oncetheFPGAisplacedonthePCB,pin assignmentsoftenneedtobechangedinordertooptimizethePCBroutingandthenthesechanges backannotatedtotheFPGAproject,tokeepthetwoprojectssynchronized.

SetupPinswappingmethods

Therearetwowaysthatpinswapscanberepresentedattheschematiclevel.Thesearecontrolled fromtheOptionstaboftheprojectoptionsdialogbox.Inbothcases,theactualwiringonthe schematicwillnotbealteredjustitsconnectivity.
Figure32.Settingpinandpartswappingmethods.
Adding/RemovingNetLabelswillmovenetlabelsontheswappedpinsornetstoreflectthe changesthatweremadeduringpinswapping.Inthiscase,theschematicsymbolwillbeleft unchanged. ChangingSchematicPinswillallowAltiumDesignertomovethepinsonschematicsymbols accordingtothepinswapsperformedatthePCBlevel. Wherebothoptionshavebeenchecked,AltiumDesignerwilldefaulttoswappingnetlabels.Ifno labelsexistonthenets,itwillswappinsontheschematicsymbols.

SetupSwapgroups

Beforepinscanbeswappedwitheachother,itisimportanttofirstsetupswapgroupIDs,asitmay notbedesirable(oracceptable)forallpinstobeswappedwithoneanother.WhileallI/Opinswithin anFPGAcantheoreticallybeswappedtogiveabetterlayoutforrouting,conditionsmaydictate otherwise.Firstly,somepinshaveadditionalspecialfunctions(clockpins,configpinsandVREFpins tonameafew),anditmaybepreferabletoreservethesefortheirspecialpurpose.Secondly,setting limitationsherewillallowanyswappingprocesstoobeythebankingandI/Ostandardsrequirements asdescribedearlier.Forthisreason,itmaybedesirableforpinsinacertainbanktoonlybe swappablewitheachother(orperhapsotherbankswithcompatibleI/Ostandards). SwapgroupsmaybedefinedatschematicorPCBlevel,asdescribedbelow.

Settingswapgroupsintheschematic
Todefineswapgroupsintheschematiclevel,selecttheToolsConfigurePinSwappingoption. Theresultingdialogboxwilllistallcomponentsinthedesign.
Figure33.Settingupswapgroupsforvariouscomponents.
SelectthecomponentyouwishtodefineswapgroupsforandclickontheConfigureComponent buttonorsimplydoubleclickthecomponentinthelisttoaccesstheConfigurePinSwappingFor dialog.
SettingswapgroupsinthePCB
RightclickthecomponentyouwishtosetupforpinswappingandselecttheComponent Actions>>ConfigurePin/PartSwapping. SelecttheTools>>Pin/PartSwapping>>ConfigureoptiontoaccesstheConfigure SwappingInformationInComponentsdialogbox(seefigureabove). Selectthe componentyouwishtodefineswapgroupsforandclickontheConfigureComponent buttontoaccesstheConfigurePinSwappingFor dialog.
Figure34.SpecifyingswapgroupIDsinthepinswapmanager.
AllpinswiththesameswapgroupIDcanbefreelyswapped. AssigneachI/Opinonthedevicetotherequiredswapgroup.Eithermanuallyenterthelabelfor thegroupdirectlyintheSwapGroupIDfield,orusetherightclickmenutoassignswapgroups byvariouspinattributes.
SetupEnablingcomponentsforpin/partswapping
Onceswapgroupshavebeendefined,onemorestepisrequiredbeforetheactualpinswap.Altium Designerwillonlyswappinsforcomponentswhichhavebeenspecificallymarkedasallowingpin swapping.Todothisforagivencomponent,selectitinPCBmodeandviewthecomponents properties.Then,underswappingoptions,makesurethatEnablePinSwapshasbeenenabled. Dothisforeachcomponentthatrequirespinswapping.
Figure35.Enablingpinswapsforacomponent.

Swapping

HavingdefinedtheSwapGroupIDsasappropriate,theactualprocessofswappingpinscannowbe performed.WiththePCBdocumentactive,simplyclickonthePin/PartSwappingentryunderthe Toolsmenuandchooseamethodtoswappins. TheAutomaticNet/PinOptimizermaybeusedonanyorallcomponentsinadocumentandisnot limitedtoFPGAcomponents.Thispinswapperwillattempttofindtheoptimalpinallocationsfor routing,whilstobeyingthepinswapGroupIDspreviouslysetup. Itrunsthroughatwostage process:thefirststageisafastsinglepassoptimizerthatwillattempttominimizecrossoversand connectionlengths,whilethesecondstageisaniterativeoptimizerwhichperformsmultiplepasses. Thesecondstageisoptional,asthetimerequiredfortheiterativeprocessincreasessignificantly whenattemptingtooptimizemultiplecomponents.
Figure36.Ratsnestpriortoautomatedpinswapping
ThetwoPCBsnapshotsdepictedaboveandbelowshowhowtheautopinswappingtoolcanbe usedtogreateffecttoobtainanoptimizedsetofpinallocationsfromwhichtoroute.Inthiscase,all I/OpinsontheFPGAdevicehavebeenassignedthesameswapgroupID.

ExecutethechangesinthesubsequentEngineeringChangeOrderdialogthatappears TheSynchronizedialogwillreappear,showingnodifferencesintheMatchedSignalslist (appearingtotallygreen).IntheFPGAWorkspaceMapdialog,thelinkwillhavereturnedtoitsfully synchronizedstatus(Green).

Exercise4Pinswapping

Thisexercisecontinuesonfromworkdoneinthepreviousexercise. 1. OpenSLRev1.01NoRoutes.PcbDoc. 2. ChecktheAdding/RemovingNetLabelsoptionintheoptionstaboftheprojectoptionsdialog box.LeavetheChangingSchematicPinsoptionunchecked. ClickOKtoclosetheproject optionsdialog. 3. Select ToolsPin/PartSwappingConfigure 4. SelecttheFPGAcomponent,andConfigureComponent 5. EnsureShowI/OPinsOnlyisselectedfromthedropdownlistonthebottomleftofthedialog box. 6. CreateauniqueSwapGroupID foreachofthefollowingsignals: a. I\N\I\T\ b. DIN 7. AllotherIOpinscanbeplacedintoasingleswapgroupcalledgeneral_IO.
Figure44.SpecifyswapgroupIDsforalloftheIO
8. SelectOK. 9. ZoomintoviewtheFPGAdeviceinthecentreofthePCB. 10. DoubleclickontheFPGAdevice.WhentheComponentU1dialogappears,changethe Rotationto180degreesandclickOK. 11. Usetheautomaticpinswappingtorearrangethepins. 12. Waitforamomentforthesystemtoperformthepinswapping. 13. GototheDesign menu,andselectUpdateSchematicstobringthechangesacrosstothePCB schematics. 14. OpentheFPGAWorkspaceMap,andresolveanyunsynchronisedsignals.ThePCBshouldbe themasterdocumentatthisstagesoselectUpdatetoFPGAwhenperforminganychanges. 15. Saveyourwork.

6.Commissioningthedesign

OneoftheadvantagesofhavingahardwareplatformsuchastheDesktopNanoBoardatyour disposalduringdevelopmentisthatyoucanperformastagedmigrationofthedesignontoacustom targetPCB.Evenifcomponentsforthetargethavenotyetarrived,initialcommissioningcanbegin bycouplingthetargettotheNanoBoardandusingNanoBoardresourcesasasubstituteforthe missingcomponents.

Exercise5Migrationstage1

Inthisexercise,weconsiderthescenariowhereoneormoreofthetargetresourcesareyettobe placed.Inthiscasewemaychoosetorunthemainapplicationfromthetargetboardbutuse peripheralsavailableontheNanoBoardtotestourapplication.Forthisexercisetofunctioncorrectly wewillneedtoloaddesignsontoboththeNanoBoardandTargetplatforms. 1. Locatethe.\Module3\Exercise5\directoryandload SLRev1.01.PrjPCBaswellasFPGA_NB\SpiritLevel_NB.PRJFPG 2. ObservethecontentsoftheschematicdocumentSL_FPGA_NB.SchDoc.Noticehowthe NEXUSJTAGConnectorneedstobepresentandtheTDI/TDOloopmadetoensurethatthe JTAGsoftchainisnotbrokenwithintheNanoBoarddevice. 3. SwitchofftheDesktopNanoBoardandtargetboardpower. 4. Usinga10pinribboncable,connectHDR1onthetargetboardtoUSERBOARDAonthe NanoBoard. 5. Usinga20pinribboncable,connectHDR2onthetargetboardtoUSERHEADERAonthe NanoBoard. 6. EnsuretheXaxisjumperisremoved fromthetargetboard. 7. EnsureallDIPSwitchesonthetargetboardaresettotheONposition. 8. PlacetheCONFIGjumperonthetargetboard. 9. SwitchontheNanoBoardandtargetboard. 10. OpentheDevicesviewandverifytheexistenceoftwoFPGAdevices(andoneconfiguration device)intheHardChain.Thefirstdevicewillalways betheNanoBoarddevice. 11. BuildanddownloadtheSpiritLevel_NB/NB_BaseconfigurationtotheNanoBoarddevice. 12. BuildanddownloadtheSpiritLevel/Tgt_Spartan2configurationtothetargetboard device. 13. ObservethestatusoftheProcessorinthesoftchain.If,afterdownloadingbothprojects,this deviceislistedasMissing,itislikelythesoftchainisbrokensomewhere.Verifythataloop betweenJTAG_NEXUS_TDIandJTAG_NEXUS_TDOexistsontheSL_FPGA_NB.SchDoc. Rebuildtheprojectifnecessary. 14. SettheNanoBoardclockfrequencyto6MHzandensurethatDIPSwitch8ontheNanoBoardis ON.Observethedisplayonthetargetboard.AssertoneortwooftheNanoBoardslowerDIP SwitchesandseewhatchangeoccursintheTargetsLCD.IfthetargetboardLEDsarenot flashingthenthisindicatesitisnotreceivingasignalfromtheNanoBoard.Ensurealloutputs fromtheDigitalIOBonthetargetboardare0andcheckthewiringbetweentheNanoBoardand thetargetboard.Alsoensuretherespectiveprojectshaveloadedcorrectly.