Altium Designer 6-module 7-fpga TO PCB
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Manual
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Altium Designer 6-module 7-fpga TO PCB
User reviews and opinions
| decebal |
3:20pm on Friday, October 22nd, 2010  |
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| larrysfo |
7:39pm on Wednesday, October 6th, 2010 |
| The electronic computer Asus 1,000 hours, the computer Intel atom is very cheap, very easy to carry. hola como andas espero que bien loco esta computadora tiene una buen placa de videoy una gran memoria ram pero el gran problema es que la placa de vid... General good none | |
| Koekiemonster |
10:42am on Monday, October 4th, 2010 |
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| XRumer879 |
9:54am on Thursday, September 23rd, 2010 |
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| Neil in Washington |
7:00am on Thursday, September 23rd, 2010 |
| This Netbook is a more expensive than other Netbooks, but this one should really be classified as a smaller Notebook. I love it. I agree with all the other positive reviews out there. battery life, bright screen, easy to use, Fast/High Speed, Memory, size & weight. | |
| oldsalt100 |
10:19am on Monday, August 2nd, 2010  |
| Being a disabled woman bringing my regular laptop is very difficult when I travel. This is very light weight and has the built in WiFi. Easy set up, not much preloaded junk sofware. It does every thing I expected from a netbook: portability, good battery life. I like it, very good machine for the price and it does not have issues like freezing up or bad battery Adequate Storage","Comfortable Keyboard". | |
| dotmatrixpc |
6:43pm on Thursday, July 29th, 2010 |
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| altu |
6:46am on Tuesday, June 29th, 2010 |
| This netbook is great. I needed something small to bring to class and meetings and this netbook is perfect. I really like this Netbook. The keyboard and lack of true Page Up/Dn keys takes some getting used to. | |
| danger4 |
3:42pm on Sunday, June 27th, 2010  |
| Since this units release a couple of years ago, I have purchased 6 of these netbooks either for myself, for others, or for work purposes. I bought this for traveling and for occasionally use for work. Ive had no trouble connecting to wifi at hotels or at home. XP is ok. | |
| Ubul |
5:30am on Wednesday, June 23rd, 2010 |
| Bought it a year ago and used it most often f... Exterior looks fine. Easy to carry over. Low price Running is slow and noisy. I have had this unit for nearly a year now. It has traveled with me to fourteen states and two countries. | |
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Documents
FPGAtoPCB TrainingModule
DocumentVersion1.2,February2008 Software,documentationandrelatedmaterials: Copyright2008AltiumLimited. Allrightsreserved.Youarepermittedtoprintthisdocumentprovidedthat(1)theuseofsuchisfor personaluseonlyandwillnotbecopiedorpostedonanynetworkcomputerorbroadcastinany media,and(2)nomodificationofthedocumentismade.Unauthorizedduplication,inwholeorpart, ofthisdocumentbyanymeans,mechanicalorelectronic,includingtranslationintoanother language,exceptforbriefexcerptsinpublishedreviews,isprohibitedwithouttheexpresswritten permissionofAltiumLimited.Unauthorizedduplicationofthisworkmayalsobeprohibitedbylocal statute.Violatorsmaybesubjecttobothcriminalandcivilpenalties,includingfinesand/or imprisonment. Altium,AltiumDesigner,BoardInsight,CAMtastic,CircuitStudio,DesignExplorer,DXP,LiveDesign, NanoBoard,NanoTalk,Nexar,nVisage,PCAD,Protel,SimCode,Situs,TASKING,andTopological AutoroutingandtheirrespectivelogosaretrademarksorregisteredtrademarksofAltiumLimitedor itssubsidiaries. Microsoft,MicrosoftWindowsandMicrosoftAccessareregisteredtrademarksofMicrosoft Corporation.OrCAD,OrCADCapture,OrCADLayoutandSPECCTRAareregisteredtrademarksof CadenceDesignSystemsInc.AutoCADisaregisteredtrademarkofAutoDeskInc.HPGLisa registeredtrademarkofHewlettPackardCorporation.PostScriptisaregisteredtrademarkofAdobe Systems,Inc.Allotherregisteredorunregisteredtrademarksreferencedhereinarethepropertyof theirrespectiveownersandnotrademarkrightstothesameareclaimed.
Module3
AltiumDesignerTraining
FPGAtoPCB
FPGAtoPCBTrainingModule
1. FromFPGAprojecttoPCBproject... 32 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 2. 2.1 2.2 2.3 2.4 3. 3.1 3.2 4. 4.1 4.2 4.3 4.4 5. 5.1 5.2 5.3 5.4 6. 6.1 6.2 6.3 6.4 6.5 7. Understandingthedocumentstack... 32 UsingtheFPGAtoPCBprojectwizard.. 34 ChoosingtheFPGAconfiguration... 34 InitialFPGApinassignments... 35 ChoosingthetargetPCBproject... 37 ConfiguringtheFPGAcomponentschematicsheet. 37 Configuringthesheetsymbolschematicsheet.. 38 Exercise1RunningtheFPGAtoPCBprojectwizard. 39 Modifyingtheautogeneratedsheet... 311 AwordaboutspecialfunctionFPGApins.. 311 Recreatingtheautogeneratedsheet.. 312 TheFPGAworkspacemap... 313 Thesynchronizedialog.... 314 Synchronizingmatchedsignals... 316 Synchronizingunmatchedsignals... 317 ConfiguringI/Ostandards... 320 Exercise2UsingtheFPGAsignalmanager.. 321 Supporteddevices... 324 Creatingthelink.... 324 LinkinganautogeneratedsheettoanexistingPCBproject.. 327 Exercise3ManuallylinkingaPCBandFPGAproject.. 327 PinswappinginthePCBdocument... 328 PinswappingintheFPGAproject... 335 PinswappinginbothPCBandFPGAprojects.. 336 Exercise4Pinswapping.. 336 Exercise5Migrationstage1... 338 Exercise6Migrationstage2... 339 Exercise7Calibration... 339 Exercise8BootstrappingtheFPGA.. 340 Exercise9Revertingtotestmode.. 341
Maintainingprojectsynchronization... 313
ConfiguringFPGAI/O.... 320
ManuallylinkingFPGAandPCBprojects.. 323
Pinswapping.... 328
Commissioningthedesign... 338
Review..... 342
AltiumDesignerTrainingModule
1.FromFPGAprojecttoPCBproject
Atsomepointinthelifeofalldesignstherecomesapointwheretheymustmovefromthelaboratory prototypetoproduction.IfadesignhasbeensuccessfullyrunningontheDesktopNanoBoard,the processofmigratingfromanFPGAbasedprojecttoaPCBbasedprojectcontainingtheFPGA projectissimplifiedthroughtheuseoftheFPGAtoPCBProjectWizard.Thismethod automaticallylinksthetwoprojectsandmaximizessynchronizationfunctionalitybetweenthem. ProjectsynchronizationisimportantasitensuresthatdesignchangesmadetoeitherthePCB documentorFPGAprojectarepropagatedinacontrolledfashion. Overtheremainderofthecoursewewilllookatmovingadesignfromthetestenvironment,tothe targetPCB.Todothiswewilluseadesignthathasalreadybeencompletedforus,aDigitalSpirit Level.TheFPGAportionofthisdesignincludesasoftcoreTSK51processorwhichtakesasitsinput theoutputofanaccelerometerandoutputsasmallbubbleonanLCDmimickingatraditionalspirit level.
Understandingthedocumentstack
Figure1.Visualizationofhowthevariousprojectdocumentsarestacked
SynchronizationbetweenPCBandFPGAprojectsiscarriedoutandmaintainedbyestablishinga linkbetweenthetoplevelportsintheFPGAprojectspecifiedintherelevantconstraintfileand thecorrespondingpinsontheFPGAcomponentschematic.Linkingisachievedusingthesignal name.ThenamegiventotheportintheFPGAprojectmustbethesameasthenetlabelassigned tothecorrespondingpinontheschematiccomponentinthePCBproject. Figure1providesa visualizationofhowthevariousdocumentsinanFPGA/PCBprojectstackarelinkedtogether.
FPGA_Top.SchDoc
FPGAproject
ThetoplevelFPGAschematicdocument mustcontainportsatthepointwhere signalsareconnectedtophysicalpinson theFPGAdevice.Thenameoftheportsis importantastheywillbeusedinthe constraintsfile. FPGA.Constraint FPGAproject
TheConstraintfiledefinesthephysicalpin numberthatportsdefinedinthetoplevel FPGAschematicwillbeconnectedto.This isreferredtoasaportnametoFPGApin numbermapping.Portnamesdeclaredin theconstraintfilemust matchthose includedinthetoplevelFPGAschematic document. FPGA_Auto.SchDoc PCBproject
Theautogeneratedschematicsheetis createdfrominformationcontainedinthe FPGAconstraintfile.Essentiallythe autosheetisaschematicrepresentationof theporttopinmappingsmadebythe constraintfile.Porttopinconnectivityon theautosheetisaccomplishedthroughthe useofnetlabelsi.e.anetlabelis attachedtowiresconnectedtotheportson thesheetandacorrespondingnetlabelis alsoattachedtothedevicepin. FPGA_Manual.SchDoc PCBproject
Anoptionalmanualsheetisgeneratedas partoftheFPGAtoPCBprojectwizard. Thismanualsheetcontainsasheetsymbol oftheautosheettheportsonthe autosheetareconnectedtocorresponding portsonthesheetsymbol.Connectingto thissheetsymbolratherthandirectlytothe FPGAsymbolintroducesanimportant abstractionlayer.Thislayerfacilitateseasy (automated)updatestotheprojectifthe deviceorpinallocationsshouldchangeas theprojectdevelops. TargetPCB.PCBDoc PCBproject TheFPGAdepictedintheautosheetand abstractedonthemanualsheetwill eventuateintoaphysicaldeviceonthefinal PCB.Thephysicalpinsofthisdevicewill beconnectedtoportsasdescribedinthe autosheet.
Figure2.Theroleofthevariousdocumentsintheprojectstack
UsingtheFPGAtoPCBprojectwizard
WithaschematicdocumentintheFPGAprojectopenastheactiveviewinthemaindesignwindow, simplychoosetheToolsFPGAToPCBProjectWizardentryfromthemenu.Thewizardwill appear,asshowninFigure:
Figure3.TheFPGAToPCBprojectwizard.
ChoosingtheFPGAconfiguration
Thesecondpageofthewizardallowsyoutochoosetheconfigurationthatwillbeusedfortargeting theFPGAdesigntothePCB.TheconfigurationusesaconstraintfilethatdefinestheFPGAdevice tobeusedanditsassociatedpinmappings. TheconfigurationcaneitherbeanexistingonethatyouhavealreadydefinedaspartoftheFPGA project,oranewone,generatedbythewizard.Inthecaseofthelatter,thewizardwillgeneratea configurationandaddtoitanewconstraintfile.Thesewillhavedefaultnames(PCB ConfigurationandPCBConstraints.Constraintrespectively)andtheconstraintfilewillbe storedinthesamelocationastheFPGAprojectfile(*.PrjFPG),unlessotherwisespecified.
Figure4.Wizardbasedconfigurationgeneration.
Theconstraintfilethatisaddedtotheconfigurationwillcontainatargetdevicedefinitionforthe FPGAproject,accordingtothedeviceyouselectintheSelectedDevice field.Youcanbrowsefora devicebyclickingthebutton,totherightofthefield.ThiswillopentheChoosePhysicalDevice dialog,fromwhereyoucanperusefromanumberofdevicesavailableacrossaspectrumofFPGA vendordevicefamilies.
Figure5.BrowsingfortherequiredFPGAdevice.
InitialFPGApinassignments
ThesecondpageoftheFPGAtoPCBProjectwizardgivesyouthechoiceofwhattodowith unconstrainedportsi.e.portsthathavenotbeentiedtoaspecificpinonthetargetdevice.The decisionastohowthesepinsareassignedissomewhatarbitraryandsothereareanumberofways ofdoingthis:
Importingpinfilefromvendorplaceandroutetools
Clearlyforthisoptiontobeavailablethedesignmusthavepreviouslybeenbuiltforthecurrent deviceandaconstraintfileandconfigurationmustalreadyexist.Fortotallynewdesignsthisisthe preferreddesignpath.Itensuresthatthevendortoolsaregiventhemostopportunitytooptimizethe designwithoutbeingundulyconstrainedanditensuresthattheselecteddeviceiscapableof supportingthedesign.Inthiscase,thepinassignmentsshouldbemadepriortorunningtheFPGA toPCBprojectwizard.Withaconstraintfileopeninthemainwindow,selectDesignImportPin File fromthemenutoimportthevendorpinfile.Thefollowingdialogboxwillappear:
Figure6.Selectingconstraintstobeimportedfromthevendortools
AssigningpinsduringtheFPGAtoPCBwizard
ProbablythequickestandsimplestwaytoallocatepinsiswhilstexecutingtheFPGAtoPCBproject wizard.SelecttheAssignUnconstrainedPortsonthesecondpageofthewizard.Asthewizard executesitwillautomaticallyallocatepinnumberstounallocatedportsupdatingtheconstraintfile andautogeneratedsheetasitgoes.
Figure7.AssigningunconstrainedportsaspartoftheFPGAtoPCBprojectwizard
AssigningunconstrainedsignalsfromtheFPGAsignalmanager
ItisalsopossibletoallocateunconstrainedsignalsbyselectingtheAssignUnconstrainedSignals buttonintheFPGASignalManagerdialog(Figure8).
Figure8.UsingtheFPGAsignalmanagertoassignunconstrainedsignals
Performingpinassignmentsviathismethodisprobablylessadvisableasitdoesnotgivetheuser thechoicewhichconstraintfile(projectortarget)recordsthepinallocations.Furthermore,an additionalstepisrequiredafterthisonetoresynchronizethenetlabelsintheautogeneratedsheet.
Assigningsignalsmanuallyintheautogeneratedsheet
Thisisthemostlaboriousmethodandgenerallynotadvisable.Usingthismethodrequiresthe designertomanuallyenterthenetnamesforallportsontotheautogeneratedsheet.Asecond synchronizationstepisalsorequiredtopropagatethepinassignmentsintotheconstraintsfile.
ChoosingthetargetPCBproject
AfterchoosingtheFPGAconfiguration,theactualtargetPCBprojectmustnowbedefined.Simply accepttheWizard'sgenerationofanewproject(PCBProject1.PrjPCB),orbrowsetoandselect anexistingproject.InthecaseofanewPCBproject,thefilewillbestoredinthesamelocationas theFPGAproject.
ConfiguringtheFPGAcomponentschematicsheet
WhetherthePCBprojectalreadyexistsorisbeingnewlycreated,therelationshipbetweenthe FPGAprojectanditscorrespondingcomponentinthePCBprojecthastobemanagedinsomeway. Thisisachievedusingadedicated,autogeneratedschematicsheet,referredtoasthe'MainSheet' intheWizard.
Exercise1RunningtheFPGAtoPCBprojectwizard
InthisexercisewewillutilizethedesigntargetedtotheSpartan2Edeviceandwewillrunthrough theFPGAtoPCBProjectWizard. 1. OpenthedesignSpiritLevel.PRJFPGinthefolder\Module3\Exercise1\ 2. OpentheconfigurationmanagerandmakesuretheNB1_6_XC2S300E6PQ208.Constraintis includedintheconfiguration.ClickOKtoclosetheconfigurationmanager. 3. OpentheFPGAschematicdocumentSL_FPGA_Complete.SchDoc. 4. Select ToolsFPGAtoPCBProjectWizard. 5. AttheSelecttheFPGAConfigurationstep,checktheUseExistingConfigurationoptionand specifyNB_Xilinx_Spartan2configuration.MakesureAssignUnconstrainedPortsisnot checked.
Figure4.UseanexistingconfigurationintheFPGAtoPCBProjectWizard
6. AttheConfigurethePCBProjectstep,specifythePCBProjectFileNameas SpiritLevel_2E.PrjPCB.
Figure5.SpecifythePCBprojectfilename.
7. AttheConfiguretheMainSheetstep,specifytheMainSheetFileNameas Auto_2E.SchDocandanyfurtheroptionsasdepictedinFigure6.ClickNexttocontinue.
Figure6.Mainsheetoptions.
8. AttheConfiguretheSheetSymbolSheetstep,checktheCreateSheetSymbolboxand specifytheSheetSymbolFileNameasSL_Top.SchDoc.ClickFinishtocompletethewizard.
Figure7.Symbolsheetoptions.
9. UseFileSaveAstosavethetwo,newlyautogeneratedschematicsheets 10. UseFileSaveProjectAstosavethenewlycreatedPCBprojectintothisdirectoryaswell. 11. Thebasicschematicfileshavenowbeencreatedandarereadyformodificationaccordingtothe specificprojectrequirements.Atthispoint,however,theFPGAprojectmaynotappearvisibly linkedtothePCBproject.RightclickonthePCBprojectintheprojectspanelandcompilethe design.Thedesigncompilerwillautomaticallychangetheprojectstructure.
Figure8.ProjectPanelaftercompiling.
12. Observethenewstructureofthecreatedschematicsheets. 13. Saveyourwork.
Modifyingtheautogeneratedsheet
Occasionallyitmaybenecessarytoperformmodificationstotheautogeneratedsheet.Thiswill causethePCBprojecttolosesynchronizationwiththeFPGAprojectandthedesignswillneedtobe resynchronizedthroughtheFPGAWorkspaceMap.Managingprojectsynchronizationisan automatedbutnotautomaticprocessandprojectsynchronizationcanonlybeperformedinone directionatonetimeie.designrevisionscanbepropagatedfromthePCBtotheFPGAorvice versabutnotbothwaysatthesametime.ExtremecautionshouldbeexercisedifboththePCBand FPGAprojectsarebeingworkedoninparallel. Situationsmightalsooccurinwhichadesignnevertotallysynchronizes.Thisiscommonlycaused whendifferencesexistinthenetnamingbetweenthePCBandFPGAschematics,or,when additionalcomponentsareconnectedtotheFPGAforpossiblefutureexpansion.Thelatter scenariomightincludetheadditionofaconnectorattheboardlevelthatisnotyetusedintheFPGA, andthusnotrepresentedintheFPGAdesign.IfthisoccursthePCBandFPGAdesignswillnot matchandthoughthismaycausethedesignstoappearoutofsync,thiswillnotaffecttheexisting functionalportionsofthedesign.
PCBdocumentschematicdocument(PCBproject)
ThislinkreflectsthesynchronizedstatusbetweentheFPGAComponentfootprintonthePCB documentandtheFPGAComponentsymbolontheschematicsheet,bothwithinthePCBproject.
Linkstatus
Alinkcanappearinoneoftwocolorsandhoveringoveralinkwillproduceatextualdescriptionofits status: Thegreenlinksignifiesuptodate(i.e.bothsidesare synchronized).Noactionisrequired. Theredlinksignifiesthatthetwosidesofthelinkarenot fullysynchronized(i.e.adesignchangehasbeenmadeon onesidebuthasyettobepassedtotheother).Clickingon aschematicFPGAprojectlinkwiththisstatuswillopenthe Synchronizedialog,fromwhereyoucanbrowseand matchanyunmatchedportsandpins.
Figure11.Determiningthelinkstatus
Whentwoelementsofthemapareshowntobeunsynchronized(i.e.thelinkbetweenthemisred), clickingonthelinkoritsassociatediconswillgiveaccesstoanumberofsynchronizationoptions. Thehintthatappearswhenhoveringoverthelinkwill,wherepossible,provideinformationonwhich directionsupdatesshouldbemadeinordertoachievesynchronization. Again,itmaybepossibleforadesigntonevertotallysynchronize. Thoughthismayoccur,itisnota signofafaileddesignitismerelythemethodwithwhichthesynchronizerevaluatesdifferences betweentheFPGAandPCBprojects.
Thesynchronizedialog
IftheFPGAWorkspaceMapdeterminesthattheprojectisnotsynchronized,aredlinkwillbe displayedbetweenthecorrespondingprojects.ClickingonthatlinkwillrevealtheSynchronize dialog.ThisdialogprovidesanautomatedmeansformaintainingsynchronizationbetweenFPGA andPCBprojects.Itisimportantatthispointthatthereaderunderstandthattheprocessis automatedbutnotautomaticandsomecareisrequiredtoensurethatrecentdesignchangesarenot overwritten.
Figure12.Thesynchronizedialogbox
TheSynchronizedialoghastwoprimaryregions.TheupperregioncontainsalistofPCBproject signalnamesthatcorrespondwithFPGAportnames.Thesesignalsarereferredtoasthematched signals.Informationconcerningthematchedsignalsisfurthersubdividedsothatsettingsrelatingto thePinnumberandElectricalTypecaneasilybecomparedbetweentheFPGAandPCBprojects. Thelowerregioncontainssignalsthatcantbe matchedbasedontheirsignalnamesotherwise knownasunmatchedsignals.TheSynchronizedialoghasnooptionbuttorequestuser interventioninknowinghowtomatchand/orhandlethesesignals. Projectsynchronizationcanonlybeperformedinonedirectionatonetimethatisdesignrevisions canbepropagatedfromthePCBtotheFPGAorviceversabutnotbothwaysatthesametime. WhereitisnecessarytoworkonboththeFPGAandPCBprojectsinparallel,astubprojectmay needtobecreatedtomanagesynchronizationbetweenthem.Moreinformationconcerningstub projectscanbefoundindocumentAP0102LinkinganFPGAProjecttoaPCBProject.pdf.
Determiningsynchronizationstatus
HowthedialogispopulateddependsontheextentofnetnamingintheFPGAcomponent schematic.Thefollowingisasummaryofthepossibilities: Anetlabelhasbeenassignedtoapinwiththesamenameasthatusedforthecorresponding portintheFPGAproject.Thepinnumberisdifferenttothat(ifspecified)intheassociated constraintfileand/ortheelectricaltypeforthepinisdifferenttothatoftheport.Astheportand pinhavethesamesignalname,theywillappearintheMatchedSignalslist.Theentrywillbe highlightedinredasthepinnumberand/orelectricaltypeisdifferent Anetlabelhasbeenassignedtoapinwiththesamenameasthatusedforthecorresponding portintheFPGAproject.Thepinnumberisidenticaltothatintheassociatedconstraintfileand theelectricaltypeforthepinisidenticaltothatoftheport.Astheportandpinhavethesame signalname,theywillappearintheMatchedSignalslist.Theentrywillbehighlightedingreen asthepinnumberandelectricaltypearealsothesame AnetlabelhasbeenassignedtoapinwithadifferentnametoanyoftheportsintheFPGA project.AnentryforthesignalnamewillappearintheUnmatchedPCBSignalslist. AllportsthathavenotbeenmatchedtopinswiththesamenamewillappearintheUnmatched FPGASignalslist. 315
Synchronizingmatchedsignals
Intheeventthatamatchedsignalhasunsynchronizedpinorelectricalproperties,the unsynchronizeditemswillappearred:
Figure13.Synchronizingmatchedsignals
Thedialogaboveishighlightingthefactthatthepinnumberingforanumberofsignalsisnot synchronizedbetweentheFPGAandPCBprojectsandthattherearesomeunmatchedPCBsignals betweenthetwoprojectsaswell.TheSynchronizedialoghasmatchedthesignalnamesbetween thetwoprojectsandsotheuserhastwooptions:
UpdatetoPCB
TheUpdatetoPCBoptionwilltaketheinformationlistedintheFPGAcolumnsandpropagateitto thePCBcolumns.Inrealterms,settingsfromtheconstraintfileandFPGAschematicwillbe propagatedtothePCBProject(i.e.theautogeneratedPCBProjectfilewillbeupdated).Thiscan beseenintheECOthatisgenerated:
Figure14.RunningECOtoupdatethePCBProjectdocuments
UpdatetoFPGA
TheUpdatetoFPGAoptionwilltakethevalue(s)listedinthePCBcolumnandpropagateittothe PCBcolumn.Inrealterms,settingstakenfromthePCBProjectwillbepropagatedtotheconstraint fileand/ortheFPGAschematic.ThiscanbeseenintheECOthatisgenerated.
Figure15.RunningECOtoupdatetheFPGAProjectdocuments
Itisimportanttorememberthatupdatescanonlyoccurinonedirectionatatime.Itisnotpossible, forinstance,forelectricaltypeinformationtobepropagatedinonedirectionandpinnumbering informationpropagatedintheoppositedirection.
Synchronizingunmatchedsignals
Exercise2UsingtheFPGAsignalmanager
1. WiththeAuto_2E.SCHDOCdocumentopen,selectToolsFPGASignalManagerfromthe menu. 2. Modifythefollowingsignalsasdescribed: a. CLK_BRD: SlewRate=FAST b. JTAG_NEXUS_TCK:SlewRate=FAST c. JTAG_NEXUS_TDI:SlewRate=FAST d. JTAG_NEXUS_TDO:SlewRate=FAST,DriveStrength=24mA e. JTAG_NEXUS_TMS:SlewRate=FAST f. LCD_DB[0.7]:DriveStrength=24mA.
Figure234.Updatedsignalsinsignalmanager
3. SelectOKtoimplementthechangesandopentheEngineeringChangeOrderdialog.
Figure25.CommittingchangesmadeviatheFPGAsignalmanager
4. ValidateChangesandExecuteChangesandthenselectClose. 5. ChecktheFPGAWorkspaceMaptoensureyourprojectisstillsynchronised. 6. Saveyourwork.
4.ManuallylinkingFPGAandPCBprojects
InsomecircumstancestheFPGAdesignwillbedevelopedinparallelwith,butseparatefrom,the PCBdesign.InthesesituationsitmaybenecessarytomanuallylinktheFPGAandPCBdesigns togethertoensuresynchronization.
Figure24.ManuallylinkingFPGAandPCBprojectsthathavebeendevelopedseparately
IntheeventofanunlinkedPCBandFPGAproject,theFPGAWorkspaceMapmaylooksomething likethis:
Figure25.FPGAworkspacemapwithnolinkbetweenthePCBandFPGAprojects
Figure25showsthattheschematicandPCBdocumentsarecorrectlylinkedandsynchronized, howevernolinkcurrentlyexistsbetweentheFPGAprojectandthePCBproject.Thisisapparentby 323
thelackofconnectinglinesbetweentheSL1XilinxSpartanIIEPQ208Rev1.01.PRJPCB andtheFPGAprojectsandalsobythecommentNolinkedconfigurationbelowthe FPGA_51_Spirit_Level.PRJFPGicon.
Supporteddevices
InorderforAltiumDesignertoestablishalinkbetweenanFPGAprojectandaPCBproject,the FPGAcomponentinusebyeachprojectmustberecognizedandsupported.Alldevicespresentin thevendorlibrariesaresupportedforlinking. Thecomponentplacedontheschematicsheethastobeverifiedagainstthelistofsupported devicesinsomeway,beforeitisrecognizedanddisplayedintheFPGAWorkspaceMapdialog. ThisisachievedusingtheDesignItemIDfieldintheComponentPropertiesdialogfortheFPGA componentsymbolonthePCBschematic.Tobearecognizeddevice,theentryinthisfieldmustbe identicaltothatintheDevicefieldforthecorrespondingdeviceintheChoosePhysicalDevice dialog.ThisisdemonstratedinFigure26:
Figure26.Verificationthatdeviceissupported.
Creatingthelink
OncetheFPGAdeviceshavebeenrecognizedassupported,itispossibletocreatethemanuallink betweenthePCBandFPGAprojects.ThisisdoneusingtheStructureEditorintheProjectspanel inmuchthesamewayaswepreviouslylinkedanembeddedprojecttoanFPGAproject. ThelowerregionoftheProjectspanelcontainsallthevalidsubprojectsthatareopeninthe workspace.ThisincludesFPGA,embeddedandcoreprojects.ForFPGAprojects,theirdefined configurationswillalsobelistedalongwithconstraintfilesassociatedtoeach.Withinthisregionof thepanel,constraintfilescanbemovedfromoneconfigurationtoanother,simplybyperforminga draganddrop.Theconstraintfilewillbedisassociatedfromthesourceconfigurationandnewly associatedtothetargetconfiguration.Tocopyaconstraintfiletoanotherconfiguration,simplyhold downtheCTRLkeywhilstperformingthedraganddrop. Topurelydisassociateaconstraintfilefromaconfiguration,simplydragtheentryfortheconstraint intofreespacewithinthelowerregionofthepanel. DoubleclickingonaconfigurationentrywilllaunchtheConfigurationManagerdialogfortheparent FPGAproject. Linkingofthetwoprojectsisachievedinoneofthefollowingways: DraggingaconfigurationdefinedfortheFPGAprojectfromthelowerregionoftheProjects panelanddroppingitontotheentryfortheFPGAcomponentinthePCBproject DraggingtheFPGAproject fromeithertheupperorlowerregionsofthepanelanddropping itontotheFPGAcomponententryinthePCBproject
Figure31.Manuallylinkinganautogeneratedsheettoasheetsymbol.
Exercise3ManuallylinkingaPCBandFPGAproject
1. OpentheSLRev1.01.PrjPCBandtheFPGA_U1\SpiritLevel.PRJFPGprojectsatthe sametime. 2. OpentheFPGAWorkspaceMapandverifythatthereisnolinkbetweentheFPGAandPCB projects. 3. ChangetotheStructureEditorandestablishalinkbetweenthePCBandFPGAprojects. 4. ReopentheFPGAWorkspaceMapandverifythatalinknowexists. 5. ClickontheredlinkbetweentheFPGAandPCBprojectstoresolvetheunsynchronisedsignals. 6. Saveyourwork.
5.Pinswapping
5.1 PinswappinginthePCBdocument
ManypeoplemaywonderwhyseparateAutoandManualschematicfilesarecreatedintheFPGA toPCBProjectWizardprocess.TheAutofilecreatestheactualFPGAschematicsymbolandlinks therelevantpinstoports.TheManualfilecontainsasheetsymbolthatcontainsalloftheports definedintheAutofile.TheportlinkagebetweentheAutoandManualfilesisalogicalonerather thanphysical.ThisabstractionmakesitpossibleforthetooltoperformpinswappingontheAuto schematicwithoutaffectingconnectivityontheManualfile. TheporttophysicalpinassignmentsforanFPGAdevicearedefinedinaconstraintfile.Youcan manuallydefinetheassignments,orlettheplaceandroutetoolsassignthemandthenimportthe assignmentsbackintotheconstraintfile.However,oncetheFPGAisplacedonthePCB,pin assignmentsoftenneedtobechangedinordertooptimizethePCBroutingandthenthesechanges backannotatedtotheFPGAproject,tokeepthetwoprojectssynchronized.
SetupPinswappingmethods
Therearetwowaysthatpinswapscanberepresentedattheschematiclevel.Thesearecontrolled fromtheOptionstaboftheprojectoptionsdialogbox.Inbothcases,theactualwiringonthe schematicwillnotbealteredjustitsconnectivity.
Figure32.Settingpinandpartswappingmethods.
Adding/RemovingNetLabelswillmovenetlabelsontheswappedpinsornetstoreflectthe changesthatweremadeduringpinswapping.Inthiscase,theschematicsymbolwillbeleft unchanged. ChangingSchematicPinswillallowAltiumDesignertomovethepinsonschematicsymbols accordingtothepinswapsperformedatthePCBlevel. Wherebothoptionshavebeenchecked,AltiumDesignerwilldefaulttoswappingnetlabels.Ifno labelsexistonthenets,itwillswappinsontheschematicsymbols.
SetupSwapgroups
Beforepinscanbeswappedwitheachother,itisimportanttofirstsetupswapgroupIDs,asitmay notbedesirable(oracceptable)forallpinstobeswappedwithoneanother.WhileallI/Opinswithin anFPGAcantheoreticallybeswappedtogiveabetterlayoutforrouting,conditionsmaydictate otherwise.Firstly,somepinshaveadditionalspecialfunctions(clockpins,configpinsandVREFpins tonameafew),anditmaybepreferabletoreservethesefortheirspecialpurpose.Secondly,setting limitationsherewillallowanyswappingprocesstoobeythebankingandI/Ostandardsrequirements asdescribedearlier.Forthisreason,itmaybedesirableforpinsinacertainbanktoonlybe swappablewitheachother(orperhapsotherbankswithcompatibleI/Ostandards). SwapgroupsmaybedefinedatschematicorPCBlevel,asdescribedbelow.
Settingswapgroupsintheschematic
Todefineswapgroupsintheschematiclevel,selecttheToolsConfigurePinSwappingoption. Theresultingdialogboxwilllistallcomponentsinthedesign.
Figure33.Settingupswapgroupsforvariouscomponents.
SelectthecomponentyouwishtodefineswapgroupsforandclickontheConfigureComponent buttonorsimplydoubleclickthecomponentinthelisttoaccesstheConfigurePinSwappingFor dialog.
SettingswapgroupsinthePCB
RightclickthecomponentyouwishtosetupforpinswappingandselecttheComponent Actions>>ConfigurePin/PartSwapping. SelecttheTools>>Pin/PartSwapping>>ConfigureoptiontoaccesstheConfigure SwappingInformationInComponentsdialogbox(seefigureabove). Selectthe componentyouwishtodefineswapgroupsforandclickontheConfigureComponent buttontoaccesstheConfigurePinSwappingFor dialog.
Figure34.SpecifyingswapgroupIDsinthepinswapmanager.
AllpinswiththesameswapgroupIDcanbefreelyswapped. AssigneachI/Opinonthedevicetotherequiredswapgroup.Eithermanuallyenterthelabelfor thegroupdirectlyintheSwapGroupIDfield,orusetherightclickmenutoassignswapgroups byvariouspinattributes.
SetupEnablingcomponentsforpin/partswapping
Onceswapgroupshavebeendefined,onemorestepisrequiredbeforetheactualpinswap.Altium Designerwillonlyswappinsforcomponentswhichhavebeenspecificallymarkedasallowingpin swapping.Todothisforagivencomponent,selectitinPCBmodeandviewthecomponents properties.Then,underswappingoptions,makesurethatEnablePinSwapshasbeenenabled. Dothisforeachcomponentthatrequirespinswapping.
Figure35.Enablingpinswapsforacomponent.
Swapping
HavingdefinedtheSwapGroupIDsasappropriate,theactualprocessofswappingpinscannowbe performed.WiththePCBdocumentactive,simplyclickonthePin/PartSwappingentryunderthe Toolsmenuandchooseamethodtoswappins. TheAutomaticNet/PinOptimizermaybeusedonanyorallcomponentsinadocumentandisnot limitedtoFPGAcomponents.Thispinswapperwillattempttofindtheoptimalpinallocationsfor routing,whilstobeyingthepinswapGroupIDspreviouslysetup. Itrunsthroughatwostage process:thefirststageisafastsinglepassoptimizerthatwillattempttominimizecrossoversand connectionlengths,whilethesecondstageisaniterativeoptimizerwhichperformsmultiplepasses. Thesecondstageisoptional,asthetimerequiredfortheiterativeprocessincreasessignificantly whenattemptingtooptimizemultiplecomponents.
Figure36.Ratsnestpriortoautomatedpinswapping
ThetwoPCBsnapshotsdepictedaboveandbelowshowhowtheautopinswappingtoolcanbe usedtogreateffecttoobtainanoptimizedsetofpinallocationsfromwhichtoroute.Inthiscase,all I/OpinsontheFPGAdevicehavebeenassignedthesameswapgroupID.
Figure37.Unraveledratsnestafterautomatedpinswapping
TheInteractivePin/NetSwappingtoolallowsforfinetuningandgivesthepowertomakeany numberofindividualpinswapsagain,inaccordancewiththepinswapgroupIDsalready configured. Asequenceofswappingprocessescanbeperformed.Forexample,theautomatictoolmayberun initiallyandthentheinteractivetoolusedafterwardstofinetuneacoupleofoutofplacenets/pins. IfanyFPGAcomponentsinthedesignarelinked,duetothedesignbeingmultichannelinnature, (e.g.U1_X1,U1_X2),theymustbeoptimizedtogether.Whenusingtheinteractivepinswapping tool,swappingcannotbecarriedoutonthelinkedcomponentandadialogwillappearalertingyou tothisfact.Forexample,ifU1_X2islinkedtoU1_X1,bothcomponentsmustbeoptimizedtogether, butmanualpinswappingcanonlybecarriedoutonU1_X1.
Apinswapoperationachievestwothings.Firstlyitcopiestheimportantpropertiesfromthenewpin thiswillbetheelectricaltypeofthepinaswellasanyparametersonthatpin.Secondlyitwill add/rename/removeanattachednetlabelforthatpinasappropriate.Notethatthissecondstepcan onlyoccuriftheFPGAcomponentschematicsheethasbeenautogeneratedusingtheFPGATo PCBProjectWizardorhasbeencreatedusingasimilardesignstyle. AfterupdatingthePCB,thechangesneedtobepropagatedtotherestoftheproject.Toupdatethe PCBschematics,gotoDesign>>Update. Onceupdated,youcanthenusetheFPGA WorkspaceMaptopropagatethenewchangesintotheFPGAproject.Youwillnoticethatthe schematicFPGAprojectlinkappearsoutofdate.
Figure38.ResynchronizingthePCB/FPGAprojectlinkafterpinswapping
ClickingonthislinkwillbringuptheSynchronizedialog,withtheaffected(swapped)pins highlightedinred,asshownbelow.
Figure39.ManagingsynchronizationsbetweenPCBandFPGAprojects
ClickontheUpdateToFPGAbuttontopushthechangestotheFPGAproject,ormorespecifically, theappropriateFPGAconstraintfile.TheupdatewillconsistofanumberofparameterchangeECOs (appearingasaseriesofchangeparametervaluemodificationsintheEngineeringChangeOrder dialog).
Figure40.ConfirmECOs
DespitehavingpassedthedesignchangesthroughfromthePCBprojecttotheFPGAproject,the FPGAWorkspaceMapdialogwillnotshowthedesignsasbeingfullysynchronized.Thisis becauseFPGAsignalshavebeenrenamedwithdifferentnetnamesinthePCBproject.Also,the PCBdesigncontainsadditionalconnectionsnotrepresentedattheFPGAlevel(foralternateFPGA implementations).Thisdoesnotmeanthatfunctionallythetwodesignswillnotworkbutratherthat initscurrentimplementation,thesetwodesignshavesomedifferencesnotrelatedtothe functionality.
ExecutethechangesinthesubsequentEngineeringChangeOrderdialogthatappears TheSynchronizedialogwillreappear,showingnodifferencesintheMatchedSignalslist (appearingtotallygreen).IntheFPGAWorkspaceMapdialog,thelinkwillhavereturnedtoitsfully synchronizedstatus(Green).
Exercise4Pinswapping
Thisexercisecontinuesonfromworkdoneinthepreviousexercise. 1. OpenSLRev1.01NoRoutes.PcbDoc. 2. ChecktheAdding/RemovingNetLabelsoptionintheoptionstaboftheprojectoptionsdialog box.LeavetheChangingSchematicPinsoptionunchecked. ClickOKtoclosetheproject optionsdialog. 3. Select ToolsPin/PartSwappingConfigure 4. SelecttheFPGAcomponent,andConfigureComponent 5. EnsureShowI/OPinsOnlyisselectedfromthedropdownlistonthebottomleftofthedialog box. 6. CreateauniqueSwapGroupID foreachofthefollowingsignals: a. I\N\I\T\ b. DIN 7. AllotherIOpinscanbeplacedintoasingleswapgroupcalledgeneral_IO.
Figure44.SpecifyswapgroupIDsforalloftheIO
8. SelectOK. 9. ZoomintoviewtheFPGAdeviceinthecentreofthePCB. 10. DoubleclickontheFPGAdevice.WhentheComponentU1dialogappears,changethe Rotationto180degreesandclickOK. 11. Usetheautomaticpinswappingtorearrangethepins. 12. Waitforamomentforthesystemtoperformthepinswapping. 13. GototheDesign menu,andselectUpdateSchematicstobringthechangesacrosstothePCB schematics. 14. OpentheFPGAWorkspaceMap,andresolveanyunsynchronisedsignals.ThePCBshouldbe themasterdocumentatthisstagesoselectUpdatetoFPGAwhenperforminganychanges. 15. Saveyourwork.
6.Commissioningthedesign
OneoftheadvantagesofhavingahardwareplatformsuchastheDesktopNanoBoardatyour disposalduringdevelopmentisthatyoucanperformastagedmigrationofthedesignontoacustom targetPCB.Evenifcomponentsforthetargethavenotyetarrived,initialcommissioningcanbegin bycouplingthetargettotheNanoBoardandusingNanoBoardresourcesasasubstituteforthe missingcomponents.
Exercise5Migrationstage1
Inthisexercise,weconsiderthescenariowhereoneormoreofthetargetresourcesareyettobe placed.Inthiscasewemaychoosetorunthemainapplicationfromthetargetboardbutuse peripheralsavailableontheNanoBoardtotestourapplication.Forthisexercisetofunctioncorrectly wewillneedtoloaddesignsontoboththeNanoBoardandTargetplatforms. 1. Locatethe.\Module3\Exercise5\directoryandload SLRev1.01.PrjPCBaswellasFPGA_NB\SpiritLevel_NB.PRJFPG 2. ObservethecontentsoftheschematicdocumentSL_FPGA_NB.SchDoc.Noticehowthe NEXUSJTAGConnectorneedstobepresentandtheTDI/TDOloopmadetoensurethatthe JTAGsoftchainisnotbrokenwithintheNanoBoarddevice. 3. SwitchofftheDesktopNanoBoardandtargetboardpower. 4. Usinga10pinribboncable,connectHDR1onthetargetboardtoUSERBOARDAonthe NanoBoard. 5. Usinga20pinribboncable,connectHDR2onthetargetboardtoUSERHEADERAonthe NanoBoard. 6. EnsuretheXaxisjumperisremoved fromthetargetboard. 7. EnsureallDIPSwitchesonthetargetboardaresettotheONposition. 8. PlacetheCONFIGjumperonthetargetboard. 9. SwitchontheNanoBoardandtargetboard. 10. OpentheDevicesviewandverifytheexistenceoftwoFPGAdevices(andoneconfiguration device)intheHardChain.Thefirstdevicewillalways betheNanoBoarddevice. 11. BuildanddownloadtheSpiritLevel_NB/NB_BaseconfigurationtotheNanoBoarddevice. 12. BuildanddownloadtheSpiritLevel/Tgt_Spartan2configurationtothetargetboard device. 13. ObservethestatusoftheProcessorinthesoftchain.If,afterdownloadingbothprojects,this deviceislistedasMissing,itislikelythesoftchainisbrokensomewhere.Verifythataloop betweenJTAG_NEXUS_TDIandJTAG_NEXUS_TDOexistsontheSL_FPGA_NB.SchDoc. Rebuildtheprojectifnecessary. 14. SettheNanoBoardclockfrequencyto6MHzandensurethatDIPSwitch8ontheNanoBoardis ON.Observethedisplayonthetargetboard.AssertoneortwooftheNanoBoardslowerDIP SwitchesandseewhatchangeoccursintheTargetsLCD.IfthetargetboardLEDsarenot flashingthenthisindicatesitisnotreceivingasignalfromtheNanoBoard.Ensurealloutputs fromtheDigitalIOBonthetargetboardare0andcheckthewiringbetweentheNanoBoardand thetargetboard.Alsoensuretherespectiveprojectshaveloadedcorrectly.
Figure48.SpecifyingtheconfigurationPROMdevice
3. SelectthemcsoptionundertheFormatdropdown. 4. Rebuildtheentireprojecttoensurethatyourcalibrationvaluesareincludedinthebuildandthe configurationPROMfilegetscreated. 340
RightclickontheconfigurationdeviceinthehardchainandselectChooseFileandDownload fromthepopupmenu.
Figure49.DownloadingaPROMtotheconfigurationdevice.
5. LocatetheMCSbitfile.Youwillfinditunder \ProjectOutputs\Tgt_Spartan2\spiritlevel.mcs.Onceyouselectit,downloading willbeginimmediately. 6. Theprogrammingprocessmaytakeseveralsecondsasthedevicehastofirstbeerasedbefore itcanbeprogrammed.WhenaskedifyouwishtoverifyprogrammingselectYes.Besurenot toremovepowerfromthedeviceuntilprogrammingiscomplete.Youwillbenotifiedof successfulprogrammingwiththefollowinginformationdialog.
Figure50.PROMfileprogrammingconfirmation
7. Removepowerfromthetargetboard. 8. Disconnectthe10pinUSERBOARDribboncablefromthetargetboard. 9. RemovetheCONFIGjumperfromthetargetboardbutmakesuretheXaxisjumperremains connected. 10. Reapplypowertothetargetboardandverifythattheapplicationcorrectlyloadsandrunsitself. 11. SwitchofftheNanoBoardandthetargetboardandreconnectthe10pinUSERBOARDribbon cablebetweenthetargetboardandtheNanoBoard. 12. ReapplypowertothetargetboardandNanoBoardandobserveintheDevicesviewthatthe downloadableinstrumentsarestillaccessible.
Exercise9Revertingtotestmode
1. Toensurethetargetboardsareleftinastatereadyforthenextusers,itwillbenecessaryto reprogramthePROMwiththeTestModeconfigurationfile.Youwillfindthisfileas \Exercise9\ConfigTest.mcs.Usethestepsoutlinedinthepreviousexercisetoprogram thistestfilebackintothePROM.
7.Review
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