FPGAtoPCB TrainingModule
DocumentVersion1.2,February2008 Software,documentationandrelatedmaterials: Copyright2008AltiumLimited. Allrightsreserved.Youarepermittedtoprintthisdocumentprovidedthat(1)theuseofsuchisfor personaluseonlyandwillnotbecopiedorpostedonanynetworkcomputerorbroadcastinany media,and(2)nomodificationofthedocumentismade.Unauthorizedduplication,inwholeorpart, ofthisdocumentbyanymeans,mechanicalorelectronic,includingtranslationintoanother language,exceptforbriefexcerptsinpublishedreviews,isprohibitedwithouttheexpresswritten permissionofAltiumLimited.Unauthorizedduplicationofthisworkmayalsobeprohibitedbylocal statute.Violatorsmaybesubjecttobothcriminalandcivilpenalties,includingfinesand/or imprisonment. Altium,AltiumDesigner,BoardInsight,CAMtastic,CircuitStudio,DesignExplorer,DXP,LiveDesign, NanoBoard,NanoTalk,Nexar,nVisage,PCAD,Protel,SimCode,Situs,TASKING,andTopological AutoroutingandtheirrespectivelogosaretrademarksorregisteredtrademarksofAltiumLimitedor itssubsidiaries. Microsoft,MicrosoftWindowsandMicrosoftAccessareregisteredtrademarksofMicrosoft Corporation.OrCAD,OrCADCapture,OrCADLayoutandSPECCTRAareregisteredtrademarksof CadenceDesignSystemsInc.AutoCADisaregisteredtrademarkofAutoDeskInc.HPGLisa registeredtrademarkofHewlettPackardCorporation.PostScriptisaregisteredtrademarkofAdobe Systems,Inc.Allotherregisteredorunregisteredtrademarksreferencedhereinarethepropertyof theirrespectiveownersandnotrademarkrightstothesameareclaimed.

Module3

AltiumDesignerTraining

FPGAtoPCB

FPGAtoPCBTrainingModule
1. FromFPGAprojecttoPCBproject... 32 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 2. 2.1 2.2 2.3 2.4 3. 3.1 3.2 4. 4.1 4.2 4.3 4.4 5. 5.1 5.2 5.3 5.4 6. 6.1 6.2 6.3 6.4 6.5 7. Understandingthedocumentstack... 32 UsingtheFPGAtoPCBprojectwizard.. 34 ChoosingtheFPGAconfiguration... 34 InitialFPGApinassignments... 35 ChoosingthetargetPCBproject... 37 ConfiguringtheFPGAcomponentschematicsheet. 37 Configuringthesheetsymbolschematicsheet.. 38 Exercise1RunningtheFPGAtoPCBprojectwizard. 39 Modifyingtheautogeneratedsheet... 311 AwordaboutspecialfunctionFPGApins.. 311 Recreatingtheautogeneratedsheet.. 312 TheFPGAworkspacemap... 313 Thesynchronizedialog.... 314 Synchronizingmatchedsignals... 316 Synchronizingunmatchedsignals... 317 ConfiguringI/Ostandards... 320 Exercise2UsingtheFPGAsignalmanager.. 321 Supporteddevices... 324 Creatingthelink.... 324 LinkinganautogeneratedsheettoanexistingPCBproject.. 327 Exercise3ManuallylinkingaPCBandFPGAproject.. 327 PinswappinginthePCBdocument... 328 PinswappingintheFPGAproject... 335 PinswappinginbothPCBandFPGAprojects.. 336 Exercise4Pinswapping.. 336 Exercise5Migrationstage1... 338 Exercise6Migrationstage2... 339 Exercise7Calibration... 339 Exercise8BootstrappingtheFPGA.. 340 Exercise9Revertingtotestmode.. 341
Maintainingprojectsynchronization... 313
ConfiguringFPGAI/O.... 320
ManuallylinkingFPGAandPCBprojects.. 323

Pinswapping.... 328

Commissioningthedesign... 338

Review..... 342

AltiumDesignerTrainingModule
1.FromFPGAprojecttoPCBproject
Atsomepointinthelifeofalldesignstherecomesapointwheretheymustmovefromthelaboratory prototypetoproduction.IfadesignhasbeensuccessfullyrunningontheDesktopNanoBoard,the processofmigratingfromanFPGAbasedprojecttoaPCBbasedprojectcontainingtheFPGA projectissimplifiedthroughtheuseoftheFPGAtoPCBProjectWizard.Thismethod automaticallylinksthetwoprojectsandmaximizessynchronizationfunctionalitybetweenthem. ProjectsynchronizationisimportantasitensuresthatdesignchangesmadetoeitherthePCB documentorFPGAprojectarepropagatedinacontrolledfashion. Overtheremainderofthecoursewewilllookatmovingadesignfromthetestenvironment,tothe targetPCB.Todothiswewilluseadesignthathasalreadybeencompletedforus,aDigitalSpirit Level.TheFPGAportionofthisdesignincludesasoftcoreTSK51processorwhichtakesasitsinput theoutputofanaccelerometerandoutputsasmallbubbleonanLCDmimickingatraditionalspirit level.
Understandingthedocumentstack
Figure1.Visualizationofhowthevariousprojectdocumentsarestacked
SynchronizationbetweenPCBandFPGAprojectsiscarriedoutandmaintainedbyestablishinga linkbetweenthetoplevelportsintheFPGAprojectspecifiedintherelevantconstraintfileand thecorrespondingpinsontheFPGAcomponentschematic.Linkingisachievedusingthesignal name.ThenamegiventotheportintheFPGAprojectmustbethesameasthenetlabelassigned tothecorrespondingpinontheschematiccomponentinthePCBproject. Figure1providesa visualizationofhowthevariousdocumentsinanFPGA/PCBprojectstackarelinkedtogether.

FPGA_Top.SchDoc

FPGAproject
ThetoplevelFPGAschematicdocument mustcontainportsatthepointwhere signalsareconnectedtophysicalpinson theFPGAdevice.Thenameoftheportsis importantastheywillbeusedinthe constraintsfile. FPGA.Constraint FPGAproject

InitialFPGApinassignments
ThesecondpageoftheFPGAtoPCBProjectwizardgivesyouthechoiceofwhattodowith unconstrainedportsi.e.portsthathavenotbeentiedtoaspecificpinonthetargetdevice.The decisionastohowthesepinsareassignedissomewhatarbitraryandsothereareanumberofways ofdoingthis:
Importingpinfilefromvendorplaceandroutetools
Clearlyforthisoptiontobeavailablethedesignmusthavepreviouslybeenbuiltforthecurrent deviceandaconstraintfileandconfigurationmustalreadyexist.Fortotallynewdesignsthisisthe preferreddesignpath.Itensuresthatthevendortoolsaregiventhemostopportunitytooptimizethe designwithoutbeingundulyconstrainedanditensuresthattheselecteddeviceiscapableof supportingthedesign.Inthiscase,thepinassignmentsshouldbemadepriortorunningtheFPGA toPCBprojectwizard.Withaconstraintfileopeninthemainwindow,selectDesignImportPin File fromthemenutoimportthevendorpinfile.Thefollowingdialogboxwillappear:
Figure6.Selectingconstraintstobeimportedfromthevendortools
AssigningpinsduringtheFPGAtoPCBwizard
ProbablythequickestandsimplestwaytoallocatepinsiswhilstexecutingtheFPGAtoPCBproject wizard.SelecttheAssignUnconstrainedPortsonthesecondpageofthewizard.Asthewizard executesitwillautomaticallyallocatepinnumberstounallocatedportsupdatingtheconstraintfile andautogeneratedsheetasitgoes.
Figure7.AssigningunconstrainedportsaspartoftheFPGAtoPCBprojectwizard
AssigningunconstrainedsignalsfromtheFPGAsignalmanager
ItisalsopossibletoallocateunconstrainedsignalsbyselectingtheAssignUnconstrainedSignals buttonintheFPGASignalManagerdialog(Figure8).
Figure8.UsingtheFPGAsignalmanagertoassignunconstrainedsignals
Performingpinassignmentsviathismethodisprobablylessadvisableasitdoesnotgivetheuser thechoicewhichconstraintfile(projectortarget)recordsthepinallocations.Furthermore,an additionalstepisrequiredafterthisonetoresynchronizethenetlabelsintheautogeneratedsheet.
Assigningsignalsmanuallyintheautogeneratedsheet
Thisisthemostlaboriousmethodandgenerallynotadvisable.Usingthismethodrequiresthe designertomanuallyenterthenetnamesforallportsontotheautogeneratedsheet.Asecond synchronizationstepisalsorequiredtopropagatethepinassignmentsintotheconstraintsfile.
ChoosingthetargetPCBproject
AfterchoosingtheFPGAconfiguration,theactualtargetPCBprojectmustnowbedefined.Simply accepttheWizard'sgenerationofanewproject(PCBProject1.PrjPCB),orbrowsetoandselect anexistingproject.InthecaseofanewPCBproject,thefilewillbestoredinthesamelocationas theFPGAproject.
ConfiguringtheFPGAcomponentschematicsheet
WhetherthePCBprojectalreadyexistsorisbeingnewlycreated,therelationshipbetweenthe FPGAprojectanditscorrespondingcomponentinthePCBprojecthastobemanagedinsomeway. Thisisachievedusingadedicated,autogeneratedschematicsheet,referredtoasthe'MainSheet' intheWizard.

Figure2.TheautogeneratedFPGAcomponentschematicsheet.
ThisschematicsheetwillbecreatedwiththecomponentsymbolplacedfortheFPGAdevice targetedintheconstraintfile.TheWizardallowsyoutodeterminewhereandbywhatname,the schematiciscreated.Bydefault,theschematicwillbenamedusingthechosendesignatorforthe FPGAcomponent(e.g.FPGA_U1_Auto.SchDoc)andwillbestoredinthesamelocationasthe FPGAproject.Eachusedpinonthecomponentsymbolislinkedtoaportentryintheconstraintfile bysignal(netlabel/port)name.ThenamesfornetsinthePCBprojectarethereforerequiredtobe thesameasthoseintheFPGAproject.Oncelinked,anychangesmadetothesourcedocumentsof eitherPCBorFPGAprojectcanbepassedon,ensuringthatthetwoprojectsremainsynchronized. 37
ConfiguringunallocatedI/O
TheWizardalsoallowsyoutodeterminehowanyunusedI/Opinsonthecomponentarehandled. YouhavetheabilitytocontrolthetreatmentofvariouscategoriesofpintypesindividuallyInput onlypins,VREFpins,SpecialFunctionpinsandallotherunusedpins. Foreachcategory,thepinscanbehandledinoneofthefollowingways: Tietosingleport Tieallunusedpinsinthecategorytoasingleport(whichwillalso appearontheparentsheetsymbol(ifapplicable)onthesheetabove)
Tietoindividualports Tieallunusedpinsinthecategorytotheirown,individualports (whichwillalsoappearontheparentsheetsymbol(ifapplicable)on thesheetabove) TietoportsbyIO bank(VREFonly) AddNoERCdirective Ignore TieallunusedVREFpinstoaportonabankbybankbasis(which willalsoappearontheparentsheetsymbol(ifapplicable)onthe sheetabove). AddaNoERCdirectivetoanunusedpin,sothatitisnotincludedas partoferrorcheckingwhenthedesigniscompiled Donothingwithanunusedpin
Figure3.SelectinghowunusedI/Oistobehandled
Note:ForVREFpins,whentheTietosingleportor TietoportsbyIObankoptionsareselected, youaregiventheadditionaloptionofwhetherornottoconnectviaPowerPorts.
Configuringthesheetsymbolschematicsheet
AspartofthePCBproject,youhavetheoptionofdefiningthe'owner'oftheFPGAComponent sheet(holdingthecomponentsymbolfortheFPGAdevice).ThefinalpageoftheWizardallowsyou todefinetheownerasasheetsymbol,which,ifenabled,willbecreatedonanadditionalschematic sheet,thenameandlocationofwhichyoucanfreelychoose.Bydefault,theschematicwillbe namedusingthechosendesignatorfortheFPGAcomponentonthepreviouspageoftheWizard (e.g.FPGA_U1_Manual.SchDoc)andwillbestoredinthesamelocationastheFPGAproject. Insummary,afteralloftheoptionsintheWizardhavebeensetasrequired,thefollowingwillbe generated: AnewPCBproject(ifspecified) Anewschematicsheet,addedtotheneworexistingPCBproject,whichcontainstheschematic representationoftheFPGAcomponent Anewschematicsheetwithparentsheetsymbol(ifspecified).Ifanexistingsheetistargeted, theparentsheetsymbolfortheFPGAComponentschematicwillbeadded/updatedas necessary Anewconfiguration(ifspecified),whichwillbeaddedtotheFPGAprojectfileandwhich containsanewconstraintfile Theconstraintfileeithernewforanewconfigurationoranexistingonecontainedinachosen configurationcontaining: apartconstraint aPCBboardconstraint alistofconstraintsforallportsonthetoplevelsourcefileoftheFPGAproject.Eachof theseportconstraintsismatched(andthereforelinked),bynetname,totheequivalentpin ontheFPGAcomponentinthePCBproject'sautogeneratedschematicsheet.

Exercise1RunningtheFPGAtoPCBprojectwizard
InthisexercisewewillutilizethedesigntargetedtotheSpartan2Edeviceandwewillrunthrough theFPGAtoPCBProjectWizard. 1. OpenthedesignSpiritLevel.PRJFPGinthefolder\Module3\Exercise1\ 2. OpentheconfigurationmanagerandmakesuretheNB1_6_XC2S300E6PQ208.Constraintis includedintheconfiguration.ClickOKtoclosetheconfigurationmanager. 3. OpentheFPGAschematicdocumentSL_FPGA_Complete.SchDoc. 4. Select ToolsFPGAtoPCBProjectWizard. 5. AttheSelecttheFPGAConfigurationstep,checktheUseExistingConfigurationoptionand specifyNB_Xilinx_Spartan2configuration.MakesureAssignUnconstrainedPortsisnot checked.
Figure4.UseanexistingconfigurationintheFPGAtoPCBProjectWizard
6. AttheConfigurethePCBProjectstep,specifythePCBProjectFileNameas SpiritLevel_2E.PrjPCB.
Figure5.SpecifythePCBprojectfilename.
7. AttheConfiguretheMainSheetstep,specifytheMainSheetFileNameas Auto_2E.SchDocandanyfurtheroptionsasdepictedinFigure6.ClickNexttocontinue.
Figure6.Mainsheetoptions.
8. AttheConfiguretheSheetSymbolSheetstep,checktheCreateSheetSymbolboxand specifytheSheetSymbolFileNameasSL_Top.SchDoc.ClickFinishtocompletethewizard.
Figure7.Symbolsheetoptions.
9. UseFileSaveAstosavethetwo,newlyautogeneratedschematicsheets 10. UseFileSaveProjectAstosavethenewlycreatedPCBprojectintothisdirectoryaswell. 11. Thebasicschematicfileshavenowbeencreatedandarereadyformodificationaccordingtothe specificprojectrequirements.Atthispoint,however,theFPGAprojectmaynotappearvisibly linkedtothePCBproject.RightclickonthePCBprojectintheprojectspanelandcompilethe design.Thedesigncompilerwillautomaticallychangetheprojectstructure.
Figure8.ProjectPanelaftercompiling.
12. Observethenewstructureofthecreatedschematicsheets. 13. Saveyourwork.
Modifyingtheautogeneratedsheet
Occasionallyitmaybenecessarytoperformmodificationstotheautogeneratedsheet.Thiswill causethePCBprojecttolosesynchronizationwiththeFPGAprojectandthedesignswillneedtobe resynchronizedthroughtheFPGAWorkspaceMap.Managingprojectsynchronizationisan automatedbutnotautomaticprocessandprojectsynchronizationcanonlybeperformedinone directionatonetimeie.designrevisionscanbepropagatedfromthePCBtotheFPGAorvice versabutnotbothwaysatthesametime.ExtremecautionshouldbeexercisedifboththePCBand FPGAprojectsarebeingworkedoninparallel. Situationsmightalsooccurinwhichadesignnevertotallysynchronizes.Thisiscommonlycaused whendifferencesexistinthenetnamingbetweenthePCBandFPGAschematics,or,when additionalcomponentsareconnectedtotheFPGAforpossiblefutureexpansion.Thelatter scenariomightincludetheadditionofaconnectorattheboardlevelthatisnotyetusedintheFPGA, andthusnotrepresentedintheFPGAdesign.IfthisoccursthePCBandFPGAdesignswillnot matchandthoughthismaycausethedesignstoappearoutofsync,thiswillnotaffecttheexisting functionalportionsofthedesign.

AwordaboutspecialfunctionFPGApins
SpecialFunctionPinsarehandledinaspecialwaywhencreatingtheautogeneratedsheet. Extremecaremustbeobservedtoensuretheirconnectivityismaintained.Asaruleofthumbitis besttoselecttheTietoindividualportsforSpecialFunctionPinsevenifyoudontintendtouse theminthefinaldesign.IfyouneedtouseanI/Opinthathasaspecialfunctionnetlabelattached toit,justremovethespecialfunctionnetlabelandreplaceitwiththenetlabelforthenetthatyoudo wishtobeconnected.Resynchronizethedesignasnecessary.
SelectinganyotheroptionotherthantheTietoindividualportswillcausespecialfunctionnet labelstoberippeduporrenamed.Beware!
Recreatingtheautogeneratedsheet
TheSynchronizedialogprovidesabuttontoRecreateAutogeneratedSheet.Thisfeatureshould beusedunderextremecare.IfthereareanyPCBdesignchangesthatareyettohavebeen propagatedbacktotheFPGAprojectthentheycanbedestroyedoncetheautogeneratedsheetis recreated.
Figure9.Recreatingtheautogeneratedsheetfromthesynchronizedialog.
Recallourpreviouswarningaboutthenatureofspecialfunctionpinsselectinganyotheroption otherthantheTietoindividualportswillcausespecialfunctionnetlabelstoberippedupor renamed.Beware!
2.Maintainingprojectsynchronization
MaintainingsynchronizationbetweenanFPGAprojectanditsparentPCBprojectisgreatly improvedthroughtheinternalsynchronizationmechanismsthatoperatewithinAltiumDesigner.Itis important,however,thatusersunderstandhowthissynchronizationprocessworkssothattheydont inadvertentlymakedesignchangesthatwilldefeatprojectsynchronization.

TheFPGAworkspacemap

Atanygiventimeduringthedesignprocess,thestatusofthelinkingbetweenFPGAandPCB projectscanbereadilycheckedbylaunchingtheFPGAWorkspaceMapdialog.Accesstothis dialogisprovidedbychoosingthecommandofthesamenamefromtheProjectsmenu,orby pressingthe buttonontheProjectspanel. IntheexamplebelowtheFPGAWorkspaceMapdisplaystherelationships(links)betweenvarious elementsofFPGAandPCBprojectsandthestatusoftheselinkswhetherthetwosidesofalink aresynchronizedanduptodateorwhethersomeactionisrequiredtoresynchronizethem.
Figure10.TheFPGAworkspacemapdialog.
Thevariouselementsinthetwoprojecttypesarelinkedinalogicalflowfromasoftcore microcontrollerplacedwithinanFPGAproject,toaPCBdesigndocumentwithinalinkedPCB project.Eachofthelinksaresummarizedbelow:

Figure23.FPGASignalManager
Note:thelistofavailableI/Ostandardsiscontextsensitiveonlystandardsthatareapplicablefor thatparticularFPGAwillbeavailable.
FPGAsignalscanberapidlyupdatedingroupsbyusingthestandardshift/ctrlselecttechniqueand rightclickingoneoftheselectedrowstoaccessthepopupmenu.Additionalcolumnscanalsobe enabledfromthismenu. Afterdefiningthecharacteristicsfortheappropriatepinsofthedeviceasrequired,clickOKtoclose thedialog.TheEngineeringChangeOrderdialogwillappear,withthesettingsyoudefinelistedas aseriesofparameterstobeaddedtotheaffectedportconstraintentriesinthelinkedconstraintfile.
Figure23.Updatingtheconstraintfilewithsignalmanagerchanges
Thesechangesaretosignalcharacteristicsonlynotpinspecificchanges.Assuch,theyaffectonly therelevantentriesintheassociatedconstraintfile.TheschematicrepresentationoftheFPGA componentisnotaffectedandlaunchingtheFPGAWorkspaceMapdialogwillshowthelink betweentheschematiccomponentandtheFPGAprojectstillgreen,highlightingthefactthatthetwo sidesarefullysynchronized. Thechangeswillbestoredasconstraintsontheportsintheconstraintfile.Eachrequiredchange willbeperformedviaanECOandbyexecutingthechanges,thenewI/Ostandardswillbesavedin theconstraintfile.Anyfuturesynthesis/buildprocesswillthenusetheseconstraintsforprogramming theFPGA.(TheseconstraintswouldalsobeusedwhenperformingaSignalIntegrityanalysisonthe PCBproject).
Exercise2UsingtheFPGAsignalmanager
1. WiththeAuto_2E.SCHDOCdocumentopen,selectToolsFPGASignalManagerfromthe menu. 2. Modifythefollowingsignalsasdescribed: a. CLK_BRD: SlewRate=FAST b. JTAG_NEXUS_TCK:SlewRate=FAST c. JTAG_NEXUS_TDI:SlewRate=FAST d. JTAG_NEXUS_TDO:SlewRate=FAST,DriveStrength=24mA e. JTAG_NEXUS_TMS:SlewRate=FAST f. LCD_DB[0.7]:DriveStrength=24mA.
Figure234.Updatedsignalsinsignalmanager
3. SelectOKtoimplementthechangesandopentheEngineeringChangeOrderdialog.
Figure25.CommittingchangesmadeviatheFPGAsignalmanager
4. ValidateChangesandExecuteChangesandthenselectClose. 5. ChecktheFPGAWorkspaceMaptoensureyourprojectisstillsynchronised. 6. Saveyourwork.
4.ManuallylinkingFPGAandPCBprojects
InsomecircumstancestheFPGAdesignwillbedevelopedinparallelwith,butseparatefrom,the PCBdesign.InthesesituationsitmaybenecessarytomanuallylinktheFPGAandPCBdesigns togethertoensuresynchronization.

Figure31.Manuallylinkinganautogeneratedsheettoasheetsymbol.
Exercise3ManuallylinkingaPCBandFPGAproject
1. OpentheSLRev1.01.PrjPCBandtheFPGA_U1\SpiritLevel.PRJFPGprojectsatthe sametime. 2. OpentheFPGAWorkspaceMapandverifythatthereisnolinkbetweentheFPGAandPCB projects. 3. ChangetotheStructureEditorandestablishalinkbetweenthePCBandFPGAprojects. 4. ReopentheFPGAWorkspaceMapandverifythatalinknowexists. 5. ClickontheredlinkbetweentheFPGAandPCBprojectstoresolvetheunsynchronisedsignals. 6. Saveyourwork.

5.Pinswapping

5.1 PinswappinginthePCBdocument
ManypeoplemaywonderwhyseparateAutoandManualschematicfilesarecreatedintheFPGA toPCBProjectWizardprocess.TheAutofilecreatestheactualFPGAschematicsymbolandlinks therelevantpinstoports.TheManualfilecontainsasheetsymbolthatcontainsalloftheports definedintheAutofile.TheportlinkagebetweentheAutoandManualfilesisalogicalonerather thanphysical.ThisabstractionmakesitpossibleforthetooltoperformpinswappingontheAuto schematicwithoutaffectingconnectivityontheManualfile. TheporttophysicalpinassignmentsforanFPGAdevicearedefinedinaconstraintfile.Youcan manuallydefinetheassignments,orlettheplaceandroutetoolsassignthemandthenimportthe assignmentsbackintotheconstraintfile.However,oncetheFPGAisplacedonthePCB,pin assignmentsoftenneedtobechangedinordertooptimizethePCBroutingandthenthesechanges backannotatedtotheFPGAproject,tokeepthetwoprojectssynchronized.

SetupPinswappingmethods

Therearetwowaysthatpinswapscanberepresentedattheschematiclevel.Thesearecontrolled fromtheOptionstaboftheprojectoptionsdialogbox.Inbothcases,theactualwiringonthe schematicwillnotbealteredjustitsconnectivity.
Figure32.Settingpinandpartswappingmethods.
Adding/RemovingNetLabelswillmovenetlabelsontheswappedpinsornetstoreflectthe changesthatweremadeduringpinswapping.Inthiscase,theschematicsymbolwillbeleft unchanged. ChangingSchematicPinswillallowAltiumDesignertomovethepinsonschematicsymbols accordingtothepinswapsperformedatthePCBlevel. Wherebothoptionshavebeenchecked,AltiumDesignerwilldefaulttoswappingnetlabels.Ifno labelsexistonthenets,itwillswappinsontheschematicsymbols.

SetupSwapgroups

Beforepinscanbeswappedwitheachother,itisimportanttofirstsetupswapgroupIDs,asitmay notbedesirable(oracceptable)forallpinstobeswappedwithoneanother.WhileallI/Opinswithin anFPGAcantheoreticallybeswappedtogiveabetterlayoutforrouting,conditionsmaydictate otherwise.Firstly,somepinshaveadditionalspecialfunctions(clockpins,configpinsandVREFpins tonameafew),anditmaybepreferabletoreservethesefortheirspecialpurpose.Secondly,setting limitationsherewillallowanyswappingprocesstoobeythebankingandI/Ostandardsrequirements asdescribedearlier.Forthisreason,itmaybedesirableforpinsinacertainbanktoonlybe swappablewitheachother(orperhapsotherbankswithcompatibleI/Ostandards). SwapgroupsmaybedefinedatschematicorPCBlevel,asdescribedbelow.
Settingswapgroupsintheschematic
Todefineswapgroupsintheschematiclevel,selecttheToolsConfigurePinSwappingoption. Theresultingdialogboxwilllistallcomponentsinthedesign.
Figure33.Settingupswapgroupsforvariouscomponents.
SelectthecomponentyouwishtodefineswapgroupsforandclickontheConfigureComponent buttonorsimplydoubleclickthecomponentinthelisttoaccesstheConfigurePinSwappingFor dialog.
SettingswapgroupsinthePCB
RightclickthecomponentyouwishtosetupforpinswappingandselecttheComponent Actions>>ConfigurePin/PartSwapping. SelecttheTools>>Pin/PartSwapping>>ConfigureoptiontoaccesstheConfigure SwappingInformationInComponentsdialogbox(seefigureabove). Selectthe componentyouwishtodefineswapgroupsforandclickontheConfigureComponent buttontoaccesstheConfigurePinSwappingFor dialog.
Figure34.SpecifyingswapgroupIDsinthepinswapmanager.
AllpinswiththesameswapgroupIDcanbefreelyswapped. AssigneachI/Opinonthedevicetotherequiredswapgroup.Eithermanuallyenterthelabelfor thegroupdirectlyintheSwapGroupIDfield,orusetherightclickmenutoassignswapgroups byvariouspinattributes.
SetupEnablingcomponentsforpin/partswapping
Onceswapgroupshavebeendefined,onemorestepisrequiredbeforetheactualpinswap.Altium Designerwillonlyswappinsforcomponentswhichhavebeenspecificallymarkedasallowingpin swapping.Todothisforagivencomponent,selectitinPCBmodeandviewthecomponents properties.Then,underswappingoptions,makesurethatEnablePinSwapshasbeenenabled. Dothisforeachcomponentthatrequirespinswapping.
Figure35.Enablingpinswapsforacomponent.

Swapping

HavingdefinedtheSwapGroupIDsasappropriate,theactualprocessofswappingpinscannowbe performed.WiththePCBdocumentactive,simplyclickonthePin/PartSwappingentryunderthe Toolsmenuandchooseamethodtoswappins. TheAutomaticNet/PinOptimizermaybeusedonanyorallcomponentsinadocumentandisnot limitedtoFPGAcomponents.Thispinswapperwillattempttofindtheoptimalpinallocationsfor routing,whilstobeyingthepinswapGroupIDspreviouslysetup. Itrunsthroughatwostage process:thefirststageisafastsinglepassoptimizerthatwillattempttominimizecrossoversand connectionlengths,whilethesecondstageisaniterativeoptimizerwhichperformsmultiplepasses. Thesecondstageisoptional,asthetimerequiredfortheiterativeprocessincreasessignificantly whenattemptingtooptimizemultiplecomponents.

Figure36.Ratsnestpriortoautomatedpinswapping
ThetwoPCBsnapshotsdepictedaboveandbelowshowhowtheautopinswappingtoolcanbe usedtogreateffecttoobtainanoptimizedsetofpinallocationsfromwhichtoroute.Inthiscase,all I/OpinsontheFPGAdevicehavebeenassignedthesameswapgroupID.
Figure37.Unraveledratsnestafterautomatedpinswapping
TheInteractivePin/NetSwappingtoolallowsforfinetuningandgivesthepowertomakeany numberofindividualpinswapsagain,inaccordancewiththepinswapgroupIDsalready configured. Asequenceofswappingprocessescanbeperformed.Forexample,theautomatictoolmayberun initiallyandthentheinteractivetoolusedafterwardstofinetuneacoupleofoutofplacenets/pins. IfanyFPGAcomponentsinthedesignarelinked,duetothedesignbeingmultichannelinnature, (e.g.U1_X1,U1_X2),theymustbeoptimizedtogether.Whenusingtheinteractivepinswapping tool,swappingcannotbecarriedoutonthelinkedcomponentandadialogwillappearalertingyou tothisfact.Forexample,ifU1_X2islinkedtoU1_X1,bothcomponentsmustbeoptimizedtogether, butmanualpinswappingcanonlybecarriedoutonU1_X1.
Apinswapoperationachievestwothings.Firstlyitcopiestheimportantpropertiesfromthenewpin thiswillbetheelectricaltypeofthepinaswellasanyparametersonthatpin.Secondlyitwill add/rename/removeanattachednetlabelforthatpinasappropriate.Notethatthissecondstepcan onlyoccuriftheFPGAcomponentschematicsheethasbeenautogeneratedusingtheFPGATo PCBProjectWizardorhasbeencreatedusingasimilardesignstyle. AfterupdatingthePCB,thechangesneedtobepropagatedtotherestoftheproject.Toupdatethe PCBschematics,gotoDesign>>Update. Onceupdated,youcanthenusetheFPGA WorkspaceMaptopropagatethenewchangesintotheFPGAproject.Youwillnoticethatthe schematicFPGAprojectlinkappearsoutofdate.
Figure38.ResynchronizingthePCB/FPGAprojectlinkafterpinswapping
ClickingonthislinkwillbringuptheSynchronizedialog,withtheaffected(swapped)pins highlightedinred,asshownbelow.
Figure39.ManagingsynchronizationsbetweenPCBandFPGAprojects
ClickontheUpdateToFPGAbuttontopushthechangestotheFPGAproject,ormorespecifically, theappropriateFPGAconstraintfile.TheupdatewillconsistofanumberofparameterchangeECOs (appearingasaseriesofchangeparametervaluemodificationsintheEngineeringChangeOrder dialog).

Figure40.ConfirmECOs

DespitehavingpassedthedesignchangesthroughfromthePCBprojecttotheFPGAproject,the FPGAWorkspaceMapdialogwillnotshowthedesignsasbeingfullysynchronized.Thisis becauseFPGAsignalshavebeenrenamedwithdifferentnetnamesinthePCBproject.Also,the PCBdesigncontainsadditionalconnectionsnotrepresentedattheFPGAlevel(foralternateFPGA implementations).Thisdoesnotmeanthatfunctionallythetwodesignswillnotworkbutratherthat initscurrentimplementation,thesetwodesignshavesomedifferencesnotrelatedtothe functionality.

ItmaybethatpinchangeshavebeenmadeinboththePCBprojectandFPGAprojectwithouta synchronizeoccurring.Ifthisisthecase,enteringtheFPGAWorkspaceMapdialogwillshowthe schematicFPGAprojectlinkoutofdate(Red). ClickingonthelinkwillopentheSynchronizedialog,withalldifferenceshighlightedinred.Itisnot possibletopasstherelevantchangesintheirrespectivedirections(PCBtoFPGAandFPGAto PCB)simultaneously.Thesequenceforpassingthechangesasrequiredandresynchronizingthe linkissummarizedasfollows: Firstchoosetheinitialdirectioninwhichtopasschanges,byclickingoneithertheUpdateTo PCBorUpdateToFPGAbuttons IntheEngineeringChangeOrderdialogthatappears,allchangeswillbegearedtothechosen direction.Enableonlythosemodificationsthatarerequiredforthatdirection. Executethechanges WhentheSynchronizedialogreappears,clickontheUpdatebuttonthatwasnotinitially pressed,inordertopasschangesinthesecondofthetwodirections
ExecutethechangesinthesubsequentEngineeringChangeOrderdialogthatappears TheSynchronizedialogwillreappear,showingnodifferencesintheMatchedSignalslist (appearingtotallygreen).IntheFPGAWorkspaceMapdialog,thelinkwillhavereturnedtoitsfully synchronizedstatus(Green).

Exercise4Pinswapping

Thisexercisecontinuesonfromworkdoneinthepreviousexercise. 1. OpenSLRev1.01NoRoutes.PcbDoc. 2. ChecktheAdding/RemovingNetLabelsoptionintheoptionstaboftheprojectoptionsdialog box.LeavetheChangingSchematicPinsoptionunchecked. ClickOKtoclosetheproject optionsdialog. 3. Select ToolsPin/PartSwappingConfigure 4. SelecttheFPGAcomponent,andConfigureComponent 5. EnsureShowI/OPinsOnlyisselectedfromthedropdownlistonthebottomleftofthedialog box. 6. CreateauniqueSwapGroupID foreachofthefollowingsignals: a. I\N\I\T\ b. DIN 7. AllotherIOpinscanbeplacedintoasingleswapgroupcalledgeneral_IO.
Figure44.SpecifyswapgroupIDsforalloftheIO
8. SelectOK. 9. ZoomintoviewtheFPGAdeviceinthecentreofthePCB. 10. DoubleclickontheFPGAdevice.WhentheComponentU1dialogappears,changethe Rotationto180degreesandclickOK. 11. Usetheautomaticpinswappingtorearrangethepins. 12. Waitforamomentforthesystemtoperformthepinswapping. 13. GototheDesign menu,andselectUpdateSchematicstobringthechangesacrosstothePCB schematics. 14. OpentheFPGAWorkspaceMap,andresolveanyunsynchronisedsignals.ThePCBshouldbe themasterdocumentatthisstagesoselectUpdatetoFPGAwhenperforminganychanges. 15. Saveyourwork.

6.Commissioningthedesign

OneoftheadvantagesofhavingahardwareplatformsuchastheDesktopNanoBoardatyour disposalduringdevelopmentisthatyoucanperformastagedmigrationofthedesignontoacustom targetPCB.Evenifcomponentsforthetargethavenotyetarrived,initialcommissioningcanbegin bycouplingthetargettotheNanoBoardandusingNanoBoardresourcesasasubstituteforthe missingcomponents.

Exercise5Migrationstage1

Inthisexercise,weconsiderthescenariowhereoneormoreofthetargetresourcesareyettobe placed.Inthiscasewemaychoosetorunthemainapplicationfromthetargetboardbutuse peripheralsavailableontheNanoBoardtotestourapplication.Forthisexercisetofunctioncorrectly wewillneedtoloaddesignsontoboththeNanoBoardandTargetplatforms. 1. Locatethe.\Module3\Exercise5\directoryandload SLRev1.01.PrjPCBaswellasFPGA_NB\SpiritLevel_NB.PRJFPG 2. ObservethecontentsoftheschematicdocumentSL_FPGA_NB.SchDoc.Noticehowthe NEXUSJTAGConnectorneedstobepresentandtheTDI/TDOloopmadetoensurethatthe JTAGsoftchainisnotbrokenwithintheNanoBoarddevice. 3. SwitchofftheDesktopNanoBoardandtargetboardpower. 4. Usinga10pinribboncable,connectHDR1onthetargetboardtoUSERBOARDAonthe NanoBoard. 5. Usinga20pinribboncable,connectHDR2onthetargetboardtoUSERHEADERAonthe NanoBoard. 6. EnsuretheXaxisjumperisremoved fromthetargetboard. 7. EnsureallDIPSwitchesonthetargetboardaresettotheONposition. 8. PlacetheCONFIGjumperonthetargetboard. 9. SwitchontheNanoBoardandtargetboard. 10. OpentheDevicesviewandverifytheexistenceoftwoFPGAdevices(andoneconfiguration device)intheHardChain.Thefirstdevicewillalways betheNanoBoarddevice. 11. BuildanddownloadtheSpiritLevel_NB/NB_BaseconfigurationtotheNanoBoarddevice. 12. BuildanddownloadtheSpiritLevel/Tgt_Spartan2configurationtothetargetboard device. 13. ObservethestatusoftheProcessorinthesoftchain.If,afterdownloadingbothprojects,this deviceislistedasMissing,itislikelythesoftchainisbrokensomewhere.Verifythataloop betweenJTAG_NEXUS_TDIandJTAG_NEXUS_TDOexistsontheSL_FPGA_NB.SchDoc. Rebuildtheprojectifnecessary. 14. SettheNanoBoardclockfrequencyto6MHzandensurethatDIPSwitch8ontheNanoBoardis ON.Observethedisplayonthetargetboard.AssertoneortwooftheNanoBoardslowerDIP SwitchesandseewhatchangeoccursintheTargetsLCD.IfthetargetboardLEDsarenot flashingthenthisindicatesitisnotreceivingasignalfromtheNanoBoard.Ensurealloutputs fromtheDigitalIOBonthetargetboardare0andcheckthewiringbetweentheNanoBoardand thetargetboard.Alsoensuretherespectiveprojectshaveloadedcorrectly.
Figure45.Devicesviewwithalldevicescorrectlyconnectedandprogrammed.
Figure46.Devicesviewafteralldeviceshavebeenprogrammedbutwithbrokensoftchain

Exercise6Migrationstage2

Inthisfinalstage,wewillremovetheNanoBoardfromtheloopandrunthedesigncompletelyfrom thetargetboard.Thisexercisewillfollowondirectlyfromthepreviousone. 1. ClosetheSpiritLevel_NB.PRJFPGproject. 2. EnsurethatboththeDesktopNanoBoardandtargetboardareswitchedoff. 3. RemovethedaughterboardfromtheNanoBoard. 4. Disconnectthe20pinribboncablebutleavethe10pincableconnected. 5. EnsuretheXaxisjumperisinplaceonthetargetboard. 6. EnsuretheCONFIGjumperisinplaceonthetargetboard. 7. ApplypowertoboththeNanoBoardandtargetboard. 8. BuildanddownloadtheSpiritLevel/Tgt_Spartan2configurationtothetargetboard device. 9. Oncethedesignisloaded,trytiltingthetargetboardandobservetheLCD. 10. Notetheexistenceofanumberofdownloadableinstrumentspresentinthetargetdevice.Note thattheyarefullyfunctionalonthetargetdeviceanddontrequirethepresenceofthe NanoBoard.

Exercise7Calibration

Someofthetargetboardswillnotdisplayazeroreadingwhenplacedonalevelsurface.Inthis exercisewewillshowhowtocalibratethiserrorout.Thisexerciseflowsonfromtheprevious exerciseandusesthesamesourcefiles. 1. Ensurethattheprojectfromthepreviousexercisehasbeenloadedandisoperational. 2. OpenTimeTSK51.C andlocatelines93and94.Tryanonzeronumber(between1and255)to applyacalibrationfactor.RemembertousetheCompileandDownloadbuttontoquicklyrebuild andrunthesoftware.
Figure47.Applyingacalibrationfactorbyhardcodingitintothesourcecode
3. Iterativelytrytofindthebestcalibrationfactortoproduceazeroreadingonaflat,levelsurface. 4. Saveyourwork.
Exercise8BootstrappingtheFPGA
AnFPGAdesignisnotmuchgoodifeverytimetheboardispoweredupitneedstobeconnectedto someprogrammingdevicetoconfiguretheFPGA.Thespiritlevelapplicationwasdesignedto operateasastandalonesystemandsoitneedssomemeansforstoringtheFPGAconfiguration whenpowerisremoved.Forthispurpose,aserialconfigurationdevicehasbeeninstalledonthe targetboard.Onpowerup,theFPGAdeviceobservesthatitisconnectedtotheconfiguration deviceandautomaticallyconfiguresitselffromthedevice.Inthisfinalexercisewewillprogramthe configurationdeviceandmakethespiritlevelatrulyselfcontainedembeddedsystem.Thisexercise flowsonfromthepreviousone.Anycalibrationfactorsincorporatedintothesourcecodewillbe includedinthedeviceconfiguration. 1. Ensurethattheprojectfromthepreviousexercisehasbeenloadedandisoperational. 2. IftheMakePROMFilestepintheBuildflowiscurrentlygreyedout,enablethisstepbyclicking onitsoptionsiconandspecifytheappropriateconfigurationPROMdevice.

FPGADesignBasics
AltiumDesignerTrainingModule

FPGADesign

DocumentVersion1.2,February2008 Software,documentationandrelatedmaterials: Copyright2008AltiumLimited. Allrightsreserved.Youarepermittedtoprintthisdocumentprovidedthat(1)theuseofsuchisfor personaluseonlyandwillnotbecopiedorpostedonanynetworkcomputerorbroadcastinany media,and(2)nomodificationsofthedocumentismade.Unauthorizedduplication,inwholeorpart, ofthisdocumentbyanymeans,mechanicalorelectronic,includingtranslationintoanother language,exceptforbriefexcerptsinpublishedreviews,isprohibitedwithouttheexpresswritten permissionofAltiumLimited.Unauthorizedduplicationofthisworkmayalsobeprohibitedbylocal statute.Violatorsmaybesubjecttobothcriminalandcivilpenalties,includingfinesand/or imprisonment. Altium,AltiumDesigner,BoardInsight,CAMtastic,CircuitStudio,DesignExplorer,DXP,LiveDesign, NanoBoard,NanoTalk,Nexar,nVisage,PCAD,Protel,SimCode,Situs,TASKING,andTopological AutoroutingandtheirrespectivelogosaretrademarksorregisteredtrademarksofAltiumLimitedor itssubsidiaries. Microsoft,MicrosoftWindowsandMicrosoftAccessareregisteredtrademarksofMicrosoft Corporation.OrCAD,OrCADCapture,OrCADLayoutandSPECCTRAareregisteredtrademarksof CadenceDesignSystemsInc.AutoCADisaregisteredtrademarkofAutoDeskInc.HPGLisa registeredtrademarkofHewlettPackardCorporation.PostScriptisaregisteredtrademarkofAdobe Systems,Inc.Allotherregisteredorunregisteredtrademarksreferencedhereinarethepropertyof theirrespectiveownersandnotrademarkrightstothesameareclaimed.

Module1

1 FPGADesign.... 11 1.1 Learningobjectives... 11 1.2 Topicoutline.... 11 IntroductiontoFPGADesign... 12 2.1 FPGAbasics.... 12 CreatinganFPGAproject... 13 3.1 Overview.... 13 3.2 Aquickwordaboutprojectsanddesignworkspaces.. 13 3.3 FPGAproject.... 14 FPGAschematicconnectivity... 15 4.1 Overview.... 15 4.2 Wiringthedesign... 15 4.3 IncludingHDLsourcefilesinaschematic... 15 4.4 Establishingconnectivitybetweendocuments.. 15 4.5 Usingbusesandbusjoiners... 16 FPGAreadyschematiccomponents.. 19 5.1 Overview.... 19 5.2 Processorcores.... 19 5.3 DesktopNanoBoardportplugins.. 110 5.4 PeripheralComponents... 110 5.5 Genericcomponents... 110 5.6 Vendormacroandprimitivelibraries.. 110 5.7 Exercise1CreateaPWM... 111 Targetingthedesign... 113 6.1 Constraintfiles.... 113 6.2 Configurations... 114 6.3 NanoBoardconstraintfiles.. 114 6.4 ConfigurationManager.... 114 6.5 AutoConfiguringanFPGAproject.. 115 6.6 Definingconstraintsmanually.. 115 6.7 Editingaconstraintfile... 116 6.8 Exercise2ConfiguringMyPWM... 117 Runningthedesign.... 119 7.1 Overview... 119 7.2 Controllingthebuildprocess... 119 7.3 Understandingthebuildprocess... 120 7.4 Buttonregions... 120 7.5 Accessingstagereports/outputs... 121 7.6 Buildstages.... 121 7.7 Configuringabuildstage... 124 7.8 HowAltiumDesignerinteractswithbackendvendortools. 125 7.9 Exercise3RunMyPWMontheNanoBoard.. 125 Embeddedinstruments... 126 8.1 Overview... 126 8.2 OnChipdebugging.... 126 8.3 CLKGEN... 127 8.4 CROSSPOINT_SWITCH... 127 8.5 FRQCNT2... 127
8.6 8.7 8.8 8.9 8.10 8.11 8.12 9
IOB_x... 128 DIGITAL_IO... 128 LAX_x.... 129 TerminalConsole... 131 Exercise4AUsingembeddedinstruments.. 131 WherearetheInstruments?... 135 Enablingembeddedinstruments... 135
InteractingwiththeNanoBoard... 137 9.1 Overview... 137 9.2 NanoBoardcommunications... 137 9.3 Technicalbackground... 138 9.4 TheNanoBoardcontroller... 140 9.5 FPGAI/Oview... 141 9.6 Livecrossprobing... 142 9.7 Exercise4BViewMyPWMontheNanoBoard.. 142 Creatingacorecomponent... 143 10.1 Coreproject.... 143 10.2 CreatingacorecomponentfromanFPGAproject. 143 10.3 AwordaboutEDIF... 144 10.4 Settingupthecoreproject.. 144 10.5 Constrain/configure... 145 10.6 Creatinganewconstraintfile... 146 10.7 Creatingaconfiguration... 147 10.8 Synthesize.... 148 10.9 Publish.... 149 10.10 Creatingacoreschematicsymbol.. 149 10.11 Usingacorecomponent... 151 10.12 Exercise5CreateacorecomponentfromMyPWM. 152 FPGAdesignsimulation... 153 11.1 Creatingatestbench... 153 11.2 AssigningtheTestbenchDocument... 153 11.3 Initiatingasimulationsession.. 154 11.4 Projectcompileorder... 154 11.5 Settingupthesimulationdisplay... 155 11.6 Runninganddebuggingasimulation... 156 11.7 Exercise6CreateatestbenchandsimulateMyPWM.. 158 Review..... 159

LCD_BUSY VALIDKEY

NotethatapartfromtheJBtypejoiner,allbusjoinerpinshaveanIOdirectionusethecorrect joinertomaintaintheIOflow.PinIOcanbedisplayedonsheetifyouenablethePinDirection optionintheSchematicPreferencesdialog. TheuseofbusjoinersinFPGAdesignsisasignificantdeparturefromhowbusconnectivityis establishedonotherschematicdocumentshoweverthebenefitsofbusjoinerssoonbecomeclear. Netsextractedfromabusjoinerneednotberelatedinanywayie.havethesamenameand differingonlybynumber(Data[0],Data[1],Data[2],etc).Thebusjoinerexampleaboveshows howasinglebuscanbeusedtorouteanumberofLCDandKeypadsignalstogether,evenallowing thejoiningofotherbussesintoasinglebusofalargerwidth.
4.5.1 Busjoinernamingconvention
Busjoinersfollowastandardizednamingconventionsothattheycanbeeasilyfoundwithinthe FPGAGeneric.IntLiblibrary. J<width><B/S>[Multiples]_<width><[B/S]>[Multiples] Forexample: J8S_8B:describesabusjoinerthatroutes8singlewirestoasingle,8bitbus. J8B_8S:describesabusjoinerthatroutesasingle,8bitbusinto8singlewires. J8B_4B2:describesabusjoinerthatroutesasingle8bitbusintotwo4bitbusses, J4B4_16B:describesabusjoinerthatroutesfour,4bitbussesintoasingle16bitbus.
4.5.2 Busjoinersplitting/mergingbehaviour
Thebasicruleisthatbusjoinersseparate/mergethebits(orbusslice) fromleastsignificantbit(orslice)downtomostsignificantbit(orslice). Forexample,inFigure9,U17splitstheincoming8bitbusonpinI[7.0] intotwo4bitbusslices,OA[3.0]andOB[3.0].Obeyingtheleasttomost mappingattheslicelevel,thelowerfourbitsoftheinputbusmapto OA[3.0],andtheupperfourbitsmaptoOB[3.0].Followingthisthroughto thebitlevel,I0willconnecttoOA0,andI7willconnecttoOB3. ThejoinerU27mergesthefourincoming4bitslicesintoa16bitbus.With thisjoinerIA0connectstoO0,andID3connectstoO15.
4.5.3 Matchingbusesofdifferentwidthsusingthe JBtypebusjoiner

Figure9.Busjoiners

TheJBtypebusjoinerallowsyoutomatchnetsinbusesofdifferent mergeandsplitbuses widths.Itdoesthisvia2componentparameters,IndexAandIndexBthat mapfromonebusthroughtotheotherbus.TheseindicesmustbedefinedwhenyouuseaJB joiner.

Figure10.Joinbusesofdifferentwidths,andcontrolthenettonetmapping
ReadtheflowofnetsthroughaJBtypebusjoinerbymatchingfromthenetsintheattachedbus,to thefirstindexonthebusjoiner,tothesecondindexinthebusjoiner,tothenetsdefinedinthe secondbusnetlabel. LeftBusIndexAIndexBRightBus Therulesformatchingnetsateachofthepointsareasfollows:
Figure11.AnexampleofusingtheJBbusjoinertoachievesubsetmapping
Ifbothbusrangesaredescending,matchbysamebusindex(onerangemustliewithintheother forvalidconnections).InFigure11thematchingis:
IndexA9 IndexB9 ROMADDR9,thruto ADDR0 IndexA0 IndexB0 ROMADDR0
(InthisexampleROMADDR10thruROMADDR13willbeunconnected)
Figure12.Usingofabusjoinerforoffsetmapping

InFigure12thematchingis:

INPUTS15 INPUTS0
IndexA15 IndexB31 PORTB31,thruto IndexA0 IndexB0 PORTB16
Figure13.Usingabusjoinerforrangeinversion
Ifonebusrangeisdescendingandanotherisascending,theindicesarematchedfromleftto right.InFigure13thematchingis:
IndexA15 IndexB31 PORTB31,thruto INPUTS15 IndexA0 IndexB16 PORTB16

INPUTS0

Figure14.Anotherexampleofusingabusjoinerforrangeinversion

InFigure14thematchingis:

IndexA15 IndexB31 PORTB0,thruto IndexA0 IndexB16 PORTB15
5 FPGAreadyschematiccomponents

5.1 Overview

AwidevarietyofFPGAreadyschematic componentsareincludedwiththesystem,ranging fromprocessors,toperipheralcomponents,down togenericlogic.Placingandwiringthese schematiccomponents,orwritingVHDL,captures thehardwaredesign.TheFPGAreadyschematic componentsareliketraditionalPCBready components,exceptinsteadofthesymbolbeing linkedtoaPCBfootprinteachislinkedtoapre synthesizedEDIFmodel. Aswellascomponentsthatyouusetoimplement yourdesign,theavailableFPGAlibrariesinclude componentsforthevirtualinstruments,andthe componentsthataremountedontheNanoBoard andareaccessibleviathepinsontheFPGA. HelpforallFPGAreadycomponentscanbe accessedbypressingtheF1keywhilstthe componentisselectedinthelibrarylist.

Processorcores

Softcoreprocessorscanbeplacedfromthe \ProgramFiles\AltiumDesigner 6\Library\Fpga\FPGAProcessors.IntLib library.Atthetimeofreleaseofthismanual,the followingprocessorsandrelatedembedded softwaretoolsaresupported: TSK165Microchip165xfamilyinstructionset compatibleMCU TSK51/528051instructionsetcompatible MCU TSK80Z80instructionsetcompatibleMCU PPC405AEmbeddedPowerPCCore availableonsomeVirtexFPGAs TSK300032bitRISCprocessor Thereisalsofullembeddedtoolsupportfor: ActelCoreMP7softcore,whichrequiresthe appropriateActeldeviceandlicensetouse AlteraNiosIIsoftcore,whichrequiresthe appropriateAlteradeviceandlicensetouse XilinxMicroBlazesoftcore,whichrequiresthe appropriateXilinxdeviceandlicensetouse XilinxVirtex2ProbasedPowerPC405 AMCCPowerPC405discreteprocessorfamily ARM7,ARM9,ARM9E&ARM10Efamilies,supportedintheSharpBlueStreak(ARM20T) discreteprocessorfamily LPC2100,LPC2200,LPC2300&LPC2800ARM7baseddiscreteprocessorsfromNXP

Figure15.Thelibrariespanel
DesktopNanoBoardportplugins
HardwareresourcesontheDesktopNanoBoardcanbeaccessedviatheuseofcomponentsfrom the\ProgramFiles\AltiumDesigner6\Library\Fpga\FPGANB2DSK01Port Plugin.IntLiblibrary.

PeripheralComponents

ManyofthehardwareresourcespresentontheNanoBoardcomewithperipheralmodulesthatcan beincludedintheFPGAdesigntoeaseinterfacingtotheexternalport. Peripheralscanbeplacedfromthe\ProgramFiles\AltiumDesigner 6\Library\Fpga\FPGAPeripherals.IntLiblibrary.

Genericcomponents

Genericcomponentscanbeplacedfromthelibrary \ProgramFiles\AltiumDesigner 6\Library\Fpga\FPGAGeneric.IntLib.This libraryisincludedtoimplementtheinterfacelogic inyourdesign.Itincludespinwideandbuswide versionsformanycomponents,simplifyingthe wiringcomplexitywhenworkingwithbuses.Aswell asabroadrangeoflogicfunctions,thegeneric libraryalsoincludespullupandpulldown componentsaswellasarangeofbusjoiners,used tomanagethemerging,splittingandrenamingof buses. Foradefinitionofthenamingconventionusedin thegenericlibraryandacompletelistingof availabledevices,refertothedocument:CR0118 FPGAGenericLibraryGuide.pdf. Wildcardcharacterscanbeusedtofilterwhen searchingthecomponentlibrary.
Vendormacroand primitivelibraries
Ifvendorindependenceisnotrequired,thereare alsocompleteprimitiveandmacrolibrariesforthe currentlysupportedvendors/devicefamilies.These librariescanbefoundintherespectiveActel, Altera,LatticeandXilinxsubfoldersin\Program Files\AltiumDesigner6\Library\.The macroandprimitivelibrarynamesendwiththe Figure16.Usingwildcardstoquicklyfindaspecific string*FPGA.IntLib.Notethatsomevendors componentintheGenericLibrary requireyoutouseprimitiveandmacrolibrariesthat matchthetargetdevice.Designsthatinclude vendorcomponentscannotberetargetedto anothervendorsdevice.

Exercise1CreateaPWM

InthisexercisewewillcreateourfirstFPGAdesign.Inordertocompletethistaskyouwillneedto usethefollowingcomponentsfromtheirrespectivelibraries: Component

CLK_BRD

Library FPGANB2DSK01PortPlugin.IntLib
NameinLibrary CLOCK_BOARD

TEST_BUTTON

FPGANB2DSK01PortPlugin.IntLib

SW[7.0]

FPGANB2DSK01PortPlugin.IntLib FPGANB2DSK01PortPlugin.IntLib FPGAGeneric.IntLib

DIPSWITCH LED CB8CEB

LEDS[7.0]
U1 CB8CEB Q[7.0] CE C CEO TC CLR

FPGAGeneric.IntLib

U3 A[7.0] B[7.0] COMPM8B
I0 I1 I2 I3 I4 I5 I6 I7 U4

COMPM8B

O[7.0]

J8S_8B

1. 2. 3. 4.
OpenanewFPGAProject.SaveitasMyPWM.PrjFpg AddanewschematictoyourprojectandsaveitasMyPWM.SchDoc PlaceandwirethecomponentstocreatethePulseWidthModulator UsingcomponentsfromthetwolibrariesFPGAGeneric.IntLibandFPGANanoBoard PortPlugin.IntLib,placeandwiretheschematicshowninFigure17.
U1 CB8CEB VCC CLK_BRD U2 TEST_BUTTON INV
Q[7.0] CE C CEO TC CLR U3 A[7.0] B[7.0] COMPM8B GT LT I0 I1 I2 I3 I4 I5 I6 I7 U4 O[7.0] LEDS[7.0]
Figure17.Saveyourwork wewillcontinuewiththisschematicsoon

6 Targetingthedesign

Theschematicthatwehavejustcreatedcontainsalloftheconnectivitythatmustoccurinternallyon ourFPGAdevicebutwestillneedsomefurtherinformationtomaptheportsontheFPGAschematic tophysicalpinsonanactualFPGAdevice.Thisprocessiscalledtargetingourdesign.

Constraintfiles

Ratherthanstoringdeviceandimplementationspecificdatasuchaspinallocationsandelectrical propertiesinthesourceHDLorschematicdocuments,thisinformationisstoredinseparatefiles calledConstraintfiles.ThisdecouplingofthelogicaldefinitionofanFPGAdesignfromitsphysical implementationallowsforquickandeasyretargetingofasingledesigntomultipledevicesandPCB layouts. BelowweseeaconceptualrepresentationofanFPGAdesignsittinginsideanFPGAdevice.The redlinesindicatetheporttopinmappingsthatwouldbehandledbytheconstraintfile.
Figure18.ConceptualviewshowingthelinkageofportsonanFPGAschematicroutedtophysicaldevicepins.

Configurations

AConfigurationisasetofoneormoreconstraintfilesthatmustbeusedtotargetadesignfora specificoutput.Themigrationofadesignfromprototypetoproductionwillofteninvolveseveral PCBiterationsandpossiblyevendifferentFPGAdevices.Inthiscase,aseparateconfiguration wouldbeusedtobringtogetherconstraintfileinformationfromeachdesigniteration.Eachnew configuration(anditsassociatedconstraintfile(s)isstoredwiththeprojectandcanberecalledat anytime. Becauseconfigurationscancontainmultipleconstraintfiles,itcansometimesbehelpfultosplit constraintinformationacrossmultipleconstraintfiles.Usuallyonewouldseparatetheconstraintfiles accordingtotheclassofinformationtheycontain:
6.2.1 Deviceandboardconstraintinformation:
ThespecificFPGAdevicemustbeidentifiedandportsdefinedinthetoplevelFPGAdesignmustbe mappedtospecificpinnumbers.
6.2.2 Deviceresourceconstraintinformation:
Insomedesignsitmaybeadvantageoustomakeuseofvendorspecificresourcesthatareunique toagivenFPGAdevice.Someexamplesarehardwaremultiplicationunits,clockmultipliersand memoryresources.
6.2.3 Projectordesignconstraintinformation:

FPGAprojectfolder Usermodelstopfolder\Vendorfolder\Familyfolder Usermodelstopfolder\Vendorfolder Usermodelstopfolder Systemmodelstopfolder(Edif)\VendorFolder\Familyfolder Systemmodelstopfolder(Edif)\Vendorfolder Systemmodelstopfolder(Edif).

7.6.3 Build

Figure35.BuildstageoftheprocessflowforXilinxdevices.
Thisstageoftheprocessflowisusedtorunthevendorplaceandroutetools.Thisstagecanberun withtheDevicesviewconfiguredineitherliveornotlivemode.
Runningthetoolsatthisstagecanverifyifadesignwillindeedfitinsidethechosenphysicaldevice. YoumayalsowishtoruntheVendortoolsifyouwanttoobtainpinassignmentsforimportingback intotherelevantconstraintfile. TheendresultofrunningthisstageisthegenerationofanFPGAprogramming filethatwill ultimatelybeusedtoprogramthephysicaldevicewiththedesign.Thereareessentiallyfivemain stagestothebuildprocess: TranslateDesignusesthetoplevelEDIFnetlistandsynthesizedmodelfiles,obtainedfrom thesynthesisstageoftheprocessflow,tocreateafileinNativeGenericDatabase(NGD)format i.e.vendortoolprojectfile MapDesigntoFPGAmapsthedesigntoFPGAprimitives PlaceandRoutetakesthelowleveldescriptionofthedesign(fromthemappingstage)and worksouthowtoplacetherequiredlogicinsidetheFPGA.Oncearranged,therequired interconnectionsarerouted TimingAnalysisperformsatiminganalysisofthedesign,inaccordancewithanytiming constraintsthathavebeendefined.Iftherearenospecifiedconstraints,defaultenumerationwill beused MakeBitFilegeneratestheprogrammingfilethatisrequiredfordownloadingthedesigntothe physicaldevice. WhentargetingaXilinxdevice,anadditionalstageisavailableMakePROMFile.Thisstageis usedwhenyouwanttogenerateaconfigurationfileforsubsequentdownloadtoaXilinx configurationdeviceonaProductionboard. AftertheBuildstagehascompleted,theResultsSummarydialogwillappear(Figure36).This dialogprovidessummaryinformationwithrespecttoresourceusagewithinthetargetdevice. Informationcanbecopiedandprintedfromthedialog.Thedialogcanbedisabledfromopening, shouldyouwish,astheinformationisreadilyavailableintheOutputpanelorfromthereportfiles producedduringthebuild.
Figure36.Summarizingresourceusageforthechosendevice.

7.6.4 Program

Thisstageoftheprocessflowisusedto downloadthedesignintothephysical FPGAdeviceonaNanoBoardorproduction board.Thisstageisonlyavailablewhenthe DevicesviewisconfiguredinLivemode.
Figure37.ProgramFPGAstageoftheprocessflow.
Thisstageoftheflowcanonlybeused oncethepreviousthreestageshavebeen runsuccessfullyandaprogrammingfilehas beengenerated.Agreenarrowwillpointto thedevicetobeprogrammedintheHard DevicesChain. Astheprogrammingfileisdownloadedto thedeviceviatheJTAGlink,theprogress willbeshownintheStatusbar.Once successfullydownloaded,thetext underneaththedevicewillchangefrom ResettoProgrammed(Figure38)and anyNexusenableddevicesonthesoft chainwillbedisplayedasRunning(Figure 39).

CROSSPOINT_SWITCH

Figure45.Crosspointswitch,usedtocontroltheconnectionbetweeninputandoutputsignals
TheCROSSPOINT_SWITCHdeviceisaconfigurablesignal switchinginstrumentwhichprovidesanefficientmeansby whichtoswitchsignalsinadesign. Theinterconnectionbetweeninputandoutputblocksis completelyconfigurable.Initialconnectionscanbedefinedas partofdesigntimeconfiguration,butcanbechangedonthe flyatruntime,fromthedevice'sassociatedinstrumentpanel. Thelatterenablesyoutoswitchsignalswithouthavingtore synthesizeanddownloadtheentiredesigntotheFPGA.
U18 CrosspointSwitch AIN_A[7.0] AOUT_A[7.0] AIN_B[7.0] AOUT_B[7.0] BIN_A[7.0] BIN_B[7.0] CROSSPOINT_SWITCH BOUT_A[7.0] BOUT_B[7.0]

FRQCNT2

Figure46.Frequencycounter,usedtomeasurefrequencyinthedesign
U6 FREQA FREQB TIMEBASE FrequencyCounter FRQCNT2
Thefrequencycounterisadualinputcounterthatcandisplaythe measuredsignalin3differentmodesasafrequency,period,ornumberof pulses.
Figure47.DigitalIOmodule,usedtomonitorandcontrolnodesinthedesign
ThedigitalI/Oisageneralpurposetoolthatcanbeusedfor bothmonitoringandactivatingnodesinthecircuit.Itis availableineither8bitwideor16bitwidevariants,with1to 4channels. EachinputbitpresentsasaLED,andthesetof8or16bits alsopresentsasaHEXvalue.Outputscanbesetorcleared individuallybyclickingtheappropriatebitintheOutputsdisplay.AlternativelytypinginanewHEX valueintheHEXfieldcanaltertheentirebyteorword.IfaHEXvalueisenteredyoumustclickthe buttontooutputit.TheSynchronizebuttoncanbeusedtotransferthecurrentinputvaluetothe outputs.

DIGITAL_IO

Figure48.ConfigurableDigitalIOmodule,usedtomonitorandcontrolnodesinthedesign
TheconfigurabledigitalI/Oisageneralpurposetoolthatcanbe usedforbothmonitoringandactivatingnodesinthecircuit. Unlikeitslegacycounterparts(IOB_xfamilyofdevices),withthe DIGITAL_IOdeviceyouarenotconstrainedtolimitedsignalsof 8or16bits.Instead,anynumberofsignalsmaybeadded,and anynumberofbitscanbeassignedtoasinglesignal.Youmay alsohavedifferentnumbersofinputandoutputsignals.
ConfigurableDigitalIO InLEDs[7.0] Rot[7.0] SpareOutB[7.0] Zoom[7.0] SpareOutC[7.0] Flags[7.0] SpareOutD[7.0]
EachinputbitcanbepresentedinarangeofdifferentstylesincludingLEDs,numeric,LEDdigits,or asabar,andthesetofbitsalsopresentsasaHEXvalue.Outputstylescanalsovaryandinclude LEDs,numeric,LEDdigits,andaslider.EachoutputcanhaveapredefinedInitialValueandwill alsoincludeaHEXdisplay.Outputscanbesetorclearedindividuallyandthemethodwillvarywith thestyleselected.AlternativelytypinginanewHEXvalueintheHEXfieldcanalterthevalueofthe output.IfaHEXvalueisenteredyoumustclickthe buttontooutputit.TheSynchronizebutton canbeusedtotransferthecurrentinputvaluetotheoutputs.

Figure69.ConceptualViewofJTAGdataflows.

9.3.1 JTAGindepth

TheacronymJTAGstandsforJointTestApplicationGroupandissynonymouswithIEEE1149.1. ThestandarddefinesaTestAccessPort(TAP),boundaryscanarchitectureandcommunications protocolthatallowsautomatedtestequipmenttointeractwithhardwaredevices.Essentiallyit enablesyoutoplaceadeviceintoatestmodeandthencontrolthestateofeachofthedevicespins orrunabuiltinselftestonthatdevice.TheflexibilityoftheJTAGstandardhasalsoleadtoits usageinprogramming(configuring)devicessuchasFPGAsandmicroprocessors. Atminimum,JTAGrequiresthatthefollowingpinsaredefinedonaJTAGdevice: TCK:TestClockInput TMS:TestModeSelect
TDI:TestDataInput TDO:TestDataOutput TCKcontrolsthedatarateofdatabeingclockedintoandoutofthedevice.ArisingTCKedgeis usedbythedevicetosampleincomingdataonitsTDIpinandbythehosttosampleoutgoingdata onthedevicesTDOpin.
Figure70.UsingJTAGChaintoconnectmultipleJTAGdevicestogetherinadigitaldesign.
Figure70.JTAGTestAccessPort(TAP)StateMachine.
TheTestAccessPort(TAP)Controllerisastatemachinethatcontrolsaccesstotwointernal registerstheInstructionRegister(IR)andtheDataRegister(DR).DatafedintothedeviceviaTDI oroutofthedeviceviaTDOcanonlyeveraccessoneofthesetworegistersatanygiventime.The registerbeingaccessedisdeterminedbywhichstatetheTAPcontrollerisin.Traversalthroughthe TAPcontrollerstatemachineisgovernedbyTMS. 139

9.3.2 Nexus5001

TheflexibilityofJTAGforhardwaredebuggingpurposeshasflowedoverintothesoftwaredomain. Inthesamewaythattestengineershavesoughtastandardizedmethodfortestingsilicon,software engineershavealsosoughtastandardizedmeansfordebuggingtheirprograms. In1998,theGlobalEmbeddedDebugInterfaceStandard(GEDIS)Consortiumwasformed.Inlate 1999thegroupmovedoperationsintotheIEEEISTOandchangedtheirnametotheNexus5001 ForumandreleasedV1.0ofIEEEISTO1999.InDecember2003,V2.0wasreleased. TheNexus5001standardprovidesastandardizedmechanismfordebugtoolstointeractwithtarget systemsandperformtypicaldebuggingoperationssuchassettingbreakpointsandanalyzing variables,etc.Thereare4classesofNexuscomplianceeachwithdifferinglevelsofsupported functionality.ThelowestlevelusesJTAGasthelowlevelcommunicationsconduit. TheimplementationofNexus5001ontheDesktopNanoBoardhasbeenlabeledastheJTAGSoft Chain.Itisaserialchainjustlikethehardchainhoweverratherthanconnectingphysicaldevices together,itconnectsvirtualdevicestogether.Thesedevicesincludethesetofvirtualinstruments thataresuppliedwithAltiumDesigneranddescribedinthefollowingchapter.Controlofdeviceson theSoftChaincanbeperformedfromtheDevicesViewSoftChainDevicesarelocatedtowards thebottomoftheDevicesViewundertheHardChain. AswiththeJTAGHardChain,theSoftChaincanbetakenofftheNanoBoardviatheUserBoardA andUserBoardBconnectors.Thisprovidesthemeansfortargetsystemstoalsoincludevirtual instrumentsandtobenefitfromtheAltiumDesignerdevelopmentenvironment.SimilarlytotheHard Chain,itisimperativethatacompleteloopbemaintainedbetweentheSoftChainTDIandTDO connections.

Figure77. Specifyingthelocationofcorecomponentmodels.

Constrain/configure

TheconceptofconstraintfilesandconfigurationsiscentraltotheflexibilityofAltiumDesigner.They provideamechanismtoallowFPGAcircuitstobedevelopedindependentofthefinalphysical implementation.Ratherthanstoringdeviceandimplementationspecificdatasuchaspinallocations andelectricalpropertiesinthesourceVHDLorschematicdocuments,thisinformationisstoredin separatefilescalledConstraintfiles.ThisdecouplingofthelogicaldefinitionofanFPGAdesign fromitsphysicalimplementationallowsforquickandeasyretargetingofasingledesigntomultiple devicesandPCBlayouts. ThereareanumberofclassesofconfigurationinformationpertinenttodifferentaspectsofanFPGA project:
10.5.1 Deviceandboardconsiderations:
10.5.2 Deviceresourceconsiderations:
10.5.3 Projectordesignconsiderations:
Thiswouldincluderequirementswhichareassociatedwiththelogicofthedesign,aswellas constraintsonitstiming.Forexample,specifyingthataparticularlogicalportmustbeallocatedto globalclocknet,andmustbeabletorunatacertainspeed. Aconfigurationisasetofoneormoreconstraintfilesthatmustbeusedtotargetadesignfora specificoutput.Themigrationofadesignfromprototype,refinementandproductionwilloften involveseveralPCBiterationsandpossiblyevendifferentdevices.Inthiscase,aseparate configurationwouldbeusedtobringtogetherconstraintfileinformationforeachdesigniteration. Eachnewconfiguration(anditsassociatedconstraintfile(s)isstoredwiththeprojectandcanbe recalledatanytime. Tosummarize: Constraintfilesstoreimplementationspecificinformationsuchasdevicepinallocationsand electricalproperties. AConfigurationisagroupingofoneormoreconstraintfilesanddescribeshowtheFPGA projectshouldbebuilt.
Creatinganewconstraintfile
Whentargetingadesignforauserboard,itisoftennecessarytomanuallycreateatleastone constraintfile.Thisconstraintfilewouldincludeataminimumthedevicethatisbeingtargetedand mayincludeanynumberofadditionalconstraintsappropriateforthetargetPCB.Ascoresmay oftenbesynthesizedforanumberofpossibletargets,itisusefultodiscusstheprocessofmanually constrainingandconfiguringadesigninthecontextofcreatingcoreprojects. Beforeaconfigurationcanbebuilt,aconstraintfilemustexist.Constraintfileshavetheextension.Constraint.ConstraintfilesforusewiththeDesktopNanoBoardcanbefoundinthe\Program Files\AltiumDesigner6\Library\Fpga\directory.Ingeneralitisadvisabletotakeacopy ofthesefilesandstoreitinyourprojectdirectorybeforeaddingittotheproject.Thiswaytheproject iskeptselfcontainedandanyeditsyoumayinadvertentlymakewillnotaffectthesupplied constraintfile. Toaddyourown,newconstraintfile,rightclickontheprojectnameintheProjectspaneland selectAddNewToProjectConstraintFile. Anewblankconstraintfilewillappear.TospecifythetargetdeviceselectDesignAdd/Modify ConstraintPartandtheBrowsePhysicalDevicesdialogwillopen.

Figure78.TheBrowsePhysicalDevicesdialog,whereyouselectthetargetFPGA.
Figure79.Basicconstraintfile.
Selectthevendor,family,deviceand temperature/speedgradesasdesiredandclick OK. Alinesimilartotheoneabovewillbe automaticallyinsertedintotheconstraintfile: Savetheconstraintfile.Typicallyitwouldbe namedtoreflectitsrole forexampleifthe targetdevicewasaXilinxSpartan3FPGA mountedonyourprojectPCByoumightcallit MyProject_Spartan3_1500.Constraint. Youwillnoticetheconstraintfilehasbeen addedtotheprojectunderthesettingstab.
Figure80.ProjectwithconstraintFile.

Creatingaconfiguration

Aspreviouslymentioned,configurationsgroupanumberofconstraintfilestogethertocreateasetof instructionsfortheFPGAbuildprocess.Todefineaconfiguration: RightclickontheprojectnameintheProjectspanelandselectConfigurationManager
Figure81.Specifyingaconfigurationusingtheconfigurationmanager.
Ifyouhavejustrecentlycreatedanewconstraintsfile,youwillseeitlistedundertheConstraint Filename.Existingconstraintfilesthatcurrentlyarentintheprojectcanbeaddedbyselecting theAddbuttonnexttotheConstraintFilestext. Todefineanewconfiguration,selecttheAddbuttonnexttotheConfigurationstext.Adialog willappearrequestingyoutoprovideanameforthenewconfiguration.Thenamecanbe arbitrarybutitishelpfulifitprovidessomeindicationastowhattheconfigurationis for.
Havingdefinedthenewconfiguration,youmaynowassignconstraintfilestoitbytickingtheir associatedcheckbox.HerewehaveassignedtheconstraintfileMyConstraint_Spartan3_1500 totheTarget_XC3S1500configuration. ClickOKtosavetheconfiguration.
Figure82.Specifyingaconfigurationusingtheconfigurationmanager.
Althoughtheabovesimplisticexampleonlyhadoneconstraintfileandoneconfiguration,thepower ofconfigurationsreallybecomesapparentasthedesignmatures.Belowweseehowadesignhas beentargetedtomultipleplatforms:
Figure83.Exampleofaprojectwithmultipleconfigurationsdefined.
Configurationscanbeupdatedormodifiedasdesiredatanytimethroughouttheprojects developmentbyreturningtotheConfigurationManagerdialog.

Synthesize

Nowthatwehavedefinedaconfiguration wearereadytosynthesizethecoreforthe target. WiththetoplevelFPGAdocumentopen selectDesignSynthesize.Ifwehad definedmorethanoneconfigurationand wishedtosynthesizeallconfigurationsat oncewecouldselectDesign SynthesizeAllConfigurations. Ifyouhavenotalreadynominatedthe toplevelentity/configurationinthe SynthesistaboftheOptionsforCore Figure84.SpecifyinganFPGAprojectstopleveldocument. Project,theChooseTopleveldialogwill appear.EnterthecoreprojectnameorselectfromthedropdownlistandclickOKtocontinue. TheprojectwillbesynthesizedresultinginthegenerationofVHDLfilesfortheschematic,EDIF filesfortheschematicwiringandparts,andasynthesislogfile.Thesewillallbelocatedunder theGeneratedfolderintheprojectpanel. YouwillobservetheconfigurationnameinbracketsbesidetheGeneratedFolder.Hadwe synthesizedmorethanoneconfigurationthenaseparateGeneratedfolderwouldhaveappeared foreachofthedefinedconfigurations.

Whenacorecomponentissynthesizedandpublished,theEDIFmodelisarchivedintothelocation specifiedintheFPGAPreferencesdialog.Anyprojectthatsubsequentlyusesthecorecomponent mustensurethattheEDIFarchivecanbefoundwithinthesearchpath.Thesearchsequencefor EDIFmodelsis: $project_dir $user_edif\$vendor\$family $user_edif\$vendor $user_edif $system_edif\$vendor\$family $system_edif\$vendor $system_edif Notethatthesearchlocationsincludestheprojectdirectorywhichmakesitusefulifyouneedto transferthedesigntoanotherPCthatdoesnothavetheuserEDIFmodelslocationdefined. 151
10.12 Exercise5CreateacorecomponentfromMyPWM
1. CreateanewcoreprojectandcallitMyPWMCore.PrjCor.Notethatthefilenamemustnothave spacesinit. 2. SettheIncludemodelsinpublishedarchivecheckboxintheProjectOptionsdialog. 3. InthePreferencesdialog,gotoFPGASynthesis,andselectanoutputpathforEDIFfiles. Thispathshouldnotincludeanyspaces. 4. AttachtheexistingMyPWM.SchDocthatyoucreatedaspartofexercise3. 5. CreateaprojectlevelconstraintfileandcallitMyPWMPrj.Constraint.Addthefollowingtothis constraintfile:
Record=Constraint|TargetKind=Port|TargetId=CLK_BRD|FPGA_CLOCK_PIN=True Record=Constraint|TargetKind=Port|TargetId=CLK_BRD|FPGA_CLOCK=True Record=Constraint|TargetKind=Port|TargetId=CLK_BRD|FPGA_CLOCK_FREQUENCY=50Mhz Figure90.UpdatestobemadetoMyPWMPrj.Constraintfile.
6. CreateaconstraintfileeachforanAlteraCycloneIIdeviceaswellasaXilinxSpartan3device. 7. Createaconfigurationthatlinkseachoftheindividualdeviceconstraintfileswiththeproject constraintfile. 8. Synthesizeallconfigurationsandpublishthedesign.ChecktheUserPresynthesizedmodel Folder(assetinStep3)usingwindowsexplorerandviewthedirectoriesthatarecreatedand theircontents. 9. CreateacoreschematicsymbolandsaveittothelibraryMyCoreLib.SchLib 10. CreateanewFPGAprojectandschematicthatmakesuseofyourPWMcoreandtestitonthe NanoBoard.
U1 CLK_BRD LEDS[7.0] LEDS[7.0]

SW[7.0] TEST_BUTTON

MyPWMCore
Figure90.TestprojectusedtotestthefunctionofMyPWMCore.

11 FPGAdesignsimulation

AltiumDesignersupportsbehavioralsimulationofVHDLdesigns.Thisisparticularlyusefulwhen verifyingthefunctionaloperationofdigitalcircuitspriortoimplementingtheminsideanFPGA.

Creatingatestbench

Beforesimulationcanbegin,aVHDLTestbenchfilemustbecreatedtodrivethesimulation session.Conceptually,theTestbenchstraddlestheDesignUnderTest(DUT)anddrivestheDUTs inputswhilstobservingitsoutputs. VHDLTestbench

DUT Inputs

DesignUnderTest(DUT)

DUT Outputs

Figure91.ConceptualviewofhowaVHDLtestbenchinteractswiththeDesignUnderTest(DUT).
AltiumDesignerprovidesaconvenientmethodforbuildingaVHDLTestbenchbasedontheinputs andoutputsofthenominatedDUT.Ashelltestbenchfilecanbeautomaticallycreatedbythe system. Openaschematicdocumentandselect ToolsConvertCreateVHDLTestbench fromthemenu. OpenaVHDLdocumentandselectDesignCreateVHDLTestbench. AnewVHDLdocumentwillbecreatedwiththeextension.VHDTSTandwillbeaddedtotheproject. WithintheTestbenchfilewillbeacommentinsertstimulushere.ByplacingVHDLcodeatthis pointyoucancontroltheoperationofthesimulationsession.Ataminimum,theTestbenchmustset alloftheDUTsinputstoaknownstate.IftheDUTrequiresaclockthenthattoomustbeprovided bytheTestbench.MostsimulationerrorsoccurasaresultoftheTestbenchfailingtoproperly initializetheinputsoftheDUT.

AssigningtheTestbenchDocument
OnceyouhavecreatedtheTestbenchfilebutbeforeasimulationcanbegin,AltiumDesignerneeds tobeformallytoldwhichVHDLdocumentintheprojectwillbeusedtodrivethesimulation.Select ProjectOptionsbyrightclickingontheFPGAprojectintheProjectspanelorusethemenuto selectProjectProjectOptionsSelecttheSimulationtabfromwithintheProjectOptionsdialog andselecttheappropriate TestbenchDocument fromthedropdownlist.
Figure9218.Specifyingthetestbenchdocument
Initiatingasimulationsession
Asimulationsessioncanbeinitiatedby selectingSimulatorSimulatefromthe menuorbyclickingthesimulationbutton intheVHDLToolstoolbarwhilstaVHDL documentisactiveinthemainwindow.

Projectcompileorder

Whenyoufirstrunasimulationfromatestbench,AltiumDesignermayneedtoestablishthe compilationorderoftheVHDLdocuments.Whilstperformingthisprocess,youmayseeanerror appearintheMessagespanelwiththemessage:UnboundinstanceDUTofcomponentDonot beconcernedasthisisnormalwhenyoufirstrunasimulation.

Figure93.Messagespanel.

Afterabriefmoment,adialogmayappear promptingyoutospecifythetoplevel documentforsimulation(Figure94). Thecompilationorderoftheprojectcanbe changedatalatertimeifnecessaryby selectingProjectProjectOrder orbyright clickingontheFPGAprojectintheProjects panelandselectingProjectOrder.
Figure94.Choosingthetopleveldocument.
Settingupthesimulation display
TheSimulationSignalsdialog(Figure95)is automaticallypresentedatthebeginningofa simulationoritcanbeaccessedviaSimulator Signals. TheWatchNameisthenameofthesignaldeclared insidetheblockofVHDLcode. SignalsmustbeEnabledinordertobeapartofthe simulation.Furthermore,iftheyneedtobe displayedaspartofthesimulationoutputthen ShowWavemustalsobeselected. TheWaveformviewer(Figure95)providesa visualizationofthestatusofeachofthedisplayed signals. Theicon nexttothebusnameindicatesabus signal.Clickingonthisiconwillexpandthebus intoitsindividualsignalsforcloserinspection. Thetimecursor(indicatedbythepurplevertical bar)canbedraggedalongthetimeaxisviathe mouse.Thecurrentpositionofthecursoris providedinthetimebaracrossthetopofthe display. Zoominginoroutisachievedbypressingthe PageUporPageDownkeysrespectively. Thedisplayformatoftheindividualsignalscan bealteredviathemenuitemToolsFormat andRadix.