Understandingthedocumentstack
Figure1.Visualizationofhowthevariousprojectdocumentsarestacked
SynchronizationbetweenPCBandFPGAprojectsiscarriedoutandmaintainedbyestablishinga linkbetweenthetoplevelportsintheFPGAprojectspecifiedintherelevantconstraintfileand thecorrespondingpinsontheFPGAcomponentschematic.Linkingisachievedusingthesignal name.ThenamegiventotheportintheFPGAprojectmustbethesameasthenetlabelassigned tothecorrespondingpinontheschematiccomponentinthePCBproject. Figure1providesa visualizationofhowthevariousdocumentsinanFPGA/PCBprojectstackarelinkedtogether.

FPGA_Top.SchDoc

FPGAproject
ThetoplevelFPGAschematicdocument mustcontainportsatthepointwhere signalsareconnectedtophysicalpinson theFPGAdevice.Thenameoftheportsis importantastheywillbeusedinthe constraintsfile. FPGA.Constraint FPGAproject
TheConstraintfiledefinesthephysicalpin numberthatportsdefinedinthetoplevel FPGAschematicwillbeconnectedto.This isreferredtoasaportnametoFPGApin numbermapping.Portnamesdeclaredin theconstraintfilemust matchthose includedinthetoplevelFPGAschematic document. FPGA_Auto.SchDoc PCBproject
Theautogeneratedschematicsheetis createdfrominformationcontainedinthe FPGAconstraintfile.Essentiallythe autosheetisaschematicrepresentationof theporttopinmappingsmadebythe constraintfile.Porttopinconnectivityon theautosheetisaccomplishedthroughthe useofnetlabelsi.e.anetlabelis attachedtowiresconnectedtotheportson thesheetandacorrespondingnetlabelis alsoattachedtothedevicepin. FPGA_Manual.SchDoc PCBproject
Anoptionalmanualsheetisgeneratedas partoftheFPGAtoPCBprojectwizard. Thismanualsheetcontainsasheetsymbol oftheautosheettheportsonthe autosheetareconnectedtocorresponding portsonthesheetsymbol.Connectingto thissheetsymbolratherthandirectlytothe FPGAsymbolintroducesanimportant abstractionlayer.Thislayerfacilitateseasy (automated)updatestotheprojectifthe deviceorpinallocationsshouldchangeas theprojectdevelops. TargetPCB.PCBDoc PCBproject TheFPGAdepictedintheautosheetand abstractedonthemanualsheetwill eventuateintoaphysicaldeviceonthefinal PCB.Thephysicalpinsofthisdevicewill beconnectedtoportsasdescribedinthe autosheet.
Figure2.Theroleofthevariousdocumentsintheprojectstack
UsingtheFPGAtoPCBprojectwizard

WithaschematicdocumentintheFPGAprojectopenastheactiveviewinthemaindesignwindow, simplychoosetheToolsFPGAToPCBProjectWizardentryfromthemenu.Thewizardwill appear,asshowninFigure:
Figure3.TheFPGAToPCBprojectwizard.
ChoosingtheFPGAconfiguration
Thesecondpageofthewizardallowsyoutochoosetheconfigurationthatwillbeusedfortargeting theFPGAdesigntothePCB.TheconfigurationusesaconstraintfilethatdefinestheFPGAdevice tobeusedanditsassociatedpinmappings. TheconfigurationcaneitherbeanexistingonethatyouhavealreadydefinedaspartoftheFPGA project,oranewone,generatedbythewizard.Inthecaseofthelatter,thewizardwillgeneratea configurationandaddtoitanewconstraintfile.Thesewillhavedefaultnames(PCB ConfigurationandPCBConstraints.Constraintrespectively)andtheconstraintfilewillbe storedinthesamelocationastheFPGAprojectfile(*.PrjFPG),unlessotherwisespecified.
Figure4.Wizardbasedconfigurationgeneration.
Theconstraintfilethatisaddedtotheconfigurationwillcontainatargetdevicedefinitionforthe FPGAproject,accordingtothedeviceyouselectintheSelectedDevice field.Youcanbrowsefora devicebyclickingthebutton,totherightofthefield.ThiswillopentheChoosePhysicalDevice dialog,fromwhereyoucanperusefromanumberofdevicesavailableacrossaspectrumofFPGA vendordevicefamilies.
Figure5.BrowsingfortherequiredFPGAdevice.
InitialFPGApinassignments
ThesecondpageoftheFPGAtoPCBProjectwizardgivesyouthechoiceofwhattodowith unconstrainedportsi.e.portsthathavenotbeentiedtoaspecificpinonthetargetdevice.The decisionastohowthesepinsareassignedissomewhatarbitraryandsothereareanumberofways ofdoingthis:
Importingpinfilefromvendorplaceandroutetools
Clearlyforthisoptiontobeavailablethedesignmusthavepreviouslybeenbuiltforthecurrent deviceandaconstraintfileandconfigurationmustalreadyexist.Fortotallynewdesignsthisisthe preferreddesignpath.Itensuresthatthevendortoolsaregiventhemostopportunitytooptimizethe designwithoutbeingundulyconstrainedanditensuresthattheselecteddeviceiscapableof supportingthedesign.Inthiscase,thepinassignmentsshouldbemadepriortorunningtheFPGA toPCBprojectwizard.Withaconstraintfileopeninthemainwindow,selectDesignImportPin File fromthemenutoimportthevendorpinfile.Thefollowingdialogboxwillappear:
Figure6.Selectingconstraintstobeimportedfromthevendortools
AssigningpinsduringtheFPGAtoPCBwizard
ProbablythequickestandsimplestwaytoallocatepinsiswhilstexecutingtheFPGAtoPCBproject wizard.SelecttheAssignUnconstrainedPortsonthesecondpageofthewizard.Asthewizard executesitwillautomaticallyallocatepinnumberstounallocatedportsupdatingtheconstraintfile andautogeneratedsheetasitgoes.
Figure7.AssigningunconstrainedportsaspartoftheFPGAtoPCBprojectwizard

AssigningunconstrainedsignalsfromtheFPGAsignalmanager
ItisalsopossibletoallocateunconstrainedsignalsbyselectingtheAssignUnconstrainedSignals buttonintheFPGASignalManagerdialog(Figure8).
Figure8.UsingtheFPGAsignalmanagertoassignunconstrainedsignals
Performingpinassignmentsviathismethodisprobablylessadvisableasitdoesnotgivetheuser thechoicewhichconstraintfile(projectortarget)recordsthepinallocations.Furthermore,an additionalstepisrequiredafterthisonetoresynchronizethenetlabelsintheautogeneratedsheet.
Assigningsignalsmanuallyintheautogeneratedsheet
Thisisthemostlaboriousmethodandgenerallynotadvisable.Usingthismethodrequiresthe designertomanuallyenterthenetnamesforallportsontotheautogeneratedsheet.Asecond synchronizationstepisalsorequiredtopropagatethepinassignmentsintotheconstraintsfile.
ChoosingthetargetPCBproject
AfterchoosingtheFPGAconfiguration,theactualtargetPCBprojectmustnowbedefined.Simply accepttheWizard'sgenerationofanewproject(PCBProject1.PrjPCB),orbrowsetoandselect anexistingproject.InthecaseofanewPCBproject,thefilewillbestoredinthesamelocationas theFPGAproject.
ConfiguringtheFPGAcomponentschematicsheet
WhetherthePCBprojectalreadyexistsorisbeingnewlycreated,therelationshipbetweenthe FPGAprojectanditscorrespondingcomponentinthePCBprojecthastobemanagedinsomeway. Thisisachievedusingadedicated,autogeneratedschematicsheet,referredtoasthe'MainSheet' intheWizard.
Figure2.TheautogeneratedFPGAcomponentschematicsheet.
ThisschematicsheetwillbecreatedwiththecomponentsymbolplacedfortheFPGAdevice targetedintheconstraintfile.TheWizardallowsyoutodeterminewhereandbywhatname,the schematiciscreated.Bydefault,theschematicwillbenamedusingthechosendesignatorforthe FPGAcomponent(e.g.FPGA_U1_Auto.SchDoc)andwillbestoredinthesamelocationasthe FPGAproject.Eachusedpinonthecomponentsymbolislinkedtoaportentryintheconstraintfile bysignal(netlabel/port)name.ThenamesfornetsinthePCBprojectarethereforerequiredtobe thesameasthoseintheFPGAproject.Oncelinked,anychangesmadetothesourcedocumentsof eitherPCBorFPGAprojectcanbepassedon,ensuringthatthetwoprojectsremainsynchronized. 37
ConfiguringunallocatedI/O
TheWizardalsoallowsyoutodeterminehowanyunusedI/Opinsonthecomponentarehandled. YouhavetheabilitytocontrolthetreatmentofvariouscategoriesofpintypesindividuallyInput onlypins,VREFpins,SpecialFunctionpinsandallotherunusedpins. Foreachcategory,thepinscanbehandledinoneofthefollowingways: Tietosingleport Tieallunusedpinsinthecategorytoasingleport(whichwillalso appearontheparentsheetsymbol(ifapplicable)onthesheetabove)
Tietoindividualports Tieallunusedpinsinthecategorytotheirown,individualports (whichwillalsoappearontheparentsheetsymbol(ifapplicable)on thesheetabove) TietoportsbyIO bank(VREFonly) AddNoERCdirective Ignore TieallunusedVREFpinstoaportonabankbybankbasis(which willalsoappearontheparentsheetsymbol(ifapplicable)onthe sheetabove). AddaNoERCdirectivetoanunusedpin,sothatitisnotincludedas partoferrorcheckingwhenthedesigniscompiled Donothingwithanunusedpin

Figure3.SelectinghowunusedI/Oistobehandled
Note:ForVREFpins,whentheTietosingleportor TietoportsbyIObankoptionsareselected, youaregiventheadditionaloptionofwhetherornottoconnectviaPowerPorts.
Configuringthesheetsymbolschematicsheet
AspartofthePCBproject,youhavetheoptionofdefiningthe'owner'oftheFPGAComponent sheet(holdingthecomponentsymbolfortheFPGAdevice).ThefinalpageoftheWizardallowsyou todefinetheownerasasheetsymbol,which,ifenabled,willbecreatedonanadditionalschematic sheet,thenameandlocationofwhichyoucanfreelychoose.Bydefault,theschematicwillbe namedusingthechosendesignatorfortheFPGAcomponentonthepreviouspageoftheWizard (e.g.FPGA_U1_Manual.SchDoc)andwillbestoredinthesamelocationastheFPGAproject. Insummary,afteralloftheoptionsintheWizardhavebeensetasrequired,thefollowingwillbe generated: AnewPCBproject(ifspecified) Anewschematicsheet,addedtotheneworexistingPCBproject,whichcontainstheschematic representationoftheFPGAcomponent Anewschematicsheetwithparentsheetsymbol(ifspecified).Ifanexistingsheetistargeted, theparentsheetsymbolfortheFPGAComponentschematicwillbeadded/updatedas necessary Anewconfiguration(ifspecified),whichwillbeaddedtotheFPGAprojectfileandwhich containsanewconstraintfile Theconstraintfileeithernewforanewconfigurationoranexistingonecontainedinachosen configurationcontaining: apartconstraint aPCBboardconstraint alistofconstraintsforallportsonthetoplevelsourcefileoftheFPGAproject.Eachof theseportconstraintsismatched(andthereforelinked),bynetname,totheequivalentpin ontheFPGAcomponentinthePCBproject'sautogeneratedschematicsheet.
Exercise1RunningtheFPGAtoPCBprojectwizard
InthisexercisewewillutilizethedesigntargetedtotheSpartan2Edeviceandwewillrunthrough theFPGAtoPCBProjectWizard. 1. OpenthedesignSpiritLevel.PRJFPGinthefolder\Module3\Exercise1\ 2. OpentheconfigurationmanagerandmakesuretheNB1_6_XC2S300E6PQ208.Constraintis includedintheconfiguration.ClickOKtoclosetheconfigurationmanager. 3. OpentheFPGAschematicdocumentSL_FPGA_Complete.SchDoc. 4. Select ToolsFPGAtoPCBProjectWizard. 5. AttheSelecttheFPGAConfigurationstep,checktheUseExistingConfigurationoptionand specifyNB_Xilinx_Spartan2configuration.MakesureAssignUnconstrainedPortsisnot checked.
Figure4.UseanexistingconfigurationintheFPGAtoPCBProjectWizard
6. AttheConfigurethePCBProjectstep,specifythePCBProjectFileNameas SpiritLevel_2E.PrjPCB.
Figure5.SpecifythePCBprojectfilename.
7. AttheConfiguretheMainSheetstep,specifytheMainSheetFileNameas Auto_2E.SchDocandanyfurtheroptionsasdepictedinFigure6.ClickNexttocontinue.

Figure6.Mainsheetoptions.
8. AttheConfiguretheSheetSymbolSheetstep,checktheCreateSheetSymbolboxand specifytheSheetSymbolFileNameasSL_Top.SchDoc.ClickFinishtocompletethewizard.
Figure7.Symbolsheetoptions.
9. UseFileSaveAstosavethetwo,newlyautogeneratedschematicsheets 10. UseFileSaveProjectAstosavethenewlycreatedPCBprojectintothisdirectoryaswell. 11. Thebasicschematicfileshavenowbeencreatedandarereadyformodificationaccordingtothe specificprojectrequirements.Atthispoint,however,theFPGAprojectmaynotappearvisibly linkedtothePCBproject.RightclickonthePCBprojectintheprojectspanelandcompilethe design.Thedesigncompilerwillautomaticallychangetheprojectstructure.
Figure8.ProjectPanelaftercompiling.
12. Observethenewstructureofthecreatedschematicsheets. 13. Saveyourwork.
Modifyingtheautogeneratedsheet
Occasionallyitmaybenecessarytoperformmodificationstotheautogeneratedsheet.Thiswill causethePCBprojecttolosesynchronizationwiththeFPGAprojectandthedesignswillneedtobe resynchronizedthroughtheFPGAWorkspaceMap.Managingprojectsynchronizationisan automatedbutnotautomaticprocessandprojectsynchronizationcanonlybeperformedinone directionatonetimeie.designrevisionscanbepropagatedfromthePCBtotheFPGAorvice versabutnotbothwaysatthesametime.ExtremecautionshouldbeexercisedifboththePCBand FPGAprojectsarebeingworkedoninparallel. Situationsmightalsooccurinwhichadesignnevertotallysynchronizes.Thisiscommonlycaused whendifferencesexistinthenetnamingbetweenthePCBandFPGAschematics,or,when additionalcomponentsareconnectedtotheFPGAforpossiblefutureexpansion.Thelatter scenariomightincludetheadditionofaconnectorattheboardlevelthatisnotyetusedintheFPGA, andthusnotrepresentedintheFPGAdesign.IfthisoccursthePCBandFPGAdesignswillnot matchandthoughthismaycausethedesignstoappearoutofsync,thiswillnotaffecttheexisting functionalportionsofthedesign.
AwordaboutspecialfunctionFPGApins
SpecialFunctionPinsarehandledinaspecialwaywhencreatingtheautogeneratedsheet. Extremecaremustbeobservedtoensuretheirconnectivityismaintained.Asaruleofthumbitis besttoselecttheTietoindividualportsforSpecialFunctionPinsevenifyoudontintendtouse theminthefinaldesign.IfyouneedtouseanI/Opinthathasaspecialfunctionnetlabelattached toit,justremovethespecialfunctionnetlabelandreplaceitwiththenetlabelforthenetthatyoudo wishtobeconnected.Resynchronizethedesignasnecessary.

SelectinganyotheroptionotherthantheTietoindividualportswillcausespecialfunctionnet labelstoberippeduporrenamed.Beware!
Recreatingtheautogeneratedsheet
TheSynchronizedialogprovidesabuttontoRecreateAutogeneratedSheet.Thisfeatureshould beusedunderextremecare.IfthereareanyPCBdesignchangesthatareyettohavebeen propagatedbacktotheFPGAprojectthentheycanbedestroyedoncetheautogeneratedsheetis recreated.
Figure9.Recreatingtheautogeneratedsheetfromthesynchronizedialog.
Recallourpreviouswarningaboutthenatureofspecialfunctionpinsselectinganyotheroption otherthantheTietoindividualportswillcausespecialfunctionnetlabelstoberippedupor renamed.Beware!
2.Maintainingprojectsynchronization
MaintainingsynchronizationbetweenanFPGAprojectanditsparentPCBprojectisgreatly improvedthroughtheinternalsynchronizationmechanismsthatoperatewithinAltiumDesigner.Itis important,however,thatusersunderstandhowthissynchronizationprocessworkssothattheydont inadvertentlymakedesignchangesthatwilldefeatprojectsynchronization.

TheFPGAworkspacemap

Atanygiventimeduringthedesignprocess,thestatusofthelinkingbetweenFPGAandPCB projectscanbereadilycheckedbylaunchingtheFPGAWorkspaceMapdialog.Accesstothis dialogisprovidedbychoosingthecommandofthesamenamefromtheProjectsmenu,orby pressingthe buttonontheProjectspanel. IntheexamplebelowtheFPGAWorkspaceMapdisplaystherelationships(links)betweenvarious elementsofFPGAandPCBprojectsandthestatusoftheselinkswhetherthetwosidesofalink aresynchronizedanduptodateorwhethersomeactionisrequiredtoresynchronizethem.
Figure10.TheFPGAworkspacemapdialog.
Thevariouselementsinthetwoprojecttypesarelinkedinalogicalflowfromasoftcore microcontrollerplacedwithinanFPGAproject,toaPCBdesigndocumentwithinalinkedPCB project.Eachofthelinksaresummarizedbelow:

FPGAprojectsoftprocessor

TheSoftProcessorsregionofthedialogispurelyaddedforcompletenessandoffersataglance informationonthecoremicrocontroller(s)thatarebeingusedinaparticularFPGAproject.Thelink, assuch,isthereforecosmetic.Itwillalwaysbedisplayedassynchronized. 313
Schematicdocument(PCBproject)FPGAproject
ThislinkreflectsthesynchronizedstatusbetweentheFPGAcomponentinthePCBprojectandthe appropriateconfigurationintheFPGAproject.Whendeterminingthestatus,thesoftwareislooking foranynetrelatedchanges.

PCBdocumentschematicdocument(PCBproject)
ThislinkreflectsthesynchronizedstatusbetweentheFPGAComponentfootprintonthePCB documentandtheFPGAComponentsymbolontheschematicsheet,bothwithinthePCBproject.

Linkstatus

Alinkcanappearinoneoftwocolorsandhoveringoveralinkwillproduceatextualdescriptionofits status: Thegreenlinksignifiesuptodate(i.e.bothsidesare synchronized).Noactionisrequired. Theredlinksignifiesthatthetwosidesofthelinkarenot fullysynchronized(i.e.adesignchangehasbeenmadeon onesidebuthasyettobepassedtotheother).Clickingon aschematicFPGAprojectlinkwiththisstatuswillopenthe Synchronizedialog,fromwhereyoucanbrowseand matchanyunmatchedportsandpins.
Figure11.Determiningthelinkstatus
Whentwoelementsofthemapareshowntobeunsynchronized(i.e.thelinkbetweenthemisred), clickingonthelinkoritsassociatediconswillgiveaccesstoanumberofsynchronizationoptions. Thehintthatappearswhenhoveringoverthelinkwill,wherepossible,provideinformationonwhich directionsupdatesshouldbemadeinordertoachievesynchronization. Again,itmaybepossibleforadesigntonevertotallysynchronize. Thoughthismayoccur,itisnota signofafaileddesignitismerelythemethodwithwhichthesynchronizerevaluatesdifferences betweentheFPGAandPCBprojects.

Thesynchronizedialog

IftheFPGAWorkspaceMapdeterminesthattheprojectisnotsynchronized,aredlinkwillbe displayedbetweenthecorrespondingprojects.ClickingonthatlinkwillrevealtheSynchronize dialog.ThisdialogprovidesanautomatedmeansformaintainingsynchronizationbetweenFPGA andPCBprojects.Itisimportantatthispointthatthereaderunderstandthattheprocessis automatedbutnotautomaticandsomecareisrequiredtoensurethatrecentdesignchangesarenot overwritten.
Figure12.Thesynchronizedialogbox
TheSynchronizedialoghastwoprimaryregions.TheupperregioncontainsalistofPCBproject signalnamesthatcorrespondwithFPGAportnames.Thesesignalsarereferredtoasthematched signals.Informationconcerningthematchedsignalsisfurthersubdividedsothatsettingsrelatingto thePinnumberandElectricalTypecaneasilybecomparedbetweentheFPGAandPCBprojects. Thelowerregioncontainssignalsthatcantbe matchedbasedontheirsignalnamesotherwise knownasunmatchedsignals.TheSynchronizedialoghasnooptionbuttorequestuser interventioninknowinghowtomatchand/orhandlethesesignals. Projectsynchronizationcanonlybeperformedinonedirectionatonetimethatisdesignrevisions canbepropagatedfromthePCBtotheFPGAorviceversabutnotbothwaysatthesametime. WhereitisnecessarytoworkonboththeFPGAandPCBprojectsinparallel,astubprojectmay needtobecreatedtomanagesynchronizationbetweenthem.Moreinformationconcerningstub projectscanbefoundindocumentAP0102LinkinganFPGAProjecttoaPCBProject.pdf.

Figure21.Creatinga'RenamePCBNet'ToDoitem

RenameFPGAporttoPCBnet

Figure22.Creatinga'RenameFPGAPort'ToDoitem
OnceToDoitemshavebeenexported,performtheupdatesmanually,savetheaffectedfilesand checktheFPGAWorkspaceMapdialogagaintoensuresynchronizationhasbeenreestablished.

3.ConfiguringFPGAI/O

TheFPGAWorkspaceMapdialoggivesyoutheabilitytocheckthestateofthedesignacross linkedFPGAandPCBprojectsandthemeanstopropagatedesignchangesbetweenthetwo.The followingsectionsconsidersomeofthemorecommondesignchangesthatmightbemadeandthat requireuseofthisdialogtodetectsuchchangesandensuresynchronizationoftheentiredesign. Ineachcase,itisassumedthatthetwo,fulldesignprojectsarelocaltothedesignerstoredonthe onemachineandinthesamedirectorystructure.

ConfiguringI/Ostandards

FPGAdevicesgenerallysupportarangeofI/Ostandards.Thesestandardsfollowindustry specificationsandoftenincludeoptionslikeLVTTL,LVCMOSandPCItonameafew.Thisenables theFPGAtocommunicatedirectlywithotherdevicesrequiringacertainstandard.Oftenthe standardswillalsosupportfurthercustomizationincludingtheslewrate,currentstrengthand voltage. Eachdevicewillhaveitsownsetofsupportedstandards.Onlysupportedstandardscanbeselected forthecurrentdevice. ThereisacomplexsetofinteractionsbetweendifferentI/OstandardsinanFPGA.SomeI/O standardswillbeabletocoexistwhileothersaremutuallyexclusive.Oftentherequirementsare limitedtoI/Obanks,suchthatallpinswithinanI/ObankonanFPGAmusthavecompatibleI/O standards.ThisbecomesparticularlyimportantwithvoltagereferencedstandardssuchasGTL,as anI/Obankwillgenerallyonlybeabletosupportonevoltagereferencevalue. TheinteractionofselectedI/Ostandardswithoneanotherisnotmodeledhereandvendor documentationshouldbereferredtoformoredetailedinformation.Asageneralruleofthumb, keepingpinsusingdifferentI/OstandardsinseparateI/Obankswillensurecompatibility.Anyerrors willbepickedupwhenthevendorplace&routetoolsprocessthedesign.

Selectingstandards

I/Ostandards,slewratesanddrivestrengthsforeachpinofanFPGAdevicecanbedefinedinthe FPGASignalManagerdialog.ThisdialogisaccessedbychoosingtheFPGASignalManager entryundertheTools menu,fromanyschematicdocumentwithinthePCBorFPGAproject.When accessedfromaschematicinthePCBproject,ifmorethanoneFPGAcomponentispresenta dialogwillappearbeforehandlistingthecomponentsfromwhichtochoose.
Figure23.FPGASignalManager
Note:thelistofavailableI/Ostandardsiscontextsensitiveonlystandardsthatareapplicablefor thatparticularFPGAwillbeavailable.
FPGAsignalscanberapidlyupdatedingroupsbyusingthestandardshift/ctrlselecttechniqueand rightclickingoneoftheselectedrowstoaccessthepopupmenu.Additionalcolumnscanalsobe enabledfromthismenu. Afterdefiningthecharacteristicsfortheappropriatepinsofthedeviceasrequired,clickOKtoclose thedialog.TheEngineeringChangeOrderdialogwillappear,withthesettingsyoudefinelistedas aseriesofparameterstobeaddedtotheaffectedportconstraintentriesinthelinkedconstraintfile.

Figure28.Selectingaconfigurationtobelinked.
Whentherequiredconfigurationhasbeenassigned,theparentFPGAprojectwillbecomelinkedto thePCBprojectandisshowninthestructurehierarchyasasubdesignoftheschematicFPGA component.
Figure29.StructuralviewofaFPGAprojectlinkedtoaPCBproject.
Tobreakthelinkbetweenthetwoprojects,simplyclickanddragtheFPGAprojectentryintofree spacewithinthepanel(belowthelastentry). Nowthataconfigurationhasbeenlinked,theFPGAandPCBprojectsbecomelinkedandtheFPGA WorkspaceMapdialogwilldisplayalinkbetweentheschematiccomponentinthePCBprojectand theFPGAproject.
Figure30.FPGAworkspacemapshowingthesynchronizationstatusoflinkedprojects.
Theprojectsarenowlinked,buttheyareyettobesynchronized.
LinkinganautogeneratedsheettoanexistingPCBproject
IfyouselecttheoptiontoCreateSheetSymbol inthelaststageoftheFPGAtoPCBProject WizardasheetcontainingasheetsymboloftheFPGAprojectwillbecreated.Thiscanbeusedas thebasisforbuildingacompleteschematictodescribethetargetPCBhardware. Alternatively,ifyouareworkingwithaPCBprojectthatalreadyexists,youwillprobablyalreadyhave asheetwithmanysheetsymbolsleadingtovariousothersubsheets.Inthiscaseyoumaysimply wishtoconnectanexistingsheetsymboltotheautogeneratedsheet.Thisscenariowouldlikely occurwhereithasbeendecidedtochangetheFPGAdeviceonanexistingPCBdesign.Inthis case,youwouldopentheSheetSymboldialogfortheexistingsheetsymbolandmanuallyeditthe Filenamefieldtopointtotheautogeneratedsheet.
Figure31.Manuallylinkinganautogeneratedsheettoasheetsymbol.
Exercise3ManuallylinkingaPCBandFPGAproject
1. OpentheSLRev1.01.PrjPCBandtheFPGA_U1\SpiritLevel.PRJFPGprojectsatthe sametime. 2. OpentheFPGAWorkspaceMapandverifythatthereisnolinkbetweentheFPGAandPCB projects. 3. ChangetotheStructureEditorandestablishalinkbetweenthePCBandFPGAprojects. 4. ReopentheFPGAWorkspaceMapandverifythatalinknowexists. 5. ClickontheredlinkbetweentheFPGAandPCBprojectstoresolvetheunsynchronisedsignals. 6. Saveyourwork.

5.Pinswapping

5.1 PinswappinginthePCBdocument

Settingswapgroupsintheschematic
Todefineswapgroupsintheschematiclevel,selecttheToolsConfigurePinSwappingoption. Theresultingdialogboxwilllistallcomponentsinthedesign.
Figure33.Settingupswapgroupsforvariouscomponents.
SelectthecomponentyouwishtodefineswapgroupsforandclickontheConfigureComponent buttonorsimplydoubleclickthecomponentinthelisttoaccesstheConfigurePinSwappingFor dialog.
SettingswapgroupsinthePCB
RightclickthecomponentyouwishtosetupforpinswappingandselecttheComponent Actions>>ConfigurePin/PartSwapping. SelecttheTools>>Pin/PartSwapping>>ConfigureoptiontoaccesstheConfigure SwappingInformationInComponentsdialogbox(seefigureabove). Selectthe componentyouwishtodefineswapgroupsforandclickontheConfigureComponent buttontoaccesstheConfigurePinSwappingFor dialog.
Figure34.SpecifyingswapgroupIDsinthepinswapmanager.
AllpinswiththesameswapgroupIDcanbefreelyswapped. AssigneachI/Opinonthedevicetotherequiredswapgroup.Eithermanuallyenterthelabelfor thegroupdirectlyintheSwapGroupIDfield,orusetherightclickmenutoassignswapgroups byvariouspinattributes.
SetupEnablingcomponentsforpin/partswapping
Onceswapgroupshavebeendefined,onemorestepisrequiredbeforetheactualpinswap.Altium Designerwillonlyswappinsforcomponentswhichhavebeenspecificallymarkedasallowingpin swapping.Todothisforagivencomponent,selectitinPCBmodeandviewthecomponents properties.Then,underswappingoptions,makesurethatEnablePinSwapshasbeenenabled. Dothisforeachcomponentthatrequirespinswapping.
Figure35.Enablingpinswapsforacomponent.

Swapping

HavingdefinedtheSwapGroupIDsasappropriate,theactualprocessofswappingpinscannowbe performed.WiththePCBdocumentactive,simplyclickonthePin/PartSwappingentryunderthe Toolsmenuandchooseamethodtoswappins. TheAutomaticNet/PinOptimizermaybeusedonanyorallcomponentsinadocumentandisnot limitedtoFPGAcomponents.Thispinswapperwillattempttofindtheoptimalpinallocationsfor routing,whilstobeyingthepinswapGroupIDspreviouslysetup. Itrunsthroughatwostage process:thefirststageisafastsinglepassoptimizerthatwillattempttominimizecrossoversand connectionlengths,whilethesecondstageisaniterativeoptimizerwhichperformsmultiplepasses. Thesecondstageisoptional,asthetimerequiredfortheiterativeprocessincreasessignificantly whenattemptingtooptimizemultiplecomponents.
Figure36.Ratsnestpriortoautomatedpinswapping
ThetwoPCBsnapshotsdepictedaboveandbelowshowhowtheautopinswappingtoolcanbe usedtogreateffecttoobtainanoptimizedsetofpinallocationsfromwhichtoroute.Inthiscase,all I/OpinsontheFPGAdevicehavebeenassignedthesameswapgroupID.
Figure37.Unraveledratsnestafterautomatedpinswapping
TheInteractivePin/NetSwappingtoolallowsforfinetuningandgivesthepowertomakeany numberofindividualpinswapsagain,inaccordancewiththepinswapgroupIDsalready configured. Asequenceofswappingprocessescanbeperformed.Forexample,theautomatictoolmayberun initiallyandthentheinteractivetoolusedafterwardstofinetuneacoupleofoutofplacenets/pins. IfanyFPGAcomponentsinthedesignarelinked,duetothedesignbeingmultichannelinnature, (e.g.U1_X1,U1_X2),theymustbeoptimizedtogether.Whenusingtheinteractivepinswapping tool,swappingcannotbecarriedoutonthelinkedcomponentandadialogwillappearalertingyou tothisfact.Forexample,ifU1_X2islinkedtoU1_X1,bothcomponentsmustbeoptimizedtogether, butmanualpinswappingcanonlybecarriedoutonU1_X1.

Figure42.ManagingsynchronizationsbetweenPCBandFPGAprojects
ClickontheUpdateToPCBbuttontopushthechangestothePCBproject.Thiswillperforma seriesofpinswapoperations(usingECOs)ontheschematicdocument. PerformingthesechangeswillthenmakethePCBschematiclinkoutofdate(ifPCBcomponents existatthisstage).ClickingtherelevantlinkwillupdatethePCBdocumentbychangingthenetsof thenewlyswappedpins(againusingECOs,seebelow).Furtherchangesmaystillberequiredtothe PCBdocumentifthesepins/netscontainedanyrouting.

Figure43.ConfirmECOs

PinswappinginbothPCBandFPGAprojects
ItmaybethatpinchangeshavebeenmadeinboththePCBprojectandFPGAprojectwithouta synchronizeoccurring.Ifthisisthecase,enteringtheFPGAWorkspaceMapdialogwillshowthe schematicFPGAprojectlinkoutofdate(Red). ClickingonthelinkwillopentheSynchronizedialog,withalldifferenceshighlightedinred.Itisnot possibletopasstherelevantchangesintheirrespectivedirections(PCBtoFPGAandFPGAto PCB)simultaneously.Thesequenceforpassingthechangesasrequiredandresynchronizingthe linkissummarizedasfollows: Firstchoosetheinitialdirectioninwhichtopasschanges,byclickingoneithertheUpdateTo PCBorUpdateToFPGAbuttons IntheEngineeringChangeOrderdialogthatappears,allchangeswillbegearedtothechosen direction.Enableonlythosemodificationsthatarerequiredforthatdirection. Executethechanges WhentheSynchronizedialogreappears,clickontheUpdatebuttonthatwasnotinitially pressed,inordertopasschangesinthesecondofthetwodirections
ExecutethechangesinthesubsequentEngineeringChangeOrderdialogthatappears TheSynchronizedialogwillreappear,showingnodifferencesintheMatchedSignalslist (appearingtotallygreen).IntheFPGAWorkspaceMapdialog,thelinkwillhavereturnedtoitsfully synchronizedstatus(Green).

Exercise4Pinswapping

Thisexercisecontinuesonfromworkdoneinthepreviousexercise. 1. OpenSLRev1.01NoRoutes.PcbDoc. 2. ChecktheAdding/RemovingNetLabelsoptionintheoptionstaboftheprojectoptionsdialog box.LeavetheChangingSchematicPinsoptionunchecked. ClickOKtoclosetheproject optionsdialog. 3. Select ToolsPin/PartSwappingConfigure 4. SelecttheFPGAcomponent,andConfigureComponent 5. EnsureShowI/OPinsOnlyisselectedfromthedropdownlistonthebottomleftofthedialog box. 6. CreateauniqueSwapGroupID foreachofthefollowingsignals: a. I\N\I\T\ b. DIN 7. AllotherIOpinscanbeplacedintoasingleswapgroupcalledgeneral_IO.
Figure44.SpecifyswapgroupIDsforalloftheIO

8. SelectOK. 9. ZoomintoviewtheFPGAdeviceinthecentreofthePCB. 10. DoubleclickontheFPGAdevice.WhentheComponentU1dialogappears,changethe Rotationto180degreesandclickOK. 11. Usetheautomaticpinswappingtorearrangethepins. 12. Waitforamomentforthesystemtoperformthepinswapping. 13. GototheDesign menu,andselectUpdateSchematicstobringthechangesacrosstothePCB schematics. 14. OpentheFPGAWorkspaceMap,andresolveanyunsynchronisedsignals.ThePCBshouldbe themasterdocumentatthisstagesoselectUpdatetoFPGAwhenperforminganychanges. 15. Saveyourwork.

6.Commissioningthedesign

OneoftheadvantagesofhavingahardwareplatformsuchastheDesktopNanoBoardatyour disposalduringdevelopmentisthatyoucanperformastagedmigrationofthedesignontoacustom targetPCB.Evenifcomponentsforthetargethavenotyetarrived,initialcommissioningcanbegin bycouplingthetargettotheNanoBoardandusingNanoBoardresourcesasasubstituteforthe missingcomponents.

Exercise5Migrationstage1

Inthisexercise,weconsiderthescenariowhereoneormoreofthetargetresourcesareyettobe placed.Inthiscasewemaychoosetorunthemainapplicationfromthetargetboardbutuse peripheralsavailableontheNanoBoardtotestourapplication.Forthisexercisetofunctioncorrectly wewillneedtoloaddesignsontoboththeNanoBoardandTargetplatforms. 1. Locatethe.\Module3\Exercise5\directoryandload SLRev1.01.PrjPCBaswellasFPGA_NB\SpiritLevel_NB.PRJFPG 2. ObservethecontentsoftheschematicdocumentSL_FPGA_NB.SchDoc.Noticehowthe NEXUSJTAGConnectorneedstobepresentandtheTDI/TDOloopmadetoensurethatthe JTAGsoftchainisnotbrokenwithintheNanoBoarddevice. 3. SwitchofftheDesktopNanoBoardandtargetboardpower. 4. Usinga10pinribboncable,connectHDR1onthetargetboardtoUSERBOARDAonthe NanoBoard. 5. Usinga20pinribboncable,connectHDR2onthetargetboardtoUSERHEADERAonthe NanoBoard. 6. EnsuretheXaxisjumperisremoved fromthetargetboard. 7. EnsureallDIPSwitchesonthetargetboardaresettotheONposition. 8. PlacetheCONFIGjumperonthetargetboard. 9. SwitchontheNanoBoardandtargetboard. 10. OpentheDevicesviewandverifytheexistenceoftwoFPGAdevices(andoneconfiguration device)intheHardChain.Thefirstdevicewillalways betheNanoBoarddevice. 11. BuildanddownloadtheSpiritLevel_NB/NB_BaseconfigurationtotheNanoBoarddevice. 12. BuildanddownloadtheSpiritLevel/Tgt_Spartan2configurationtothetargetboard device. 13. ObservethestatusoftheProcessorinthesoftchain.If,afterdownloadingbothprojects,this deviceislistedasMissing,itislikelythesoftchainisbrokensomewhere.Verifythataloop betweenJTAG_NEXUS_TDIandJTAG_NEXUS_TDOexistsontheSL_FPGA_NB.SchDoc. Rebuildtheprojectifnecessary. 14. SettheNanoBoardclockfrequencyto6MHzandensurethatDIPSwitch8ontheNanoBoardis ON.Observethedisplayonthetargetboard.AssertoneortwooftheNanoBoardslowerDIP SwitchesandseewhatchangeoccursintheTargetsLCD.IfthetargetboardLEDsarenot flashingthenthisindicatesitisnotreceivingasignalfromtheNanoBoard.Ensurealloutputs fromtheDigitalIOBonthetargetboardare0andcheckthewiringbetweentheNanoBoardand thetargetboard.Alsoensuretherespectiveprojectshaveloadedcorrectly.

Figure48.SpecifyingtheconfigurationPROMdevice
3. SelectthemcsoptionundertheFormatdropdown. 4. Rebuildtheentireprojecttoensurethatyourcalibrationvaluesareincludedinthebuildandthe configurationPROMfilegetscreated. 340
RightclickontheconfigurationdeviceinthehardchainandselectChooseFileandDownload fromthepopupmenu.
Figure49.DownloadingaPROMtotheconfigurationdevice.
5. LocatetheMCSbitfile.Youwillfinditunder \ProjectOutputs\Tgt_Spartan2\spiritlevel.mcs.Onceyouselectit,downloading willbeginimmediately. 6. Theprogrammingprocessmaytakeseveralsecondsasthedevicehastofirstbeerasedbefore itcanbeprogrammed.WhenaskedifyouwishtoverifyprogrammingselectYes.Besurenot toremovepowerfromthedeviceuntilprogrammingiscomplete.Youwillbenotifiedof successfulprogrammingwiththefollowinginformationdialog.
Figure50.PROMfileprogrammingconfirmation
7. Removepowerfromthetargetboard. 8. Disconnectthe10pinUSERBOARDribboncablefromthetargetboard. 9. RemovetheCONFIGjumperfromthetargetboardbutmakesuretheXaxisjumperremains connected. 10. Reapplypowertothetargetboardandverifythattheapplicationcorrectlyloadsandrunsitself. 11. SwitchofftheNanoBoardandthetargetboardandreconnectthe10pinUSERBOARDribbon cablebetweenthetargetboardandtheNanoBoard. 12. ReapplypowertothetargetboardandNanoBoardandobserveintheDevicesviewthatthe downloadableinstrumentsarestillaccessible.
Exercise9Revertingtotestmode
1. Toensurethetargetboardsareleftinastatereadyforthenextusers,itwillbenecessaryto reprogramthePROMwiththeTestModeconfigurationfile.Youwillfindthisfileas \Exercise9\ConfigTest.mcs.Usethestepsoutlinedinthepreviousexercisetoprogram thistestfilebackintothePROM.

7.Review

1 FPGADesign

Theprimaryobjectiveofthisdayoftrainingistomakeparticipantsproficientintheprocessof developing,downloadingandrunninganFPGAdesignontheDesktopNanoBoard.Wewillgo throughtheFPGAdesignframeworkanddemonstratejusthowsimpleFPGAdesigniswithAltium Designer.

Learningobjectives

TobecompetentindevelopingFPGAdesignsusingstandardFPGAbasedlibrariesandthe schematiccaptureenvironment TounderstandandbeabletomakeuseoftheFPGAbuildprocess TobefamiliarwiththeperipheralcapabilitiesoftheDesktopNanoBoardandknowhowto incorporatetheiruseincustomFPGAdesigns. Toappreciatethedifferentcommunicationmechanismsusedbythesoftwaretocontrolandprobe arunningFPGAdesign. TobecompetentwiththeuseofvirtualinstrumentsinanFPGAdesign.

Topicoutline

CoreTopics FPGA Project Creation FPGA Schematic Extensions
FPGABuild Process FPGAdesign builtand loadedonto NanoBoard

NanoBoard Concepts

FPGA Instruments
AdvancedTopics(TimePermitting)

FPGACore Components

Digital Simulation
Figure1.TopicOutlineforPartIFPGADesignBasics.
2 IntroductiontoFPGADesign

2.1 FPGAbasics

FPGA:FieldProgrammableGateArray.Conceptuallyitcanbeconsideredasanarrayof ConfigurableLogicBlocks(CLBs)thatcanbeconnectedtogetherthroughavastinterconnection matrixtoformcomplexdigitalcircuits.
Figure2.ExplodedviewofatypicalFPGA
FPGAshavetraditionallyfounduseinhighspeedcustomdigitalapplicationswheredesignstendto bemoreconstrainedbyperformanceratherthancost.Theexplosionofintegrationandreductionin pricehasledtothemorerecentwidespreaduseofFPGAsincommonembeddedapplications. FPGAs,alongwiththeirnonvolatilecousinsCPLDs(ComplexProgrammableLogicDevices),are emergingasthenextdigitalrevolutionthatwillbringaboutchangeinmuchthesamewaythat microprocessorsdid. Withcurrenthighenddevicesexceeding2000pinsandtoppingbillionsoftransistors,thecomplexity ofthesedevicesissuchthatitwouldbeimpossibletoprogramthemwithouttheassistanceofhigh leveldesigntools. Xilinx,Altera,Actel,andLatticeallofferhighendEDAtoolsuitesdesigned specificallytosupporttheirowndeviceshowevertheyalsoofferfreeversionsaimedatsupporting thebulkofFPGAdevelopment.Thesevendorsunderstandtheimportanceoftoolavailabilityto increasedsiliconsalesandtheyallseemcommittedtosupportingafreeversionoftheirtoolsforthe foreseeablefuture. ThroughtheuseofEDAtools,developerscandesigntheircustomdigitalcircuitsusingeither schematicbasedtechniques,VHDL,Verilogoranycombinationofthesemethods.Priortothe AltiumDesignersystem,vendorindependentFPGAdevelopmenttoolswereextremelyexpensive. FurthermoretheywereonlyusefulforcircuitsthatresidedwithintheFPGAdevice.Oncethedesign wasextendedtoincludeaPCBandancillarycircuits,aseparateEDAtoolwasneeded.Altium DesignerhaschangedallofthisbybeingthefirstEDAtoolcapableofofferingcompleteschematic toPCBtoolintegrationalongwithmultivendorFPGAsupport. AltiummadethelogicalextrapolationoftrendsintheFPGAworldandrecognizedthatFPGAsare quicklybecomingastapleinmoderndesigns.Bymakingavailablearangeofprocessorcoresthat canbedownloadedontoanFPGAdeviceandbundlingthemwithacompletesuiteofembedded softwaredevelopmenttools,AltiumDesignerrepresentsaunifiedPCBandembeddedsystems developmenttool.

LCD_BUSY VALIDKEY

NotethatapartfromtheJBtypejoiner,allbusjoinerpinshaveanIOdirectionusethecorrect joinertomaintaintheIOflow.PinIOcanbedisplayedonsheetifyouenablethePinDirection optionintheSchematicPreferencesdialog. TheuseofbusjoinersinFPGAdesignsisasignificantdeparturefromhowbusconnectivityis establishedonotherschematicdocumentshoweverthebenefitsofbusjoinerssoonbecomeclear. Netsextractedfromabusjoinerneednotberelatedinanywayie.havethesamenameand differingonlybynumber(Data[0],Data[1],Data[2],etc).Thebusjoinerexampleaboveshows howasinglebuscanbeusedtorouteanumberofLCDandKeypadsignalstogether,evenallowing thejoiningofotherbussesintoasinglebusofalargerwidth.
4.5.1 Busjoinernamingconvention
Busjoinersfollowastandardizednamingconventionsothattheycanbeeasilyfoundwithinthe FPGAGeneric.IntLiblibrary. J<width><B/S>[Multiples]_<width><[B/S]>[Multiples] Forexample: J8S_8B:describesabusjoinerthatroutes8singlewirestoasingle,8bitbus. J8B_8S:describesabusjoinerthatroutesasingle,8bitbusinto8singlewires. J8B_4B2:describesabusjoinerthatroutesasingle8bitbusintotwo4bitbusses, J4B4_16B:describesabusjoinerthatroutesfour,4bitbussesintoasingle16bitbus.
4.5.2 Busjoinersplitting/mergingbehaviour
Thebasicruleisthatbusjoinersseparate/mergethebits(orbusslice) fromleastsignificantbit(orslice)downtomostsignificantbit(orslice). Forexample,inFigure9,U17splitstheincoming8bitbusonpinI[7.0] intotwo4bitbusslices,OA[3.0]andOB[3.0].Obeyingtheleasttomost mappingattheslicelevel,thelowerfourbitsoftheinputbusmapto OA[3.0],andtheupperfourbitsmaptoOB[3.0].Followingthisthroughto thebitlevel,I0willconnecttoOA0,andI7willconnecttoOB3. ThejoinerU27mergesthefourincoming4bitslicesintoa16bitbus.With thisjoinerIA0connectstoO0,andID3connectstoO15.
4.5.3 Matchingbusesofdifferentwidthsusingthe JBtypebusjoiner

Figure9.Busjoiners

TheJBtypebusjoinerallowsyoutomatchnetsinbusesofdifferent mergeandsplitbuses widths.Itdoesthisvia2componentparameters,IndexAandIndexBthat mapfromonebusthroughtotheotherbus.TheseindicesmustbedefinedwhenyouuseaJB joiner.
Figure10.Joinbusesofdifferentwidths,andcontrolthenettonetmapping
ReadtheflowofnetsthroughaJBtypebusjoinerbymatchingfromthenetsintheattachedbus,to thefirstindexonthebusjoiner,tothesecondindexinthebusjoiner,tothenetsdefinedinthe secondbusnetlabel. LeftBusIndexAIndexBRightBus Therulesformatchingnetsateachofthepointsareasfollows:

Figure11.AnexampleofusingtheJBbusjoinertoachievesubsetmapping
Ifbothbusrangesaredescending,matchbysamebusindex(onerangemustliewithintheother forvalidconnections).InFigure11thematchingis:
IndexA9 IndexB9 ROMADDR9,thruto ADDR0 IndexA0 IndexB0 ROMADDR0
(InthisexampleROMADDR10thruROMADDR13willbeunconnected)
Figure12.Usingofabusjoinerforoffsetmapping

InFigure12thematchingis:

INPUTS15 INPUTS0
IndexA15 IndexB31 PORTB31,thruto IndexA0 IndexB0 PORTB16
Figure13.Usingabusjoinerforrangeinversion
Ifonebusrangeisdescendingandanotherisascending,theindicesarematchedfromleftto right.InFigure13thematchingis:
IndexA15 IndexB31 PORTB31,thruto INPUTS15 IndexA0 IndexB16 PORTB16

INPUTS0

Figure14.Anotherexampleofusingabusjoinerforrangeinversion

InFigure14thematchingis:

IndexA15 IndexB31 PORTB0,thruto IndexA0 IndexB16 PORTB15
5 FPGAreadyschematiccomponents

5.1 Overview

AwidevarietyofFPGAreadyschematic componentsareincludedwiththesystem,ranging fromprocessors,toperipheralcomponents,down togenericlogic.Placingandwiringthese schematiccomponents,orwritingVHDL,captures thehardwaredesign.TheFPGAreadyschematic componentsareliketraditionalPCBready components,exceptinsteadofthesymbolbeing linkedtoaPCBfootprinteachislinkedtoapre synthesizedEDIFmodel. Aswellascomponentsthatyouusetoimplement yourdesign,theavailableFPGAlibrariesinclude componentsforthevirtualinstruments,andthe componentsthataremountedontheNanoBoard andareaccessibleviathepinsontheFPGA. HelpforallFPGAreadycomponentscanbe accessedbypressingtheF1keywhilstthe componentisselectedinthelibrarylist.

Processorcores

Softcoreprocessorscanbeplacedfromthe \ProgramFiles\AltiumDesigner 6\Library\Fpga\FPGAProcessors.IntLib library.Atthetimeofreleaseofthismanual,the followingprocessorsandrelatedembedded softwaretoolsaresupported: TSK165Microchip165xfamilyinstructionset compatibleMCU TSK51/528051instructionsetcompatible MCU TSK80Z80instructionsetcompatibleMCU PPC405AEmbeddedPowerPCCore availableonsomeVirtexFPGAs TSK300032bitRISCprocessor Thereisalsofullembeddedtoolsupportfor: ActelCoreMP7softcore,whichrequiresthe appropriateActeldeviceandlicensetouse AlteraNiosIIsoftcore,whichrequiresthe appropriateAlteradeviceandlicensetouse XilinxMicroBlazesoftcore,whichrequiresthe appropriateXilinxdeviceandlicensetouse XilinxVirtex2ProbasedPowerPC405 AMCCPowerPC405discreteprocessorfamily ARM7,ARM9,ARM9E&ARM10Efamilies,supportedintheSharpBlueStreak(ARM20T) discreteprocessorfamily LPC2100,LPC2200,LPC2300&LPC2800ARM7baseddiscreteprocessorsfromNXP
Figure15.Thelibrariespanel
DesktopNanoBoardportplugins

HardwareresourcesontheDesktopNanoBoardcanbeaccessedviatheuseofcomponentsfrom the\ProgramFiles\AltiumDesigner6\Library\Fpga\FPGANB2DSK01Port Plugin.IntLiblibrary.

PeripheralComponents

ManyofthehardwareresourcespresentontheNanoBoardcomewithperipheralmodulesthatcan beincludedintheFPGAdesigntoeaseinterfacingtotheexternalport. Peripheralscanbeplacedfromthe\ProgramFiles\AltiumDesigner 6\Library\Fpga\FPGAPeripherals.IntLiblibrary.

Genericcomponents

Genericcomponentscanbeplacedfromthelibrary \ProgramFiles\AltiumDesigner 6\Library\Fpga\FPGAGeneric.IntLib.This libraryisincludedtoimplementtheinterfacelogic inyourdesign.Itincludespinwideandbuswide versionsformanycomponents,simplifyingthe wiringcomplexitywhenworkingwithbuses.Aswell asabroadrangeoflogicfunctions,thegeneric libraryalsoincludespullupandpulldown componentsaswellasarangeofbusjoiners,used tomanagethemerging,splittingandrenamingof buses. Foradefinitionofthenamingconventionusedin thegenericlibraryandacompletelistingof availabledevices,refertothedocument:CR0118 FPGAGenericLibraryGuide.pdf. Wildcardcharacterscanbeusedtofilterwhen searchingthecomponentlibrary.
Vendormacroand primitivelibraries
Ifvendorindependenceisnotrequired,thereare alsocompleteprimitiveandmacrolibrariesforthe currentlysupportedvendors/devicefamilies.These librariescanbefoundintherespectiveActel, Altera,LatticeandXilinxsubfoldersin\Program Files\AltiumDesigner6\Library\.The macroandprimitivelibrarynamesendwiththe Figure16.Usingwildcardstoquicklyfindaspecific string*FPGA.IntLib.Notethatsomevendors componentintheGenericLibrary requireyoutouseprimitiveandmacrolibrariesthat matchthetargetdevice.Designsthatinclude vendorcomponentscannotberetargetedto anothervendorsdevice.

Exercise1CreateaPWM

InthisexercisewewillcreateourfirstFPGAdesign.Inordertocompletethistaskyouwillneedto usethefollowingcomponentsfromtheirrespectivelibraries: Component

CLK_BRD

Library FPGANB2DSK01PortPlugin.IntLib
NameinLibrary CLOCK_BOARD

TEST_BUTTON

FPGANB2DSK01PortPlugin.IntLib

SW[7.0]

FPGANB2DSK01PortPlugin.IntLib FPGANB2DSK01PortPlugin.IntLib FPGAGeneric.IntLib

DIPSWITCH LED CB8CEB

LEDS[7.0]
U1 CB8CEB Q[7.0] CE C CEO TC CLR

FPGAGeneric.IntLib

U3 A[7.0] B[7.0] COMPM8B
I0 I1 I2 I3 I4 I5 I6 I7 U4

6.2.3 Projectordesignconstraintinformation:
Thiswouldincluderequirementswhichareassociatedwiththelogicofthedesign,aswellas constrainsonitstiming.Forexample,specifyingthataparticularlogicalportmustbeallocatedto globalclocknet,andmustbeabletorunatacertainspeed.

NanoBoardconstraintfiles

ConstraintfilesforusewiththeNanoBoarddaughter/peripheralboardmodulescanbefoundinthe \ProgramFiles\AltiumDesigner6\Library\Fpgadirectory.Toprotectthesesystem filesfrominadvertentmodification,itisadvisabletomakethisdirectoryreadonly.

ConfigurationManager

ThegroupingofmultipleconstraintsintoasingleconfigurationismanagedviatheConfiguration ManageraccessiblebyrightclickingtheFPGAprojectintheProjectspanelandselecting ConfigurationManagerfromthemenu.
Figure19.ConfigurationManagershowingmultipleconfigurationsandconstraintfiles.
Figure19showstheConfigurationManagerdialogforaprojectthatcontainsmultipleconfigurations andconstraintfiles.TheConstraintfilesarelistedintheleftcolumnandcanbeincludedina Configuration(listedastheheadingsinthefourrightcolumns)byplacingatickattherow/column intersectionpoint.Althoughthisexampleonlyshowsoneconstraintfilebeingusedineachofthe configurations,thereisnoreasonwhyaconstraintfilecantbeusedbymorethanoneconfiguration noristhereanyreasonwhyaconfigurationcantmakeuseofmultipleconstraintfiles.
AutoConfiguringanFPGAproject
Configuringadesignforuse withtheDesktopNanoBoard hasbeenalmostcompletely automatedwiththeintroduction oftheAutoConfigurationoption inAltiumDesigner.Fromthe DevicesViewlocatedunder ViewDevicesViewor alternativelyaccessedfromthe iconinthetoolbar,simply rightclicktheimageofthe DesktopNanoBoardandselect theoptionConfigureFPGA Project<ProjectName>.
Figure20.AutoconfiguringanFPGA
ThiswillautomaticallyconfiguretheFPGAProjecttoincludetheconstraintfilesrequiredtotargetthe hardwareontheDesktopNanoboardandwilllaunchtheConfigurationManagerdialogforthe currentFPGAproject.
Figure21.Autoconfigurationdisplayedintheconfigurationmanager
Definingconstraintsmanually
Oftenitisnecessarytomanuallycreatedesignconstraints.Theseincludeconstraintsforsuch physicalattributesasthefrequencyofasystemclock,ortheassociationofsignalstospecificdevice pins(suchasonemightexpecttofindwhentargetingadesignforauserboard).Tocreateauser constraintfile,rightclicktheFPGAprojectandselectAddNewtoProjectConstraintFile.This willcreateanewblankconstraintfileandaddittotheproject.

7 Runningthedesign

HavingjustconfiguredourdesignfortheNanoBoardthenextstepistobuildandrunthedesignon theNanoBoard.

Overview

BeforeanFPGAdesigncanbedownloadedontoitstargethardware,itmustfirstundergoamulti stagebuildprocess.Thisprocessisakintothecompilationprocessthatsoftwareundergoesin ordertocreateaselfcontainedprogram.Inthissectionwewilldiscussthevariousstepsnecessary tobuildanFPGAdesigntothepointwhereitisreadytobedownloadedontothetargetdevice.
Controllingthebuildprocess
TheprocessofconvertingaschematicorVHDLdescriptionofadigitalcircuitintoabitfilethatcan bedownloadedontoanFPGAisquitecomplex.Fortunately,AltiumDesignergoestogreatlengths toensurethatnavigationthroughthisprocessisaseasyaspossible.Asavendorindependent FPGAdevelopmenttool,AltiumDesignerprovidesatransparentinterfacetothevendorspecific backendtools.CurrentlyAltiumDesignersupportsinteractionwithActelDesigner(Actel),QuartusII (Altera),ispLEVER(Lattice),andISE(Xilinx)toperformFPGAprocessing.Thisisallhandled seamlesslythroughtheDevicesView(ViewDevices).TheDevicesViewprovidesthecentral locationtocontroltheprocessoftakingthedesignfromthecapturestatethroughtoimplementingit inanFPGA.
Figure29.DevicesviewofanFPGAdesignthatisyettobeprocessed.
WhenrunintheLivemode,AltiumDesignerisintelligentenoughtodetectwhichdaughterboard deviceispresentontheDesktopNanoBoard.Intheaboveinstance,ithasdetectedthatthe Spartan3daughterboardisinstalled.Withthisinformation,itthensearchesthecurrentprojects configurationlisttoseeifanyconfigurationsmatchthisdevice.Ifmorethanoneconfigurationis found,thedropdownlistbelowthedeviceiconwillbepopulatedwithalistofvalidconfigurations.If noconfigurationcanbefound,thelistwilldisplaythefollowing:
Figure30.ThismessageindicatesthattheprojectisnotconfiguredtotargettheavailableFPGA.
Assumingavalidconfigurationcanbefound,thesimplestwaytobuildanddownloadadesignonto theNanoBoardistoleftclickontheProgramFPGAbutton.Thiswillinvoketheappropriatebuild processesthatneedtoberun.Intheaboveexamplewherenopreviousbuildshavetakenplace,all processeswillneedtoberun. Inothersituationswhereaprojecthasjustbeenmodified,itmaybe necessaryforonlyasubsetofthebuildprocessestorun.
Understandingthebuildprocess

Figure36.Summarizingresourceusageforthechosendevice.

7.6.4 Program

Thisstageoftheprocessflowisusedto downloadthedesignintothephysical FPGAdeviceonaNanoBoardorproduction board.Thisstageisonlyavailablewhenthe DevicesviewisconfiguredinLivemode.
Figure37.ProgramFPGAstageoftheprocessflow.
Thisstageoftheflowcanonlybeused oncethepreviousthreestageshavebeen runsuccessfullyandaprogrammingfilehas beengenerated.Agreenarrowwillpointto thedevicetobeprogrammedintheHard DevicesChain. Astheprogrammingfileisdownloadedto thedeviceviatheJTAGlink,theprogress willbeshownintheStatusbar.Once successfullydownloaded,thetext underneaththedevicewillchangefrom ResettoProgrammed(Figure38)and anyNexusenableddevicesonthesoft chainwillbedisplayedasRunning(Figure 39).
Figure38.SuccessfulprogrammingofthephysicalFPGAdevice.
Figure39.Softdevicesrunningaftersuccessfulprogramdownload.

Configuringabuildstage

Shouldyouwishtoconfigureanyofthespecificoptionsassociated witheachofthedifferentsubstagesintheFPGAbuildflow,youcan dosobyclickingontheappropriateconfigurationicon. ConsiderthecasewhereyouwanttogenerateaPROMfilefor subsequentdownloadtoaXilinxconfigurationdeviceonaproduction board.IntheprocessflowassociatedtothetargetedFPGAdevice, expandthebuildsection.ThelastentryinthebuildmenuisMake PROMFile Clickingonthe icon,tothefarrightofthismenuentry,willopen theOptionsforPROMFileGenerationdialog(Figure41).From hereyoucanchoosethenonvolatileconfigurationdevicethatwillbe usedbytheproductionboardtostoretheFPGAconfiguration.
Figure41.AccessingtheoptionsdialogforPROMfilegeneration.
HowAltiumDesignerinteractswithbackendvendortools
IfyouarealreadyfamiliarwiththebuildflowsofferedbyAlteraandXilinx,youwillbefamiliarwith oneorbothofthefollowingpanels:
Figure42.Xilinx(left)andAltera(right)vendortoolinterfaces.
AlthoughAltiumDesignerhasitsownHDLsynthesizer,itisreliantonbackendvendortoolsto implementthedesignonaspecificdevice.Thismakessense,asitisthedevicevendorswhohave themostintimateknowledgeoftheirspecificdevicesandwhohavealreadydevelopedwellproven targetingtechnologies. Mostvendorspecifictoolshavebeendevelopedinamodularfashionandcontainanumberof separateexecutableprogramsforeachphaseoftheimplementationprocess.ThevendorGUIsthat arepresentedtotheuserarecocoordinatingprogramsthatsimplypasstheappropriateparameters tobackend,commandlineprograms. WhenitcomestoFPGAtargeting,AltiumDesigneroperatesinasimilarfashioninthatitactsasa coordinatorofbackend,vendorspecificprograms.Parametersthatneedtobepassedfromthe AltiumDesignerfrontendtothevendorspecificbackendprogramsarehandledbyaseriesoftext basedscriptfiles.Userswhoarealreadyfamiliarwiththebackendprocessingtoolsmayfindsome useinaccessingthesescriptfilesshouldtheywishtomodifyortweakinteractionwithbackend processingtools.Thishoweverisconsideredahighlyadvancedtopicandonethatshouldbe handledcautiously.Ensurebackupsaretakenpriortomodification. ThefilescontrollinginteractionwithvendorspecificbackendtoolscanbefoundintheSystem directoryundertheAltiumDesigner6installdirectory.Thenamingconventionusedforthese filesis: Device[Options|Script]_<vendor>[_<tool>|<family>].txt soforexampleDeviceOptions_Xilinx_PAR.txtcontrolsthedefaultoptionsforXilinxsPlace andRoutetool.

CROSSPOINT_SWITCH

Figure45.Crosspointswitch,usedtocontroltheconnectionbetweeninputandoutputsignals
TheCROSSPOINT_SWITCHdeviceisaconfigurablesignal switchinginstrumentwhichprovidesanefficientmeansby whichtoswitchsignalsinadesign. Theinterconnectionbetweeninputandoutputblocksis completelyconfigurable.Initialconnectionscanbedefinedas partofdesigntimeconfiguration,butcanbechangedonthe flyatruntime,fromthedevice'sassociatedinstrumentpanel. Thelatterenablesyoutoswitchsignalswithouthavingtore synthesizeanddownloadtheentiredesigntotheFPGA.
U18 CrosspointSwitch AIN_A[7.0] AOUT_A[7.0] AIN_B[7.0] AOUT_B[7.0] BIN_A[7.0] BIN_B[7.0] CROSSPOINT_SWITCH BOUT_A[7.0] BOUT_B[7.0]

FRQCNT2

Figure46.Frequencycounter,usedtomeasurefrequencyinthedesign
U6 FREQA FREQB TIMEBASE FrequencyCounter FRQCNT2
Thefrequencycounterisadualinputcounterthatcandisplaythe measuredsignalin3differentmodesasafrequency,period,ornumberof pulses.
Figure47.DigitalIOmodule,usedtomonitorandcontrolnodesinthedesign
ThedigitalI/Oisageneralpurposetoolthatcanbeusedfor bothmonitoringandactivatingnodesinthecircuit.Itis availableineither8bitwideor16bitwidevariants,with1to 4channels. EachinputbitpresentsasaLED,andthesetof8or16bits alsopresentsasaHEXvalue.Outputscanbesetorcleared individuallybyclickingtheappropriatebitintheOutputsdisplay.AlternativelytypinginanewHEX valueintheHEXfieldcanaltertheentirebyteorword.IfaHEXvalueisenteredyoumustclickthe buttontooutputit.TheSynchronizebuttoncanbeusedtotransferthecurrentinputvaluetothe outputs.

DIGITAL_IO

Figure48.ConfigurableDigitalIOmodule,usedtomonitorandcontrolnodesinthedesign
TheconfigurabledigitalI/Oisageneralpurposetoolthatcanbe usedforbothmonitoringandactivatingnodesinthecircuit. Unlikeitslegacycounterparts(IOB_xfamilyofdevices),withthe DIGITAL_IOdeviceyouarenotconstrainedtolimitedsignalsof 8or16bits.Instead,anynumberofsignalsmaybeadded,and anynumberofbitscanbeassignedtoasinglesignal.Youmay alsohavedifferentnumbersofinputandoutputsignals.
ConfigurableDigitalIO InLEDs[7.0] Rot[7.0] SpareOutB[7.0] Zoom[7.0] SpareOutC[7.0] Flags[7.0] SpareOutD[7.0]
EachinputbitcanbepresentedinarangeofdifferentstylesincludingLEDs,numeric,LEDdigits,or asabar,andthesetofbitsalsopresentsasaHEXvalue.Outputstylescanalsovaryandinclude LEDs,numeric,LEDdigits,andaslider.EachoutputcanhaveapredefinedInitialValueandwill alsoincludeaHEXdisplay.Outputscanbesetorclearedindividuallyandthemethodwillvarywith thestyleselected.AlternativelytypinginanewHEXvalueintheHEXfieldcanalterthevalueofthe output.IfaHEXvalueisenteredyoumustclickthe buttontooutputit.TheSynchronizebutton canbeusedtotransferthecurrentinputvaluetotheoutputs.

Figure54.PWMcircuitwithseveralembeddedinstrumentsconnected.
1. OpentheprovidedprojectanddownloadittoyourNanoBoard. 2. Followonyourowncircuitastheinstructordiscussesthevariousembeddedinstruments.
3. DoubleclicktheNanoBoardiconintheDevicesViewtoopentheinstrumentrackforthe NanoBoardandsetitsclockfrequencyto50MHz.
Figure55.NanoBoardcontroller.
4. Openthefrequencygenerators instrumentpanel.Ifthetimebase indicatedinthewindownexttothe SetTimeBasebuttonisnot50 MHzthenpresstheSetTime Basebuttontoopenadialogbox thatwillenableyoutosetit correctly.TheRequire50/50 Dutycheckboxshouldbe checked. Thefrequencygeneratorshould besetto1MHzasindicatedin Figure.
Figure56.Counteroptionsdialog
Figure57.FrequencygeneratorPanel
5. Openthefrequencycounters instrumentpanel.Selectthe CounterOptionsbuttononthe frequencycountermoduleand makesuretheCounterTimeBase isalsosetto50MHz(thesameas theNanoBoardclockfrequency), asshowninFigure57.PressOK. UsetheModebuttonasnecessary oneachchannelofthefrequency countermoduletotogglethe displaymodebetweenfrequency, periodorcount.Youshouldgeta similardisplaytowhatisdepicted inFigure59.
Figure58.Counteroptionsdialog
Figure59.Frequencycountercontrolpanel
6. OpentheDigitalIOBsinstrumentpanel.
Figure60.DigitalIOBinstrumentcontrolpanel
7. ModifytheOutputsoftheIOBmoduleandobservechangesintheLEDs. 8. Adjusttheoutputfrequencyofthefrequencygeneratormoduletoalowerfrequencytry1KHz. ObservetheimpactthishasontheLEDs.ModifytheOutputsoftheIOBandobservefurther changesintheLEDs. 9. Adjusttheoutputfrequencyofthefrequencygeneratormodulebackto1MHz. 10. Openthelogicanalysersinstrumentcontrolpanel.
Figure61.Logicanalyserinstrumentcontrolpanel
11. SelectShowPanelonthelogicanalyzer.SetthepanelupasdepictedinFigure62.
Figure62.Logicanalysertriggeringoptions.
12. SelectOptionsonthelogic analyser.Settheclockcapture frequencyto1MHzthesameas thefrequencygeneratormodule. Adjusttheothercontrolstobethe sameasshowninFigure63. 13. SelectArmandobservethe waveformdisplayedinthewaveform viewer.SelectContinuousCapture fromtheLogicAnalyzermenuand adjusttheIOBoutput.Observethe changeinthePWMmarktospace ratio.
Figure63.Logicanalysersetupoptions.
Figure64.Logicanalyzerwaveformwithbit7oftheIOBset.
Figure65.Logicanalyzerwaveformwithbits6&7oftheIOBset.

WherearetheInstruments?

TheimportantdifferentiatorbetweenAltiumDesignersembeddedinstrumentsandothersimulation basedvirtualinstrumentsisthatAltiumDesignersembeddedinstrumentsaretruephysicaldevices thataredownloadedintotheFPGAdeviceaspartofthedesign.Theinformationprovidedtothe designerbytheembeddedinstrumentscanberelieduponasitistakenfromrealphysical measurementstakenonchip. FigureillustratesthispointasitshowstheFPGArealestateusedbytheembeddedinstruments.

9.2.3 JTAGSoftChain

TheJTAGSoftChainisaseparateJTAGchannelthatprovidescommunicationwiththeEmbedded InstrumentsthatcanbeincorporatedintoanFPGAdesign.Thischainislabeledasasoftchain sinceitdoesnotconnecttangiblephysicaldevicestogetherbutratherconnectssoftordownloadable instrumentsthatresideinsideahardorphysicalFPGAdevice.

Technicalbackground

TD DI T I
Parallel P r le a al Data Flow D t Fo a l

JT G TA J AG Cel el C ll

TD DO T O
Figure69.ConceptualViewofJTAGdataflows.

9.3.1 JTAGindepth

TheacronymJTAGstandsforJointTestApplicationGroupandissynonymouswithIEEE1149.1. ThestandarddefinesaTestAccessPort(TAP),boundaryscanarchitectureandcommunications protocolthatallowsautomatedtestequipmenttointeractwithhardwaredevices.Essentiallyit enablesyoutoplaceadeviceintoatestmodeandthencontrolthestateofeachofthedevicespins orrunabuiltinselftestonthatdevice.TheflexibilityoftheJTAGstandardhasalsoleadtoits usageinprogramming(configuring)devicessuchasFPGAsandmicroprocessors. Atminimum,JTAGrequiresthatthefollowingpinsaredefinedonaJTAGdevice: TCK:TestClockInput TMS:TestModeSelect
TDI:TestDataInput TDO:TestDataOutput TCKcontrolsthedatarateofdatabeingclockedintoandoutofthedevice.ArisingTCKedgeis usedbythedevicetosampleincomingdataonitsTDIpinandbythehosttosampleoutgoingdata onthedevicesTDOpin.
Figure70.UsingJTAGChaintoconnectmultipleJTAGdevicestogetherinadigitaldesign.
Figure70.JTAGTestAccessPort(TAP)StateMachine.
TheTestAccessPort(TAP)Controllerisastatemachinethatcontrolsaccesstotwointernal registerstheInstructionRegister(IR)andtheDataRegister(DR).DatafedintothedeviceviaTDI oroutofthedeviceviaTDOcanonlyeveraccessoneofthesetworegistersatanygiventime.The registerbeingaccessedisdeterminedbywhichstatetheTAPcontrollerisin.Traversalthroughthe TAPcontrollerstatemachineisgovernedbyTMS. 139

9.3.2 Nexus5001

TheflexibilityofJTAGforhardwaredebuggingpurposeshasflowedoverintothesoftwaredomain. Inthesamewaythattestengineershavesoughtastandardizedmethodfortestingsilicon,software engineershavealsosoughtastandardizedmeansfordebuggingtheirprograms. In1998,theGlobalEmbeddedDebugInterfaceStandard(GEDIS)Consortiumwasformed.Inlate 1999thegroupmovedoperationsintotheIEEEISTOandchangedtheirnametotheNexus5001 ForumandreleasedV1.0ofIEEEISTO1999.InDecember2003,V2.0wasreleased. TheNexus5001standardprovidesastandardizedmechanismfordebugtoolstointeractwithtarget systemsandperformtypicaldebuggingoperationssuchassettingbreakpointsandanalyzing variables,etc.Thereare4classesofNexuscomplianceeachwithdifferinglevelsofsupported functionality.ThelowestlevelusesJTAGasthelowlevelcommunicationsconduit. TheimplementationofNexus5001ontheDesktopNanoBoardhasbeenlabeledastheJTAGSoft Chain.Itisaserialchainjustlikethehardchainhoweverratherthanconnectingphysicaldevices together,itconnectsvirtualdevicestogether.Thesedevicesincludethesetofvirtualinstruments thataresuppliedwithAltiumDesigneranddescribedinthefollowingchapter.Controlofdeviceson theSoftChaincanbeperformedfromtheDevicesViewSoftChainDevicesarelocatedtowards thebottomoftheDevicesViewundertheHardChain. AswiththeJTAGHardChain,theSoftChaincanbetakenofftheNanoBoardviatheUserBoardA andUserBoardBconnectors.Thisprovidesthemeansfortargetsystemstoalsoincludevirtual instrumentsandtobenefitfromtheAltiumDesignerdevelopmentenvironment.SimilarlytotheHard Chain,itisimperativethatacompleteloopbemaintainedbetweentheSoftChainTDIandTDO connections.

TheNanoBoardcontroller

TheNanoBoardControllercanbeaccessedbydoubleclickingontheNanoBoardiconinthe DevicesView.
Figure71.TheNanoBoardControllerInstrumentRack.
TheClockFrequencyindicatedinthewindowwillbesuppliedtothe CLK_BRDportontheNanoBoard.Accessingthisclockoncustomdesignsis assimpleasplacingtheCLOCK_BOARDcomponentfromtheFPGANB2DSK01Port Plugin.IntLibLibrary.

P182 P182 CLK_BRD

SelectinganonstandardfrequencyispossiblebyclickingtheOtherFrequencybutton.The NanoBoardclocksystememploysaseriallyprogrammableclocksource(partnumberICS30702) thatiscapableofsynthesizinganyclockfrequencybetween6and200MHz.Advancedaccessto theClockControlICregistersisavailablethroughtheClockControlOptionsbutton.Adatasheet forthisdeviceisavailablefromtheICSwebsitehttp://www.icst.com/products/pdf/ics3070102.pdf. AnonlineformusefulforcalculatingsettingsfortheclockcontrolICisalsoavailableat http://www.icst.com/products/ics307inputForm.html. TotherightoftheNanoBoardControllerisasectionwiththeheading FlashRAM.TheFPGABootbuttonaffordsthefacilitytostoreadaughter boardconfigurationfilethatwillgetautomaticallyloadedintothedaughter boardonpowerup.TheEmbeddedbuttonexposesmemorythatcanbe usedbytheuserapplicationtostorenonvolatleuserdata.The EmbeddedMemorydeviceisaccessibleviatheSERIALFMEMORYcomponentintheFPGA NB2DSK01PortPlugin.IntLibLibrary.

FPGAI/Oview

TodisplaytheInstrumentrackforadevice,doubleclickonthedeviceintheJTAGHardchain. ClickingontheJTAGViewerPanelbuttonthenbringsuptheJTAGViewerPanel.
Figure72.TheHardDevicesinstrumentrack.
Figure73.TheFPGAI/OInstrumentRackandJTAGViewerPanel.
Thisinterfaceenablesthedevelopertoseeinrealtimetheflowofsignalsacrossthedevicespins. Thiscanbeparticularlyusefulwhenensuringthatsignalsarebeingcorrectlypropagatedtoandfrom thedevice. PlacingatickintheLiveUpdatecheckboxwillcausethedisplaytoupdateinrealtime. Alternatively,leavingtheLiveUpdatecheckboxclearandselectingtheupdateiconwillcause signalinformationtobelatchedtothedisplayandheld. CheckHideUnassignedI/OPinstoremoveclutterfromthedisplay. TheBSDLInformationdropdownlistshouldonlyneedtobeaccessedfordeviceswhichare unknowntoAltiumDesigner.Inthiscase,youwillneedtoprovidethelocationofthevendor suppliedBSDLfileforthedeviceyouareviewing. TheFPGAIOinstrumentrackisavailableforalldevicesontheJTAGHardChainincluding devicesonauserboardthatisconnectedtotheJTAGHardChain. 141

Livecrossprobing

ProbedirectivescanbeplacedontheFPGA schematiconanyI/Onetandwillupdateinrealtime aslongastheHardDevicesInstrumentPanelis displayed.UsethePlaceDirectivesProbeto placeacrossprobeononeoftheI/Onets.
Figure74.UsingLiveCrossProbing.

1. 2. 3. 4. 5.

OncethecoreprojecthasbeencreateditisimportanttomakeavailableitsEDIFmodelswhenyou eventuallypublishit.MakesuretheIncludemodelsinpublishedarchivecheckboxistickedinthe OptionstaboftheProjectOptionsdialog.
Figure76.Settingoptionsforacorecomponent.
YoumustnowspecifythefolderonyourharddiskthatyouwishtheEDIFmodelstobesavedinto. ThisfolderwillbesearchedalongwiththestandardsystemEDIFfolders(\AltiumDesigner 6\Library\EDIF)whenyousynthesizeanydesign.ItisgoodpracticetokeepEDIFmodelsgenerated fromcoreprojectsinasinglelocationforeasiersearching. Tospecifythelocationoftheuser presynthesizedmodelfolder,openthePreferencesdialog,andnavigatetoFPGA>Synthesis.
Figure77. Specifyingthelocationofcorecomponentmodels.

Constrain/configure

TheconceptofconstraintfilesandconfigurationsiscentraltotheflexibilityofAltiumDesigner.They provideamechanismtoallowFPGAcircuitstobedevelopedindependentofthefinalphysical implementation.Ratherthanstoringdeviceandimplementationspecificdatasuchaspinallocations andelectricalpropertiesinthesourceVHDLorschematicdocuments,thisinformationisstoredin separatefilescalledConstraintfiles.ThisdecouplingofthelogicaldefinitionofanFPGAdesign fromitsphysicalimplementationallowsforquickandeasyretargetingofasingledesigntomultiple devicesandPCBlayouts. ThereareanumberofclassesofconfigurationinformationpertinenttodifferentaspectsofanFPGA project:
10.5.1 Deviceandboardconsiderations:
10.5.2 Deviceresourceconsiderations:
10.5.3 Projectordesignconsiderations:
Thiswouldincluderequirementswhichareassociatedwiththelogicofthedesign,aswellas constraintsonitstiming.Forexample,specifyingthataparticularlogicalportmustbeallocatedto globalclocknet,andmustbeabletorunatacertainspeed. Aconfigurationisasetofoneormoreconstraintfilesthatmustbeusedtotargetadesignfora specificoutput.Themigrationofadesignfromprototype,refinementandproductionwilloften involveseveralPCBiterationsandpossiblyevendifferentdevices.Inthiscase,aseparate configurationwouldbeusedtobringtogetherconstraintfileinformationforeachdesigniteration. Eachnewconfiguration(anditsassociatedconstraintfile(s)isstoredwiththeprojectandcanbe recalledatanytime. Tosummarize: Constraintfilesstoreimplementationspecificinformationsuchasdevicepinallocationsand electricalproperties. AConfigurationisagroupingofoneormoreconstraintfilesanddescribeshowtheFPGA projectshouldbebuilt.

Figure98.Thesimulationdebuggeroptionsinthepreferencesdialog.
Exercise6CreateatestbenchandsimulateMyPWM
1. OpentheprojectyoucreatedinExercise2andmakeMyPWM.VHDtheactivedocument. 2. SelectDesignCreateVHDLTestbenchfromthemenu. Updatethetestbenchtobethe sameasthecodelistedinFigure99.
Figure99.TestbenchcodefortestingMyPWM
3. Updatethetestbenchdocument,toplevelentity/configurationandtoplevelarchitecture fieldsinthesimulationtaboftheProjectProjectOptionsdialog. 4. Compilethetestbenchdocumentandrectifyanyerrors. 5. RunthesimulationbyselectingSimulatorSimulate. 6. Runthesimulatorfor2us. 7. ObservethewaveformsforLEDS[0]andLEDS[1].Isitwhatyouexpect?Trychangingthe PWMperiodbychangingthevalueofSWinthetestbench.

12 Review