All egr o F P G A Sy stem P lan n er

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Cadence FPGA System Planner technologies are available in the following product offerings: Allegro FPGA System Planner L, XL, and GXL Allegro FPGA System Planner Two FPGA Option L Cadence OrCAD FPGA System Planner
The Cadence Allegro FPGA System Planner addresses the challenges that engineers encounter when designing one or more large-pin-count FPGAs on the PCB boardwhich includes creating the initial pin assignment, integrating with the schematic, and ensuring that the device is routable on the board. It delivers a complete, scalable technology for FPGA-PCB co-design that automates creation of optimum device-rulesaccurate pin assignment. By replacing manual, error-prone processes with automatic pin assignment synthesis, this unique placement-aware solution eliminates unnecessary physical design iterations while shortening the time required to create optimum pin assignment.

Differential User IO

Congurable

Clock Capable

Figure 1: Color-coded map of the I/Os of a multi-bank FPGA with different types of configurable pins
Designing large-pincount FPGAs on PCBs
Integrating todays FPGAswith their many different types of assignment rules and user-configurable pinson PCBs is time consuming and extends design cycles. Often the pin assignment for these FPGAs is done manually at a pin-by-pin level in an environment that is unaware of the placement of critical PCB components that are connected to FPGAs. Without understanding the impact to PCB routing, FPGA-based design projects are forced to choose between two poor options: live with suboptimal pin assignment, which can increase the number of layers on a PCB design; or deal with several unnecessary iterations at the tail end of the design cycle. Even with several iterations, this manual and error-prone approach can result in unnecessary PCB design re-spins. With the added time required to generate pin assignments for FPGAs using manual approaches, users are unable to do tradeoffs between the different FPGA devices available and the cost of devices used in an FPGA sub-system. This is because performing the trade-offs would mean that users would have to do two projects in parallel with no design reuse of any kind between the two. The Allegro FPGA System Planner provides a complete, scalable solution for FPGA-PCB co-design that allows users to create an optimum correct-byconstruction pin assignment. FPGA pin assignment is synthesized automatically based on user-specified, interface-based connectivity (design intent), as well as FPGA pin assignment rules (FPGA-rules), and actual placement of FPGAs on PCB (relative placement). With automatic pin assignment synthesis, users avoid manual error-prone processes while shortening the time to create initial pin assignment that accounts for FPGA placement on the PCB (placement-aware pin assignment synthesis). This unique placement-aware pin assignment approach eliminates unnecessary physical design iterations that are inherent in manual approaches.
With a way to quickly synthesize optimum pin assignment using user-specified design intent at a high-level, the Allegro FPGA System Planner enables designers to explore their FPGA-based architecture and to create an optimum correct-by-construction pin assignment for either production or prototype designs that use FPGAs. The Allegro FPGA System Planner is integrated with the Cadence design creation tools: Cadence OrCAD Capture and Cadence Allegro Design Entry (CIS and HDL). It reads and creates schematic symbols for both OrCAD Capture and Allegro Design Entry HDL. In addition, a floorplan view uses existing footprint libraries for OrCAD PCB Designer and Allegro PCB Editor. Should placement change during layout, pin optimization using the Allegro FPGA System Planner can be accessed directly from the Allegro PCB Editor.

Accelerates integration of FPGAs with Cadence PCB design creation environments Eliminates unnecessary, frustrating design iterations during the PCB layout process Eliminates unnecessary physical prototype iterations due to FPGA pin assignment errors Reduces PCB layer count through placement aware pin assignment and optimization

FEATURES

Allegro FPGA SYSTEM PLANNER TECHNOLOGY
An FPGA system is defined as a subset of the PCB design that includes one or more FPGA and non-FPGA components that are connected to FPGAs. Traditional approaches to pin assignment are typically manual and often based on a spreadsheet. Tools such as these require users to do pin assignment without taking into consideration the placement of other components and routability of the interfaces and signals. Above all, there is no online rules-checking to ensure that the right pin types are being

BENEFITS

Scalable, cost-effective FPGA-PCB co-design solution from OrCAD Capture to Allegro GXL Shortens time for optimum initial pin assignment, accelerating PCB design schedules
Figure 2: Placement/Floorplan view of the Allegro FPGA System Planner provides users relative placement of critical components for optimum pin assignment synthesis

www.cadence.com

C ade nce Allegro FPGA Sy ste m Pla nn er

FPGA Vendor Tools

Allegro FPGA System Planner

Allegro Design Entry

Allegro PCB Design
definitions. Users can create interfaces such as DDR2, DDR3, and PCI Express, and use these to specify connectivity between a FPGA and a memory DIMM module or between two FPGAs. The Allegro FPGA System Planner understands differential signals, and power signals, as well as clock signals.
Allegro Part Library Symbols, Footprints
Figure 3: The Allegro FPGA System Planner uses symbols and footprints from existing libraries

FPGA DEVICE RULES

The Allegro FPGA System Planner comes with a library of device-accurate FPGA models that incorporate pin assignment rules and electrical rules specified by FPGA device vendors. These FPGA models are used by the synthesis engine to ensure that the vendor-defined electrical usage rules of the FPGAs are strictly adhered to. These rules dictate such things as clock and clock region selection, bank allocation, SSO budgeting, buffer driver utilization, I/O standard voltage reference levels,etc. During synthesis, the Allegro FPGA System Planner automatically checks hundreds of combinations of these rules to ensure that the FPGA pins are optimally and accurately utilized.

used for the signals that are assigned to the FPGA pins. As a result, users have to make several iterations between the spreadsheet-based tools and the tools from FPGA vendors. Often this adds an increased number of iterations between the PCB layout designer who cannot route the signals from FPGA pins on available layers and the FPGA designer who has to accept paper-based or verbal pin-assignment suggestions from the PCB layout designer. Once a change is made to the pin assignment by the FPGA designer, the pin assignment change has to be made in the schematic design by the hardware designer. Such iterations add several days if not weeks to the design cycle and possibly a great deal of frustration for the team members. Since this is a manual process, mistakes that are not detected can also cause expensive physical prototype iterations. While it may help to automate the synchronization of changes made to the pin assignment by the FPGA designer, hardware designer, or PCB layout designer, it doesnt reduce the root cause of these iterations. Pin assignment that is not guided by all three aspectsFPGA resource availability, FPGA vendor pin assignment rules, and routability of FPGA pins on a PCBrequires many iterations at the tail end of the design process, thereby extending the time it takes to integrate todays complex, large-pin-count FPGAs on a PCB.

SPECIFYING DESIGN INTENT

The Allegro FPGA System Planner comes with an FPGA device library to help with selection of devices to be placed. It uses OrCAD PCB Designer or Allegro PCB Editor footprints for the floorplan view and allows users to quickly create relative placement of the FPGA system components. The Allegro FPGA System Planner allows users to specify connectivity between components within the FPGA sub-system at a higher level through interface
Figure 4: The Allegro FPGA System Planner optimizes multiple FPGAs concurrently
PLACEMENT AWARE PIN ASSIGNMENT SYNTHESIS
The Allegro FPGA System Planner provides users a way to create an FPGA system placement view using Allegro PCB footprints. Users specify connectivity between components in the placement view and the FPGA at a high level using interfaces such as DDRx, PCI Express, SATA, Front Side Bus, etc. that connect FPGAs and other components in the design, shortening the time to specify design intent for the FPGA system. Once the connectivity of the FPGA to other components in the sub-system is defined, the Allegro FPGA System Planner then synthesizes the pin assignment based on the users design intent, available FPGA resources, component placement around the FPGA, and the FPGA vendors pin assignment rules. The Allegro FPGA System Planner has a built-in DRC engine that incorporates the rules provided by FPGA vendors for pin assignment, reference voltages, and terminations. This rules-based engine prevents PCB physical prototype iterations as the FPGAs are always correctly connected.

Pin assignment algorithms are optimized to assign interface signals to a group of pins, thereby minimizing net crossovers and improving routability on the PCB.
ASIC PROTOTYPING USING FPGAs
Some companies choose to do ASIC prototyping using FPGAs on the PCB. In these cases, the number of FPGAs used grows rapidly. This sometimes requires using several PCBs to place all the FPGAs. With a large number of FPGAs, the time to do initial pin assignment can be very long using manual processes. Additionally, without taking placement of these FPGAs into account, the pin assignment can make routing of the PCB a very long process, extending the time it takes for designers to get to the ASIC prototype using FPGAs. The Allegro FPGA System Planner shortens the time required to create pin assignment for a large number of FPGAs through placement-aware pin assignment synthesis that is driven by a device-accurate FPGA models library. With the ability to export port information in Verilog and import Verilog-based connectivity, the Allegro FPGA System Planner allows users to iterate with RTL partitioning software, shortening the time to define the FPGA-based system and quickly creating DRC-accurate FPGA pin assignment.
ARCHITECTURAL EXPLORATION ENABLED
During the device selection process, FPGA designers need a way to evaluate if the FPGA(s) they choose can meet their application needs while keeping the cost of devices as low as possible. Estimating FPGA resource requirements can be tricky and requires designers to balance Look Up Tables (LUTs), high-speed I/O requirements, and memory with I/Os for low-speed signals. Sometimes choosing more than one FPGA may be cheaper than choosing one large FPGA. While at other times choosing an FPGA with a larger pin count will suffice, thereby saving board space and routing channels. Manual pin assignment approaches make performing these cost and performance trade-offs very time consuming and tedious. With its placement-aware FPGA I/O pin assignment synthesis, the Allegro FPGA System Planner helps designers do trade-offs quickly, enabling architectural exploration that is not practical with manual approaches.

OrCAD FPGA System Planner Concurrent device optimization Placement-aware synthesis Reuse symbols and footprints Symbols & schematic generation Post-placement optimization Schematic power connections Schematic terminations 1 FPGA Yes Yes OrCAD Capture No No No
Allegro FPGA System Planner L 1 FPGA Yes Yes
Allegro FPGA System Planner Two FPGA Option 2 FPGAs Yes Yes
Allegro FPGA System Planner XL 4 FPGAs Yes Yes
Allegro FPGA System Planner GXL Unlimited FPGAs Yes Yes
Allegro Design Entry Allegro Design Entry Allegro Design Entry Allegro Design Entry CIS / Allegro Design CIS / Allegro Design CIS / Allegro Design CIS / Allegro Design Entry HDL Entry HDL Entry HDL Entry HDL Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
TIGHT INTEGRATION WITH CADENCE DESIGN CREATION
The Allegro FPGA System Planner generates Allegro Design Entry CIS and Allegro Design Entry HDL schematics for the FPGA sub-system. It uses existing symbols for FPGA in Allegro Design Entry symbol libraries. If the user desires, the Allegro FPGA System Planner can create split symbols for FPGA based on the connectivity or one split symbol per bank.
hardware designer. Once the PCB layout designer starts to plan the routing of interfaces and signals on FPGA, it is possible to further refine the FPGA pin assignment based on route intent, layer constraints, and fanout chosen for the FPGA. The Allegro FPGA System Planner offers users a way to optimize FPGA pin assignment after placement and during routing of the interfaces and signals on a FPGA.

OPERATING SYSTEM SUPPORT

Allegro platform technology

Linux Windows

OrCAD technology

Windows

Scalability
The Allegro FPGA System Planner technology is available in the following product offerings: Allegro FPGA System Planner GXLfor synthesizing and optimizing pin assignment of more than four FPGAs at a time. Suitable for companies that use FPGAs to prototype ASICs Allegro FPGA System Planner XLfor concurrent pin assignment, synthesis, and post-placement optimization of up to four FPGAs at a time Allegro FPGA System Planner Lfor pin assignment synthesis and post-placement optimization of a single FPGA OrCAD FPGA System Plannerfor optimum initial pin assignment synthesis of a single FPGA.
INTEGRATION WITH FPGA VENDOR TOOLS
In addition to integration with Cadence PCB design tools, the Allegro FPGA System Planner communicates seamlessly with FPGA design tools. It generates and reads supported FPGA vendors pin assignment constraint files. This capability enables the FPGA designer to evaluate pin assignments against the functional needs of the FPGA. Any changes made by the FPGA designer to account for these requirements can be imported into the Allegro FPGA System Planner so that the complete set of pin assignments remain in sync.

CADENCE SERVICES AND SUPPORT
Cadence application engineers can answer your technical questions by telephone, email, or Internet; they can also provide technical assistance and custom training. Cadence certified instructors teach more than 70 courses and bring their real-world experience into the classroom. More than 25 Internet Learning Series (iLS) online courses allow you the flexibility of training at your own computer via the Internet. SourceLink online customer support gives you answers to your technical questions24 hours a day, 7 days a weekincluding the latest in quarterly software rollups, product change release information, technical documentation, solutions, software updates, and more.
PRE-ROUTE PIN ASSIGNMENT OPTIMIZATION
The initial pin assignmentthat accounts for placement and routability of the FPGA on a PCBgoes a long way toward reducing costly design iterations between FPGA designer, PCB layout designer, and
For more information contact Cadence sales at:

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2009 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Allegro, OrCAD, SourceLink, and Verilog are registered trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 20889 06/09 KM/MVC/DM/PDF

SUCCESS STORY

BUSINESS CHALLENGES
Meet an aggressive project timeline Reduce the number of PCB layers to accommodate design complexity and manufacturing requirements

JDSU AND CADENCE

JDSU turns to Cadence Allegro technology for more automation, shorter design cycle, and lower project cost
With Allegro FPGA System Planner, we finalized the pin assignment after the first pass, with only one or two pin swaps. In the front-end design process alone, we realized a 30% to 40% time savings. In addition, we realized a 50% time reduction in routing high-speed signals.
Bogdan Petrisor, Hardware Design Engineer, JDSU

THE CUSTOMER

CADENCE SOLUTIONS
Cadence Allegro FPGA System Planner Cadence Allegro Global Route Environment

DESIGN CHALLENGES

Pin assignment for multiple FPGAs on a new optical network tester board High-density, multi-port design with 5,500 components and stringent communications requirements 4,596 high-speed nets with constraints

RESULTS

A first-time-right board Routed in the fixed number of layers in half the time 3040% time savings in the front-end design process 50% shorter back-end design cycle compared to previous interactive approaches
JDSU is the leading provider of communications test and measurement solutions and optical products for a wide range of industries. One area of focus for the companys Communications Test and Measurement Group is developing instruments, systems, and software for broadband communication service providers, equipment manufacturers, and major communication users. Putting a large, complex field programmable gate array (FPGA) on a printed circuit board (PCB) can invite a host of challengesfrom unworkable pin assignments in the board layout to problems with signal integrity. So when JDSU embarked upon a new optical network tester board project with complex requirements and a tight timeline, it turned to Cadence for FPGA/PCB co-design and global routing technologies.
Allegro Global Route Environment helped us successfully reduce PCB place-and-route design time In the end we were able to shorten the cycle by 50% compared to previous interactive approaches. Dejan Banic, Hardware Design Engineer, JDSU
With Allegro FPGA System Planner, we finalized the pin assignment after the first pass, with only one or two pin swaps, Petrisor says. In the front-end design process alone, we realized a 30% to 40% time savings. In addition, we realized a 50% time reduction in routing high-speed signals.

THE CHALLENGE

JDSUs Communications Test and Measurement Group knew its nextgeneration optical network tester board would be challenging for several reasons. The board would include a high-density, multi-port design with more than 5,500 components covering both sides of a compact 11x11-inch design, as well as stringent communications requirements. The design had 4,596 high-speed nets that included DDR3, PCI Express, and other advanced high-speed interfaces. In addition, the project schedule was very aggressive. Given the complexity of the design and the aggressive schedule, we knew our current process would be inadequate and would delay the project, says Dejan Banic, Hardware Design Engineer, JDSU. On the board layout side, we knew that routing some of the high-speed interfaces would take a long time and possibly add layers if we didnt have time to do it right the first time.
ALLEGRO FPGA SYSTEM PLANNER
Allegro FPGA System Planner provided JDSU with a complete, scalable technology for FPGA-PCB co-design. It enabled the design team to complete the project in a shorter, more predictable mannerwith a first-pass success on the board. Bogdan Petrisor, Hardware Design Engineer at JDSU, told his manager that in order to adhere to the aggressive project schedule, the team would need Allegro FPGA System Planner. With this Cadence technology we were able to automatically synthesize FPGA pin assignment based on user-specified, interface-based connectivity, FPGA device pin assignment rules, and placement of FPGAs on the PCB, Petrisor says. With automatic pin assignment synthesis, we avoided internal custom-made tools and error-prone processes while shortening the design cycle time. Allegro FPGA System Planner provided JDSU with a floorplan view to place components in the FPGA system. Through interface definitions, the design team was able to specify connectivity between components within the FPGA sub-system at a higher level. The JDSU team shortened its time for optimum initial pin assignment, accelerating the design schedule. It also eliminated unnecessary design iterations during the layout process and reduced the PCB layer count through placement-aware pin assignment.

ALLEGRO GLOBAL ROUTE ENVIRONMENT
For the back end of the design process, the JDSU team relied on Allegro Global Route Environmentwhich provides interconnect planning and routing technology for PCB design. This technology provided JDSU with automation for various stages of interconnect planning and routing where no automation was previously available. Our first reaction was, This tool will leave the PCB designers without much work to do, Banic jokes. We used Allegro Global Route Environment to create our high-level routing strategy. We used the Interconnect Feasibility capability to check on available space for each of the flows and modify our routing strategy accordingly. The Allegro Global Route Environment built upon this feasibility analysis, including all of the engineers input, and automatically completed the routing. This approach was very effective for our high-speed memory interfaces, with their stringent high-speed design constraints, Banic says. Allegro Global Route Environment helped us successfully reduce PCB place-and-route design time. There was a short learning curve, but Cadence support addressed our issues quicklyoften within 24 hours. In the end we were able to shorten the cycle by 50% compared to previous interactive approaches.

THE SOLUTION

This JDSU design team had a long history of using Cadence OrCAD and Allegro tools with good results, so the team decided to look into two robust Cadence Allegro solutions: FPGA System Planner and Global Route Environment.

LESSONS LEARNED

This JDSU design group plans to continue using their new Allegro technologies on upcoming projectsand recommend them to other teams at JDSUto improve boards, reduce design cycle times, speed time to market, and reduce cost.
2011 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and Allegro are registered trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 21655 03/11 IW/MK/DM