Allegro PCB Librarian

Maximizing productivity in a powerful library development environment
Cadence Allegro PCB Librarian comprises an advanced library development environment for board-level design components. A comprehensive library toolset makes part creation fast and easy by reducing development time associated with large-pin-count parts from days to just minutes. Allegro PCB Librarian automates part creation tasks, eliminates manual validation, and captures revision history for schematic symbols. When used with Allegro Design Workbench, it becomes part of a scalable, comprehensive library creation, management, and component information system.
Allegro PCB Librarian maximizes the productivity of librarians who create schematic symbols, PCB footprints, and digital simulation map files for use in the Allegro PCB design flow. An easy-to-use interface, a configurable work environment, and an array of advanced verification utilities make it a powerful library development environment.
Allegro Design Workbench PDM Option

Allegro Design Workbench

Allegro Library Workbench
Allegro Library Management Server Library and Team Design Management
Allegro Library Management Server Library, Team, and Design Data Management and Collaboration

Benefits

Accelerates part creation with the help of advanced part creation and verification utilities Offers integrated online verification and flow verification using interactive and batch tools to provide known-good library data for design tools Enables easy import of part information from tables, grids, text files, and several other commonly used formats omplete for new parts C ncremental for changed parts to I expedite updates

Library Development

Figure 1: Allegro library development and management solution
Delivers powerful graphics-editing capabilities to create schematic symbols and reusable shapes Provides a common library development environment for multivendor schematic design tools Integrates with Allegro Design Authoring and Allegro Design Workbench

Features

Imports from more than 15 common file formats in full and incremental modes Exports to 5 common file formats Capture EDA XML CSV Mentor DxDesigner Design Architect Provides integrated spreadsheet and graphical editors for schematic symbols
In Allegro PCB Librarian, all changes made to a part are tracked and the differences between part versions are captured and saved automatically. This removes the burden on librarians to record all changes made to a part. Check-sum verification is integrated into the system and tracks any modification to parts made outside the library system. This protects the data against unauthorized modifications and notifies librarians when a modified part is opened in the system.

Multi-Vendor Support

Allegro PCB Librarian allows users to create symbols for Allegro Design Entry HDL, Cadence OrCAD Capture, Mentor Graphics Viewdraw/DxDesigner, and Mentor Graphics Design Architect. Part information can also be exported in comma-separated values (CSV) and XML formats. This allows single sourcing of part data in companies where librarians need to support designs teams who use multiple schematic editors with Allegro PCB Designer. Direct export to multiple schematic editor formats makes it easy to develop parts in a single toolset for use with multiple schematic editors. Export in XML can be used to publish part data for external access or verification. Exporting text files allows users to store electronic datasheets. The ability to convert from CSV to PDF helps in the migration of parts from other vendors. Allegro PCB Librarian also allows users to save parts in formats compatible with older releases of Allegro PCB Designer and Allegro Design Entry HDL. This enables users to adopt the latest librarian releases and features while still supporting previous releases of Allegro solutions.

Figure 2: Integrated spreadsheet and graphics editor
Supports the creation of reusable shape libraries Enables real-time, online verification Provides batch verification scripts Supports symbol property templates Includes configurable rule checkers for both schematic symbols and footprints Provides strong metadata support to enable built-in version management
A powerful graphics editor makes symbol creation easy and quick. Users can not only create complex IEC and IEEE shapes to represent pins and functions, but also save them as reusable library elements. The Allegro PCB footprint wizard makes it easy to create footprints by providing templates for most commonly used parts. Using the footprint wizard, users can accurately create complex footprints with thousands of pins in minutes. Allegro PCB Librarian also provides the ability to quickly associate Hardware Description Language (HDL) models with schematic parts for both Verilog and Verilog Hardware Descripton Language (VHDL) models for use in system-level digital simulation.

Part Creation

Largepin-count devices are becoming common for off-the-shelf components. Creating these largepin-count parts for schematic and PCB layout can take hours or even days without special tools to accelerate part creation. The powerful import and spreadsheet editing features of Allegro PCB Librarian aid in manipulating largepin-count part data. Users can quickly split pins across multiple symbols, map pin names to pin numbers, and specify the visibility of power and ground pins.
Figure 3: Symbols with reusable shapes

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Data Import
Allegro PCB Librarian provides a variety of import options and utilities to accelerate part creation. Users can create schematic parts by importing part data in formats such as: EDA XML Si2 PinPak XML VHDL Verilog Synopsys PTM models CSV and text files Die text Pin grids Pin tables Cadence OrCAD Capture Mentor Graphics DxDesigner Mentor Graphics Design Architect Allegro Package Designer FPGA (Xilinx, Actel, Altera) IBIS DML Die file import enables co-design while FPGA import helps in implementing FPGA flows in front-end design. With IBIS and DML model import, front-end models can be easily created from third-party highspeed models. User-configurable data translation rules make it easy to customize data import. These rules manipulate part, pin, and property names as well as other part details. Allegro PCB Librarian checks the data being imported for consistency and validity, flagging errors upfront. A preview window allows users to review the part data before the part is created. These reduce the chance of errors in the source data being propagated into the part.

Figure 4: Preview window for viewing and editing part data before importing
users the flexibility to do bulk operations and intricate graphics work according to their needs. Automatic symbol generation based on user preferences makes it easy to create large-pin-count devicesdevices that might have thousands of pins distributed among dozens of symbols. A simple pin distribution interface makes it easy to move pins between symbols to meet engineering requirements. The spreadsheet editor for part information speeds many part development operations, including: Converting scalar pins to vector pins and vice-versa Expanding and collapsing vector pins Switching between visible and invisible power pins Filtering and hiding operations Finding and replacing A comparison UI makes it easy to compare interfaces of various part entities including footprints, schematic symbols, and SI models. The ECO import mode makes implementing incremental changes remarkably easy. This mode retains original data, while allowing new, possibly conflicting data to be imported. The data can then be compared and resolved to produce parts. The ECO mode greatly reduces rework in cases where input data changes frequently. The ECO preview window allows users to view and evaluate newly imported data before committing to the change.
copy pin-out/ball-map diagrams from datasheets into Allegro PCB Librarian. The data is automatically interpreted and can be fine-tuned to meet company naming standards. Additionally, users can copy complete tables of information from datasheets with configurable translation of pin types and bus notations.

Schematic Symbol Editing

Allegro PCB Librarian comes with a powerful graphics editor for creating reusable shapes and schematic symbols. An editable spreadsheet with symbol information and a symbol editing canvas with expert features, such as separate grid controls for pins and non-pin objects, give
Pinout description in PDF

Datasheet Mining

The ability to read pin tables and pin grids makes it easy to create parts from descriptions in PDF datasheets. Users can
Imported data after mining

Created and validated part Figure 5: Import of part data in pin-grid format from PDF

PCB Footprint Editing

The PCB footprint creation process is designed to simplify the ever-increasing complexity of todays package models. A powerful wizard enables users to quickly create footprints using templates that handle most package typesincluding DIP, SOIC, PLCC/QFP, PGA/BGA throughhole discrete, SMD discrete, SIP, and ZIP. The pad designer facilitates the creation of any shape pad and padstack. It allows users to define the pads for each layer in the stack-up as well as various mask layers, hole types, and slots.
Comprehensive rule development and checking guidelines are provided both for schematic symbols and PCB footprints. Consistency checks are done whenever a part is saved or loaded for editing. Part error status is stored with the part and displayed whenever the part is opened or closed. Allegro PCB Librarian provides a standard rule set and a developers toolkit for building user-defined rules. Using these rule sets and the built-in part validation system, librarians can push parts through the advanced rule checking and advisement system. This reduces costly design iterations by ensuring that a part is correct from the start.
Cadence Services and Support
Cadence application engineers can answer your technical questions by telephone, email, or Internetthey can also provide technical assistance and custom training Cadence certified instructors teach more than 70 courses and bring their real-world experience into the classroom More than 25 Internet Learning Series (iLS) online courses allow you the flexibility of training at your own computer via the Internet Cadence Online Support gives you 24x7 online access to a knowledgebase of the latest solutions, technical documentation, software downloads, and more

Validation

Allegro PCB Librarian provides extensive part validation capabilities with built-in checks at every stage of the part creation process. For imported data, validation occurs at the time of import. When data is entered in the part editor, it is checked in real time for valid characters, lengths, permitted values, and syntax. Symbolpackage checks guarantee that parts will work in the complete PCB design flow. Footprint validation routines allow users to compare pin numbers specified at the time of schematic symbol development with PCB footprints. This online check ensures that schematic components and footprints are in sync. Most verification is done in real time without leaving the editor. Additionally, batch validation provides automated design flow verification that significantly reduces the burden on librarians. Users can run detailed packaging checks that instantiate the schematic symbol in a schematic sheet, create a netlist, and place the footprint into a layout file or quick checks that help them determine, in considerably less time, if a part can be packaged. User-defined symbol and footprint checks can be built for schematic parts and footprints. These can operate on one part at a time or on complete libraries.

Allegro Design Workbench Integration
Allegro PCB Librarian is an integral part of Allegro Design Workbench. When combined, these technologies comprise the most powerful board-level library and design data management system available today. It allows users to manage and distribute their Allegro schematic and PCB libraries. Component information can be included from datasheets, ERP, MRP, or other sources. By setting up a standardized part development flow across their organization, users can reduce errors and accelerate library development. This approach significantly increases productivity and improves the quality of their library. Configurable flow management capabilities allow users to manage their library development process and tailor it to their specific needs.

For More Information

Contact Cadence sales at 1.800.746.6223 or visit www.cadence.com for additional information. To locate a Cadence sales office or channel partner in your area, visit www.cadence.com/contact_us.

Operating System Support

Sun Solaris Linux IBM AIX Windows
Cadence is transforming the global electronics industry through a vision called EDA360. With an application-driven approach to design, our software, hardware, IP, and services help customers realize silicon, SoCs, and complete systems efficiently and profitably. www.cadence.com
2011 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Allegro, OrCAD, and Verilog are registered trademarks a of Cadence Design Systems, Inc. All others are properties of their respective holders. 22114 05/11 MP/DM/PDF

Whats New In All products For The 16.3 Release

ALLEGRO AMS SIMULATOR

Cadence Allegro AMS Simulator release 16.3 provides users with a complete makeover of its waveform environment, along with new usability improvements, enhanced cursor support, and new simulation models. Easy To Use Pop-Up Menu for Traces: The context-sensitive menu for traces is now more usable with all the trace related options grouped together. When users select a trace and right-click, they are presented with the options in context of the trace. Easier Access to Trace Properties: Users can now choose Trace Property in the trace pop-up menu to open the Trace Properties dialog box. This dialog box gives a range of choices to change color, pattern, width, and symbol for a selected trace, making it easier to identify individual traces. This dialog box also allows users to easily hide all traces or show all traces. Controlling Background and Foreground Colors: Users can now specify different colors for the background of the Probe window, as well as grids and axis lines in the foreground. Customizing Auto-Rotation of Trace Color: Allegro AMS Simulator 16.3 users can choose to change the default trace colors from an extended list of 145 supported colors. Setting Cursor Width and Color: The Cursor Settings tab of the Probe Settings dialog box allows users to specify the vertical and horizontal width and color for two cursors. The number of cursor digits can also be specified. Placing Cursors Across Multiple Traces and Plots: Allegro AMS Simulator 16.3 users can add cursors across multiple traces and plots. The cursor window displays values for the different traces. Exporting and Copying Cursor Data: Allegro AMS Simulator 16.3 users can export the cursor information to a comma separated value (.csv) file that can then be opened in various tools, such as Microsoft Excel. Users can also copy selected values from the cursor window and paste the information from the clipboard to any text editor. Dockable Cursor Window: In Allegro AMS Simulator 16.3, the Cursor window is now dockable and can be placed anywhere the user finds convenient. Exporting Comma Separated (CSV) Files: Users can now easily export trace information as.csv files by choosing File Export Comma Separated in the Allegro AMS Simulator Probe window. The trace information for specified variables will be exported to a location and file as specified by the user and can be read using various tools, such as Microsoft Excel. Faster.dat File Import and Export: In previous releases, the performance of large.dat files 2GB or more in size was improved. In the 16.3 release, the performance when opening a.dat file has been enhanced for files of all sizes. Highlighting In Circuit And.out Files: In Allegro AMS Simulator 16.3, circuit and.out file syntax are presented in easy to read colors that highlight the different groups, such as text, numbers, comments, expressions, operators, and keyword. Users can also specify their own color schemes for the files. New Design Templates: Allegro AMS Simulator 16.3 comes with a set of design templates covering basic electronics circuits and SMPS topologies. These design templates cover the range of analog, digital, and mixed designs. Users can use the new design templates, which are a combination of design and simulation profiles, as a starting point for new designs.
New Models in 16.3: More than 330 new models are now available for simulation in Allegro AMS Simulator 16.3 under the following categories:
Pulse Width Controlled (PWM) Models Linear Regulators Zener Voltage Regulators Glass Passivated Zener Diode

ALLEGRO DESIGN ENTRY CIS

Cadence Allegro Design Entry CIS release 16.3 continues to boost productivity through new GUI updates, 3-D footprint viewing, a new auto-wire connection capability, and enhanced scripting with TCL/TK support. Allegro Design Entry CIS release 16.3 provides more control and visibility over the relational data from the CIS database. Auto-Wiring: Allegro Design Entry CIS 16.3 now includes an auto-wiring feature that allows users to wire two or more pins or wires on a schematic page. With this new functionality, wiring between component pins is as simple as selecting a starting pin and a destination pin and letting the software add the connection - all automatically and quickly. Design Navigation Improvements: In Allegro Design Entry CIS 16.3, users can create intersheet references on flat designs as well as simple or complex hierarchical designs. The design navigation now includes a signal navigation feature to navigate the connected signals on a design. Users can select and highlight the signals from the browse list. User Interface Enhancements: Allegro Design Entry CIS 16.3 users can now change the color, line style, or line width of a wire or net; the color of a block; embed or link an object or image; and place elliptical arcs and multi-point bezier curves on schematic pages. Allegro PCB Editor 3-D Footprint Viewer: The Allegro PCB Design 3-D Footprint viewer provides a three dimensional view of the footprint symbol of a selected part on the schematic or the part editor. Along with the footprint symbol, the viewer also displays pin numbers and pin names, and can be rotated to view different perspectives. A 3D measure tool can be used to measure points in x, y, or z axis. Scripting Support: Allegro Design Entry CIS 16.3 includes a TCL/TK scripting functionality that allows users to execute a command through a command prompt. The command can be stored and replayed later. This capability gives users more time to identify the type of script (set of steps) that is required for a specific task. PCB Flow Enhancements: Allegro Design Entry CIS 16.3 now provides a new locking mechanism and warning filter to further enhance users PCB flow experience. The Object Locking feature allows users to temporarily lock an object on the schematic or board while cross-probing. The Output Warnings filter provides the option of ignoring numerous electrical constraints during PCB netlist creation. Electrical Rules: The DRC check in Allegro Design Entry CIS 16.3 is now separated out between physical rules and electrical rules. This allows users to choose to run design checks from the available physical and/or electrical rules. Check and Save: The new Check and Save option (available through the project manager file menu) allows users to run a DRC on the currently checked rules in the DRC dialog. Power Pin Enhancements: Allegro Design Entry CIS 16.3 now includes a new Assign Power Pins command that allows users to select the power pins on the design they want to route and then set all the other power pins as NC pins. Bill of Materials: With Allegro Design Entry CIS 16.3, users can now include relational fields in their Bill of Materials if there are defined relational fields in their CIS configuration. Relational Data Report: When users include relational data in their reports, they can also choose the display format for this data. Relational data can be displayed horizontally (in the same row) or vertically (one line item per related data). The maximum number of related child items to output can also be specified.

ALLEGRO DESIGN ENTRY HDL

Costraint Driven Design Flow
Differential Pair Dynamic Phase Control Match Via constraints for high-speed interfaces (DDR2, PCI Express Gen2, )
Allegro Design Entry HDL improvements Ease of use improvements Alignment & Distribution Anchor Point Wire Stretch Set Font for text objects Differential Pair Renaming
Improved layout driven RF PCB design generates RF schematic circuit diagram from RF layout Single schematic drives layout and mixed-signal simulation using Allegro AMS Simulator eliminating need to redraw schematics for production flow
Single schematic for simulation and layout
New look and feel in AMS Probe Improved netlisting performance for faster edit-simulate-edit cycles Improved Probe marker window control All design probe markers of design are visible Probe markers in schematic and plot windows synchronized Probes in schematic associated with simulation sessions

ALLEGRO DESIGN WORKBENCH

Design Lifecycle Improvements
Multiple Library Release Support Allows single corporate library to support co-existence of 2 different versions of Allegro Design Workbench libraries Designers, sites and/or project teams have the flexibility to independently migrate to the new version as required, minimizing overhead and maximizing productivity Enables concurrent library and project development focused on reducing time associated with new part adoption while increasing design team efficiency Provides easy way for librarians to create and distribute mechanical parts and kits via the ECAD environment facilitating faster overall design output Introduction of MCAD part classification enables designers to more efficiently search for mechanical parts and have them incorporated in a final , consolidated BOM greatly reducing time and minimizing potential for error
Pre-Release / Temporary Part Capability
ECAD-MCAD Part Data Management
Environmental Compliance Improvements
Obsolete Part Information Support Allows dynamic integration of part obsolescence data (ie: RoHS) directly from the enterprise PLM system enabling intelligent part selection early in the design cycle while minimizing librarian overhead Automated part updates and recommended replacements are easily and instantly communicated allowing engineers to take appropriate action(s) Configurable environment enables warnings or prevents adoption of bad parts to ensure quality of results

ALLEGRO PCB DESIGN

Improvements for Design Miniaturization
Improvements for Flex and Rigid-flex designs include Contour Lock while adding interconnect Enhanced Arc Editing Multi-Line Generator
3-D Design and interconnect Viewer Constraint-driven HDI design flow Exclusive Microvia Stacking rule for HDI designs Exclusive Via List DRC Via List cross section Viewer Elimination of Unused Stacked Vias

Asymmetrical clearances for RF circuits
High Speed Constraint Driven Flow Differential Pair Dynamic Phase Control Setting the Dynamic Phase DRC New Match Vias Constraint
Productivity enhancements Flip Design User customizable Data tips Placement Replication enhanced to support Interconnects
Etch Edit Productivity Enhancements Enhanced Pad Entry, Exit capability Support for Jumpers
Interconnect Flow Planner improvements Constraint Manager Integration for selection and creation of bundles Expanded Rake Functionality to aid in planning New Functionality to Select, Get Information and Route plan status Faster plan creation through Copy, Move and Split flows
PCB Router Improvements Explicit Via Usage in Regions supported at region level Micro via stacking rules support BB via clearance rules support clearance between Blind/Buried vias and ALL other Via types
Design for Manufacturing Pastemask Clearance DRC Negative Plane Sliver DRC
RF PCB Design improvements
Ease of use improvements Asymmetrical clearances Via Arrays improvements Improvements to layout driven design (schematic generation)

ALLEGRO PCB LIBRARIAN XL

Multiple Library Release Support Allows single corporate library to support co-existence of 2 different versions of Allegro Design Workbench libraries Designers, sites and/or project teams have the flexibility to independently migrate to the new version as required, minimizing overhead and maximizing productivity Pre-Release / Temporary Part Capability Enables concurrent library and project development focused on reducing time associated with new part adoption while increasing design team efficiency ECAD-MCAD Part Data Management Provides easy way for librarians to create and distribute mechanical parts and kits via the ECAD environment facilitating faster overall design output Introduction of MCAD part classification enables designers to more efficiently search for mechanical parts and have them incorporated in a final , consolidated BOM greatly reducing time and minimizing potential for error

ALLEGRO PCB SI

Allegro PCB SI All tiers
SigXp User Interface Overhaul Next generation Signal Explorer (SigXp) brings pre-route exploration to every engineers desktop PCB layer stackup aware for early tradeoff studies Context sensitive right-mouse-button Never more than a few mouse clicks away from a waveform Improved support for IO Modeling Standards Assign, view, or edit models in IBIS format Current DML flow remains as an alternative Manual model wrapping no longer required Models can be managed in definable search paths
IBIS libraries and models remain in native format
New wizard imports HSpice models
Allegro PCB SI XL and GXL
Full Wave field solver now supports surface roughness Three modeling techniques to choose from: Hammerstad, Modified Hammerstad, or Exponential model

Allegro PCB SI GXL

Signal Quality Screening of routed signals streamlines Channel Analysis flow Signal quality screening reduces verification cycle Ability to screen channels for candidates to perform detailed analysis Results based on signal-to-noise ratio of impulse response Enables more design cycles to improve design performance

ALLEGRO SYSTEM ARCHITECT

Constraint Driven Design Flow
Differential Pair Dynamic Phase Control Match Via constraints for high-speed interfaces (DDR2, PCI Express Gen2, ) Improved layout driven RF PCB design generates RF schematic circuit diagram from RF layout Single schematic drives layout and mixed-signal simulation using Allegro AMS Simulator eliminating need to redraw schematics for production flow
Allegro System Architect improvements
Unique Multi-style design authoring environment Effective for Large Pin count devices, backplane designs Improved Placement Associated Components closer to the Pins Custom Placement between components Remove over laps Port Cleanup Project Hierarchy recreated in Allegro Design Entry HDL schematics Saves time when schematics are reused Design reuse and system integration through import Verilog, existing schematics in Allegro Design Entry HDL Improved schematic generation capabilities
Export reuse (packageable) schematics to create a Design Entry HDL project
2010 Cadence Design Systems, Inc. All Rights Reserved.