ALL E G R O P C B R F O P T I O N

DATASHEET

PCB RF DESIGN SOLUTION
PCB designers face significant challenges in integrating RF circuits on a mixed-signal design. Todays advanced designs are more complex and need to incorporate all design portions such as digital, RF/ microwave, and analog circuits on the same board. To deal with this complexity on a PCB, designers must be able to create a mixed-signal design within an integrated, production-ready PCB design environment. RF/microwave modules are different from digital circuits in many respects. For example, distributed RF components are usually parameterized with widths and lengths; RF circuits have symmetric structures, with many large irregular shapes used for RF layout. Designers need a feature-rich, efficient, reliable, and easy-to-use mixed-signal PCB design tool to handle all of these design needs.
The Cadence Allegro PCB RF Option is a mixed-signal design environment, from schematic to layout with backannotation, proven to increase RF design productivity up to 50%. It allows engineers to create, integrate, and update RF/ microwave circuits with digital/analog circuits in the Allegro PCB Design environment. With its rich layout capability and powerful interfaces with RF simulation tools, it allows engineers to start RF design from Allegro Design Entry-HDL, Allegro PCB Editor, or Agilent ADS.

ALLEGRO PCB RF OPTION

The Allegro PCB RF Option is the answer. This RF design solution combines the strength of both Cadence Allegro and Agilent ADS design environments for designing and integrating RF circuits on mixed-signal PCBs. The Allegro PCB RF Option provides everything needed to develop complex RF/mixed-signal designs simply and quickly in an integrated environment with Allegro Design Entry-HDL (DE-HDL) and Allegro PCB Editor. The Allegro PCB RF Option provides a robust set of layout functionalities: parameterized etch element generation, quick placement, RF-style routing, editing of RF etch elements, and the ability to place via arrays along user-specified objects such as an RF component, a connect line (cline), or a discrete component. The generated etch elements will be recognized as RF components with parameters. Users can easily change the
parameters of the elements after they are placed; the system will re-generate those elements. The Allegro PCB RF Option also supports complex copper shape creation and editing with its Flexible Shape Editor, which is a supplement to the existing shape functionality of Allegro PCB Editor. With the ability to understand RF components in PCB layout, the Allegro PCB RF Option offers the unique capability of layout-driven design, which generates the RF circuit schematic changes in Allegro DE-HDL for new RF elements introduced in PCB design. The Allegro PCB RF Option also supports different design flows working with RF design and analysis tools from Agilent. It provides a bi-directional interface for design data exchange (partial or complete), a discrete component translator, and import of schematics from Agilent ADS.
Convert Allegro connect lines (clines) to transmission line components Chamfer corners of a RF trace Variable/expression display and modification Replicate RF circuits quickly, including flip mode for symmetrical/balanced circuits

FLEXIBLE SHAPE EDITOR (FSE)
The FSE module includes a robust set of editing functionality for line, shape edge, vertex, or whole shapes. It enhances the existing Allegro PCB Editor line/shape editing functions; it provides powerful and flexible functions for copper editing, adjustment, and resizing. This capability increases the flexibility to modify RF shapes and is particularly helpful for cases in which irregular shapes are used heavily, such as power amplifier circuits and filter circuits.
Figure 1: The Allegro PCB RF Option supports creation and editing of complex RF components

BENEFITS

Shortens time to integrate RF circuits on a mixed-signal design Seamlessly integrated with Allegro DE-HDL and Allegro PCB Editor Provides a complete RF/microwave design solution using a unified design environment and database Improves design productivity and reduces design time for complex RF shape creation, RF trace routing, and via arrays Enables designers to use the same front-to-back and backannotation flow for both digital and RF/mixed-signal designs Integrates with Agilent ADS RF design and analysis environment Shortens time to update schematics through layout-driven design for RF circuits

RF LAYOUT

The Allegro PCB RF Option provides a powerful and flexible set of manual and interactive placement, routing, and editing tools within Allegro PCB Editor. Since the Allegro PCB RF Option understands RF etch elements, it provides a very easy mechanism for the creation, placement, and connection of RF components. It easily routes an RF trace with different bend styles such as optimally mitered RF bend, curved, or square. It can also connect two points by a direct RF trace or a meander. Other RF layout features include: Move, rotate, flip, and copy individual RF components or a selected set of objects (shape, cline, etch elements, vias) Group copy, flip, and rotate RF components or a selected set of objects Push RF components or a group of etch objects from one layer to another Change RF parameters and re-generate RF etch components Insert an RF component during the RF routing process Electrical calculation and display for RF trace Define a custom RF component Convert RF components to shapes
ALLEGRO DFI FROM AGILENT ADS
The Advanced Design System (ADS) from Agilent includes a design flow integration (DFI) for Allegro technology that allows import of traces, vias, lumped elements, bonds wires, and ball grid arrays for analysis using the 3D electromagnetic field simulators in ADS. Besides the multi-port frequency response output data (S-parameters), ADS provides 3D visualization tools for geometry, fields, and currents. This insight into the physical behavior of internal nodes lets engineers adjust the design to meet performance goals.

RF SCHEMATIC IMPORT

Allegro DE-HDL allows engineers to import RF circuits from the Agilent ADS design environment to integrate with digital/analog portions of the mixed-signal PCB design. The schematic import uses a wizard-driven flow, simplifying the process of symbol creation and schematic update. All parametric RF components will be mapped to Allegro RF libraries automatically. A packaged part can be mapped to map to an existing library using the Universal Component Browser or an

FEATURES

PARAMETERIZED ETCH ELEMENTS
The Allegro PCB RF Option enables creation and editing of RF etch elements that are parameterized to enable their use in RF circuit design creation. There are more than 600 such parameterized elements, from Microstrip to Stripline to lumped components.

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DISCRETE COMPONENTS LIBRARY TRANSLATION
The Allegro PCB RF Option allows users to translate discrete, packaged parts from ADS to the Allegro parts library: schematic symbols and package footprints. The schematic and layout files are handled at the same time.

Offset Via Array

Circular Via Array

OPERATING SYSTEM SUPPORT

ALLEGRO PLATFORM TECHNOLOGY: Cline Via Array Foundary Via Array
Sun Solaris Linux IBM AIX Allegro symbol can be created using the information from the imported design. It supports variables/expressions and hierarchical structures.
Figure 2: Via arrays easily instantiated around user-selected group of objects
BI-DIRECTIONAL INTERFACE WITH ADS LAYOUT
The bi-directional physical interface between Allegro PCB Editor and Agilent ADS enables designers to implement their RF layout designs either in Allegro PCB Editor or in the ADS environment. With PCB RF features, designers can implement the RF design with parameterized components based on a pre-defined RF library or create desired flexible shapes and lines with FSE functionality. The layout structure in Allegro PCB Editor can be transferred to ADS quickly and accurately. It also enables any change/ optimization for layout structure in ADS based on electromagnetic simulation to be backannotated to Allegro PCB Editor.
ADS Schematic Allegro DE-HDL Allegro PCB RF

Windows

OrCAD TECHNOLOGY:

VIA ARRAYS

RF designers use via arrays on RF circuits to provide good grounding/shielding and to mitigate electromagnetic radiation effects. The Allegro PCB RF Option provides an easy method to instantiate an array of vias. Users can place these vias along the boundaries of RF etch components, any copper shape boundary, or along the discrete components.

CADENCE SERVICES AND SUPPORT
Cadence application engineers can answer your technical questions by telephone, email, or Internetthey can also provide technical assistance and custom training. SourceLink online customer support gives you answers to your technical questions24 hours a day, 7 days a weekincluding the latest in quarterly software rollups, product release information, technical documentation, software updates, and more. Cadence-certified instructors teach more than 80 courses and bring their real-world experience into the classroom. More than 25 Internet Learning Series (iLS) online courses allow you the flexibility of training at your own computer via the Internet.

LAYOUT-DRIVEN RF DESIGN

The Allegro PCB RF Option enables the backannotation process to automatically generate schematics for RF subcircuits that were added to the PCB RF layout. This allows RF engineers to create elements in layout, model them using Momentum, and then validate them through simulation using ADS. Automating the creation of schematics for added RF elements reduces the time it takes to update schematics once the RF circuit is validated.
Agilent ADS Momentum + Simulation
Figure 3: The Allegro PCB RF Option supports various RF design flows with the Agilent ADS environment

FOR MORE INFORMATION

Contact Cadence sales at 1.800.746.6223 or visit www.cadence.com for additional information. To locate a Cadence sales office or Cadence Channel Partner in your area, visit www.cadence.com/contact_us.
For more information contact Cadence sales at:

+1.408.943.1234

or log on to:
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2009 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Allegro, and SourceLink are registered trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 20885 09/09 MK/DM/PDF

Cadence Allegro PCB Design Solution
Managing complexity for faster, more cost-effective implementations
Systems companies are impacted by new devices and design methodologies offered by the semiconductor industry. New devices often bring more challenges, like increasing pin counts packaged in shrinking pin pitch ball grid arrays (BGAs). Additionally, new devices use evolving standards-based interfaces, such as DDR3, DDR4, PCI Express Gen3, USB 3.0 and others, that may require learning new ways to implement them on the board. Coupled with these increasingly complex technologies is the desire by companies to differentiate their offerings and get them to market faster, cheaper, with more functionality and in reduced end product size. As a result, many companies now outsource to or partner with companies in low-cost geographies. To manage such increasing complexities, PCB designers need a solution that addresses their technological and methodological challenges.
Allegro PCB Designer is a scalable, proven PCB design environment that addresses technological and methodological challenges while making the design cycles shorter and predictable. Available in base plus options configuration, the PCB design solution contains everything needed to create a PCB layout with a fully integrated design flow. The base Allegro PCB Designerincludes a common, consistent constraint management solution, PCB Editor, an auto/interactive router, as well as interfaces for manufacturing and mechaniFigure 1: Allegro PCB design solution brings together all the tools needed to design simple-tocal CAD. PCB Editor provides a complex PCBs complete placement and routing environmentfrom basic Eliminates unnecessary iterations Features a common, consistent floor-planning, placement, through constraint-driven PCB constraint management system and routing to placement replication, design flow for creation, management, and advanced interconnect planningfor validation of constraints from front simple to complex PCB designs. Supports a comprehensive rule set to back for physical, spacing, design for Benefits fabrication, assembly and test (DFx), Open environment for third party high-density interconnect (HDI), and application improves productivity Offers a proven, scalable, electrical (high speed) domains while providing access to best of cost-effective PCB editing and breed integrated point tools routing solution in on-demand base plus options configuration

PCB Editor Technology

Constraint-Driven PCB Editing Environment
At the heart of Allegro PCB Designer is a PCB editoran intuitive, easy-to-use, constraint-driven environment for creating and editing simple to complex PCBs. Its extensive feature set addresses a wide range of design and manufacturability challenges: A powerful set of floorplanning and placement tools including placement replication for accelerating placement of the design Powerful shape-based shove, hug interactive etch creation, editing establishes a highly productive interconnect environment while providing real-time, heads-up displays of length and timing margins Dynamic shape capability offers real-time copper pour plowing & healing functionality during placement and routing iterations The PCB editor can also generate a full suite of phototooling, bare-board fabrication, and test outputs, including Gerber 274x, NC drill, and bare-board test in a variety of formats.
Figure 2: Design For assembly (DFA) rules driven placement allows for compact placement of components without introducing errors
cal representation of whether constraints pass (highlighted in green) or fail (highlighted in red). This approach allows designers to immediately see the progress of the design in the spreadsheets, as well as the impact of any design changes.

Placement Replication

Superior placement replication technology within Allegro PCB Designer allows users to quickly place and route multiple similar circuits in a design. It allows users to create a template using one instance of placed and routed circuit that can be applied to other instances within the design. The saved placement template can be used with other designs where similar circuits are used. When replicating placement, users can flip or mirror the circuit from top layer to bottom layer. All associated etch elements, including blind buried vias, are mapped to correct layers when circuit is moved from top layer to bottom layer.
Floorplanning and Placement
The constraint and rules-driven methodology of PCB design solutions includes a powerful and flexible set of placement capabilities, including interactive and automatic. The engineer or designer can assign components or subcircuits to specific rooms during design entry or floor- planning. Components can be filtered and selected by reference designator, device package/footprint style, associated net name, part number, or the schematic sheet/page number. With thousands of components comprising todays boards, precise management is critical. Real-time assembly analysis and feedback can facilitate this managementhelping designers increase productivity and efficiency by placing components according to corporate or EMS guidelines. Dynamic design-forassembly (DFA)-driven placement offers real-time package-to-package clearance checking during interactive component placement (see Figure 2). Driven from a two-dimensional spreadsheet array of classes and package instances, real-time feedback provides minimum clearance requirements. Based on the packages side-to-side, side-to-end, designers can simultaneously place devices for optimum routability, manufacturability, and signaltiming.

Constraint Management

A constraint management system displays physical/spacing and high-speed rules along with their status (based on the current state of the design) in real time and is available at all stages of the design process. Each worksheet provides a spreadsheet interface that enables users to define, manage, and validate the different rules in a hierarchical fashion. With this powerful application, designers can graphically create, edit, and review constraint sets as graphical topologies that act as electronic blueprints of an ideal implementation strategy. Once they exist in the database, constraints can drive the placement and routing processes for constrained signals. The constraint management system is completely integrated with the PCB editor, and constraints can be validated in real time as the design process proceeds. The result of the validation process is a graphi-
Display and Visualization
The built-in 3D viewer is available in all PCB Editor products. The 3D environment supports several filtering options, camera views, graphic display options such as solid, transparency and wireframe, and mouse-driven controls for pan, zoom, and spinning the display. 3D viewing also supports the display of complex via structures or isolated sections of the board. Multiple display windows can be opened using the context sensitive command structure, and 3D images can be captured and saved in JPEG format. (see Figure 3.) The flipboard capability flips the design about its Y axis inverting the design database in the canvas. This flip reorganizes the display of the design such that what was displayed as top through to bottom becomes bottom through to top. Having a true bottom side view from within the CAD system is essential for hardware

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Viewer. The ODB++ data format creates accurate and reliable manufacturing data for high-quality Gerberless manufacturing.

High-Speed Design

Increasing use of standards-based advanced interfaces such as DDR3, DDR4, PCI Express, USB 3.0 are bringing a set of constraints that must be adhered to while implementing a PCB. Allegro PCB Designer through its High-Speed Option makes adhering to constraints on advanced interfaces quick and easy. It offers an extensive range of electrical rules to ensure that the PCB design implementation is complaint with the specification for advanced interfaces. Additionally, it allows users to extend the rules through the use of formulas with existing rules or post-route data such as actual trace lengths.
Figure 3: Built-in 3D viewer allows reviewing of a section of the board or complex via structures with pan, zoom, rotation and spinning to reduce iterations with mechanical design teams or PCB fabricators without introducing errors
engineers when debugging a board in the lab, or for assembly/test engineers on the manufacturing floor. Flipboard is not just limited to viewing; design edits can also be performed while in this mode.

ing traces with curves that are aligned to contour of the flex portion of the design. (See Figure 4.)

Miniaturization

Constraint-Driven HDI Design Flow
With BGA pin pitches decreasing to below 1mm0.8mm or lower with 0.65 or 0.5mm pin pitchesusers are forced to implement a buildup PCB technology using high-density interconnect (HDI). While miniaturization is not necessarily the primary objective in many market segments, the move to buildup technol-

PCB Manufacturing

A full suite of phototooling, bare-board fabrication, and test outputs, including Gerber 274x, NC drill, and bare-board test in a variety of formats, can be generated. More importantly, Cadence supports the industry initiative toward Gerberless manufacturing through its Valor ODB++ interface that also includes the Valor Universal

Interactive Etch Editing

The routing feature of the PCB editor provides powerful, interactive capabilities that deliver controlled automation to maintain user control, while maximizing routing productivity. Real-time, shapebased, any-angle, push/shove routing enables users to choose from shovepreferred, hug-preferred, or hugonly modes. During etch editing, the designer can view a real-time, graphical heads-up display of how much timing slack remains for interconnect that has high-speed constraints. Interactive routing also enables group routing on multiple nets and interactive tuning of nets with high-speed length or delay constraints.

Multi-Line Routing

Multi-line routing allows users to quickly route multiple lines as a group on the PCB. Coupled with hug-contour option, this utility can help designers route multiple lines on the flex portion of the rigid-flex design in minutes instead of hours with traditional one trace at a time. Hug-contour option takes care of insert-
Figure 4: Multi-line routing with contour hug option accelerates through no-click routing on flex section of the PCB designs
ogy is necessary for fanning out a BGA particularly if it has three or four rows of pins on each side. The Allegro PCB Designer through its Miniaturization Option offers a proven constraint-driven HDI design flow with a comprehensive set of design rules for all different styles of HDI designs, from a hybrid buildup/core combination to a complete buildup process like ALIVH. In addition, it includes automation for adding HDI to shorten the time to create designs that are correct-by-construction.

Figure 5: Dynamic fileting during etch editing shaves significant time from manufacturing prep phase

Analog/RF Design

The Allegro PCB Designer through its Analog/RF Design Option offers a mixedsignal design environment, from schematic to layout with back annotation, proven to increase RF design productivity up to 50%. It allows engineers to create, integrate, and update analog/ RF/ microwave circuits with digital/analog circuits in the Allegro PCB Design environment. With its rich layout capability and powerful interfaces with RF simulation tools, it allows engineers to start RF design from Allegro Design Authoring, Allegro PCB Designer, or Agilent ADS.

Embedded Components

Reducing end product size can be accomplished in many different ways. One of the approaches PCB designers are taking is to embed packaged components on inner layers. Allegro PCB Designer through its Miniaturization Option offers constraintdriven embedded component placement and routing. It supports traditional directattach as well as new indirect-attach techniques. Additionally it offers the ability to create and manage cavities on layers specified for embedding components. tens of thousands down to hundreds resulting in a significant reduction in the manual interaction required. Using the abstracted data, the planning and routing process can be accelerated by providing a visual/spatial map of the open area in relation to the data and the users design intent. The route engine can then deal with the details of the routing, adhering to the specified intent, without the user having to both visualize and solve the interconnect problems at once. This significant simplification over current design tools means users converge on a successful interconnect solution far faster and more easily than ever before, reducing design cycle time through increased efficiency and productivity. (See Figure 6.)

Concurrent Team Design

Globally dispersed design teams are on the rise, which compounds the challenge of shortening design cycle times. Manual workarounds that address multi-user issues are time-consuming, slow, and prone to error. Allegro PCB Design Partitioning technology provides a multi-user, concurrent design methodology for faster time to market and reduced layout time. Multiple designers working concurrently on a layout share access to a single database, regardless of team proximity. Designers can partition designs into multiple sections or areas for layout and editing by several design team members. Designs can be partitioned vertically (sections) with soft boundaries or horizontally (layers). As a result, each designer can see all partitioned sections and

Design Planning and Routing
Highly constrained, high-density designs dominated by bussed interconnect can take significant time to strategically plan and route. Compound this with the density issues of todays components, new signaling levels, and specific topology requirementsand its no wonder that traditional CAD tools and technologies fall short of capturing a designers specific routing intent and acting upon it. The Global Route Environment provides the technology and methodology to capture as well as adhere to a designers intent. Through the interconnect flow planning architecture and the global route engine, users can for the first time put their experience and design intent into a tool that understands what they wantnatively. Users create abstracted interconnect data (through the interconnect flow planning architecture) and can quickly converge on a solution and validate it with the global route engine. The interconnect abstraction reduces the number of elements the system has to deal withfrom potentially
Figure 6: Allegro Interconnect Flow Planner technology allows users reduce layer counts and shorten design cycle through design planning
update the design view for monitoring the status and progress of other users sections. Such partitioning can dramatically reduce over-all design cycles and accelerate the design process.
PCB Autorouter Technology
PCB routing technologies are tightly integrated with the PCB editor. Through the PCB Router interface, all design information and constraints are automatically passed from the PCB editor. Once the route is completed, all route information is automatically passed back to the PCB editor. Increased design complexity, density, and high-speed routing constraints make manual routing of PCBs difficult and time-consuming. The challenges inherent in complex interconnect routing are best addressed with powerful, automated technology. The robust, productionproven autorouter includes a batch routing mode with extensive user-defined routing strategy control as well as built-in automatic strategy capabilities.
starting from the largest to the smallest value. Test point insertion automatically adds testable vias or pads as test points. Testable vias can be probed on the front, back, or both sides of the PCB, supporting both single side and clamshell testers. Designers have the flexibility to select the test point insertion methodology that conforms to their manufacturing requirements. Test points can be fixed to avoid costly test fixture modifications. Test point constraints include test probe surfaces, via sizes, via grids, and minimum center-tocenter distance.
Cadence Services and Support
Cadence application engineers can answer your technical questions by telephone, email, or Internetthey can also provide technical assistance and custom training Cadence certified instructors teach more than 70 courses and bring their real-world experience into the classroom More than 25 Internet Learning Series (iLS) online courses allow you the flexibility of training at your own computer via the Internet Cadence Online Support gives you 24x7 online access to a knowledge base of the latest solutions, technical documentation, software downloads, and more

High-Speed Constraints-Driven Autorouting
High-speed routing constraints and algorithms handle differential pairs, net scheduling, timing, crosstalk, layer set routing, and the special geometry requirements demanded by todays high-speed circuits. The autorouting algorithms intelligently handle routing around or through vias, and automatically conform to defined length or timing criteria. Automatic net shielding is used to reduce noise on noisesensitive nets. Separate design rules may be applied to different regions of the design; for example, you can specify tight clearance rules in the connector area of a design and less stringent rules elsewhere.

For More Information

Contact Cadence sales at 1.800.746.6223 or visit www.cadence.com for additional information. To locate a Cadence sales office or channel partner in your area, visit www.cadence.com/contact_us.
DFM Rules-Driven Autorouting
The design for manufacturing capability within Allegro PCB Router significantly improves manufacturing yields. Manufacturing algorithms provide a spreading capability that automatically increases conductor clearances on a space-available basis. Automatic conductor spreading helps improve manufactuability by repositioning conductors to create extra space between conductors and pins, conductors and SMD pads, and adjacent conductor segments. Users gain the flexibility to define a range of spacing values or to use the default values. Mitered corners and test points can be added throughout the routing process. The manufacturing algorithms automatically use the optimal setback range,

Operating System Support

Allegro Platform Technology:
Sun Solaris Linux IBM AIX Windows

OrCAD Technology:

Windows
Allegro PCB Designer Base Plus Options Features
Feature Allegro PCB Designer Design Planning Option Design Planning Option Design Planning Option PCB High-Speed Option PCB High-Speed Option PCB High-Speed Option PCB High-Speed Option PCB High-Speed Option PCB High-Speed Option PCB High-Speed Option Miniaturization Option Miniaturization Option Miniaturization Option Miniaturization Option Miniaturization Option Miniaturization Option Miniaturization Option Miniaturization Option Miniaturization Option PCB Team Design Option PCB Team Design Option PCB Team Design Option PCB Team Design Option PCB Analog / RF Option PCB Analog / RF Option PCB Analog / RF Option PCB Analog / RF Option PCB Analog / RF Option PCB Analog / RF Option
Allegro Design Authoring Allegro Design Entry CIS Constraint-Manager: Physical, spacing and samenet rules Constraint Manager: Properties and DRCs Constraint Manager: Differential pair rules Constraint Manager: Region rules Floorplanning, placement, placement replication DFA, DFF, DFT Dynamic feedback on DFA compliance during placement IDF3.0, DXF in/out EDMD schema-based ECAD-MCAD co-design Native 3D viewer Hierarchical interconnect flow planning Length-based rules for high-speed signals Constraint-driven flow for length-based high-speed signals Match groups, layer sets, extended nets T-point rules (pin to T-point) 6-layer automatic shape-based autorouter High-speed rules-based autorouting Layer-specific rules-based autorouting Design planning - plan spatial feasibility analysis and feedback Design planning - generate topological plan Design planning - Convert Topological plan to traces (CLINES) Constraint Manager: Electrical rule set (relection, timing, crosstalk) Constraint-driven flow using electrical rules Electrical constraint rule set (ECSets) / topology apply Formula and relationship based (advanced) constraints Backdrilling Die2Die pin delay, dynamic phase control, Z-axis delay Return path management for critical signals Constraint Manager: HDI rule set Micro-via and associated spacing, stacking, and via-in-pad rules Constraint-driven HDI design flow Manufacturing rule support for embedding components Embedd components on inner layers HDI micro-via stack editing Dynamic shape-based filleting, line fattening, and trace filleting Hug contour routing (Flex) Support for cavities on inner layers Concurrent team design - layer by layer partitioning Concurrent team design - functional block partitioning Concurrent team design - team design dashboard Concurrent team design - soft nets Parameterized RF etch elements editing Asymmetrical clearances Bi-directional interface with Agilent ADS Import Agilent ADS schematics into DE-HDL Layout-driven RF design creation Flexible Shape Editor

Feature

Allegro PCB Designer PCB Routing Option PCB Routing Option PCB Routing Option PCB Routing Option PCB Routing Option
256-layer Autorouting DFM rules-based autorouting Automatic trace spreadiing ATP generation Layer-specific rules-based autorouting
Cadence is transforming the global electronics industry through a vision called EDA360. With an application-driven approach to design, our software, hardware, IP, and services help customers realize silicon, SoCs, and complete systems efficiently and profitably. www.cadence.com
2011 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and Allegro are registered trademarks of Cadence Design Systems, Inc., All rights reserved. 22173 05/11 MP/MV/DM/PDF