Cade nce Or C A D F P G A Syste m P la n ner

DATASHEET DATASHEET

Cadence FPGA System Planner technologies are available in the following product offerings: Cadence Allegro FPGA System Planner L, XL, and GXL Cadence Allegro FPGA System Planner Two FPGA Option L Cadence OrCAD FPGA System Planner
The Cadence OrCAD FPGA System Planner addresses the challenges that engineers encounter when designing largepin-count FPGAs on the PCB boardwhich includes creating the initial pin assignment, integrating with the schematic, and ensuring that the device is routable on the board. It delivers a complete, scalable technology for FPGA-PCB co-design that automates creation of optimum device-rules-accurate pin assignment. By replacing manual, error-prone processes with automatic pin assignment synthesis, this unique placementaware solution eliminates unnecessary physical design iterations while shortening the time required to create optimum pin assignment.

Differential User IO

Congurable

Clock Capable

Figure 1: Color-coded map of the I/Os of a multi-bank FPGA with different types of configurable pins
Designing large-pincount FPGAs on PCBs
Integrating todays FPGAswith their many different types of assignment rules and user-configurable pinson PCBs is time consuming and extends design cycles. Often the pin assignment for these FPGAs is done manually at a pin-by-pin level in an environment that is unaware of the placement of critical PCB components that are connected to FPGAs. Without BENEFITS understanding the impact to PCB routing, FPGA-based design projects are forced to Scalable, cost-effective FPGA-PCB choose between two poor options: live co-design solution from OrCAD to with suboptimal pin assignment, which Allegro GXL can increase the number of layers on a PCB Shortens time for optimum initial pin design; or deal with several unnecessary assignment, accelerating PCB design iterations at the tail end of the design cycle. schedules Even with several iterations, this manual and error-prone approach can result in Accelerates integration of FPGAs with unnecessary PCB design re-spins. OrCAD PCB design creation environments With the added time required to generate Eliminates unnecessary, frustrating pin assignments for FPGAs using manual design iterations during the PCB layout approaches, users are unable to do tradeprocess offs between the different FPGA devices available and the cost of devices used Eliminates unnecessary physical in an FPGA sub-system. This is because prototype iterations due to FPGA pin performing the trade-offs would mean assignment errors that users would have to do two projects in parallel with no design reuse of any kind between the two. The Cadence OrCAD FPGA System Planner provides a complete, scalable solution for FPGA-PCB co-design that allows users to create an optimum correct-byconstruction pin assignment. FPGA pin assignment is synthesized automatically based on user-specified, interface-based connectivity (design intent), as well as FPGA pin assignment rules (FPGA-rules), and actual placement of FPGAs on PCB (relative placement). With automatic pin assignment synthesis, users avoid manual error-prone processes while shortening the time to create initial pin assignment that accounts for FPGA placement on the PCB (placement-aware pin assignment synthesis). This unique placement-aware pin assignment approach eliminates unnecessary physical design iterations that are inherent in manual approaches.

The OrCAD FPGA System Planner is integrated with both OrCAD Capture and OrCAD PCB Editor. It reads and creates Capture schematics and symbols. In addition, a floorplan view uses existing footprint libraries from OrCAD PCB Editor. Should placement change during layout, pin optimization using FPGA System Planner can be accessed directly from OrCAD PCB Editor.
Reduces PCB layer count through placement aware pin assignment and optimization

FEATURES

OrCAD FPGA SYSTEM PLANNER TECHNOLOGY
An FPGA system is defined as a subset of the PCB design that includes one or more FPGA and non-FPGA components that are connected to FPGAs. Traditional approaches to pin assignment are typically manual and often based on a spreadsheet. Tools such as these require users to do pin assignment without taking into consideration the placement of other components and routability of the interfaces and signals. Above all, there is no online rules-checking to ensure that the right pin types are being used for the signals that are assigned to the FPGA pins. As a result, users have to make several iterations between the spreadsheet-based tools and the tools from FPGA vendors. Often this adds an increased number of iterations between the PCB layout designer who cannot route the signals from FPGA pins on available layers and the FPGA designer who has to accept paper-based or verbal
Figure 2: Placement/Floorplan view of the OrCAD FPGA System Planner provides users relative placement of critical components for optimum pin assignment synthesis

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C ade nce OrCAD FPGA Sy ste m Pla nn er

FPGA Vendor Tools

OrCAD FPGA System Planner

OrCAD Capture/CIS

OrCAD PCB Designer
module or between two FPGAs. The OrCAD FPGA System Planner understands differential signals, and power signals, as well as clock signals.

FPGA DEVICE RULES

The OrCAD FPGA System Planner comes with a library of device-accurate FPGA models that incorporate pin assignment rules and electrical rules specified by FPGA device vendors. These FPGA models are used by the synthesis engine to ensure that the vendor-defined electrical usage rules of the FPGAs are strictly adhered to. These rules dictate such things as clock and clock region selection, bank allocation, SSO budgeting, buffer driver utilization, I/O standard voltage reference levels,etc. During synthesis, the OrCAD FPGA System Planner automatically checks hundreds of combinations of these rules to ensure that the FPGA pins are optimally and accurately utilized.

OrCAD Part Library Symbols, Footprints
Figure 3: The OrCAD FPGA System Planner uses symbols and footprints from existing libraries
pin-assignment suggestions from the PCB layout designer. Once a change is made to the pin assignment by the FPGA designer, the pin assignment change has to be made in the schematic design by the hardware designer. Such iterations add several days if not weeks to the design cycle and possibly a great deal of frustration for the team members. Since this is a manual process, mistakes that are not detected can also cause expensive physical prototype iterations. While it may help to automate the synchronization of changes made to the pin assignment by the FPGA designer, hardware designer, or PCB layout designer, it doesnt reduce the root cause of these iterations. Pin assignment that is not guided by all three aspectsFPGA resource availability, FPGA vendor pin assignment rules, and routability of FPGA pins on a PCBrequires many iterations at the tail end of the design process, thereby extending the time it takes to integrate todays complex, large-pin-count FPGAs on a PCB.
The OrCAD FPGA System Planner allows users to specify connectivity between components within the FPGA sub-system at a higher level through interface definitions. Users can create interfaces such as DDR2, DDR3, and PCI Express, and use these to specify connectivity between an FPGA and a memory DIMM

SPECIFYING DESIGN INTENT

The OrCAD FPGA System Planner comes with an FPGA device library to help with selection of devices to be placed. It uses OrCAD PCB Editor footprints for the floorplan view and allows users to quickly create relative placement of the FPGA system components.
Figure 4: OrCAD FPGA System Planner optimization
PLACEMENT AWARE PIN ASSIGNMENT SYNTHESIS
The OrCAD FPGA System Planner provides users a way to create an FPGA system placement view using OrCAD PCB footprints. Users specify connectivity between components in the placement view and the FPGA at a high level using interfaces such as DDRx, PCI Express, SATA, Front Side Bus, etc. that connect FPGAs and other components in the design, shortening the time to specify design intent for the FPGA system. Once the connectivity of the FPGA to other components in the sub-system is defined, the OrCAD FPGA System Planner then synthesizes the pin assignment based on the users design intent, available FPGA resources, component placement around the FPGA, and the FPGA vendors pin assignment rules. The OrCAD FPGA System Planner has a built-in DRC engine that incorporates the rules provided by FPGA vendors for pin assignment, reference voltages, and terminations. This rules-based engine prevents PCB physical prototype iterations as the FPGAs are always correctly connected.

Pin assignment algorithms are optimized to assign interface signals to a group of pins, thereby minimizing net crossovers and improving routability on the PCB.
OrCAD FPGA System Planner so that the complete set of pin assignments remain in sync.
TIGHT INTEGRATION WITH CADENCE DESIGN CREATION
The OrCAD FPGA System Planner generates OrCAD Capture, schematics for the FPGA sub-system. It uses existing symbols for FPGA in OrCAD Capture symbol libraries. If the user desires, the FPGA System Planner products can create split symbols for FPGA based on the connectivity or one split symbol per bank.
PRE-ROUTE PIN ASSIGNMENT OPTIMIZATION
The initial pin assignmentthat accounts for placement and routability of the FPGA on a PCBgoes a long way toward reducing costly design iterations between FPGA designer, PCB layout designer, and hardware designer. Once the PCB layout designer starts to plan the routing of interfaces and signals on FPGA, it is possible to further refine the FPGA pin assignment based on route intent, layer constraints, and fanout chosen for the FPGA. The OrCAD FPGA System Planner offers users a way to optimize FPGA pin assignment after placement and during routing of the interfaces and signals on an FPGA.
INTEGRATION WITH FPGA VENDOR TOOLS
In addition to integration with OrCAD PCB design tools, the OrCAD FPGA System Planner communicates seamlessly with FPGA design tools. It generates and reads supported FPGA vendors pin assignment constraint files. This capability enables the FPGA designer to evaluate pin assignments against the functional needs of the FPGA. Any changes made by the FPGA designer to account for these requirements can be imported into to the
OrCAD FPGA System Planner Concurrent device optimization Placement-aware synthesis Reuse symbols and footprints Symbols & schematic generation Post-placement optimization Schematic power connections Schematic terminations 1 FPGA Yes Yes OrCAD Capture No No No
Allegro FPGA System Planner L 1 FPGA Yes Yes

Allegro FPGA System Planner Two FPGA Option 2 FPGAs Yes Yes
Allegro FPGA System Planner XL 4 FPGAs Yes Yes
Allegro FPGA System Planner GXL Unlimited FPGAs Yes Yes
Allegro Design Entry Allegro Design Entry Allegro Design Entry Allegro Design Entry CIS / Allegro Design CIS / Allegro Design CIS / Allegro Design CIS / Allegro Design Entry HDL Entry HDL Entry HDL Entry HDL Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Scalability

The OrCAD and Allegro FPGA System Planner technology is available in the following product offerings: Allegro FPGA System Planner GXLfor synthesizing and optimizing pin assignment of more than four FPGAs at a time. Suitable for companies that use FPGAs to prototype ASICs Allegro FPGA System Planner XLfor concurrent pin assignment, synthesis, and post-placement optimization of up to four FPGAs at a time Allegro FPGA System Planner Lfor pin assignment synthesis and post-placement optimization of a single FPGA OrCAD FPGA System Plannerfor optimum initial pin assignment synthesis of a single FPGA.
SALES, TECHNICAL SUPPORT, AND TRAINING
The OrCAD product line is owned by Cadence Design Systems, Inc., and supported by a worldwide network of Cadence Channel Partners (VARs). For sales, technical support, or training, contact your local Cadence Channel Partner. For a complete list of authorized Cadence Channel Partners, visit www.cadence.com/Alliances/channel_ partner.
2009 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Allegro, OrCAD, SourceLink, and Verilog are registered trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 20990 06/09 KM/DM/PDF

CADENCE OrCAD CAPTURE

PCB SCHEMATIC ENTRY

DATASHEET

Cadence OrCAD PCB schematic entry technology is available in the following products: Cadence OrCAD Capture Cadence OrCAD Capture CIS Cadence OrCAD PCB Designer Basics Cadence OrCAD PCB Designer Cadence OrCAD PCB Designer with PSpice Cadence OrCAD EE Designer Cadence OrCAD EE Designer Plus
Cadence OrCAD Capture includes numerous features that facilitate PCB schematic entry. An industry standard in PCB schematic entry, it is one of the most popular systems because of its intuitive use model and out-of-the-box capabilities. With OrCAD Capture CIS, component information can be accessed from both online and centralized part databasesexpediting circuit creation.
Whether used for designing a new analog circuit, revising digital schematic diagrams for an existing PCB, or implementing hierarchical block design, OrCAD Capture delivers everything needed to take circuit design from concept to production. Seamless interfaces establish robust data paths plus integration with OrCAD PCB Editor for physical PCB design and with Cadence PSpice A/D for analog/circuit simulation. OrCAD Capture CIS integrates the OrCAD Capture schematic design application with the added capabilities of a Component Information System (CIS), allowing easy access to component databases and part information.

BENEFITS

Offers full-featured schematic editing for fast, intuitive design capture Boosts efficiency in schematic editing of complex designs through hierarchical and variant design capabilities Accelerates the design process and lowers project costs through integration with a robust CIS that promotes preferred current parts
Figure 1: OrCAD Capture and OrCAD Capture CIS provide powerful capabilities to enter, modify, and verify schematic circuits including part management, flat and hierarchal design, and circuit reuse
colorization of wires/nets/parts, and a tabbed/dockable interface all provide a better user experience.

DESIGN REUSE

The re-use of existing logical circuits that have already been tested and proven is one of the best ways to reduce cycle time and maximize quality. Having already been placed, routed, and validated on a previous design, the effort that went into the original design can be preserved. Typical examples include power supply modules, RF circuit designs, multichannel circuits (I/O, drivers, etc.), and memory.

DESIGN RULE CHECK

Figure 2: Tight product integration provides cross-probing and accurate data passing between OrCAD Capture and OrCAD PCB Editor
Reduces time spent researching parts and enables intelligent component selection with access to MRP, ERP, and PLM data Provides access to more than two million parts with Cadence ActiveParts, for greater flexibility when choosing design components
and publishing design data. The autowire capability, for example, automates the often tedious and time-consuming task of wiring signal pins. Wiring between component pins is as simple as selecting a starting pin and a destination pin and letting the software automatically and quickly add the connection. Contextsensitive menus, OLE support, custom
The configurable design rule check (DRC) feature in OrCAD Capture allows comprehensive verification of the design before committing to downstream design processes saving the time and cost of ECOs later in the design cycle. Design rules checks include reports of duplicate parts, invalid design packaging, and electrical violations.

FEATURES

SCHEMATIC EDITOR
The flat and hierarchical schematic page editor of OrCAD Capture builds on the OrCAD legacy of fast and easy schematic editing. It combines an intuitive interface with the features and functionality needed to speed design tasks and facilitate circuit creation. For larger, more complex designs, OrCAD Capture supports multi-sheet and hierarchical designs. It also makes hierarchical designs easy to traverse and ensures that all connections are maintained accurately throughout the design.

EASE OF USE

The schematic page editor combines an intuitive user interface with functionality and features that enhance usability and speed for accomplishing design tasks
Figure 3: Constraint worksheets provide a spreadsheet interface that enables users to define, manage, and validate design rules

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CADENCE OrCAD CAPTURE PCB SCHEMATIC ENTRY
COMPONENT INFORMATION SYSTEM
The Component Information System (CIS) is a central part of the OrCAD Capture design solution. It automatically synchronizes and validates the externally sourced data with the schematic design database. CIS works with any database that complies with Microsofts ODBC standard to directly access data in an MRP, ERP, or PLM system, or in an intermediate database dedicated to engineering component data.
through ICAcontains more than two million parts. With ActiveParts, users can search for and select parts based on specific criteria, and preview parts before placing them in a schematic.

DESIGN VARIANTS

With the design variants capability, designers can manage unlimited board assembly variations without having to maintain duplicate schematics or manually edit BOMs. This reduces the number of files by maintaining all design assembly variations within a single design. Substituted and/or unplaced components within each assembly are displayed through graphical indicators. Schematic variants with BOMs can be generated at any point in the design process.
tailor symbol creation to the design needs. FPGA components can also be exported using the export FPGA dialog box. The export FPGA completes the bi-directional link between FPGA designers and PCB designers.

CO-DESIGN

OrCAD FPGA System Planner provides a complete, scalable solution for FPGAPCB co-design that allows users to create an optimum correct-by-construction pin assignment. FPGA pin assignment is synthesized automatically based on user-specified, interface-based connectivity (design intent), as well as FPGA pin assignment rules (FPGA rules), and actual placement of FPGAs on PCB (relative placement). With automatic pin assignment synthesis, users avoid manual error-prone processes while shortening the time to create initial pin assignment that accounts for FPGA placement on the PCB (placement-aware pin assignment synthesis). This unique placement-aware pin assignment approach eliminates unnecessary physical design iterations that are inherent in manual approaches. OrCAD FPGA System Planner is integrated with both OrCAD Capture and OrCAD PCB Editor. It reads and creates OrCAD Capture schematics and symbols. In addition, a floorplan view uses existing footprint libraries from OrCAD PCB Editor. Should placement change during layout, pin optimization using FPGA System Planner can be accessed directly from OrCAD PCB Editor.

RELATIONAL DATA SUPPORT

CIS allows for the creation and use of relational tables in the component parts database. These relational tables have a one-to-many relationship with the part information (primary) tables. The relational database may contain a vendor table with multiple vendor/manufacture part numbers for a single company part number in the electrical (e.g. resistor) table. With this structure, search and query for data across the primary and relational tables is possible.
OrCAD Capture, together with OrCAD FPGA System Planner, addresses the challenges that engineers encounter when designing large pin-count FPGAs on the PCB boardwhich includes creating the initial pin assignment, integrating with the schematic, and ensuring that the device is routable on the board. They deliver a complete, scalable technology for FPGA-PCB design-in and co-design that automates creation of optimum devicerules-accurate pin assignment, symbol creation, and flow. By replacing manual, error-prone processes with automatic pin assignment synthesis, this unique placement-aware solution eliminates unnecessary physical design iterations while shortening the time required to create optimum pin assignment.

PART SELECTION

With easy access to component databases and part information, designers can reduce the amount of time spent researching parts. CIS allows users to identify, utilize, and design with preferred components. Parts can be queried based on their electrical, physical, or corporate characteristics, then be automatically retrieved for use in the schematic. Adding components directly from company databases minimizes errors in bills of materials (BOMs) and parts lists, and allows control of part usage for industry directives such as RoHS and WEEE.

DESIGN-IN

OrCAD Capture supports the FPGA design flow with the ability to quickly import and/or create FPGA symbols and components. With an ever-increasing pin count and complexity for FPGA parts, the easy to use GUI-based options of OrCAD Capture can be used to create single and multi-section FPGA parts based on the device I/O pin files. Support for split parts, power pin visibility, pin shape, and pin group management provide flexibility to
ORCAD PCB FLOW INTEGRATION
Seamless bi-directional integration with OrCAD PCB Editor enables synchronization and cross-probing/ placing between the schematic and the board. Automated engineering change orders (ECOs) backannotate layout changes, gate/pin swaps, and changes to component names or values. OrCAD Capture CIS comes with a library of schematic symbols and associated VHDL models, as well as the EDIF schematic and other CAD vendor netlist interfaces.

INTERNET COMPONENT ASSISTANT
CIS also features the Internet Component Assistant (ICA) for accessing component information in online databases. As with corporate database access, online parts can be queried based on electrical, physical, or manufacturing characteristics, and be automatically retrieved for the schematic. The free Cadence ActiveParts online electronic databaseaccessible
SALES, TECHNICAL SUPPORT, AND TRAINING
The OrCAD product line is owned by Cadence Design Systems, Inc., and supported by a worldwide network of Cadence Channel Partners (VARs). For sales, technical support, or training, contact your local Cadence Channel Partner (VAR). For a complete list of authorized Cadence Channel Partners (VARs), visit www.cadence.com/Alliances/ channel_partner.
2010 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, OrCAD, and PSpice are registered trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 21417 04/10 MK/DM/PDF