Technical PAPER

Encounter Conformal ECODesigner
Revolutionizing the Art of ECOs

Overview

Engineering change order (ECO) is a common term in the semiconductor industry. It has a wide variety of connotationsfrom adding or removing logic to more subtle changes such as cleaning up routing for signal integrity. An ECO can come at any point in the design cycle, with the goal being to deliver the product to market as quickly as possible with minimal risk to correctness and schedule. Whenever it occursand whether it represents a simple design fix or spinning a derivative productan ECO is widely recognized by engineering and management as a time ofhighstress, long work hours, and uncertainty.

Micro Architecture

Golden RTL

Accelerate

RTL-to-GDS

Product

Figure 1: ECO challenge
Todays ECO flows are manual and labor-intensive, and remove only some of the uncertainty regarding whether the product will function properly. Since designers typically dont know if a change made in the logical netlist can be executed in the physical netlist, completing the ECO process typically requires many cycles. However, if designers are provided with early knowledge of the feasibility of implementation, an ECO can be achieved with only metal layer changes, enabling the design team to dramatically reduce cost by changing plans and targeting workable solutions. The manual process imposes another significant restriction. Keeping track of used spare cells and freed cells with accuracy becomes increasingly difficult when performing changes on several different levels, which makes some ECOs too complex to handle manually.

Old RTL R1

Synthesis

Test Insertion

P&R
P&R Which logic cones are affected? New RTL R2 EC Old Netlist G1 Old DEF Incremental optimizations and P&R Assign unplaced cells
Difcult to identify where to x

Manual Editing

Physical Feasability

Final Netlist (New DEF)

New Netlist G2
Figure 2: Manual ECO flow

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The flow outlined in Figure 2 represents a typical manual flow. It starts by comparing the old netlist to the modified RTL using an equivalency checker. By looking at the differences, the designer can locate the changes necessary in the netlist. After manual editing and rechecking, the netlist is ready for physical implementation. Typically, there are many imeconsuming cycles in this loop (which can t be tedious when coupled with the task of keeping track of freed gates and used spare cells). Next, the place and route tool assesses the differences ofthe modified logical netlist and the physical def file to correct the physical implementation. Finally, the new netlist needs to be compared to the modified RTL. This is not always possible using someequivalency checking tools, which rely on information passed from the synthesis tool. With mask costs running into the millions of dollars, an ECO can mean the life or death of a projector even a company. Knowing that an ECO can be implemented with the gates on the mask and then processed with a limited number of metal layers enables a design team to move with confidence and efficiency. By adding more flexibility, chips can be processed through the base levels and several metal layers, and then finished with new ECO metal layers, thereby saving cost and ensuring that time-to-market goals are met.

Application

Pre-Mask and Post-Mask
When the ECO is applied, it is important to consider if the state of the design is pre-mask or post-mask. Pre-mask ECOs are performed during place and route and before the design is taped out. Pre-mask ECOs can be broken down into two categories: functional and non-functional. Functional ECOs deal with making logical changes to the design, while non-functional ECOs handle changes that affect timing and signal integrity, such as design rule verification (DRV) or routing. Atthis point, there is no mask to limit resources utilized, nor is it necessary to keep track of freed cells or utilized spare gates. Post-mask ECOs are performed after the design has been sent to manufacturing. Once fabrication has begun, the number of gates on the die is fixed and any changes will need to be accomplished with these resources. Ideally, a post-mask ECO will be achievable with simple metal layer changes, thereby greatly reducing the cost of the ECO.

ECO Feasibility

Feasibility is another consideration for ECOs. Many customers want to process multiple ECOs but are uncertain if all of the ECOs can be implemented. To increase the level of certainty, designers willperform the ECOs one at a time. However, this strategy causes many projects to run out of schedule, and forces design teams to defer some changes to the next revision of the chip to meet time-to-market considerations. If engineers can determine which ECOs can be implemented, they can focus on the feasible ECOs and proceed to tapeout of the design. To determine the feasibility, Cadence Conformal ECO Designer compares each logic cone in the design, determines which cones are different, and identifies only the changes needed to complete the ECO. The changes are highlighted by the green ECO fragment in the new netlist shown in Figure 3. Only the necessary changes are made to a cone of logic. Design teams are often challenged with ECOs that may be too complex to handle manually. In a post-mask flow, the ECO changes are mapped to available gates or freed gates. If insufficient resources are available, Conformal ECO Designer will inform the user. By only making needed changes to a cone of logic the amount of change to the physical design is limited. As demonstrated in Figure 3, reducing the amount of change required by the place-and-route tools minimizes the complexity and risk of the ECO.
En c o u n ter C o n fo rma l ECO D esi g n er: Revo lu ti o n i zi n g th e Art o f ECO s
Old P&R Netlist (G1) o1 o2 o3
Encounter Conformal Equivalence Checker

o1 o2 o3

o1 ECO New P&R Netlist (G2)
Figure 3: Conformal ECO Designer process diagram

New Netlist

A Complete ECO Solution
By enhancing the integration between Conformal ECO Designer and the Cadence SoC Encounter RTL-to-GDSII system, Cadence has created a complete ECO solution (Figure 4) that spans all parts of the design flow to achieve the highest quality ECO. Conformal ECO Designer performs feasibility analysis and implements the changes to the netlist if possible. Changes are then translated into physical implementation by the SoC Encounter System.

Old Gate/DEF

New RTL w/ECO
Encounter Conformal ECO Designer

Figure 4: ECO framework

Conformal ECO Designer generates the modified logical netlist that is converted into the physical design. The conversion is handled by the SoC Encounter System, which has special features to process ECOs quickly and efficiently. The following paragraphs will highlight the capabilities of SoCEncounter.

The ECO flow, shown in Figure 5, starts with the Conformal ECO Designer. Conformal ECO Designer performs an analysis for post-mask designs to determine the feasibility of the ECO. IftheECO is not feasible, Conformal ECO Designer will indicate this to the user. The intent is todetermine differences between the original netlist and the updated netlist. This provides information regarding the changes in the design. The changes are managed and merged with theoriginal netlist to achieve the new logical netlist. The updated logical netlist is then passed tothe SoC Encounter System for processing, which maps the changes to the physical netlist.

Old RTL R2

SoC Encounter System
Old Netlist G2 Old Netlist G1 Old DEF ECO Placement & Routing

Final Netlist

Figure 5: ECO Designer detailed flow

Place and Route

SoC Encounter System handles place and route. Within the SoC Encounter System there are several choices made depending on the state of manufacturing and cost savings that is desired. The most typical choices are pre- and post-mask ECOs. In pre-mask ECOs, designers can make changes by adding and removing gates, while at the same time minimizing changes to routing and existing placements. In post-mask ECOs, the changes made are based on spare gates or freed gates in the design. With post-mask ECOs, the goal is to preserve the base layers and only re-mask the metal layers. The post-mask ECO choices also apply to gate array cells, where the changes focus on the routing layers. Notably, SoC Encounter System will re-map the ECO to meet the physical design needs. It balances the needs of timing, design rule verification (DRV), and available spare gates to automatically optimize the ECO to the physical design. SoC Encounter System also offers two sub-options for metal routing, shown in Figure 6. One is a complete mask change in which all metal layers are re-routed. The other is a limited mask change where only a few metal layers are processed, such as, for example, changing only a few metal layers (i.e., metals 1 to 3, in an 8-metal layer process). Reprocessing only a limited number of layers provides a significant cost savings over reprocessing all layers.

Add/Delete Gates

Pre-Mask

Pre or Post Mask?

Post-Mask

Spare Cell Re-Mapping

Incremental Optimization

All or Limited Metals?

ECO Route

Final Design

Figure 6: ECO routing decision tree
With SoC Encounter System, the design is physically remapped to meet the specific physical design requirements. As seen in Figure 7, a freshly imported ECO consists of spare cells, placed cells (untouched by the ECO), deleted cells (cells disconnected by the ECO), and new cells. Note, inthisdiagram the new cells have yet to be placed. The deleted cells are not actually deleted butpreserved for post-mask ECOs to be used as possible spare cells.
Spare Cell Placed Cell Deleted Cell New Cells
Figure 7: Design with ECO
When the design is physically remapped automatically, SoC Encounter System makes several decisions based on the function required, timing and DRV requirements, and the functions available in the spare cells and freed cells. For example, in Figure 8, a design requires a two-input NAND gate. The only device available to meet the design requirements is a three-input AND gate and an INVERTER. SoC Encounter System will take advantage of those devices to meet the function and
the design requirements. This is a simplified version of the devices and functions that can be utilized. This now means ECOs are no longer limited to a one-to-one mapping of cells, but to the availability of unused logic functions in the design.
Desire Function VDD Available Spare Gates

Spare Cell Mapping

Figure 8: Physical remapping
As can be seen in the Figure 9, the new cells are functionally mapped into the design utilizing both spare cells and deleted cells. These are color-coded in the diagram according to the legend on the right. During remapping, SoC Encounter System will make the minimal number of changes. This includes minimizing route changes while connecting in new cells.
Figure 9: Design with ECO physically remapped
In addition, ECO Route can be limited to specific metal layers. By limiting the layer changes, SoC Encounter System can accomplish ECOs at greatly reduced cost. In Figure 10, the routing changes will be limited to metals 1 through 3 in a 5-layer process. The disconnected cell is broken off of NetC and the new spare cell is connected in metal 3 or below. All the while, the now disconnected upper metal layers are preserved to ensure the previously generated masks for the upper layers arepreserved.

Disconnected Cell

Spare Cell

Upper Metal Layers

Figure 10: Limited layer ECO Route

Sequential ECO

Functional ECOs can be further categorized into two types: combinatorial and sequential. Combinational changes are less involved and can usually be accomplished in metal layer changes (post-mask) if enough spare gates are available on the mask. Sequential changes are more involved and require rerunning of clock tree synthesis, and may also require fixing of scan chains. The steps involved in fixing scan chains depends on whether sequential elements were removed or added, and whether scan chains were broken. In the event spare sequential elements were already in scan chains, no breakage occurs. Similarly, sequential elements can be removed from the design and still remain in the scan chains with no breakage. The difficulty arises when new sequential elements are added (with no scan connections these then require incremental stitching). This capability exists with the synthesis technology of Conformal ECO Designer. As shown in Figure 11, the user can choose to make no changes to the scan or do incremental scan mapping and stitching. Once complete, the netlist is passed through to SoC Encounter System for processing to clean up the place and route. The last step in this flow is to pass the new scan setup and netlist to the ATPG solution for regeneration of the ATPG patterns.

ECO Netlist (G3)

Incremental Scan Map and Connect

No Change

SoC Encounter
ECO Netlist w/ ReOrdered Scan

Re-Generate ATPG

Figure 11: DFT in the ECO flow

Conclusion

With the high cost of generating and producing IC designs, all steps in the process are critical. When performing ECOs, mask costs alone can exceed a million dollars. The ability to limit mask changes to a few metal layers greatly reduces risk and cost. In addition, many ECOs are too c omplex to perform manually, which can limit an organizations ability to develop features sets andnew products. Conformal ECO Designer, together with the SoC Encounter System, forms a complete Cadence ECO solutionfrom RTL to GDSII. Customers using the solution enjoy better predictability, faster process times, high-quality results, and lower costs, enabling design teams to process more ECOs to ensure products ship on time.

References

Engineering Change Order http://en.wikipedia.org/wiki/Engineering_Change_Order, October 8, 2007 Cadence Conformal LEC The Intel Experience, Itai Yarom, Michael Zuckerman, Erik Seligman and Aviad Sokolover http://www.cdnusers.org/Portals/0/cdnlive/emea2006/Encounter/11.00%203.3-2.6%20cdn06_ emea_itai_yarom_final.pdf, January 28, 2008 Cadence Virtuoso and Encounter Interoperability using OpenAccess 2.2 http://www.chiptalk.org/modules/wfsection/article.php?articleid=14, January 28, 2008
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2008 Cadence Design Systems, Inc. All rights reserved. Cadence, Conformal, and Encounter are registered trademarks and the Cadence logo and SoC Encounter are trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 20602 07/08 KM/FLD/CS/PDF

ENC O U NT E R C O N FO R M AL ECO DE S I G NE R

DATASHEET

ENCOUNTER CONFORMAL TECHNOLOGY
To shorten overall design-cycle times and minimize silicon re-spins, designers need production-proven validation. Encounter Conformal verification technologies, part of the Cadence Logic Design Team Solution, offer the most comprehensive solutions for equivalence checking, design-constraint management, functional ECO analysis and generation, and lowpower design verification.
Cadence Encounter Conformal ECO Designer enables designers to implement RTL engineering change orders (ECOs) for pre- and post-mask layout. It combines automatic ECO analysis and design netlist modification with world-class equivalence checking to provide superior performance, productivity, capacity, and easeof-use.
design fix that can happen at any time in the design cycle up to spinning a derivative product. All ECOs are focused on delivering products to market as fast as possible with minimal risk to correctness and schedule. Engineering and management recognize ECOs as a time of high stress, long work hours, and uncertainty. Even if the logic change is implemented in the netlist, there might not be enough spare gates on the mask to implement the change. A better method is needed for implementing ECOs. Available flows for processing ECOs may remove some of the uncertainty of whether the product will work, but they are still a manual process that typically requires many cycles to achieve correct implementation. And once the ECO is logically implemented in the netlist, there is no guarantee if the change can be implemented in the physical netlist. If the ECO were implemented with only metallayer changes, the cost would be greatly reduced. Having this knowledge can have great impact on team confidence and planning. With early knowledge of
implementability, a design team can change plans and target workable solutions rather than wasting time in failed attempts and extended schedules.
ENCOUNTER CONFORMAL ECO DESIGNER
Cadence has created a complete ECO solution that spans different parts of the RTL-to-GDS flow to achieve the highest quality ECOs. This solution consists of Encounter Conformal ECO Designer coupled with the SoC Encounter System. This combined solution brings automation and predictability to the ECO process. Encounter Conformal ECO Designer is a unique technology that offers functional ECO analysis and generation capability. It combines proven equivalence checking and functional checks, and uses formal techniques to analyze and implement the functional ECO. Encounter Conformal ECO Designer is available as a standalone offering and incorporates Conformal XL features.
ENGINEERING CHANGE ORDERS
Engineering change orders (ECOs) have a wide variety of implementations that range from adding or removing logic in a design to more subtle changes such as cleaning up routing for signal integrity. A logical change to a design netlist is referred to as functional ECO while all other changes are classified as nonfunctional. The ECO is essentially a local change to a design. The focus is either a
RTL Logic Synthesis (area Power, Timing, Yield) Datapath and Test Synthesis Floorplanning and Physical Synthesis ECOs Place and Route
Logic Equivalence Checking Extended Functional Checks Clock Domain Crossing Checks Semantic Checks Structural Checks Equivalence Checking Support for Complex Datapath Old Gate/DEF New RTL w/ECO

Encounter Conformal ECO Designer
Automatic ECO Analysis and Design Netlist Modification

Final Layout

Modified Gate Netlist
Figure 1: Encounter Conformal ECO Designer offers automatic ECO analysis and design netlist modification

New RTL (R2)

Old RTL (R1)
Design netlist (G3) is the hand-off point to the back-end physical implementation tool targeting a pre-mask or post-mask flow. Tool features: Supports combinational and sequential (the addition of new state elements) changes of the design Supports the addition of new ports SoC Encounter System Preserves the clock trees Preserves the scan chain Preservers the original netlist structure (G1) when it creates the new ECO netlist (G3) Recycles freed-up cells during the ECO analysis process

Synthesis

Synthesis Test Insertion P&R

New Netlist (G2)

Old Netlist (G1)

Old DEF

Incremental Optimizations P&R

Conformal ECO Designer

ECO Netlist (G3)

Final Netlist

Figure 2: The Encounter Conformal ECO Designer implementation flow

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EN C O U N TER C O N FO RMA L EC O D ESI G N ER

BENEFITS

Provides faster turnaround time by minimizing manual intervention and eliminating time-consuming iterations Generates early estimates on ECO feasibility Provides high value in the design cycle when schedule delays are highly visible Improves designer productivity and offers flexibility to do ECO with metalonly layers, thus reducing manufacturing costs Reduces verification time significantly by verifying multimillion-gate designs much faster than traditional gate-level simulation Decreases the risk of missing critical bugs through independent verification technology
stages and enables designers to identify and correct errors as soon as they are introduced. Equivalence checking also plays an important role in the ECO implementation process. It helps the ECO analysis tool identify which modules and logic cones in the design require change to implement the ECO. For instance in Figure 2, the original netlist (G1) is compared against the new netlist (G2) to determine what has changed. Equivalence checking is also used at the tail end of the process to make sure the ECO implementation was successful both for front-end and back-end signoff.
Full cross-highlighting between RTL model and circuit Automatic error candidate identification with assigned and weighted percentages Logic-cone pruning to focus debugging on relevant information

SMART SETUP AND DIAGNOSIS
Conformal ECO Designer includes a set of intelligent analyze commands to ease setup and diagnosis. analyze setup investigates the current environment and automatically remedies common setup issues sometimes experienced by new users. In tandem, analyze nonequivalent can be invoked if non-equivalences are encountered. The command then presents a one-line answer as to what is wrong.

FUNCTIONAL ECO ANALYSIS

Conformal ECO Designer has a built-in ECO analysis engine that can identify the differences between the old design netlist (G1) and the new design netlist (G2). Users can perform ECO analysis on the entire design or on specific modules within the design hierarchy, which is typically more efficient. Once the ECO analysis step is completed, Conformal ECO Designer performs the necessary netlist modifications to achieve the new function in the old netlist (G1). The output is the ECO netlist (G3).

PLATFORMS

Linux (32-bit, 64-bit) Sun Solaris (32-bit, 64-bit) IBM AIX (32-bit, 64-bit)

FEATURES

Encounter Conformal ECO Designer combines logic equivalence checking (for the most complex SoC and datapathintensive designs) with functional ECO analysis, design netlist modification, clock domain synchronization, and semantics checks.

LANGUAGE SUPPORT

Verilog (1995, 2001) SystemVerilog VHDL (87, 93) SPICE (traditional, LVS) EDIF Liberty Mixed languages

INTEGRATED ENVIRONMENT

An intuitive graphical user interface (GUI) is provided for setup and debugging, allowing the user to work more productively and quickly pinpoint the cause of equivalence mismatches. Included are: Graphical debugging via an integrated schematic viewer that shows logic values for each error vector
EQUIVALENCE CHECKING FOR ECO
During development, a design undergoes numerous iterations prior to final layout, and each step in this process has the potential to introduce logical bugs. Conformal ECO Designer checks the functional equivalence of different versions of a design at these various
For more information, log on to www.cadence.com
2008 Cadence Design Systems, Inc. All rights reserved. Cadence, Conformal, Encounter, and Verilog are registered trademarks and the Cadence logo and SoC Encounter are trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. 20474 02/08 MK/MVC/JA/PDF