ENC O U N T E R T I M I N G S Y S T E M
Figure 1: Encounter digital IC design platform

DATASHEET

ENCOUNTER TIMING SYSTEM
Industry-endorsed and production-proven, Encounter Timing System is a full-chip signoff STA solution consisting of gatelevel timing, signal integrity, power, thermal, and statistical analyses. It serves both front-end designers looking for the highest quality timing analysis and ease of use, as well as back-end designers looking for a complete, silicon-accurate signoff solution. The underlying technologies for both timing and signal integrity (SI) analysis and optimization have been in production use for nearly a decade. With Encounter Timing System, designers benefit from the utmost in signoff timing accuracy, usability, and functionality for mainstream and innovative digital designs.
Designers need a comprehensive timing solution that ensures accuracy while supporting both front-end analysis and backend signoff. Cadence Encounter Timing System, a key technology of the Encounter digital IC design platform, enables designers to analyze and debug multimillion-gate designs with significant gains in productivity. With Encounter Timing System, designers benefit from a consistent, integrated static timing analysis (STA) environment for optimization and signoff, leading to faster convergence and design closure.

ENCOUNTER

ING TIM

YIEL D

RTL Synthesis Silicon Virtual Prototyping Global Physical Synthesis Nanometer Routing
Constraint Management & Equivalence Checking

Manufacturing

STA Test & Diagnostics Power & SI Analysis

BENEFITS

Delivers consistent, integrated STA and statistical static timing analysis (SSTA) for optimization and signoff Enables faster design convergence and accelerates timing closure Eliminates the need for multiple products by integrating timing, SI, power, thermal, and SSTA analyses Boosts productivity and shaves weeks off tapeout schedules Global timing debug speeds up root-cause and bottleneck analysis Advanced analysis algorithms reduce false SI failures by 10x Higher performance with multiprocessing Performs concurrent multi-mode/ multi-corner analysis with distributed processing Enables virtual flat SI analysis with distributed processing Enables advanced nanometer design through effective current source models (ECSMs) Delivers accurate delay calculation to within 2% of SPICE Offers built-in critical path simulation for delay/SI correlation with SPICE
Supported by major foundries, ASIC and IP vendors, and integrated device manufacturers
Capability to check for missing or inconsistent library and design data

FEATURES

ENCOUNTER TIMING SYSTEM L
Encounter Timing System L provides a comprehensive signoff verification solution that combines STA, accurate delay calculation, advanced modeling, and global timing debug. It helps designers achieve first-pass silicon success and fast time to market on their multimillion-gate designs. Encounter Timing System L provides incremental and what-if analysis, reducing runtimes for minor design changes and thus improving productivity.
Consistent, Integrated STA for Optimization and Signoff
Designers have traditionally relied on one STA method for implementation and another STA method for signoff analysis. This leads to corrective iterations with the place-and-route system when discrepancies are found during signoff analysis. Encounter Timing System is a consistent, integrated STA environment for optimization during the place-androute stage and for signoff verification. This gives designers the flexibility to use Encounter Timing System as a standalone solution or as part of the integrated Cadence SoC Encounter RTL-to-GDSII system.

Powerful GUI

Command console with command completion, history, and context highlighting Timing constraint viewer to find specific timing constraints based on design object name or constraint group type Schematic and layout viewers with the ability to cross-probe from the timing report Script editor to evaluate scripts with ability to crosslink and expand Tcl procedures

Global Timing Debug

Global timing debug allows designers to pinpoint the root cause of timing and constraint problems quickly. Users can view the slack histogram and generate detailed timing views with individual cell/wire delays, slack details, hierarchy allocations, and constraint cross-probing. It employs unique path visualization capabilities to determine a paths cause of failure. Paths that share a common failure mode can then be categorized dynamically while the debugging of uncategorized paths can continue. Path categories can be visualized in the global timing context to determine which categories can be fixed in parallel or which ones should be fixed first. This reduces iterations to timing closure by intelligent debugging more than just the worst path.
ECSM*.lib SPEF/SDF SDC Verilog cdB* DEF* CPF*
Location-Based On-Chip Variation (LOCV)
In nanometer geometries, designers must address on-chip variation (OCV) effects, including removal of pessimism caused by common paths. However, traditional OCV analysis is inaccurate and pessimistic since it employs a constant de-rating factor. Encounter Timing System employs location-based on-chip variation (LOCV), which uses logic level and physical

Encounter Timing System

Timing and power reports

*Optional

Figure 2: Encounter Timing System data flow and user interface

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Accurate Crosstalk Analysis and Faster SI Closure
Encounter Timing System XL calculates the impact of crosstalk using a combination of cell- and transistor-level models. For noisy nets that exhibit the most nonlinear behavior, Encounter Timing System XL uses an on-the-fly SPICE simulation engine to calculate noise-on-delay effects accurately. It also deploys the unique path-based alignment (PBA) technique to ensure realistic SI delay effects on critical timing paths. Without PBA, SI delay calculation can create an unrealistic or overly pessimistic worst-case path delay. Further removal of path delay pessimism is achieved through noise path pessimism removal (NPPR), which finds the maximum noise delay change for the overall critical path instead of for each individual net on that path. Encounter Timing System XL also guarantees functional validity by performing glitch noise propagation to register endpoints and by ensuring that the register is not driven unstable. These unique PBA, NPPR, and glitch noise propagation capabilities greatly reduce the number of false crosstalk problems. This translates into much less work for placeand-route systems and a dramatically reduced number of SI closure iterations.

Figure 3: Global timing debug
location to select the optimal de-rating factor. LOCV eliminates the excessive guardbanding associated with traditional de-rating and improves timing closure.
Interface to Encounter Conformal Constraint Designer
A seamless interface between Encounter Timing System and Encounter Conformal Constraint Designer enables advanced constraint checking and critical false path analysis. Constraint checking eliminates bad constraints that cause iterations, longer design time, and silicon failure. Critical false path analysis greatly reduces the need to manually remove false paths from the critical paths. Removal of these false paths eliminates unnecessary netlist optimizations and can improve design area and timing.
builds on the strengths of the customertrusted, tapeout-proven Cadence CeltIC NDC (nanometer delay calculator) engine. It also employs the more accurate current source model libraries (ECSM, cdB) to analyze the complex effects of crosstalk delay, noise (glitch), timing, and IR drop.
Advanced Nanometer Electrical Analysis
Implementing multimillion-instance nanometer designs requires very efficient yet highly precise delay calculation. Designers must also consider SI effects such as IR drop and crosstalk, and advanced low-power design techniques that use multiple voltage levels and level shifters. Delay calculation based on table lookup or polynomial models are not accurate enough for todays nanometer circuits. Encounter Timing System XL supports the effective current source Fig 1: Rising complexity SYSTEM ENCOUNTER TIMING drives an XL exponential growth in the verification challenge (ECSM), which enables accurate model In addition to all the features of Encounter prediction of actual silicon performance, Timing System L, Encounter Timing particularly for complex nets, long RC System XL offers accurate SI and IR drop networks, and multiple driver scenarios analysis and its impact on both timing and (clock meshes). functionality. Encounter Timing System XL

Unified Power Analysis

Power management is a key concern and major design challenge with todays increasingly complex chips. Encounter Timing System XL provides a comprehensive static and dynamic solution for cell-level power analysis by combining timing and power analysis into a single environment. This integrated environment enables faster results and improves designer productivity. Encounter Timing System XL provides power analysis

Reported SI glitch violations

2000 0

120K inst 860K inst 534K inst 838K inst 829K inst
No propagation ETS XL propagation

18 2970

5 3081

17 5175

Figure 4: SI pessimism reduction and critical path simulation
by employing both vectored and vectorless approaches. Vectorless analysis allows accurate power analysis to be done early in the design flow, while vectors are used to achieve the highest accuracy.

Low-PowerDriven Signoff

In smaller geometries, power supplies are typically around one volt, and even small voltage drops can compromise signal timing and lead to chip failures. IR drop further increases the risk of crosstalk failure. Encounter Timing System XL accurately models the non-linear IR drop impact and eliminates the inaccuracies of the traditional linear K-factor approach. Encounter Timing System XL incorporates instance-based IR drop data from Cadence VoltageStorm power integrity analysis to account for the effects of static and dynamic IR drop on path delays and SI. Advanced low-power techniques such as multi-supply/multi-voltage (MSMV) and dynamic voltage and frequency scaling (DVFS) can introduce errors and complicate the traditional timing signoff flow. Encounter Timing System XL
enables a simple flow where designers can characterize just three libraries at three voltage points, which are sufficient to perform accurate non-linear delay calculation across a much wider range of voltage points. Encounter Timing System XL also supports the Common Power Format (CPF), which describes the power intent throughout the design flow from system specification to tapeout.
to a larger variation as a percentage of the process geometries. As a result, designs that pass traditional signoff standards might still fail in silicon due to process variations. Encounter Timing System GXL helps prevent these catastrophic silicon failures.
Statistical Static Timing Analysis
Traditional STA accounts for process variations by introducing more aggressive gross guardband and using multiple analysis corners to model different process and environmental variation combinations. This corner-based approach can be overly pessimistic since it reports timing scenarios that have an extremely small likelihood of occurring. Also, the exponential growth in the number of corner combinations with the increasing number of parameters makes analysis on every corner impractical. Encounter Timing System GXL supplements traditional corner-based methods with powerful and accurate SSTA that can account for the variability of process parameters in a single run. It uses advanced statistical ECSM models to identify cells and nets on both clock and data paths that are sensitive to variations, and also determines the probability of timing failure over the full range of process variation. This reduces pessimism and allows for reduced Guardbanding, resulting in decreased area and power consumption while improving chip performance. It lets designers explore potential tradeoffs between parametric yield and clock speed.

Critical Path Simulation

Encounter Timing System XL enables on-the-fly path simulation of critical paths and offers a graphical view of the impact of crosstalk and IR drop along the path, including the propagation of non-linear waveform effects. This enables easy validation of timing, SI, and IR-drop effects, and verification of fixes, prior to implementation.

Multi-Processing

Encounter Timing System XL supports multi-processing for concurrent multimode/multi-corner timing analysis and virtual flat SI analysis. By distributing different parts of a task between two or more processing units, multi-processing allows Encounter Timing System XL to significantly improve turnaround time and to handle larger, more complex designs.
ECSM* cdB* SPEF/SDF S-SPEF.lib SDC Verilog DEF* CPF* SPDF S-ECSM
ENCOUNTER TIMING SYSTEM GXL
In addition to the features of Encounter Timing Systems L and XL, Encounter Timing System GXL offers statistical static timing analysis (SSTA) to enable maximum design performance with minimum power consumption at advanced process nodes. It helps reduce the design cycle with fewer timing runs and enables designers to tape out with confidence in achieving their timing goals.
Features of Encounter Timing System SSTA include:
Within-the-die, die-to-die, and random variation support Block-based and path-based modes Standardized statistical ECSM library models and characterization support Consistency and integration with SoC Encounter implementation system to fix variation problems automatically
Comprehensive Support for Process Variation
Variations in manufacturing result in structural changes in devices and interconnects, leading to deviations in their electrical behavior. At 65nm and below, process control is difficult, leading
Percentage yield Probability of violation Parameter sensitivity report

Figure 5: SSTA Data Flow

PLATFORMS
Linux (32-bit, 64-bit) Sun Solaris (32-bit, 64-bit) HP-UX (32-bit, 64-bit) IBM AIX (32-bit, 64-bit)

STANDARD INTERFACE SUPPORT
Inputs: Verilog, lib, SDC, SDF, SPEF, Tcl Optional: ECSM, cdB, DEF, CPF, OA, VCD SSTA: Sensitivity ECSM (S-ECSM), Sensitivity SPEF (S-SPEF), Sensitivity Probability Distribution Function (SPDF) Outputs: Timing reports, SDF, DRV report, power reports For more information about this and other products contact:

info@cadence.com

or log on to:

www.cadence.com

2007 Cadence Design Systems, Inc. All rights reserved. Cadence, CeltIC, Conformal, Encounter, Verilog, and VoltageStorm are registered trademarks and the Cadence logo and SoC Encounter are trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. MK/GDA/JA/PDF

ENC O U N T E R T i m ing S yste m

eter Routin nom g Na

DATASHEET

ENCOUNTER TIMING SYSTEM

Industry-endorsed and production-proven, Encounter Timing System is a full-chip signoff static timing analysis (STA) solution consisting of gate-level timing, signal integrity, power, and variation analyses. It serves front-end designers seeking high-quality timing analysis and ease of use, as well as back-end designers looking for a complete, silicon-accurate signoff solution. The underlying technologies for both timing and SI analysis have been in production use for nearly a decade. With Encounter Timing System, you benefit from the utmost in signoff timing accuracy, usability, and functionality for both mainstream and advanced node digital designs.
Final design closure with timing and power signoff can consume more than one-third of the overall silicon realization process. An efficient and convergent implementation and signoff flow is critical. Using Cadence Encounter Timing System with Encounter Digital Implementation System, design teams benefit from tightly coupled implementation optimization and signoff environments featuring shared analysis, interface, and database infrastructureproven to greatly improve design convergence. As a standalone solution, Encounter Timing System offers highly accurate signoff timing and noise analysis with advanced debug and a multiprocessing infrastructure to boost productivity when analyzing multimillion-gate designs.
lI Digita mpleme ter nt n a ng/Prototypi ou nni n a
Design Closure Signoff Analysis

Pred ic

ity bil ta

Low-Power Design

l Synthe ysica sis Ph

Design Closure

Advanced Node Design
Figure 1: Tightly coupled optimization and signoff environments ensure faster design convergence and timing closure
- Consistent static timing, signal integrity, statistical static timing, and on-chip variation analyses for optimization and signoff - Faster design convergence and timing closure with less margin - Common database infrastructure for fast setup Seamlessly integrated with Encounter Power System

Mixed-Signal Design

n o ff A n a

s l y si

Stacked Die
- Shared cockpit, database, and viewers -Gate-level power analysis, IR drop impact on timing, noise, and clock jitter in one environment Eliminates the need for multiple products -Integrates timing, noise, power, and statistical variation analyses Offers higher throughput for faster signoff

BENEFITS

Supported by major foundries, ASIC, and IP vendors, and used exclusively by multiple IDMs for signoff Integrated with Encounter Digital Implementation System
End-to-end multi-threaded timing and noise analysis for faster signoff turnaround Concurrent multi-mode, multi-corner (MMMC) timing and SI analysis with distributed and threaded processing Innovative memory architecture to improve capacity and get the most out of your existing hardware Boosts productivity and shaves weeks off tapeout schedules Industry-renowned global timing debug accelerates root-cause and bottleneck analysis MMMC-aware debug quickly tracks down timing problems across all modes MMMC- and SI-aware incremental engineering change orders Advanced analysis algorithms to reduce false SI failures by 10x Unmatched signoff accuracy - Prevents the excessive overdesign that saps performance, power, and die area - Delivers accurate delay calculation to within 2% of SPICE - Leverages current source models for greater accuracy with advanced node designs - Offers built-in critical path simulation for delay/SI correlation with SPICE
Power Reports VCD SPEF/SDF
SDC.lib DEF + LEF Verilog Spice ECSM

Encounter Timing System

Figure 2: Encounter Timing System data flow and user interface

POWERFUL GUI

Command console with command completion, history, and context highlighting Timing constraint viewer to find path-specific timing constraints based on design object name or constraint group type Schematic and layout viewers with the ability to cross-probe from the timing report Script editor for evaluating scripts to enable cross link and expand Tcl procedures Structural checks on timing paths to identify potential issues Checks for missing or inconsistent library and design data
flexibility to use Encounter Timing System as a standalone solution or as part of the integrated Encounter Digital Implementation System.

GLOBAL TIMING DEBUG

With global timing debug, you can quickly pinpoint the root cause of timing and constraint problems. You can view the slack histogram and generate detailed timing views with individual cell/wire delays, slack details, hierarchy allocations, and constraint cross-probing. Global timing debug employs unique path visualization capabilities to determine a paths cause of failure. Paths that share a common failure mode can then be categorized dynamically while the debugging of uncategorized paths continues. Path categories can be visualized in the global timing context to determine which categories can be fixed in parallel and which ones should be fixed first. This reduces iterations to timing closure by intelligent debugging more than just the worst path.

FEATURES

Encounter Timing System provides a comprehensive signoff verification solution that combines static timing analysis (STA), accurate delay calculation, crosstalk noise analysis, advanced modeling, and global timing debug. It helps you achieve first-pass silicon success and fast time to market on their multimillion-gate designs. Encounter Timing System also supports incremental engineering change orders (ECOs) and what-if analysis, reducing runtimes for minor design changes and thus improving productivity.
CONSISTENT, INTEGRATED STA FOR OPTIMIZATION AND SIGNOFF
Designers have traditionally relied on one STA method for implementation and another for signoff analysis. This leads to corrective iterations with the placeand-route system when discrepancies are found during signoff analysis. Encounter Timing System is a consistent, integrated STA environment for optimization during the place-and-route stage and for final signoff verification. This gives you the

GLOBAL CLOCK DEBUG

With global timing debug, you can quickly pinpoint the root cause of timing and constraint problems. You can view the slack histogram and generate detailed timing views with individual cell/wire delays, slack details, hierarchy allocations,

www.cadence.com

ENCOUNTER Timi ng Sy ste m

FAST, ACCURATE SIGNOFF

Encounter Timing System offers accurate analysis of signal integrity (SI) and IR drop as well as its impact on both timing and functionality. It builds on the strengths of the customer-trusted, tapeout-proven Cadence CeltIC Nanometer Delay Calculator (NDC) engine. And it employs more accurate libraries (ECSM, cdB) to analyze the complex effects of crosstalk delay, noise (glitch), timing, and IR drop.

ADVANCED NANOMETER ELECTRICAL ANALYSIS
Implementing multimillion-instance nanometer designs requires very efficient yet highly precise delay calculation. Designers must also consider SI effects such as IR drop and crosstalk, and advanced low-power design techniques that use multiple voltage levels and level shifters. Delay calculation based on table lookup or polynomial models are not accurate enough for todays nanometer circuits. Encounter Timing System supports the effective current source model (ECSM), which enables accurate prediction of actual silicon performance, particularly for complex nets, long RC networks, and multiple driver scenarios (clock meshes).
Figure 3: Global timing debug
and constraint cross-probing. Global timing debug employs unique path visualization capabilities to determine a paths cause of failure. Paths that share a common failure mode can then be categorized dynamically while the debugging of uncategorized paths continues. Path categories can be visualized in the global timing context to determine which categories can be fixed in parallel and which ones should be fixed first. This reduces iterations to timing closure by intelligent debugging more than just the worst path.
INTERFACE TO ENCOUNTER CONFORMAL CONSTRAINT DESIGNER
A seamless interface between Encounter Timing System and Encounter Conformal Constraint Designer enables advanced constraint checking and critical false-path analysis. Constraint checking eliminates bad constraints that cause iterations, longer design time, and silicon failure. Critical false-path analysis greatly reduces the need to manually remove false paths from the critical paths. Removal of these false paths eliminates unnecessary netlist optimizations and can improve design area and timing.
With global clock debug, you can see the clock structure and quickly get to the root of clock-related problems. You can quickly determine if there are issues with the specifications, clock re-convergence, skew, transition time, or insertion delay and get relevant physical information on how to fix them. You can display the graphic structure of a large and complex clock structure as needed, folding or unfolding the clock tree at any stage to tune into the relevant information, without being overwhelmed by other details.
Figure 4: Global clock debug

Reported SI Violations

10000 130nm 90nm 65nm 45nm
and vectorless approaches to power analysis. The vectorless approach enables accurate power analysis early in the design flow, while vectors are used to achieve the highest accuracy.
ETS XL Propagated No Propagation
Figure 5: SI pessimism reduction and critical path simulation
ACCURATE CROSSTALK ANALYSIS AND FASTER SI CLOSURE
Encounter Timing System calculates the impact of crosstalk using a combination of cell- and transistor-level models. For noisy nets that exhibit the most non-linear behavior, Encounter Timing System uses an on-the-fly SPICE simulation engine to accurately calculate noise-ondelay effects. It also deploys the unique path-based alignment (PBA) technique to ensure realistic SI delay effects on critical timing paths. Without PBA, SI delay calculation can create an unrealistic or overly pessimistic worst-case path delay. Further removal of path delay pessimism is achieved through noise path pessimism removal (NPPR), which finds the maximum noise delay change for the overall critical path instead of for each individual net on that path. Encounter Timing System also ensures functional validity by performing glitch noise propagation to register end points and by ensuring that the register is not driven unstable. These unique PBA, NPPR, and glitch noise propagation capabilities greatly reduce the number of false crosstalk problems. This translates into much less work for place-and-route systems and significantly fewer SI closure iterations.
AUTOMATED MMMC SIGNOFF AND ECO
Encounter Timing Systems unique multi-mode multi-corner (MMMC) infrastructure enables you to quickly analyze and debug timing problems across all modes and corners. It features

# of Violations

LOW-POWERDRIVEN SIGNOFF
499k 39.5k 2.7M 810k 184k 1.3M 682k 25 4400
concurrent MMMC analysis with distributed and threaded processing capability that provides simplified management of MMMC runs coupled with the highest possible throughput. This is complemented by the MMMC-aware incremental engineering change order (ECO) capability, which allows you to make an ECO and see the effect on timing and SI across all modes in a single session, without running additional reports or scripts.

In smaller geometries, power supplies are typically around 1 volt, and even small voltage drops can compromise signal timing and lead to chip failures. IR drop further increases the risk of crosstalk failure. Encounter Timing System accurately models the non-linear IR drop impact and eliminates the inaccuracies of the traditional linear K-factor approach. It incorporates instance-based IR drop data from Cadence VoltageStorm Power Verification to account for the effects of static and dynamic IR drop on path delays and SI. Advanced low-power design techniques such as multi-supply/multi-voltage (MSMV) and dynamic voltage and frequency scaling (DVFS) can introduce errors and complicate the traditional timing signoff flow. Encounter Timing System enables a simple flow where you can characterize just three libraries at three voltage points, which are sufficient to perform accurate non-linear delay calculation across a much wider range of voltage points. Encounter Timing System also supports the Common Power Format (CPF), which describes power intent throughout the design flow from system specification to tapeout.
MULTI-PROCESSING ARCHITECTURE
Encounter Timing System utilizes both threaded and distributed processing to greatly improve overall signoff turnaround. Through threaded timing and SI analysis, you can gain up to four times the performance over a single CPU run. In addition to threading on a single machine, Encounter Timing System includes MMMC timing analysis and superscaling SI analysis, which can be distributed across multiple machines. By distributing different parts of a task between two or more processors, Encounter Timing System can significantly improve turnaround time and handle larger, more complex designs.

CRITICAL PATH SIMULATION

Encounter Timing System enables on-the-fly path simulation of critical paths and offers a graphical view of the impact of crosstalk and IR drop along the path, including the propagation of non-linear waveform effects. This enables easy validation of timing, SI, and IR drop effectsand verification of fixesprior to implementation.

UNIFIED POWER ANALYSIS

Encounter Timing System provides a comprehensive static and dynamic solution for cell-level power analysis by combining timing and power analyses in a single environment. This integrated environment delivers faster results and improves your productivity. Encounter Timing System supports both vectored

COMPREHENSIVE VARIATION SUPPORT
At 65nm and below, process control becomes very difficult. Manufacturing variations result in deviations in electrical behavior for devices and interconnect. Traditionally, these variations have been factored into the design flow by adding bulk margin to the timing constraints or libraries. But this practice can negate the advantages gained from using smaller process nodes over larger process nodes. In addition, designs required only to pass traditional signoff standards could still fail in silicon if the corners are not chosen properly. Encounter Timing System enables you to properly analyze and account for process variation without resorting to excessive margins or overdesign to restore predictability to the design flow. It offers common-path pessimism removal (CPPR), advanced on-chip variation analysis, statistical static timing analysis (SSTA), and statistical leakage and thermal analyses to achieve maximum design performance with minimum power consumption at advanced process nodes. These technologies help reduce the design cycle with fewer timing runs and help you tape out with greater confidence.
analysis corners to model different process and environmental variation combinations. This corner-based approach can be overly pessimistic since it reports timing scenarios that have an extremely small likelihood of occurring. Also, the exponential growth in the number of corner combinations with the increasing number of parameters makes analysis on every corner impractical. Encounter Timing System supplements traditional corner-based methods with powerful and accurate statistical static timing analysis (SSTA) that can account for the process variability in a single run. It uses advanced statistical ECSMs to identify cells and nets on both clock and data paths that are sensitive to variations. It also determines the probability of timing failure over the full range of process variation. These features reduce both pessimism and guardbanding, resulting in decreased area and power consumption while improving chip performance. Encounter Timing System lets you explore potential tradeoffs between parametric yield and clock speed. Encounter Timing System SSTA features include: Within-the-die, die-to-die, and random variation support Block-based and path-based modes
Crosstalk noise impact Standardized statistical ECSM library models and characterization support Consistency and integration with Encounter Digital Implementation System to fix variation problems automatically

THERMAL ANALYSIS

Designers targeting advanced node processes are quickly discovering that on-chip thermal variation can no longer be ignored. Thermal impact at smaller process nodes can affect leakage power and introduce timing failures across the die. Simply applying more guardbanding to your design to account for this variation can negatively affect chip performance. Encounter Timing System includes a powerful thermal analysis engine that takes chip packaging into account and provides an accurate thermal map and per-instance temperature. This reduces the need for more guardbanding and enables you to target thermal hotspots more effectively.

STATISTICAL LEAKAGE POWER ANALYSIS
At smaller process geometries, leakage power begins to dominate the power consumed by CMOS devices. Accurate analysis of device leakage is paramount
LOCATION-BASED ON-CHIP VARIATION
Designers must address on-chip variation (OCV) effects, including removal of pessimism caused by common paths. However, traditional OCV analysis is inaccurate and overly pessimistic since it employs a constant de-rating factor. Encounter Timing System employs locationbased on-chip variation (LOCV), which uses logic level, cell complexity, and physical location to select the optimal de-rating factors. LOCV helps eliminate the excessive guardbanding associated with traditional de-rating, and it improves timing closure.
SDC.lib VCD SPEF/SDF DEF + LEF Verilog Spice SPDF S-ECSM
STATISTICAL STATIC TIMING ANALYSIS
Traditional STA accounts for process variations by introducing more aggressive gross guardbanding and by using multiple

Power Reports

Statistical Reports

Figure 6: SSTA data flow

to achieving a power-efficient design. Existing leakage power analysis techniques use a pessimistic worst-case approach, which is ineffective. Since cell leakage has an exponential response to process variation (that is, a small change in process variation causes a major shift in transistor leakage), the probability of the extreme worst case occurring in real silicon is very small. This leads to aggressive over-design, overcompensation for IR drop, and potentially unnecessary architectural changes. The solution is to model the leakage power as a statistical probability to avoid designing to the worst-case limit. The statistical leakage power analysis (SLPA) of Encounter Timing System helps you target a smaller, more reasonable leakage number. This number reported by statistical analysis can be as much as 40% smaller than that of traditional worst-case leakage power analysis. Using advanced statistical ECSMs, Encounter Timing System can model the following: State-dependent exponential leakage power variation with respect to process parameters Die-to-die, within-the-die (spatially correlated), and random variation

SLPA Spice Monte Carlo

3 -s igma L eakage (99.7% condenc e)

Worst-Case L eakage

Up to 200% Difference

Leakage (nW)

Figure 7: Statistical leakage power distribution
STANDARD INTERFACE SUPPORT
Inputs Verilog,.lib, SDC, SDF, SPEF, Tcl Optional: ECSM, cdB, DEF, CPF, OA, VCD, OCV SSTA: Statistical ECSM (S-ECSM), Statistical SPEF (S-SPEF), Statistical Parameter Distribution File (SPDF) Outputs Timing reports, SDF, DRV report, power reports

CADENCE SERVICES AND SUPPORT
Cadence application engineers can answer your technical questions by telephone, email, or Internetthey can also provide technical assistance and custom training Cadence certified instructors teach more than 70 courses and bring their real-world experience into the classroom More than 25 Internet Learning Series (iLS) online courses allow you the flexibility of training at your own computer via the Internet Cadence Online Support gives you 24x7 online access to a knowledge base of the latest solutions, technical documentation, software downloads, and more

PLATFORMS

Linux: 32-bit, 64-bit Sun Solaris: 64-bit IBM AIX: 64-bit

PACKAGING

Encounter Timing System is available in L and XL base licenses with an Advanced Analysis GXL Option.
For more information contact Cadence sales at:

+1.408.943.1234

or log on to:
www.cadence.com/ contact_us
2011 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, CeltIC, Conformal, Encounter, Verilog, and VoltageStorm are registered trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 21856 1/11 MK/MV/PDF