VIRTUOSO CUSTOM DESIGN PLATFORM GXL
As the high-end custom block authoring physical layout tool for the Virtuoso platform, Virtuoso Layout Suite GXL supports custom digital, mixed-signal and analog designs at the device, cell, and block levels. These accelerated features provide advanced automation to accelerate custom block authoring.
Figure 1: All components of the Virtuoso platform work together to support fast, silicon-accurate differentiated custom silicon

G0007A

DATASHEET
The Virtuoso Analog Design Environment GXL is designed to help users create manufacturing-robust designs. It gives designers access to a new parasitic estimation and comparison flow and optimization algorithms that help to center a design better for yield improvement and advanced matching and sensitivity analyses. This makes it possible to completely explore the design for problem areas. In addition, it i ncorporates the same advanced custom IC environment used within the Cadence Allegro platform for creating system-inpackage (SiP) designs.
The Cadence Virtuoso custom design platform is the i ndustrys leading design system for complete front-to-back analog, RF, mixed-signal, and custom digital design. The GXL tier comprises the platforms most advanced configuration ofdesign and analysis technologies, including expanded physical design capabilities and an enhanced simulation e nvironment.

PERFORMAN CE

PARA SI
Design Specification Multi-mode Simulation Accelerated Layout Silicon Analysis Chip Finishing
Open Database Constraint Management

PDKs Customer IP

It includes capabilities for device generation and editing, block floorplanning, automatic placement, and interactive routing. Driven by a comprehensive analog constraint capture and management system, Virtuoso Layout Suite GXL makes design reuse, engineering change, retargeting, and process migration possible. It uses unique placement and routing engines to automatically or interactively generate and optimize devicegeometry, place devices (adhering to constraints) within a cell footprint, andsubsequently complete the layout interconnect routing.
Advanced optimization algorithms improve design centering and yield Built-in parasitic estimation and comparison flow help to quickly identify severe parasitics inside the design
AUTOMATIC PLACEMENT, ROUTING AND EDITING
The GXL placement engine places devices for density, performance, and precision while maintaining symmetries and matching. Device generators produce geometry for complex devices with varying aspect ratios (variants), and then the placer explores these device variants for better packing. Similarly, the placer can optimize the cell footprint to accommodate the cell contents. Floating pins are placed to achieve optimal signal flow and proper spacing is reserved for wide wires. While optimizing latchup, the placer merges wells and creates guard ringsall automatically and with initial constraints respected throughout the placement process. The GXL routing engine optimizes wiring while adhering to the constraints specified in the Constraint Editor. The router handles arbitrary width and spacing constraints as well as known cross-talk problems. It further supports routing of self-symmetric nets to achieve balanced routing for structures such as T-nets. Also included is support for partially symmetric netsusers can choose to route the critical segments of their nets in a symmetric and highly matched form, while letting the router choose the shortest path for the non-critical net segments. The interactive editing mode allows designers to move and align devices and change their orientation and shape. Changes to devices automatically regenerate any associated wells or guard rings. Real-time DRC ensures layout quality. Designers can reroute nets and fix the location of critical wires. When the routing of one net is modified, any symmetric nets mirror the new path. As always, the layout synthesis engine respects constraints throughout the routing process.

FEATURES

PARASITIC RESIMULATION FLOW
Users can place parasitic estimates onto their schematics. These are then translated into wire constraints, which can prompt a layout person that certain nets are critical and their length and width should be minimized to minimize parasitics introduced into the system. Post-extraction, the parasitic estimates can be quickly compared to the extracted parasitics to find trouble spots within the design.

BENEFITS

Accelerated block authoring through connectivity-driven features and flow, schematic or netlist. Also promotes correct-by-construction LVS correct layout to reduce verification iterations Increased productivity and design quality with constraint- and designrule-driven features to automatically ensure design and process correctness in real time Simplification and optimization ofdevice generation using a new menu-driven QuickCell feature or thestandard SKILL programmable parameterized cells Efficient planning, placement and routing of large block designs with custom floorplanning, automatic placement, and advanced interactive routing features Enhanced analog design team p roductivity gainsup to 10x over manual methods Unique support for meeting new performance specifications, and for handling design reuse, technology migration, and ECOs

DESIGN FOR YIELD FLOW

Designers can use a series of both global and local optimization methods to center their design values to help maximize yield. This optimizes the parametric yield of circuits by extrapolating the statistical distribution up to six sigma margins.
ADVANCED LAYOUT AUTOMATION FOR SIMPLIFIED AND OPTIMIZED BLOCK AUTHORING
Virtuoso Layout Suite GXL simplifies and optimizes block authoring with advanced layout automation features that leverage the design-ruledriven functions and flow of the Virtuoso platform. Menu-driven parameterized cells (QCells) or SKILL programmable parameterized cells (Pcells) simplify and optimize device generation and editing. Floorplanning and automatic placement simplifies and optimizes the design planning and location of devices. Advanced shape-based constraint and design-rule-driven routing simplifies and optimizes the tedious interconnect task.

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VIR TUOSO CUSTOM DESIGN PLATFORM GXL
PRECISION DEVICE GENERATION AND LAYOUT SYNTHESIS
Virtoso platform GXL provides several options for generating the individual devices that are to be used by the placer. It supports Pcells (including ROD), the users proprietary cells, and even legacy GDSII layouts imported as subcells. For more complex devices, the use of one of the precision generators (Modgens) is recommended. Complex quad-FETs, interdigitated and matched FET arrays and highly matched precise passives are supported. Modgens provide the ability to map several devices to one complex group and then edit the whole arrangement easily. Virtuoso platform GXL also provides a comprehensive layout synthesis engine that generates and optimizes device geometry, cell foot print, device placement and wire routing as guided by the analog constraints for the design (see Figures 2 and 3)

SPECIFICATIONS

LAYOUT CREATION AND EDITING
Interactive Pick-From-Schematic or automated Gen-From-Source device selection Menu-driven QCell (QuickCell) or SKILLprogrammable automated device generation ExpressPcell mechanism to speed up evaluation of parameterized cells and make them more interoperable with third-party tools Automated device editing, including abutment, pin permutation, folding, chaining, and cloning Menu-driven or programmable multi-part path (MPP) feature for guard rings, slotting, etc. Design-rule driven-editing with real-time notification or enforcement of process rules Dynamic measurement Constraint-driven specification, management, and real-time notification or enforcement
Figure 2: Virtuoso Analog Design Environment GXL
Figure 3: Virtuoso Layout Suite GXL
Block floorplanning with support rectilinear blocks, pin optimization, andtemplate support Automatic constraint- and design-ruledriven placement of pins, devices, cells, and blocks Advanced shape-based constraint and design-rule-driven interactive routing Bi-directional interfacing to Virtuoso Schematic Editor, Cadence Chip Assembly router and the Cadence Space-based Router ECO support Virtuoso Layout Migration integrated into Virtuoso Layout Suite GXL Legacy non-connectivity design importing and connectivity mapping Cadence Diva and Cadence Assura physical verification support Comprehensive device and cell support All analog cells including opamps, charge pumps, bandgaps, comparators, VCOs, regulators and others in technology portable manner. Provides support for ADCs, PLLs, DLLs and others Supports Pcells including ROD, proprietary cells, and legacy GDSII layouts Complex quad-FETs, interdigitated,matched FET arrays and matched passives Supports guard rings, dummy devices wells, and mulit-part paths Comprehensive integration Cadence DFII library structure captures constraints, devices, parameters, and connectivity Full compatibility with Virtuoso XL Layout Editor connectivity model Includes technology set-up wizard for fast set-up of a new processes Tightly coupled ECO flow

VIRTUOSO Custom design PLATFORM GXL features
Virtuoso Analog Design Environment GXL
New Common Cockpit New Icon Style Multi-Tab Support Bookmarks & History Updated Pulldown Menus Window Cong Support World View Assistant Search Assistant Property Editor Assistant Navigator Assistant Constraint Browser Design Explorer Single Testbench Simple Parametric Analysis Device Checking Global Variable Support Updated Wavescan New Calculator Simulation Support: Virtuoso Multi-Mode Simulation, HSPICE Circuit Optimization Behavioral Model Generation Parasitic Resimulation Yield Analysis Mismatch/Sensitivity Analysis SiP Support Basic Polygon Editing QCells DRD Editing A & D Device Placer ModGens Cell Planning Chip Assembly Router Floorplanning Cell Block Placer Layout Optimization Space-Based Router

X X X X X X X X

Virtuoso Layout Suite GXL

X X X X X X X X X X X X

X X X X X X X X X X X X X X X X X X X X X X X X
Automatic and interactive capabilities Automatic device and device array generation Automatic device placement, including symmetry and matching Automatic routing with symmetry and cross-talk avoidance Move, align and modify devices Interactive routing with symmetric update Real-time design rule and constraint checking
SCHEMATIC AND SIMULATION ENVIRONMENT
Virtuoso Schematic Editor or netlist-driven hierarchical layout New analog schematic generator to convert netlists into schematics Simulation environment extensions Inherits all features and functionality from Virtuoso Analog Design Environment XL Tools for comparing and fixing design parasitics
Local and Global Optimization toimprove design yield and design centering Connections to Allegro platform to enable SiP design Design characterization and modeling features to create Verilog A models Sensitivity and Matching analyses

DESIGN OUTPUTS

OpenAccess database SKILL STREAM format
CADENCE SERVICES AND SUPPORT
Cadence application engineers can answer your technical questions by telephone, email, or internetthey can also provide technical assistance and custom training. SourceLink online customer support gives you answers to your technical questions24 hours a day, 7 days a weekincluding the latest in quarterly software rollups, product release i nformation, technical documentation, software updates, and more.

PLATFORM/OS

Sun/Solaris HP-UX IBM AIX LINUX

DESIGN INPUTS

SKILL STREAM format OpenAccess database Virtuoso Schematic Editor L or XL CDL and SPICE netlist format Virtuoso Chip Assembly Router database format

THIRD-PARTY SUPPORT

SKILL-based tools and functions OpenAccess tools and functions Process design kits (Please reference the Cadence Virtuoso PDK datasheet for more information)

Cadence-certified instructors teach more than 80 courses and bring theirreal-world experience into the classroom. More than 25 Internet Learning Series (iLS) online courses allow you the flexibility of training at your own c omputer via the Internet.
For more information, Email us at

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VIRTUOSO ANALOG DESIGN ENVIRONMENT L, XL, AND GXL

DATASHEET

FAMILY OVERVIEW
The Virtuoso Analog Design Environment product suite provides all the capabilities required to fully explore, analyze, and verify a design against the users desired goals, allowing the designers to maintain the design intent throughout the design cycle. As the industrys leading solution for analog simulation control and management, it allows users to flexibly select the tier that best supports their design goals and enables design convergence as they move through the design flow. Analog Design Environment L provides a quick entry into the analysis process with easy execution of simulations. Analog Design Environment XL extends the L tier capabilities, providing multiple test support; analysis over sweeps, corners, and Monte Carlo; easy reviewing of all results directly; and generating spec-comparison sheets, datasheets as needed. Analog Design Environment GXL builds on the Analog Design Environment L and XL capabilities by providing targeted tools that aid with key design challenges with early parasitic analysis, design centering, and designing in multi-technologies.
Cadence Virtuoso Analog Design Environment family of products provides a comprehensive array of capabilities for the electrical analysis and verification of analog/mixed-signal designs, including the flexibility to integrate into a variety of custom flows. The family includes Virtuoso Analog Design Environment L, Virtuoso Analog Design Environment XL, and Virtuoso Analog Design Environment GXL.

FAMILY BENEFITS

Provides built-in support for all Virtuoso simulators with integration support for third-party simulators Supports multiple test methodologies to fully explore and validate designs Enables design abstraction by allowing users to simulate and characterize designs with behavioral models Accelerates design debug using a variety of built-in analysis tools Facilitates early correction, enables design convergence via easy evaluation of pre- and post-layout parasitic effects Family Features at a Glance Single-test design analysis and exploration Script support through OCEAN Virtuoso and third-party simulator support Multi-test verification and extended analyses Flexible corners analysis Extended visualization speed with PSF XL Pre- and post-layout parasitic analysis Design characterization and modeling Design centering and yield optimization
Circuit problems are quickly detected and explored via a clear visualization cockpit Offers integrated documentation and fast waveform visualization across all tests Supports manual or automated design evaluation and sizing to target specifications Provides a tiered set of capabilities to support a variety of design flows and design challenges

ADE L

ADE XL

ADE GXL

VIRTUOSO ANALOG DESIGN ENVIRONMENT L OVERVIEW
Virtuoso Analog Design Environment L is the entry-level analog design and simulation environment for the Virtuoso custom design platform. Analog Design Environment L is the industrys leading task-based environment for simulating and analyzing full-custom, analog, and RF IC designs. It features a graphical user interface, integrated waveform display, distributed processing, and interfaces to many third-party simulators. As part of the Analog Design Environment family, Analog Design Environment L provides the foundation to facilitate extended design analysis and validation into the XL and GXL products.

BENEFITS

Reduced learning curve with a simulator-independent environment Maximum efficiency in the script-driven mode Close integration with Virtuoso Schematic Editor for interactive analysis Easy design and test parameterization for fast circuit exploration Configurable window for optimum display of relevant data Integrated visualization cockpit for exploration of simulation results helps to maintain design intent Extract quantifiable results with built-in calculator and extensive list of functions
Figure 1: Virtuoso Analog Design Environment L: Single-test environment

FEATURES

EASY-TO-USE INTERACTIVE SIMULATION ENVIRONMENT
The interactive environment has everything users need to set-up, run, and analyze results with any integrated simulator. It offers a variety of tools for displaying and analyzing results, giving designers the flexibility to visualize and understand the many interdependencies of an analog, RF, or mixed-signal design. These tools allow users to quickly and easily pinpoint critical design parameters
and their effect on circuit performance. The environment is flexible enough to take advantage of Virtuoso MultiMode Simulation technology, by making it easy to switch between different simulators without having to re-enter all measurements. Virtuoso Analog Design Environment L has an extensive scripting language (OCEAN) built-in. OCEAN is based on the Cadence SKILL programming language for development of more complex analysis. It can be used to set up, run, and post-process results in a batch-oriented methodology. Lastly, Virtuoso Analog Design Environment L includes the capability to interface with other commercially available and in-house simulators through the OASIS IntegratorsKit.

RF-specific plots. Additionally, it contains a variety of changeable display attributes for the axes, waveform colors, and labels so that you can make professional plots for your reports. Waveform markers and a built-in waveform calculator allow accurate measurement of signals in a variety of different modes, including transient, AC, and RF. The calculators algebraic expressions can be composed of any combination of input or output voltages or currents.
INTEGRAL PART OF THE VIRTUOSO CUSTOM DESIGN PLATFORM
Virtuoso Analog Design Environment L is an integral part of the Virtuoso custom design platform. It bridges the gap between schematic design and physical layout by providing a simulation environment where the designer can compare designs in both pre- and postextracted forms, thereby completing the Cadence IC design flow. It supports analog system to IC design methods with complete access to behavioral modeling languages for both simulation and cross-probing for waveform display. Post-simulation operating condition can
BUILT-IN WAVEFORM DISPLAY AND SIGNAL ANALYSIS CAPABILITIES
The waveform display tool, coupled with an extensive waveform calculator, provides a comprehensive post-simulation analysis environment. The waveform window can handle all types of analog and mixedsignal data, including advanced displays such as noise, corner, statistical, and

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Virtuoso Analog Design Environment L, XL, and GXL
be easily annotated back to the schematic with net voltages, currents, and device operating information.
Job monitoring and controlling functions Graphical user interfaces for set-up and viewing status
Quick color-coded feedback of all results against target specifications helps maintain design intent Optimum analysis throughput with simulation distribution and multi-test management across user-preferred load balancing software Simplifies design reviews through integral documentation, specifications, measurement results, and waveforms Closely integrated with Virtuoso Schematic Editor for fast test development and debug

SPECIFICATIONS

INTERACTIVE SIMULATION ENVIRONMENT
Easy to learn and easy to enter data Easy reuse of simulation set-ups Clear displays of simulation information Cross-probing support for both schematics and layouts Design variable support with ability to create dependent expressions Auto-plotting and printing of simulation data Batch scripting Schematic annotation of node voltages and device information OASIS integration of a customer proprietary or third-party simulator Launch menu to directly open Analog Design Environment XL view with Analog Design Environment L test set-up
VIRTUOSO ANALOG DESIGN ENVIRONMENT XL OVERVIEW
Virtuoso Analog Design Environment XL is the advanced design and simulation environment for the Virtuoso platform. By supporting extensive exploration of multiple designs against their objective specifications, it sets the standard in thorough, fast, and accurate design analysis and verification.

SPECIFICATION-DRIVEN DESIGN
To accelerate design verification, Virtuoso Analog Design Environment XL combines specification entry and design management in a single unified cockpit. A specification consists of all required tests, all required analyses, and all required operating conditions for validation against a measured set of goals. With Virtuoso Analog Design Environment XL, development of multiple tests is easy, along with all the different conditions to validate a designs performance against the target specification. Each Analog Design Environment XL session can be treated as a project, providing access to all the tests, sweeps,
Supports high fault coverage of designs with extensive verification over process environmental and operating conditions Analysis support of multiple simulators across multiple tests and multiple conditions for thorough design validation, compiling results in a single easy-to-use database Simulation and characterization of designs with behavioral models aids in design abstraction Support for corners, parametric sweeps, Monte Carlo, and reliability analysis

WAVEFORM DISPLAY

Supports multiple y-axes, strip plots, and Smith Charts Built-in waveform calculator Independent sub-window displays Horizontal and vertical measurement markers Independent pan and zoom capability User-defined labels and titles Color and line style controls Signal browser Color-coordinated cross-probing to schematics

DISTRIBUTED PROCESSING

Distribution of multiple simulations Efficient use of computer farms Built-in basic load balancing and interface to other load-balancing tools
Figure 2: Virtuoso Analog Design Environment XL: Mult-test environment
corners, scripts, and documentation needed to completely validate a design against the designers intent.
FLEXIBLE SIMULATION MANAGEMENT
An overview of all the tests in development is available through the test assistant, which allows easy access to add, delete, and edit all required test configurations and analyses to fully validate a design. These defined tests can be further managed with test configurations that support different testing strategies at different points in the design development/validation flow. Virtuoso Analog Design Environment XL provides users with an Analog Design Environment L-based debugging environment to make changes in the set-up for a point and simulate that point for debugging purposes. By giving users the ability to create extensive testing, Virtuoso Analog Design Environment XL provides the ability to manage the parallelized simulations with either the internal load-balancing system or with an optional third-party solution. Analog Design Environment XL provides a user interface for defining and specifying operating region expressions using the Operating Region assistant or the Operating Region Specification form. The Operating Region assistant enables users to quickly specify expressions, while the Operating Region Specification form provides advanced methods for specifying expressions.

Users can easily explore results in more detail by right clicking on any single result or set of results that pop up in Virtuoso Visualization and Analysis XL, which is included in Analog Design Environment XL. In addition, a history of results is automatically maintained so users can quickly go back to look at previous results or even results from different test configurations.
Supports matching and correlation constraints from Virtuoso Schematic EditorXL Incremental re-simulation Creation and tracking of parametric dependencies among tests for more complex analysis Integrated with Virtuoso Multi-Mode Simulation Ability to save different test configurations for different steps in the testing flow
Virtuoso Analog Design Environment XL builds upon the features and infrastructure of Virtuoso Analog Design Environment L, providing cohesive operation for the user. As a result, Analog Design Environment XL is able to work closely with Virtuoso Schematic Editor and Virtuoso Layout Suite for a complete integrated design flow.
VISUALIZATION AND ANALYSIS OF RESULTS
Creation of specifications directly from simulation results Quick overview window of test results against target specification Cross-probing and annotation to schematics and layout Calculator, OCEAN, MDL, and MATLAB measurement strategies Integrated Virtuoso Visualization and Analysis XL for fast waveform analysis Integral documentation creation and support for Text, HTML, and PDF History of prior results with the ability to compare any two sets of data Measured results are saved along with the tests as a lib/cell/view for easy design management
INTERACTIVE SIMULATION CONTROL
Integrates Analog Design Environment L capabilities for single test operation Design exploration with sweeps, corners, and Monte Carlo analysis RelXpert integration for reliability analysis
VISUAL COCKPIT EASES DESIGN VERIFICATION
An overview of all the tests, simulators used and analysis conducted (along with any defined variables and corners) is listed in easy view on the Data View assistant screen. Results of the latest analysis appear in a tabular view on the right side, with color coding to show at a glance the simulation results that pass or fail against the target specification. The results can be reordered or transposed for better visualization.
Figure 3: Sensitivity of device parameters to measured goals
DISTRIBUTED AND BATCH PROCESSING
Built-in distributed processing, with support for external load balancing software Test-specific job policy for efficient use of hardware resources Parallel analysis over multiple tests and all required corners Batch scripting support through OCEAN XL

VIRTUOSO ANALOG DESIGN ENVIRONMENT GXL OVERVIEW
Virtuoso Analog Design Environment GXL uses the same advanced design and simulation cockpit as Analog Design Environment XL and includes extended analysis capabilities for more detailed design exploration. A user can choose to launch Analog Design Environment GXL directly or just access the additional analysis capabilities from Analog Design Environment XL.
Figure 4: Virtuoso Analog Design Environment GXL: Extends analysis into parasitics and yield
process variations and for design sizing. Users can then automatically create design specific corners for signoff-level simulation. Built upon the statistical analysis capabilities in Analog Design Environment XL, Mismatch analysis can be used to further explore the sensitivities of a design for all or a selected set of devices. For designs where high-yield margin is critical, such as memory, a high-yield analysis capability provides up to six-sigma accuracy, without the cost of running extensive Monte Carlo.
an estimated view to gain full access to all the debug capabilities Analog Design Environment GXL.
Extended design exploration with sensitivity and mismatch analysis Advanced optimization algorithms improve design centering and yield Built-in parasitic estimation flow helps design convergence by making it possible to quickly identify and analyze parasitic sensitivities prior to layout Support for multiple technologies to facilitate multi-chip design analysis Generate corners specific to your design Model calibration and validation support for Verilog A and Verilog AMS languages Supports design abstraction by providing the ability to generate Liberty and Wreal models from simulation results for system-level simulation

DESIGN CENTERING

With the set-up of tests and specifications already available in Analog Design Environment XL, users can simply add the ranges of devices they want to explore and use Analog Design Environment GXL optimization engines to find the optimum design. With an array of local and global optimization choices available, the user can control how the optimizer runs to center a design over nominal, all defined corners and with parasitic estimates in place.

PARASITIC RESIMULATION

Users can explore parasitic effects early in the design flow with the ability to assign parasitic estimates onto nets and ports of their design, without editing the schematic. An estimated view is compiled for simulation across all the tests and analysis options available in Analog Design Environment XL or GXL to identify areas to focus on in the design development. Similarly, post-layout extracted designs can also be submitted for validation against the design goals or compared against the original parasitic estimates. Parasitic effects can be easily copied from an extracted view back to

DESIGN FOR YIELD

Designers can use a series of both global and local optimization methods to center their design values to help maximize yield. For circuits requiring high design margins up to six-sigma, the internal design goals are tightened as it optimizes the parametric yield.

EXTENDED ANALYSIS

To further understand the behavior of a design, users can run Sensitivity analysis to identify weaknesses in a design to
DESIGN CHARACTERIZATION AND MODELING
A number of modeling options are available. Using a template-based methodology, a user can generate all the testbenches needed to explore a
design and extract the parametric data needed to build a calibrated model. Model languages supported are Verilog A and Verilog AMS with full calibration, while users can also create models from parametric data in Verilog D, Liberty, and Wreal model formats.

PARASITIC ANALYSIS

Supports exploration of design parasitic effects before layout Adds R, L, C, or K parasitic elements without altering the schematic Full simulation support of postextracted layouts Compare pre- and post-layout parasitic effects
SKILL PSF and PSF XL waveform formats SST2 waveform format Cadence SKILL

DESIGN OUTPUTS

XML database PSF and PSF XL SST2 Comma Separate Value Cadence proprietary script language: OCEAN

MULTI-TECHNOLOGY SUPPORT

Technology support is available to aid in the design of complex multi-chip solutions, and integrate them into a single package in conjunction with the Cadence Allegro system interconnect design platform.

OPTIMIZATION OPTIONS

Four local and global algorithm choices Optimize nominally or over corners, with or without parasitic estimates Run optimization with or without a starting point Improves design yield and design centering up to six-sigma margins

EXTENDED ANALYSES

Inherits all features and functionality from Virtuoso Analog Design Environment XL Sensitivity analysis on design parameters, statistical parameters, and design variables Mismatch analyses Generate design-specific corners High-yield measurement Calibrate behavioral models for more accurate system-level simulation Import simulation results to build Liberty models without prior knowledge of the language Multiple technology support with Allegro platform to enable System-inpackage (SiP) design

PLATFORM/OS

X86 Linux Sun Solaris IBM AIX

THIRD-PARTY SUPPORT

Interface support for all commercial circuit simulators, including Synopsys Hspice, Mentor Graphics Eldo, Silvaco SmartSpice, and Agilent ADS. In addition, users can integrate their own proprietary circuit simulator.
CADENCE SERVICES AND SUPPORT

Cadence application engineers can answer your technical questions by telephone, email, or Internetthey can also provide technical assistance and custom training Cadence certified instructors teach more than 70 courses and bring their real-world experience into the classroom More than 25 Internet Learning Series (iLS) online courses allow you the flexibility of training at your own computer via the Internet Cadence Online Support gives you 24x7 online access to a knowledgebase of the latest solutions, technical documentation, software downloads, and more

DESIGN INPUTS

OpenAccess data objects Cadence proprietary languages: OCEAN and MDL SPICE netlists Circuit design language (CDL) SPICE VHDL IEEE 1076-1993 Verilog IEEE1364
2011 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Allegro, Verilog, and Virtuoso are registered trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 21924 03/11 IW/MK/DM/PDF