Virtuoso Analog Design Environment XL
By Walter Hartong and Robert Schweiger
The IC industry is integrating more and more features onto one single chip. Needless to say, specications of these chips are getting quite complex. Unfortunately, design projects have to be completed within the same or less time, requiring more efcient design methodologies. Verication is becoming the critical design step. Even though the analog part of a typical mixed signal design project is relatively small, the design and integration of such parts into the full chip context is a difcult task. Stiff analog blocks like PLLs, switched mode power supplies, or RF parts are adding another dimension to the verication problem. What does this mean for the verication process? In the following article we would like to highlight some of the new key features of the Virtuoso ADE XL simulation environment. Virtuoso ADE L It is still three weeks to tapeout, but the stress level in the ofce is increasing from day to day. The analog block we designed over the past weeks is working ne somehow. The simulation results are pretty close to spec. Its Thursday afternoon. On Monday a design review meeting is scheduled where we need to present our latest verication results So far, we used the new Virtuoso ADE L environment to set up tests for each specication, simulation, analysis, and measurement (Figure 1-1). Along with the complete redesign of the Virtuoso Platform GUI the ADE L window got a new look and feel. However, the buttons and menus are pretty much at the same place as before. The window is resizable and the common Virtuoso features such as tear off menus and edit in place functions are available. All value elds in the form can be parameterized. e.g. we set the transient stop time to 5.0/VAR(freq). By this, we always match 5 cycles of the operating frequency in the transient simulation. ADE L provides a common simulation environment for all simulators. Thus, for each simulation task we can choose the right simulator Spectre, SpectreRF, Ultrasim, AMS, We applied various measurements to the simulation results and compared those results manually with the specication. Every time something has changed in the design, all the simulations have to be manually re-executed again. This is a time consuming and error prone task. Lets check out if there isnt a more efcient way that can help us fulll these tasks.
Figure 1-1: ADE L Simulation setup.
w w w. c a d e n c e. c o m / e u
Virtuoso ADE XL A couple of years ago Cadence released the Virtuoso Specication-driven Environment (VSdE) that enabled a spec-driven design methodology. The combination of ADE and VSdE now evolved into ADE XL. The new ADE XL environment adds another layer of productivity improvement and assistance on top of ADE L. Besides all standard analyses like DC, Transient, Stability etc., ADE XL also supports advanced analyses such as, Corner and Monte Carlo Analyses and Parametric and Combination Sweeps. Instead of directly starting with the circuit design the designer enters rst the specication into ADE XL. Rather than setting up many single ADE L sessions to manually verify the design, ADE XL allows us to combine these into an executable simulation plan. ADE L sessions that were previously dened and saved as a state le can be imported and reused in ADE XL. An ADE L state directly correlates to a test inside ADE XL. Each of our ADE L states includes a set of design variables which are local variables to one or several tests. Assuming that different tests share some common local variables, it is possible to overwrite those by global variables. See the strike-through local variables in the Parameter, Sweep, and Corner assistant (Figure 2-1). Global variables are also used for an easy setup of parametric sweeps and optimizations ranges. Check out the 0.7n:01n:2n value (from by to) of the disabled global variable l_ind in Figure 2-1.
Figure 2-1: ADE XL: Local and global variables. All ADE L states can be combined into a single ADE XL test setup which works like an executable simulation plan. The ADE XL simulation environment contains the testbench schematic surrounded by the Tests and Analyses assistant pane (Figure 2-2 overleaf). Each testbench is associated with one or more tests that are listed in the Test Editor assistant pane. One out of four different testbenches that we used in our current design is also shown in the active tab on top of the schematic window.

In the screenshot you will nd 6 tests. Three of them are currently enabled. Thus, our current setup in ADE XL is equivalent to 6 independent ADE L sessions. In fact, if you double click on one of the tests an ADE L like form will pop up and allows you to modify the setup in an ADE L like form. Once a simulation plan is dened it can be automatically executed by a single button click. A pass/fail report in the Outputs assistant pane gives you immediate feedback as to which specication values are fullled or not.
Figure 2-2: ADE XL: Simulation plan including multiple testbenches. Finally, the post processing for an automatic verication can be setup. The Calculator provides a rich set of calculation and measurement functions. The Outputs assistant (Figure 2-3) helps you to add the specication values in a straight forward manner. Each output expression could be either a waveform or a real type value. For each real type value you can enter a specication value and dene the valid specication range (e.g. gain greater then 1.6, dc power less than 8m).
Figure 2-3: ADE XL: Outputs assistant for specication and measurement setup.
As shown in the Outputs report almost all specication values are marked with a green box indicating that those specications are fullled. However, the yellow box next to the slewRate_fall value indicates that this value is a little bit outside of the specication range. After doing some minor design modications we have to re-run the verication again. Now the automized verication environment of ADE XL starts paying off in just re-executing the simulation plan again. Another pass/fail report showed that we managed to pull all values into the specied range under nominal conditions. But does our circuit also work under various process, voltage and temperature conditions? Now the tricky part of our design verication starts setting up the corners. In ADE XL its easy because you just have to ll out the left hand side of the Corner Setup assistant form (Figure 2-4). After dening the process, temperature and voltage combination it can be added as a new corner case. Corners can be named and tests can be enabled or disabled for each individual corner. In our example we enabled 4 tests for each of the 4 corners. Therefore, we end up with 16 simulation runs for this testcase. There was no sweep variable enabled otherwise a Sweep analysis would be combined with the Corner run.
Figure 2-4: ADE XL: Corner Setup form.
Once the Corner setup is nished its again only a one button click to execute the whole ADE XL conguration. Since its already Friday and the team meeting is approaching, we decided to setup a job policy that starts 5 simulations in parallel on our local multi-processor machine. Unfortunately, we dont have a server farm to distribute all jobs in parallel on different machines to reduce the runtime even further.
Figure 2-5: ADE XL: Job Policy Setup. While the simulation is running, we observe the rst problems in our design. The nominal values look o.k, however, the gain and the slewrate values are obviously out of spec for some corner cases. Hmm, I guess well have a problem on Monday

Figure 2-6: ADE XL: Simulation results for nominal and corner runs.
The nal results provide hard evidence that our design failed in all corners (Figure 2-6). Since its Friday afternoon our motivation to ne-tune the circuit by hand is shrinking from minute to minute - lets check out the optimization feature of ADE GXL.
Virtuoso ADE GXL The goals for the optimization are clear - meet the spec in all corners. Since we already entered this information into ADE XL, there is no additional effort required for the optimization goal setup. We just need to dene which variables and device parameters the optimizer is allowed to change. This includes the value ranges and step size as well as device matching constraints. Lets revisit the Parameters, Sweeps and Corner assistant and add some freedom in the design variables. Figure 3-1 shows the valid ranges for the design variables l_ind, r_ind and i_bias. E.g. the value of the inductor can vary from 1.5 nH to 2 nH in 0.1nH steps. This amount of freedom is used by the optimizer to tune the circuit to meet the specication in all dened corner cases.
Figure 3-1: ADE GXL: Denition of design variable range.
Back in the Run Mode assistant we can switch the simulation mode to optimization and let the tool automatically solve the problem over the weekend.
Figure 3-2: ADE GXL: Optimization setup. Monday morning. It was a great weekend but will it also be a great start in the new week? Figure 3-3 is the rst thing you see on your screen. All specs fullled over all corners. Thats what we wanted. Now lets have a closer look on the Variable Display assistant which shows the nal values of l_ind, r_ind und i_base. The solution that the optimizer found required to change the inductance l_ind to the minimum value and the parasitic resistance r_ind to the maximum value. I_base was set to the 10.7u which is pretty much in the middle of the specied range.
Figure 3-3: ADE XL: Final simulation results for nominal and corner runs.
Checkpoints in the ADE XL environment can be used to save the active conguration of data such as corners analysis setup, global variables, sweep, test denitions and simulation results. The environment creates a checkpoint each time a simulation is started and stores checkpoints in your project directory. You can restore fragments of a checkpoint (such as just the sweep setup), edit the data, run the simulation again, and access all previous simulation and postprocessing results.
Checkpoints appear as part of history items on the Data assistant pane (Figure 3-4) in the ADE XL environment. In addition a datasheet can be generated from any checkpoint. The level of detail of the datasheet can be controlled by the designer.

Figure 3-4: Data History pane including checkpoint example. Just before the meeting is about to start we do a right mouse button click on the last checkpoint in the history assistant and generate a datasheet containing the latest information about the project status (Figure 3-5).
Figure 3-5: ADE GXL: Automatic datasheet generation.
Summary ADE XL is a spec-driven verication environment that enables a fully automatic verication. Combining single ADE L sessions into an executable simulation plan is an invaluable feature to run the simulations and execute the postprocessing without any interaction of the designer. Moreover, a lot of tests that are dened during design phase can be reused for advanced analyses like the Corners. Especially, the Output assistant gives the designer a quick overview on the project status. Tedious and time consuming tasks, like the ne tuning of the nominal design over all specied corner cases, can be automized using the integrated optimizer. This fully automated and integrated design step is another clear productivity boost for the designer. As in most design projects, documentation always falls short due to a lack of time. With the datasheet generation feature of ADE XL, designs can now be easily and fully documented at anytime. The complete setup inside ADE XL makes the reuse of existing design IP for later changes or enhancements easy. Just use your ADE XL project setup and re-run it again
Cadence Design Systems Limited
Bagshot Road, Bracknell, Berkshire RG12 0PH, United Kingdom www.cadence.com/eu
2007 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence is a registered trademark and the Cadence logo is a trademark of Cadence Design Systems, Inc. All others are the property of their respective holders.