Cadence Design Systems Virtuoso Chip Assembly Router

Solve device problem

Videos (tutorials) Documents (manuals)


Analog Devices Automates and Accelerates Layout with Virtuoso Platform

Anthony Agrillo, a layout engineer at Analog Devices, works with a team that needs to build small-scale, non-timing digital blocks ...

Breakout routing for Intel's latest Mobile CPUs

The latest Intel CPU routing guidelines call for "snake" or "slalom" style breakout routing. The latest Allegro PCB ISR release now ...

PCB-driven BGA Ball Map Optimization Using OrbitIO Architectural Planning

In this movie we start with an existing PCB design that was created in Allegro (schematic in Design Entry-HDL and layout in ...