virt u o so C H I P A S S E M B LY R OUT E R
Figure 1: All components of the Virtuoso platform work together to support fast, silicon-accurate differentiated custom silicon

G0007A

DATASHEET
The vIRTUOSO custom design platform
When design objectives dictate manipulating precise analog quantitiesvoltages, currents, charges, and continuous ratios of parameter values such as resistance and capacitancecompanies turn to custom design. Full-custom design maximizes performance while minimizing area and power. However, it requires significant handcrafting by a select set of engineers with very high skill levels. In addition, custom analog circuits are more sensitive to physical effects, which are exacerbated at new, nanometer process nodes. The Virtuoso custom design platform accelerates the design of custom ICs across various process nodes. By selectively automating aspects of custom analog design and providing advanced technologies integrated on a common database, it allows engineers to focus on precision crafting their designs without sacrificing creativity to repetitive manual tasks.
The Cadence Virtuoso Chip Assembly Router is the custom IC transistor, cell, block, and advanced chip-level interconnect technology in the Virtuoso custom design platform. The Virtuoso Chip Assembly Router is a constraint- and design-rule-driven, interactive, and fully automatic shape-based router. It supports both block authoring and chip authoring solutions for custom digital, mixedsignal, and analog designs at any level of the hierarchy.

PERFORMAN CE

PARA SI
Design Specification Multi-Mode Simulation Accelerated Layout Silicon Analysis Chip Finishing
Open Database Constraint Management

PDKs Customer IP

virtuoso CHIP ASSEMBLY ROUTER
The Virtuoso Chip Assembly Router is a design constraint- and process rule-driven, interactive, and fully automatic shapebased gridless router that supports transistor, cell, block and chip-level routing for custom digital, mixed-signal, and analog designs at any level of the design hierarchy. The Virtuoso Chip Assembly Router is interoperable with both the Virtuoso custom design platform and the Cadence Encounter digital IC design platform. A unique blend of interactive and automatic design constraint- and process rule-driven routing features are provided, simplifying the most complex interconnect issues and maximizing productivity. The Virtuoso Chip Assembly Router supports 90nm and above process technology rules and is available on OpenAccess.

Benefits

Increased productivity and design quality through the specification and adherence of complex constraint and process rules during interactive and automatic routing Simplified routing process using advanced features such as interactive push and shove, multi-net/bus, power, shielding, differential pairs, length, and crosstalk (see Figure 2) Intuitive, easy-to-use interface with menu, command, and do file use options Open and flexible interoperability with the Virtuoso Schematic Editor and Virtuoso XL Layout Editor to support dynamic cross-probing and editing (see Figure 3). Interoperability with the SoC Encounter system is also supported
Figure 2: Interactive and automatic bus and power routing
Figure 3: Real-time interoperability with the Virtuoso Schematic Editor and the Virtuoso XL Layout Editor to provide accurate and accelerated block and chip design
V irtu o s o C H IP ASSEMBLY R OUTER

w w w. c a d e n ce.com

Features
Design constraint and process rule-driven routing
The Virtuoso Chip Assembly Router accelerates the design process by providing a comprehensive set of design constraints and process rules that are specified, managed, and obeyed in a hierarchical precedence order during interactive and automatic routing. Dynamic real-time checking is performed during interactive routing with a halo display and automatic enforcement of the rules (see Figure 4). Automatic routing rules are obeyed during routing with optional post-route checking of the entire design or selective areas of the design.
Figure 4: Interactive routing uses connectivity-, constraint-, and design-ruledriven features with push and shove for fast and accurate editing
Advanced interactive routing features
The Virtuoso Chip Assembly Router simplifies the routing process with advanced interactive and automatic routing features. Interactive routing provides push and shove routing that eliminates the need to move other adjacent routing obstructions. Multi-net/bus routing supports the routing of two or more nets to efficiently route large bus structures. Power is fully automated with pin-to-trunk, cell row, block ring, I/O ring, and stripes/mesh features.

Flexible support custom block and chip routing
The Virtuoso Chip Assembly Router simplifies the adoption and implementation of its unique custom block and chip routing solution with an intuitive and easy-to-use interface. It dynamically interoperates with Virtuoso Schematic E0ditor schematics and Virtuoso XL Layout Editor layouts, with cross-probing of instances and nets in addition to dynamic editing changes. Virtuoso XL Layout Editor compatibility features are provided to map mouse and keyboard binding, selection, zoom, and panning functions from Virtuoso XL Layout Editor to Virtuoso Chip Assembly Router. The Virtuoso Chip Assembly Router is interoperable with Virtuoso Chip Editor and SoC Encounter digital floorplanning and routing tools. It is also interoperable through LEF/DEF and the OpenAccess database.

www.cadence.com

Figure 5: Interactive/automatic routing for analog, mixed-signal, and custom digital designs at the device, cell, block, and top levels

SPECIFICATIONS

Interactive and automatic routing
Variable width and spacing rules Antennae rule checking and fixing 90nm process rule support (via adjacency, width-based, proximity, and maximum width) Advanced interactive routing with push and shove, automatic completion, and route-to-cursor Automatic global, track, and detail routing Congestion analysis and automatic channel sizing Device-, cell-, block-, and top-level chip assembly routing support (see Figure 5) ECO functions Design and rule reporting
Automatic power routing (pin-to-trunk, cell row, block ring, I/O ring, and stripes/ mesh) Pre-route pin checking to insure routability Incremental design and selective net routing Polygon editor Topology editor Automatic specialty routing support for shielding, differential pairs, and symmetry (see Figure 6) Net length control including minimum, maximum, and matched Multiple via, via array, and minimum area via support Pin width matching and tapering Manufacturing and yield enhancement post-processing
Virt uo so CHIP ASSEMBLY R OUTER

Design Inputs

Cadence CDBA database OpenAccess database LEF/DEF format STREAM format EDIF
Cadence services and support
Customer-focused solutions that increase ROI, reduce risk, and achieve your design goals faster Collaborative approach and design infrastructurevirtual teaming Proven methodology and flow tuned to your design environment Design and EDA implementation expertise Product and flow training to fit your needs and preferred learning style Over 80 instructor-led coursescertified instructors, real world experience More than 25 Internet Learning Series (iLS) online courses
Cadence customer support that keeps your design team productive Cadence applications engineers provide technical assistance SourceLink online support gives you access to software updates, technical documentation, and more24 hours a day, seven days a week

Design outputs

Cadence CDBA database OpenAccess design data DEF format STREAM format
For more information Email us at info@cadence.com or log on to www.cadence.com

Platform/OS

Sun/Solaris HP-UX IBM AIX Linux
Figure 6: Analog, mixed-signal routing featuresauto net shielding
Cadence Design Systems, Inc.
2655 Seely Avenue San Jose, CA 95134 P:+1.800.746.6223 (within US) +1.408.943.1234 (outside US) www.cadence.com
2007 Cadence Design Systems, Inc. All rights reserved. Cadence, Encounter, Virtuoso, and SourceLink are registered trademarks and the Cadence logo and SoC Encounter are trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 7179B 0207/MK/NM/JA/PDF

VIRTUOSO CUSTOM DESIGN PLATFORM GXL
As the high-end custom block authoring physical layout tool for the Virtuoso platform, Virtuoso Layout Suite GXL supports custom digital, mixed-signal and analog designs at the device, cell, and block levels. These accelerated features provide advanced automation to accelerate custom block authoring.
Figure 1: All components of the Virtuoso platform work together to support fast, silicon-accurate differentiated custom silicon

G0007A

DATASHEET
The Virtuoso Analog Design Environment GXL is designed to help users create manufacturing-robust designs. It gives designers access to a new parasitic estimation and comparison flow and optimization algorithms that help to center a design better for yield improvement and advanced matching and sensitivity analyses. This makes it possible to completely explore the design for problem areas. In addition, it i ncorporates the same advanced custom IC environment used within the Cadence Allegro platform for creating system-inpackage (SiP) designs.
The Cadence Virtuoso custom design platform is the i ndustrys leading design system for complete front-to-back analog, RF, mixed-signal, and custom digital design. The GXL tier comprises the platforms most advanced configuration ofdesign and analysis technologies, including expanded physical design capabilities and an enhanced simulation e nvironment.

PERFORMAN CE

PARA SI
Design Specification Multi-mode Simulation Accelerated Layout Silicon Analysis Chip Finishing
Open Database Constraint Management

PDKs Customer IP

It includes capabilities for device generation and editing, block floorplanning, automatic placement, and interactive routing. Driven by a comprehensive analog constraint capture and management system, Virtuoso Layout Suite GXL makes design reuse, engineering change, retargeting, and process migration possible. It uses unique placement and routing engines to automatically or interactively generate and optimize devicegeometry, place devices (adhering to constraints) within a cell footprint, andsubsequently complete the layout interconnect routing.
Advanced optimization algorithms improve design centering and yield Built-in parasitic estimation and comparison flow help to quickly identify severe parasitics inside the design
AUTOMATIC PLACEMENT, ROUTING AND EDITING
The GXL placement engine places devices for density, performance, and precision while maintaining symmetries and matching. Device generators produce geometry for complex devices with varying aspect ratios (variants), and then the placer explores these device variants for better packing. Similarly, the placer can optimize the cell footprint to accommodate the cell contents. Floating pins are placed to achieve optimal signal flow and proper spacing is reserved for wide wires. While optimizing latchup, the placer merges wells and creates guard ringsall automatically and with initial constraints respected throughout the placement process. The GXL routing engine optimizes wiring while adhering to the constraints specified in the Constraint Editor. The router handles arbitrary width and spacing constraints as well as known cross-talk problems. It further supports routing of self-symmetric nets to achieve balanced routing for structures such as T-nets. Also included is support for partially symmetric netsusers can choose to route the critical segments of their nets in a symmetric and highly matched form, while letting the router choose the shortest path for the non-critical net segments. The interactive editing mode allows designers to move and align devices and change their orientation and shape. Changes to devices automatically regenerate any associated wells or guard rings. Real-time DRC ensures layout quality. Designers can reroute nets and fix the location of critical wires. When the routing of one net is modified, any symmetric nets mirror the new path. As always, the layout synthesis engine respects constraints throughout the routing process.

FEATURES

PARASITIC RESIMULATION FLOW
Users can place parasitic estimates onto their schematics. These are then translated into wire constraints, which can prompt a layout person that certain nets are critical and their length and width should be minimized to minimize parasitics introduced into the system. Post-extraction, the parasitic estimates can be quickly compared to the extracted parasitics to find trouble spots within the design.

BENEFITS

Accelerated block authoring through connectivity-driven features and flow, schematic or netlist. Also promotes correct-by-construction LVS correct layout to reduce verification iterations Increased productivity and design quality with constraint- and designrule-driven features to automatically ensure design and process correctness in real time Simplification and optimization ofdevice generation using a new menu-driven QuickCell feature or thestandard SKILL programmable parameterized cells Efficient planning, placement and routing of large block designs with custom floorplanning, automatic placement, and advanced interactive routing features Enhanced analog design team p roductivity gainsup to 10x over manual methods Unique support for meeting new performance specifications, and for handling design reuse, technology migration, and ECOs

DESIGN FOR YIELD FLOW

Designers can use a series of both global and local optimization methods to center their design values to help maximize yield. This optimizes the parametric yield of circuits by extrapolating the statistical distribution up to six sigma margins.
ADVANCED LAYOUT AUTOMATION FOR SIMPLIFIED AND OPTIMIZED BLOCK AUTHORING
Virtuoso Layout Suite GXL simplifies and optimizes block authoring with advanced layout automation features that leverage the design-ruledriven functions and flow of the Virtuoso platform. Menu-driven parameterized cells (QCells) or SKILL programmable parameterized cells (Pcells) simplify and optimize device generation and editing. Floorplanning and automatic placement simplifies and optimizes the design planning and location of devices. Advanced shape-based constraint and design-rule-driven routing simplifies and optimizes the tedious interconnect task.

www.cadence.com

VIR TUOSO CUSTOM DESIGN PLATFORM GXL
PRECISION DEVICE GENERATION AND LAYOUT SYNTHESIS
Virtoso platform GXL provides several options for generating the individual devices that are to be used by the placer. It supports Pcells (including ROD), the users proprietary cells, and even legacy GDSII layouts imported as subcells. For more complex devices, the use of one of the precision generators (Modgens) is recommended. Complex quad-FETs, interdigitated and matched FET arrays and highly matched precise passives are supported. Modgens provide the ability to map several devices to one complex group and then edit the whole arrangement easily. Virtuoso platform GXL also provides a comprehensive layout synthesis engine that generates and optimizes device geometry, cell foot print, device placement and wire routing as guided by the analog constraints for the design (see Figures 2 and 3)

SPECIFICATIONS

LAYOUT CREATION AND EDITING
Interactive Pick-From-Schematic or automated Gen-From-Source device selection Menu-driven QCell (QuickCell) or SKILLprogrammable automated device generation ExpressPcell mechanism to speed up evaluation of parameterized cells and make them more interoperable with third-party tools Automated device editing, including abutment, pin permutation, folding, chaining, and cloning Menu-driven or programmable multi-part path (MPP) feature for guard rings, slotting, etc. Design-rule driven-editing with real-time notification or enforcement of process rules Dynamic measurement Constraint-driven specification, management, and real-time notification or enforcement

Figure 2: Virtuoso Analog Design Environment GXL
Figure 3: Virtuoso Layout Suite GXL
Block floorplanning with support rectilinear blocks, pin optimization, andtemplate support Automatic constraint- and design-ruledriven placement of pins, devices, cells, and blocks Advanced shape-based constraint and design-rule-driven interactive routing Bi-directional interfacing to Virtuoso Schematic Editor, Cadence Chip Assembly router and the Cadence Space-based Router ECO support Virtuoso Layout Migration integrated into Virtuoso Layout Suite GXL Legacy non-connectivity design importing and connectivity mapping Cadence Diva and Cadence Assura physical verification support Comprehensive device and cell support All analog cells including opamps, charge pumps, bandgaps, comparators, VCOs, regulators and others in technology portable manner. Provides support for ADCs, PLLs, DLLs and others Supports Pcells including ROD, proprietary cells, and legacy GDSII layouts Complex quad-FETs, interdigitated,matched FET arrays and matched passives Supports guard rings, dummy devices wells, and mulit-part paths Comprehensive integration Cadence DFII library structure captures constraints, devices, parameters, and connectivity Full compatibility with Virtuoso XL Layout Editor connectivity model Includes technology set-up wizard for fast set-up of a new processes Tightly coupled ECO flow
VIRTUOSO Custom design PLATFORM GXL features
Virtuoso Analog Design Environment GXL
New Common Cockpit New Icon Style Multi-Tab Support Bookmarks & History Updated Pulldown Menus Window Cong Support World View Assistant Search Assistant Property Editor Assistant Navigator Assistant Constraint Browser Design Explorer Single Testbench Simple Parametric Analysis Device Checking Global Variable Support Updated Wavescan New Calculator Simulation Support: Virtuoso Multi-Mode Simulation, HSPICE Circuit Optimization Behavioral Model Generation Parasitic Resimulation Yield Analysis Mismatch/Sensitivity Analysis SiP Support Basic Polygon Editing QCells DRD Editing A & D Device Placer ModGens Cell Planning Chip Assembly Router Floorplanning Cell Block Placer Layout Optimization Space-Based Router

X X X X X X X X

Virtuoso Layout Suite GXL

X X X X X X X X X X X X

X X X X X X X X X X X X X X X X X X X X X X X X
Automatic and interactive capabilities Automatic device and device array generation Automatic device placement, including symmetry and matching Automatic routing with symmetry and cross-talk avoidance Move, align and modify devices Interactive routing with symmetric update Real-time design rule and constraint checking

SCHEMATIC AND SIMULATION ENVIRONMENT
Virtuoso Schematic Editor or netlist-driven hierarchical layout New analog schematic generator to convert netlists into schematics Simulation environment extensions Inherits all features and functionality from Virtuoso Analog Design Environment XL Tools for comparing and fixing design parasitics
Local and Global Optimization toimprove design yield and design centering Connections to Allegro platform to enable SiP design Design characterization and modeling features to create Verilog A models Sensitivity and Matching analyses

DESIGN OUTPUTS

OpenAccess database SKILL STREAM format
CADENCE SERVICES AND SUPPORT
Cadence application engineers can answer your technical questions by telephone, email, or internetthey can also provide technical assistance and custom training. SourceLink online customer support gives you answers to your technical questions24 hours a day, 7 days a weekincluding the latest in quarterly software rollups, product release i nformation, technical documentation, software updates, and more.

PLATFORM/OS

Sun/Solaris HP-UX IBM AIX LINUX

DESIGN INPUTS

SKILL STREAM format OpenAccess database Virtuoso Schematic Editor L or XL CDL and SPICE netlist format Virtuoso Chip Assembly Router database format

THIRD-PARTY SUPPORT

SKILL-based tools and functions OpenAccess tools and functions Process design kits (Please reference the Cadence Virtuoso PDK datasheet for more information)
Cadence-certified instructors teach more than 80 courses and bring theirreal-world experience into the classroom. More than 25 Internet Learning Series (iLS) online courses allow you the flexibility of training at your own c omputer via the Internet.
For more information, Email us at

info@cadence.com

or visit
2008 Cadence Design Systems, Inc. All rights reserved. Cadence, Allegro, Assura, Diva, SourceLink, and Virtuoso are registered trademarks and the Cadence logo is a trademark of Cadence Design Systems, Inc. All others are properties of their respective holders. 20584/7055B 0408 KM /FLD /CS/PDF