What if you could get immediate feedback on how a layout feature or change impacts electrical design requirements like ...
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Anthony Agrillo, a layout engineer at Analog Devices, works with a team that needs to build small-scale, non-timing digital blocks ...
Europractice Cadence 2014-15 release IC Package release_version ASSURA 4.1 CONFRML14.1 CTOS 14.1 EDI ET ETS 13.1 EXT Description Assura(TM) Design Rule Checker Layout Vs. Schematic Verifier Multiprocessor Option CCD Multi-Constraint Check Encounter (R) Conformal Constraint Designer - XL Low Power GXL ECO C-to-Silicon Compiler L Digital Implementation System CPU Accelerator Mixed Signal Giga Scale Universal 20 Clock Concurrent Optimization Advanced Node True Time ATPG to RC DFT Architect Test LBIST MBIST Diagnostics Basic Library Characterizer EPS Analysis Timing System-XL QRC Modeling20 Extraction Modeling QRCX Display Technology
Europractice Cadence 2014-15 release IC 6.1.6 Virtuoso(R) Layout Suite - GXL Analog Design Environment Virtuoso Implementation Aware Option Power System XL EAD Advanced Electrical Analysis Cadence(R) SKILL Development EDIF 200 Reader Schematic Editor Visualization & Dracula(R) Rule Checker DFM SMG Runtime Behavioral Modeling Oasis Run-Time Diva(R) Vs. Verifier Parasitic Extractor ...
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