VIRTUOSO CUSTOM DESIGN PLATFORM GXL
As the high-end custom block authoring physical layout tool for the Virtuoso platform, Virtuoso Layout Suite GXL supports custom digital, mixed-signal and analog designs at the device, cell, and block levels. These accelerated features provide advanced automation to accelerate custom block authoring.
Figure 1: All components of the Virtuoso platform work together to support fast, silicon-accurate differentiated custom silicon

G0007A

DATASHEET
The Virtuoso Analog Design Environment GXL is designed to help users create manufacturing-robust designs. It gives designers access to a new parasitic estimation and comparison flow and optimization algorithms that help to center a design better for yield improvement and advanced matching and sensitivity analyses. This makes it possible to completely explore the design for problem areas. In addition, it i ncorporates the same advanced custom IC environment used within the Cadence Allegro platform for creating system-inpackage (SiP) designs.
The Cadence Virtuoso custom design platform is the i ndustrys leading design system for complete front-to-back analog, RF, mixed-signal, and custom digital design. The GXL tier comprises the platforms most advanced configuration ofdesign and analysis technologies, including expanded physical design capabilities and an enhanced simulation e nvironment.

PERFORMAN CE

PARA SI
Design Specification Multi-mode Simulation Accelerated Layout Silicon Analysis Chip Finishing
Open Database Constraint Management

PDKs Customer IP

It includes capabilities for device generation and editing, block floorplanning, automatic placement, and interactive routing. Driven by a comprehensive analog constraint capture and management system, Virtuoso Layout Suite GXL makes design reuse, engineering change, retargeting, and process migration possible. It uses unique placement and routing engines to automatically or interactively generate and optimize devicegeometry, place devices (adhering to constraints) within a cell footprint, andsubsequently complete the layout interconnect routing.
Advanced optimization algorithms improve design centering and yield Built-in parasitic estimation and comparison flow help to quickly identify severe parasitics inside the design
AUTOMATIC PLACEMENT, ROUTING AND EDITING
The GXL placement engine places devices for density, performance, and precision while maintaining symmetries and matching. Device generators produce geometry for complex devices with varying aspect ratios (variants), and then the placer explores these device variants for better packing. Similarly, the placer can optimize the cell footprint to accommodate the cell contents. Floating pins are placed to achieve optimal signal flow and proper spacing is reserved for wide wires. While optimizing latchup, the placer merges wells and creates guard ringsall automatically and with initial constraints respected throughout the placement process. The GXL routing engine optimizes wiring while adhering to the constraints specified in the Constraint Editor. The router handles arbitrary width and spacing constraints as well as known cross-talk problems. It further supports routing of self-symmetric nets to achieve balanced routing for structures such as T-nets. Also included is support for partially symmetric netsusers can choose to route the critical segments of their nets in a symmetric and highly matched form, while letting the router choose the shortest path for the non-critical net segments. The interactive editing mode allows designers to move and align devices and change their orientation and shape. Changes to devices automatically regenerate any associated wells or guard rings. Real-time DRC ensures layout quality. Designers can reroute nets and fix the location of critical wires. When the routing of one net is modified, any symmetric nets mirror the new path. As always, the layout synthesis engine respects constraints throughout the routing process.

FEATURES

PARASITIC RESIMULATION FLOW
Users can place parasitic estimates onto their schematics. These are then translated into wire constraints, which can prompt a layout person that certain nets are critical and their length and width should be minimized to minimize parasitics introduced into the system. Post-extraction, the parasitic estimates can be quickly compared to the extracted parasitics to find trouble spots within the design.

BENEFITS

Accelerated block authoring through connectivity-driven features and flow, schematic or netlist. Also promotes correct-by-construction LVS correct layout to reduce verification iterations Increased productivity and design quality with constraint- and designrule-driven features to automatically ensure design and process correctness in real time Simplification and optimization ofdevice generation using a new menu-driven QuickCell feature or thestandard SKILL programmable parameterized cells Efficient planning, placement and routing of large block designs with custom floorplanning, automatic placement, and advanced interactive routing features Enhanced analog design team p roductivity gainsup to 10x over manual methods Unique support for meeting new performance specifications, and for handling design reuse, technology migration, and ECOs

DESIGN FOR YIELD FLOW

Designers can use a series of both global and local optimization methods to center their design values to help maximize yield. This optimizes the parametric yield of circuits by extrapolating the statistical distribution up to six sigma margins.
ADVANCED LAYOUT AUTOMATION FOR SIMPLIFIED AND OPTIMIZED BLOCK AUTHORING
Virtuoso Layout Suite GXL simplifies and optimizes block authoring with advanced layout automation features that leverage the design-ruledriven functions and flow of the Virtuoso platform. Menu-driven parameterized cells (QCells) or SKILL programmable parameterized cells (Pcells) simplify and optimize device generation and editing. Floorplanning and automatic placement simplifies and optimizes the design planning and location of devices. Advanced shape-based constraint and design-rule-driven routing simplifies and optimizes the tedious interconnect task.

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VIR TUOSO CUSTOM DESIGN PLATFORM GXL
PRECISION DEVICE GENERATION AND LAYOUT SYNTHESIS
Virtoso platform GXL provides several options for generating the individual devices that are to be used by the placer. It supports Pcells (including ROD), the users proprietary cells, and even legacy GDSII layouts imported as subcells. For more complex devices, the use of one of the precision generators (Modgens) is recommended. Complex quad-FETs, interdigitated and matched FET arrays and highly matched precise passives are supported. Modgens provide the ability to map several devices to one complex group and then edit the whole arrangement easily. Virtuoso platform GXL also provides a comprehensive layout synthesis engine that generates and optimizes device geometry, cell foot print, device placement and wire routing as guided by the analog constraints for the design (see Figures 2 and 3)

SPECIFICATIONS

LAYOUT CREATION AND EDITING
Interactive Pick-From-Schematic or automated Gen-From-Source device selection Menu-driven QCell (QuickCell) or SKILLprogrammable automated device generation ExpressPcell mechanism to speed up evaluation of parameterized cells and make them more interoperable with third-party tools Automated device editing, including abutment, pin permutation, folding, chaining, and cloning Menu-driven or programmable multi-part path (MPP) feature for guard rings, slotting, etc. Design-rule driven-editing with real-time notification or enforcement of process rules Dynamic measurement Constraint-driven specification, management, and real-time notification or enforcement
Figure 2: Virtuoso Analog Design Environment GXL
Figure 3: Virtuoso Layout Suite GXL
Block floorplanning with support rectilinear blocks, pin optimization, andtemplate support Automatic constraint- and design-ruledriven placement of pins, devices, cells, and blocks Advanced shape-based constraint and design-rule-driven interactive routing Bi-directional interfacing to Virtuoso Schematic Editor, Cadence Chip Assembly router and the Cadence Space-based Router ECO support Virtuoso Layout Migration integrated into Virtuoso Layout Suite GXL Legacy non-connectivity design importing and connectivity mapping Cadence Diva and Cadence Assura physical verification support Comprehensive device and cell support All analog cells including opamps, charge pumps, bandgaps, comparators, VCOs, regulators and others in technology portable manner. Provides support for ADCs, PLLs, DLLs and others Supports Pcells including ROD, proprietary cells, and legacy GDSII layouts Complex quad-FETs, interdigitated,matched FET arrays and matched passives Supports guard rings, dummy devices wells, and mulit-part paths Comprehensive integration Cadence DFII library structure captures constraints, devices, parameters, and connectivity Full compatibility with Virtuoso XL Layout Editor connectivity model Includes technology set-up wizard for fast set-up of a new processes Tightly coupled ECO flow
VIRTUOSO Custom design PLATFORM GXL features
Virtuoso Analog Design Environment GXL
New Common Cockpit New Icon Style Multi-Tab Support Bookmarks & History Updated Pulldown Menus Window Cong Support World View Assistant Search Assistant Property Editor Assistant Navigator Assistant Constraint Browser Design Explorer Single Testbench Simple Parametric Analysis Device Checking Global Variable Support Updated Wavescan New Calculator Simulation Support: Virtuoso Multi-Mode Simulation, HSPICE Circuit Optimization Behavioral Model Generation Parasitic Resimulation Yield Analysis Mismatch/Sensitivity Analysis SiP Support Basic Polygon Editing QCells DRD Editing A & D Device Placer ModGens Cell Planning Chip Assembly Router Floorplanning Cell Block Placer Layout Optimization Space-Based Router

X X X X X X X X

Virtuoso Layout Suite GXL

X X X X X X X X X X X X

X X X X X X X X X X X X X X X X X X X X X X X X
Automatic and interactive capabilities Automatic device and device array generation Automatic device placement, including symmetry and matching Automatic routing with symmetry and cross-talk avoidance Move, align and modify devices Interactive routing with symmetric update Real-time design rule and constraint checking
SCHEMATIC AND SIMULATION ENVIRONMENT
Virtuoso Schematic Editor or netlist-driven hierarchical layout New analog schematic generator to convert netlists into schematics Simulation environment extensions Inherits all features and functionality from Virtuoso Analog Design Environment XL Tools for comparing and fixing design parasitics
Local and Global Optimization toimprove design yield and design centering Connections to Allegro platform to enable SiP design Design characterization and modeling features to create Verilog A models Sensitivity and Matching analyses

DESIGN OUTPUTS

OpenAccess database SKILL STREAM format
CADENCE SERVICES AND SUPPORT
Cadence application engineers can answer your technical questions by telephone, email, or internetthey can also provide technical assistance and custom training. SourceLink online customer support gives you answers to your technical questions24 hours a day, 7 days a weekincluding the latest in quarterly software rollups, product release i nformation, technical documentation, software updates, and more.

PLATFORM/OS

Sun/Solaris HP-UX IBM AIX LINUX

DESIGN INPUTS

SKILL STREAM format OpenAccess database Virtuoso Schematic Editor L or XL CDL and SPICE netlist format Virtuoso Chip Assembly Router database format

THIRD-PARTY SUPPORT

SKILL-based tools and functions OpenAccess tools and functions Process design kits (Please reference the Cadence Virtuoso PDK datasheet for more information)
Cadence-certified instructors teach more than 80 courses and bring theirreal-world experience into the classroom. More than 25 Internet Learning Series (iLS) online courses allow you the flexibility of training at your own c omputer via the Internet.
For more information, Email us at

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or visit
2008 Cadence Design Systems, Inc. All rights reserved. Cadence, Allegro, Assura, Diva, SourceLink, and Virtuoso are registered trademarks and the Cadence logo is a trademark of Cadence Design Systems, Inc. All others are properties of their respective holders. 20584/7055B 0408 KM /FLD /CS/PDF

Virtuoso Layout Suite GXL

DATASHEET

VIRTUOSO LAYOUT SUITE GXL
Virtuoso Layout Suite GXL accelerates custom layout with a comprehensive set of user-configurable, easy-to-use pure polygon layout features within a fully hierarchical environment. Additional layout productivity is provided through optional parameterized cells (Pcells) and SKILL, the powerful scripting language that provides direct database access, tool configuration, and interoperability with other tools. The industry leader in advanced custom layout automation, Virtuoso Layout Suite GXL offers a robust set of technologies for custom placement and routing, layout optimization, module generation, and analog/mixed-signal floorplanning. These technologies have revolutionized the way layout is generated, complementing hand-crafted layout with rich levels of automation that boost layout designer productivity by 2-20x.
Part of the Cadence Virtuoso Layout Suite family of products, Virtuoso Layout Suite GXL is a collection of fully automated layout capabilities such as custom placement and routing, layout optimization, module generation, and analog/mixed-signal floorplanning. It supports the physical implementation of analog, custom-digital, and mixed-signal designs at the device, cell, block, and chip level. Built upon the connectivity- and constraint-driven layout environment of the Virtuoso custom design platform, Virtuoso Layout Suite GXL ensures faster convergence on design goals and more efficient layout implementation.
Figure 1: The industry-standard Virtuoso Layout Suite user interface
Virtuoso Layout Suite GXL is built upon the fully featured connectivity- and constraint-driven environment that is at the core of the Virtuoso platform. These technologies are the fundamental building blocks for realizing optimized, first-time successful silicon.
VIRTUOSO CUSTOM DESIGN PLATFORM
The Virtuoso custom design platform integrates Virtuoso Schematic Editor, Virtuoso Analog Design Environment, Virtuoso Multi-Mode Simulation, and the Virtuoso Layout Suite to speed convergence on design goals at every step for front-to-back custom analog, digital, RF, and mixed-signal design flows. The platform is backed by the largest number of process design kits (PDKs) available from the worlds leading foundries, for process nodes everywhere from mature 0.35um to advanced 28nm. It is built on the OpenAccess database, engineered by Cadence for industry-wide interoperability. The Virtuoso custom design platform also interoperates with the Cadence Encounter digital implementation platform technologies via the OpenAccess database, providing a single, complete, coherent, and unified representation of design intent. This design intent is preserved throughout the entire physical implementation phase while operating with multiple levels of design abstractions (device, cell, block, chip), speeding design convergence to realize silicon for complex mixed-signal and system-on-chip designs.
Speeds design convergence on complex advanced node designs with region-based interactive design-rule check fixing Includes full featured yield optimization driven by design intent and recommended design rules Includes fully automated process retargeting via hierarchical layout migration

VIRTUOSO LAYOUT SUITE FAMILY
The Virtuoso Layout Suite family of products comprises the layout environment of the industry-standard Virtuoso custom design platform, a complete solution for front-to-back custom analog, digital, RF, and mixedsignal design. The Virtuoso Layout Suite preserves design intent throughout the entire physical implementation process, while managing multiple levels of design abstractions from device, cell, and block levels through to the full-chip level. It provides the fastest path to design convergence for mature and advanced node silicon realization. The Virtuoso Layout Suite includes three tiers of increasing layout automation and designer productivity. By selectively automating aspects of custom-analog design and providing advanced technologies integrated on a common database, engineers can focus on precision-crafting their designs without sacrificing creativity to repetitive manual tasks. In addition to Virtuoso Layout Suite GXL, the suite includes: Virtuoso Layout Suite L, a basic design-creation and implementation environment focused on layout productivity Virtuoso Layout Suite XL, an extension to the L tier, is built upon common design intentthe connectivity- and constraint-driven environment at the core of the Virtuoso platform
VIRTUOSO LAYOUT SUITE GXL FEATURES
Hierarchical, multi-window, multi-tabbed editing environment
Virtuoso Layout Suite GXL enables users to open multiple cells or blocks in a single editing session, or to open different views of the same design, ensuring consistency in complex designs. Users can also open and manage their designs more quickly by using tabs, bookmarks, and history similar to the functionality in todays popular web browsers. A tabbed approach to viewing layouts simplifies window management and provides fast access to multiple designs in an intuitive manner. This is particularly helpful when copying portions of a layout from one design to another, or when using a pre-existing design as a reference. Users can bookmark commonly accessed designs or view the history of opened designs. Bookmarks can be a single cell or a group of cells that appear in individual tabs. A personal bookmarks toolbar makes accessing commonly used bookmarks extremely quick and easy. Virtuoso Layout Suite GXL shares the same look and feel with Virtuoso Schematic Editor and Virtuoso Analog Design Environment. This consistent use model enables a fully featured, intuitive, front-to-back design flow.
VIRTUOSO LAYOUT SUITE GXL BENEFITS
The GXL configuration includes all Virtuoso Layout Suite L and XL features (see respective datasheets) and offers these additional benefits: Speeds convergence on advanced node designs with the high-performance, high-capacity Virtuoso Space-Based Router Supports soft- and hard-design abstracts for full-custom floorplanning for both block- and chip-level designs Features advanced module generation for complex interdigitation patterns built upon SKILL-based Pcells Features full custom-analog and custom-digital placement that is fully design-intent and design-rule aware

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Docked layout assistants
Docked assistants are user-interface widgets that surround the main layout editing canvas. Virtuoso Layout Suite GXL includes a rich set of assistants, including a Design Navigator and Property Editor, Search, and World View Assistants that significantly increase layout productivity. Through the Design Navigator, users can quickly access specific cells that may be in a lower level of the design hierarchy via a tree browser built into the Design Navigator. Cells, nets, and pins can also be selected, sorted, and probed through the Design Navigator. This is a very effective feature when designing and debugging complex layouts. The Property Editor Assistant is a new twist on the traditional Edit Properties pop-up form. The streamlined interface improves the effective area of the layout canvas space while decreasing mouse clicks and wasteful pop-up dialog boxes. Through the Search Assistant, layout engineers have comprehensive search capabilities. The Search Assistant categorizes the found items into logical groups (cells, pin names, properties, etc.) and displays these items in a tree structure. This makes it very easy for users to find and access information within the design, the design libraries, menu commands, and even the SKILL manuals. Context-sensitive menus and double-click operations allow for rapid operations on selected results. The World View Assistant is an intuitive navigational aid that allows users to always see the entire design, even while zoomed into a specific section of the layout. This Assistant is particularly useful when working with large layouts where users have to perform editing while zoomed in on a portion of the design. The ability to concentrate on a specific section of layout while still viewing the overall layout decreases the need for repetitive panning and zooming. This translates into fewer mouse clicks, which improves layout productivity.
Highly customizable editing features
The architecture and implementation of the Cadence Design Framework II and the OpenAccess database allow Virtuoso Layout Suite GXL to offer a customizable layout-editing environment and useradded features. This is made possible through the support of the flexible, powerful, and industry-proven SKILL programming language, which gives users direct access to the design database and tools to meet the design requirements of any custom design methodology. Additionally, the OpenAccess database supports a C-based API and toolbox to allow for tool customization and tool interoperability.

Design-ruledriven editing
Virtuoso Layout Suite GXL provides real-time design-ruledriven editing that flags violations and automatically enforces design rules while the layout is being created. This promotes correctby-construction layout, improving productivity and eliminating physical verification iterations. All technology file process rules are supported, including complex sub-32nm nodes.
Figure 2: Docked layout assistants include a Design Navigator, Property Editor, and World View, which enhance layout productivity
Advanced layout automation
Virtuoso Layout Suite GXL simplifies and optimizes block authoring with advanced layout automation features that leverage the design-ruledriven functions and flow. Dynamic Measurement minimizes the need to manually measure geometries. Alignment speeds up the task of aligning instances, pins, and objects. Mark Net efficiently traverses the physical design hierarchy and performs continuity checking and highlighting.

Flexible SKILL Pcells

SKILL parameterized cells (Pcells) provide an advanced level of design automation to minimize tedious and repetitive layout tasks. Pcells support the changing of the size, shape, or contents of each cell instance without changing the original cell. They raise the level of abstraction to the component level, simplifying complex shapes and devices that can be generated, edited, and managed with variable settings. This results in faster design entry, accelerated layout, and fewer design-rule violations.
Connectivity-driven functions and flow
Virtuoso Layout Suite GXL changes the way custom block authoring is done. Driven by schematic connectivity and constraint design intent established in Virtuoso Schematic Editor or a netlist source (such as CDL or SPICE), an LVS-
Advanced assisted wire editing
Virtuoso Layout Suite GXL has a robust set of constraint/design-ruledriven assisted wire-editing capabilities. This comprehensive, fully interactive wire editor is natively integrated into Virtuoso Layout Suite GXL and supports advanced process nodes along with an array of custom specialty routing types such as bus/bundle, differential pair, matched length, and symmetric. In addition to driving the wire editor fully manually, users can also take advantage of the wire editors assisted capabilities. Commands such as point-topoint, finish wire, pushing and shoving of wires, along with guided routing on single nets and buses, are built upon the Virtuoso common constraint system and connectivity-driven layout. These features are productivity enablers for almost all layout engineers, who no longer need to generate complicated scripts to get desired results.
Figure 3: The GXL configuration is integrated with Virtuoso Space-Based Router, a hierarchical, grid-less, space-based, full-chip, block- and device-level routing system

correct layout can be done in real-time. This ensures correct-by-construction layout, higher productivity, and shorter verification time. Additionally, tedious design tasks can be automated, such as device generation, placement, and routing. Schematics and layout can be cross-probed to highlight instances and devices as well as quickly identify unconnected nets. In Virtuoso Layout Suite GXL, a new incremental connectivity-driven binding technology has been introduced. This approach is far superior to traditional name-based schematic-to-layout binders, which had severe limitations when supporting schematic-to-layout name mismatches. The connectivity-driven binder enables better support of legacy layouts that have name mismatches, and also improves handling of engineering charge orders (ECOs) that involve renaming of instances and terminals in the layout. The incremental nature of the connectivity binder also greatly improves the performance of a connectivity-driven layout flow.
Constraint- and design-rule driven functions
The Virtuoso platform is built upon a common constraint environment to ensure correct-by-construction layout, higher productivity, and fewer physical verification iterations. Topological constraints, electrical constraints, and/or design-rule specific constraints complete the design intent specified and managed in Virtuoso Schematic Editor, Virtuoso Analog Design Environment, or Virtuoso Layout Suite. Simply set the design intent constraints in Schematic Editor and Layout Suite can easily be configured to either enforce the constraints while generating layout or automatically flag and log constraint violations that can be discussed at subsequent design reviews. Integrated signoff constraint verification can be run and accessed from the docked annotation browser, simplifying the task of verifying that a design is meeting the design intent specification. Constraint verification can be done before, during, or after physical implementation of a design.
Advanced editing with cloning
Virtuoso Layout Suite XL has a unique capability that allows users to clone portions of the layout without altering connectivity. What differentiates cloning from a more traditional copy of geometry is that cloning supports both a geometric copy and a connectivity update. This capability is essential in todays connectivity-driven methodologies. In addition to cloning, synchronous clones enable a single change in a member of a clone to update all partner clones. This capability greatly boosts productivity when working in a connectivity-driven environment.
Virtuoso Space-Based Router
Virtuoso Space-Based Router is a hierarchical, gridless, space-based, fullchip, block- and device-level routing system for advanced analog, mixed-signal, and custom-digital designs. It has been used for production routing on design using processes from 0.5um to 28nm. The routing environment is native to Virtuoso

Layout Suite GXL and is tightly coupled with the Virtuoso common constraint environment. It is a multi-threaded routing environment, capable of routing multimillion-net designs. Virtuoso Space-Based Router also supports a robust set of specialty custom routing types such as bus/bundle, differential pair, pin-to-trunk, and shielded. These common types of custom routing can be fully automated in the space-based environment and have been proven to greatly improve layout designer productivity.
Module generators can be created from either the schematic or the layout. When users create a MODGEN from the schematic, a MODGEN constraint is inserted in the Virtuoso common constraint environment. This constraint is then enforced automatically when the layout is created.
Quick placement as schematic mode, which provides placement-based device ordering in the schematic Fully automated placement with userdefinable effort levels The Cadence custom-digital placer automatically places transistors, devices, and cells in block- and cell-based designs using more traditional row-based methods. This placer is interoperable with Virtuoso Analog Placer and preserves MODGENs and user-defined groups.
Full custom-analog and custom-digital placement
Virtuoso Analog Placer is capable of a number of analog/RF-centric automatic placement functions. This includes the automatic creation of quick placements and more robust placements that support more packing, as well as functions to fix DRC errors in the placement and adjust cell pins and sides. Virtuoso Analog Placer offers three modes of operation: Quick placement mode, which provides fast, DRC-aware placement for quick area estimation

Yield optimization

Virtuoso Yield Optimizer is used for design-for-yield (DFY) optimization, which primarily involves the enforcement of recommended rules while maintaining all hierarchy, mandatory design rules, and design constraints such as symmetry and design-rule overrides. Users can also provide the hotspots and guidelines as output from litho simulation via HIF files and Virtuoso Yield Optimizer will automatically fix the litho violations.

Full-custom floorplanning
The Virtuoso floorplanner contains automatic and interactive floorplanning tools and technologies that help mixedsignal designers develop layout from a schematic in a methodical manner. The floorplanner supports I/O constraints files, soft and hard rectilinear blocks, layout and abstract views, and digital/custom block types. It has common floorplanning capabilities such as congestion analysis, pin optimization, the ability to generate physical hierarchy, and the ability to configure the layout hierarchy in an efficient graphical manner. The floorplanner is unique in its ability to add value in both top-down and bottom-up methodologies.
Advanced module generation
Module generators (MODGENs) are designed to provide layout designers an intuitive way to quickly generate SKILL Pcell instances into a complex, highly matched, and structured array. Within the MODGEN tool, users specify the devices to be arrayed, then specify an interdigitation pattern, and then they insert dummy devices, body contacts, and guard rings. The ability to generate these complex interdigitation patterns can be achieved in two waysa user-friendly form for large arrays or interactively for minor edits to the array. Finally, users control the routing style and generate internal routing geometry.
Figure 4: Virtuoso module generators easily generate complex interdigitation schemes and are ideal for highly matched structures such as differential pairs, current mirrors, and other commonly arrayed devices

Design migration

Virtuoso Layout Migrate enables fast migration of a given design to a new or altered process geometry. Integrated with the Virtuoso platform, it provides hierarchical, two-dimensional optimization algorithms to achieve significantly higher quality of results (QoR) than traditional methods using near-linear shrinks.

Design Input

OpenAccess database SKILL STREAM format OASIS format Cadence Chip Assembly Router database format
CADENCE SERVICES AND SUPPORT
Cadence application engineers can answer your technical questions by telephone, email, or Internetthey can also provide technical assistance and custom training Cadence certified instructors teach more than 70 courses and bring their real-world experience into the classroom More than 25 Internet Learning Series (iLS) online courses allow you the flexibility of training at your own computer via the Internet Cadence Online Support gives you 24x7 online access to a knowledgebase of the latest solutions, technical documentation, software downloads, and more

Design Output

Interactive DRC fixing
Interactive DRC fixing is used for strategically fixing DRC errors in the layout in an automated fashion. This out-of-the-box technology runs natively on a Virtuoso OpenAccess technology file. The patented technology incrementally loads portions of the layout so that it can handle very large designs.

Platform/OS

Sun/Solaris HP-UX IBM AIX Linux

SPECIFICATIONS

Third-Party Support
OpenAccess-compatible tools and functions PDKs (please contact your foundry provider for more information)
For more information contact Cadence sales at:

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or log on to:
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2011 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Encounter, and Virtuoso are registered trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 21935 03/11 MK/DM/PDF