WHITE PAPER

AUTOMATIC PLACEMENT FOR CUSTOM LAYOUT IN VIRTUOSO LAYOUT SUITE GXL

ABSTRACT

The Cadence Virtuoso custom design platform is best known as the de facto standard for custom chip creation, owing primarily to its interactive and assisted design techniques. What is less generally known is that the platform also offers significant automatic design techniques. Specifically in the area of automatic placement of custom designs, Virtuoso Layout Suite GXL delivers many capabilities. In this paper we define a common terminology for placement in the platform and design space, and give some detailed recommendations on automatic placement capabilities available in it.

INTRODUCTION

The Cadence Virtuoso custom design platform is well known throughout the industry as the longstanding de facto standard for custom design. The vast majority of users create layout with the platform at the purely manual shape-based editing level (Virtuoso Layout Suite L), or the assisted connectivity-based editing level (Virtuoso Layout Suite XL). However, Virtuoso Layout Suite XL and GXL products also offer many assisted and automatic capabilities. In this paper we consider the placement1 capabilities of these products. First, we define the addressed design space and a common set of terminology for placement in the custom design platform. Then we will describe in detail the capabilities of three of the automatic placement tools: the Analog Placer, the Custom Digital Placer, and the Floorplanning Block Placer.

COMMON TERMINOLOGY

We begin by defining the design space served by the Virtuoso platform. A wide variety of designs in a wide variety of technologies are created using the platform. One usable definition of the design space is all designs done on chips, rather than on PCBs or with discrete components, which are not created using big digital synthesis/placement/routing tools such as the Cadence Encounter2 platform. This can encompass design areas as varied as MEMS3 on GaAs substrate to an RF design on SiGe to common analog designs in a typical CMOS process. For the purpose of defining the primary design space focus of custom design we will concentrate on three basic areas: Analog Design, Custom Digital Design, and Chip-level assembly of mixed-signal designs. For the purpose of this paper, we will refer to these areas as the custom design space. Although there are many other types of designs implemented by users with the Virtuoso platform, these areas comprise the majority of our users. Now we turn to the definition of placement in the custom design space. At the most basic level (Virtuoso Layout Suite L), placement means the user creating individual polygons on particular layers which are arranged to create transistors, resistors, capacitors, routing and pins. There certainly are designs and designers for whom this is the lowest cost path to the highest performance layout. But given the continuous need for higher productivity, and more designs in the custom space, for most users it makes sense to move to a slightly higher level of abstraction, which is referred to as a connectivity-driven design flow. Virtuoso Layout Suite XLwhich is typically used in the Analog Design flowprovides the capabilities for this connectivity-driven design flow. In this flow, devices such as transistors, resistors, capacitors, etc. are represented by Parameterized Cells (Pcells) specified in the technology library. Pins are defined programmatically in the tool, and routing connectivity is automatically determined from a connectivity source such as a netlist or schematic. This then simplifies the placement problem to finding a coordinate/transform (X, Y, orientation) for each Pcell and Pin, and optionally creating other associated geometry to allow proper functioning of those instances, such as guard rings or well geometry. The routing step then completes the layout by creating vias and path segments such that all necessary connectivity is completed. This flow contrasts with the Cadence Encounter design space primarily in the level of layout building-block abstraction applied to the problem. In those big digital designs, placement

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AUTOMATIC PLACEMENT FOR CUSTOM LAYOUT IN VIR TUOSO LAYOUT SUITE GXL
typically refers to assigning final transformation to standard cells or macro/IP abstracts on the chips surface. Utilizing this level of abstraction also allows many of the details of chip-level implementation (wells, guard rings, flexible cell size and pin locations) to be avoided in big digital design, leading to correspondingly higher capacity. All of these detailed implementation complexities are decided during the standard cell design phase, which is typically done in the Virtuoso platform, falling into the custom design category. In addition the Virtuoso platform can cater to mixed-signal design space at chip and block level with medium-sized designs for the chiplevel assembly flow. The basic flow of design can also be repeated at a number of levels of hierarchy to incrementally build the whole chip from the top down. Various flows like Analog on Top (AOT) have been developed specifically to generate and place hierarchical layouts in the custom design space as compared to a big flat abstract design methodology of the Cadence Encounter platform. From the discussion above, we see the common characteristics of placement in the custom design space as: device-level rather than gate/cell level, and detail-geometric-oriented rather than abstracted. Due to the wide variety of user preference on the fully manual to automated continuum we find a variety of different types of placement tasks. Within the Virtuoso platform, we refer to three basic types of placement tasks: Initial, Assisted Sub-block, and Automatic.

INITIAL PLACEMENT

In a connectivity-driven design flow, the connectivity, pins and many of the parameters controlling the creation of the instances have been specified on the netlist or schematic, typically for simulation purposes as well as driving layout. Utilizing this information, Virtuoso Layout Suite XL provides the user with initial placement capabilities as an alternative to complete manual creation of instances and pins. The most commonly used is known as Generate from Source (GFS)4 as it creates all of the instances and pins from the connectivity source. They are placed in a somewhat arbitrary manner, but are then available on the layout canvas to be interactively placed by the user. Users can make use of the re-initialize engine5 to do an initial segregated placement based on cell type of instances. It places IOs on top, Macros on the left, Standard cells on the right and Custom layouts at the bottom of the design boundary; this gives the user a better idea of the types of blocks and their number, which helps in choosing available placement options. Many users also want the option to have that initial placement roughly follow the placement of the symbols in the schematic. This feature is typically known as Place as Schematic (PAS)6, and is available as an option to GFS or as a separate command. In addition, if the user is not interested in having all instances created in a batch manner, the Pick from Schematic (PFS)7 command allows the user to interactively select instances from the schematic and create them at targeted locations in the layout. GFS, PAS and PFS provide utilities for users to assist their interactive layout process; they provide little automation for the full placement process.
ASSISTED SUB-BLOCK PLACEMENT
Once the initial instances are created, many designers utilize common layout patterns for subblocks. Features in Virtuoso Layout Suite XL and GXL have been developed to assist in the layout of these common sub-block patterns. These tools and techniques are distinguished by their ability to assist with final layout of a sub-section/sub-block of the full design. So for a particular part of the layout, they may help in getting that part of the design to 100% complete with lower effort, but it is only part of the layout. Tool capabilities in this category include Chaining8, Synchronous Clones9, and Modgens10. Chaining gives an automatic way to take a set of transistors and abut them together into a single row quickly and easily. Synchronous Clones lets the designer specify that a layout pattern will be replicated and just design it once and have the rest of the layout automatically mimic the design. With Modgens the designer can specify an arrayed-instance-based layout very quickly for typical interdigitated analog circuit sub-blocks like differential pairs, current mirrors, etc. In addition, there are various tool accelerators available to improve layout productivity for the whole layout design, such as Constraint-Aware Editing (CAE), Design-Rule Driven (DRD)

editing, and interactive device abutment. All of these tools allow the layout designer to continue the practice of custom and interactive design of the layout, while at the same time accelerating their activities and enforcing design rules, constraints, and correct abutment more automatically.
Figure 1. Basic Analog Placement design

AUTOMATIC PLACEMENT

Finally we reach the full automatic placement tools. These perform fully automatic placement on all of the instances and pins in our current design. The results produced may not be the 100% complete layout, but it takes the designer to the 80% solution with much greater productivity than the manual/assisted design flow. In the following section we will look in detail at the capabilities for each of these automatic placement features for Virtuoso Layout Suite GXL: Analog Placement, Custom Digital Placement, and Floorplanning Block Placement.
AUTOMATIC PLACEMENT CAPABILITIES
Here we provide a detailed view of the specific design space the automatic placement capability supports, and the flows that best utilize these tools.

ANALOG PLACEMENT12

The Analog Placer is designed primarily to address analog circuits with sizes of placeable instances. These placeable instances may map one-to-one with the actual transistors in the design, or groups of instances may be built into sub-blocks using the techniques discussed in 2.2. It performs flat transistor-level placement, primarily driven by constraints such as Symmetry, Alignment, Clusters, and Matching and connectivity to minimize wire length. It has the capability to automatically create well and guard ring geometry around appropriate groups of instances. The primary goal of the Analog Placer is to obey all specified constraints, then optimize for area and wirelength. Three analog design flows that use the Analog Placer most successfully are Basic Analog Placement, Analog Placement for Chip Planning and Rapid Analog Prototyping.
Figure 2. Standard Cell Placement
Basic Analog Placement uses the Analog Placer to create the 80% complete layout for typical analog circuits like Cascode OpAmps, Comparators and the like. In this type of flow the circuit designer or layout designer may spend slightly more time creating and tuning constraints on the design, to get the best placement. This has the benefit of capturing this knowledge of the critical constraints (characteristics) of the layout design to be re-used in the future. An example design that has utilized the Analog Placer for the layout can be seen in Figure 1. This design took 9.1 seconds for placement on a Linux machine with an Intel Core CPU running at 2.13 GHz. Next, looking at the Analog Placement for Chip Planning flow, Cadence has users who are successfully employing the Analog Placer as an area-estimate tool. In this flow, the designer uses the Circuit Prospector11 to automatically create reasonable constraints and then runs the Analog Placer in a scripted fashion, and collects results on the typical area, aspect ratio and pin locations and uses those for the top-down floorplanning flow. These placements can then either be used as a starting point, or only used to create the template (PRBoundary and Pin Positions) used by the layout engineer. And lastly we have our Rapid Analog Prototyping flow. In this case our circuit designers want early feedback on device and wiring parasitics without doing detailed layout design. So they might use the Analog Placer as part of an automated flow to do automatic placement and routing, and extract parasitics and then re-simulate their design with these parasitics in place. Here the process of adding constraints, especially such as Modgen constraints, can greatly aid the process, as it will ensure that the important parasitics are consistent between the prototype layout and the final layout.

Figure 3. Transistor Level Placement
CUSTOM DIGITAL PLACEMENT13
The Custom Digital Placer is used to implement small digital designs with several thousand placeable components. These components are standard cells, transistor-level devices and pins. The placer has three placement options; global placement, optimized placement and ECO mode. The placement can be run on a selected set or the entire design. The Custom Digital Placer requires user-created rows and component types. For a design with 10,000 standard cells the placer takes approximately 18 minutes to complete global and optimized placement on SunFire-V440. The Custom Digital Placer can also be driven by constraints that include Fixed, Alignment, Distance, and Cluster. The placement of standard cells includes an option to perform row compaction and has an internal global routing estimate, which minimizes area and wirelength. Additionally it has the capability to create filler cells to complete power and ground paths by filling spaces and also create standard cell substrate contacts. The Custom Digital Placer can also be used to place transistor-level devices for the creation of standard cells and macro cells. In this mode, the placer can perform abutment of components to maximize device sharing by forming chains of abutted components, which minimizes area and wirelength. For smaller standard cells the XL chaining command may produce better results.
FLOORPLANNING BLOCK PLACEMENT14
The Block Placer is designed to place macros of both hard and soft blocks to address placement problem in a design space, which caters to mixed-signal and pure analog chips. In the Analog on Top (AOT) flow, a design having a few thousands of components is partitioned into a few hard and soft blocks, which can then be developed independently in Virtuoso and Encounter platforms. To place these blocks, users start with an IO placement if the design is a mixed-signal die and then run the block placer to place the analog and digital blocks. The results are best when the number of blocks is within 16 to 20. This can be achieved with good top-level partitioning; creating too many partitions generally defeats the top down floorplanning methodology. The block placement is connectivity aware, with well connected blocks staying
Figure 4. Floorplanning Block Placer
together; this reduces the net length and improves the efficiency of the final layout. Users give additional costs like no overlapswithin boundary, net criticality, etc.to further fine-tune the results. The block placement technology is well integrated with the Virtuoso Space-based Global Router15 and can use the congestion data generated by it to improve placement results incrementally. The front end constraints provided by the schematic designerlike alignment, boundary area, distance between noisy digital and victim analog blocks and clusteringare respected faithfully by the block placer, which is well integrated with the Constraint Infrastructure16 used for visualization, transfer and modification of constraints. The custom design user utilizes the block placer because it understands the mixed-signal design space: e.g., the features of snapping origin and soft edges to manufacturing grid, automatic soft block re-size, and rectilinear blocks support to optimize space. It can place digital and analog macro layouts with equal ease to generate data that is hierarchical and perfectly interoperable with the Encounter platform. This complements the Encounter platform solution, which is used to place millions of same-sized, rectangular standard cell abstracts. So for a medium-sized mixedsignal design with irregular space availability, a low-cost path to place blocks is available, and is popular with many users for Analog on Top and Mixed-Signal on Top design flows.

CONCLUSION

A common terminology for types of placement technology in the custom design space has been presented and defined, among the areas of initial placement, assisted sub-block placement, and automatic placement. This common vocabulary for types of placement will aid in our discussion inside Cadence and with users. The current state of Virtuoso Layout Suite GXL Automatic Placement capabilities was also presented in Section 3. Clear understanding of these capabilities will assist in mapping the areas to promote adoption of automatic placement. It also gives us a common starting point for identifying areas of focus for future innovation and improvement. The descriptions of the automatic placement tools and flows presented in this paper helps our whole community better understand the capabilities and potential of the Virtuoso Layout Suite products.

REFERENCES

1. "Placement (EDA)." Wikipedia, The Free Encyclopedia. 2 Sep 2008, 18:50 UTC. 26 Jan 2009 http://en.wikipedia.org/w/index.php?title=Placement_(EDA)andoldid=235867041 2. Cadence Design Systems, Inc, Encounter User Guide, Product Version 8.1, Chapter 15 Placing the Design. http://sourcelink.cadence.com/docs/files/Release_Info/Docs/soceUG/soceUG8.1/ placement.html#12532294 3. "Microelectromechanical systems." Wikipedia, The Free Encyclopedia. 26 Jan 2009, 20:34 UTC. 27 Jan 2009 http://en.wikipedia.org/w/index.php?title=Microelectromechanical_ systems&oldid=266597492 4. Cadence Design Systems, Inc, Virtuoso Layout Suite XL User Guide, Product Version 6.1.3, Chapter 6 Generating a Layout, Generating All Components from Source. http://sourcelink. cadence.com/docs/files/Release_Info/Docs/vxlhelp/vxlhelp6.1.3/chap6.html#1034258 5. Cadence Design Systems, Inc, Virtuoso Floorplanner User Guide, Product Version 6.1.3, Chapter 1 Floorplanner Commands, Reinitializing the Design. http://sourcelink.cadence.com/ docs/files/Release_Info/Docs/fphelp/fphelp6.1.3/chap1.html#1064093 6. Cadence Design Systems, Inc, Virtuoso Layout Suite XL User Guide, Product Version 6.1.3, Chapter 7 Editing the Layout, Moving Generated Components into the Design Boundary. http://sourcelink.cadence.com/docs/files/Release_Info/Docs/vxlhelp/vxlhelp6.1.3/chap7. html#1048484 7. Cadence Design Systems, Inc, Virtuoso Layout Suite XL User Guide, Product Version 6.1.3, Chapter 6 Generating a Layout, Generating Selected Components from Source. http://sourcelink.cadence.com/docs/files/Release_Info/Docs/vxlhelp/vxlhelp6.1.3/chap6. html#1050748 8. Cadence Design Systems, Inc, Virtuoso Layout Suite XL User Guide, Product Version 6.1.3, Chapter 5 Device Abutment, Chaining Transistors Interactively. http://sourcelink.cadence.com/ docs/files/Release_Info/Docs/vxlhelp/vxlhelp6.1.3/chap5.html#1038419 9. Cadence Design Systems, Inc, Virtuoso Layout Suite XL User Guide, Product Version 6.1.3, Chapter 6. Generating a Layout, Generating Synchronous Clones. http://sourcelink.cadence. com/docs/files/Release_Info/Docs/vxlhelp/vxlhelp6.1.3/chap6.html#1054759 10. adence Design Systems, Inc, Virtuoso Analog Placement User Guide, Product Version 6.1.3, C Chapter 3 Working with Module Generators. http://sourcelink.cadence.com/docs/files/ Release_Info/Docs/anaPlaceGXL/anaPlaceGXL6.1.3/modgens.html 11. adence Design Systems, Inc, Virtuoso Unified Custom Constraints User Guide, Product C Version 6.1.3, Chapter 2 The Circuit Prospector Assistant. http://sourcelink.cadence.com/docs/ files/Release_Info/Docs/constraints/constraints6.1.3/chap2.html

12. adence Design Systems, Inc, Virtuoso Analog Placement User Guide, Product Version 6.1.3, C Chapter 4 Creating an Analog Placement. http://sourcelink.cadence.com/docs/files/Release_ Info/Docs/anaPlaceGXL/anaPlaceGXL6.1.3/autoplace.html#1035250 13. adence Design Systems, Inc, Virtuoso Custom Placer User Guide, Product Version 6.1.3. C http://sourcelink.cadence.com/docs/files/Release_Info/Docs/vcphelp/vcphelp6.1.3/vcphelpTOC. html 14. adence Design Systems, Inc, Virtuoso Floorplanner User Guide, Product Version 6.1.3, C Chapter 1 Floorplan Commands, Placing Blocks. http://sourcelink.cadence.com/docs/files/ Release_Info/Docs/fphelp/fphelp6.1.3/chap1.html#1058663 15. adence Design Systems, Inc, Virtuoso Space-based Router User Guide, Product Version C 6.1.3, Chapter 1 Getting Started with the Space-based Router. http://sourcelink.cadence.com/ docs/files/Release_Info/Docs/autouser/autouser6.1.3/start.html 16. adence Design Systems, Inc, Virtuoso Unified Custom Constraints User Guide, Produce C Version 6.1.3, Chapter 1 The Constraint Manager Assistant. http://sourcelink.cadence.com/ docs/files/Release_Info/Docs/constraints/constraints6.1.3/chap1.html
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2009 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Encounter, and Virtuoso are either trademarks or registered trademarks of Cadence Design Systems, Inc. in the United States and/or other jurisdictions. All others are properties of their respective holders. 20933 07/09 KM/MVC/DM/PDF

Virtuoso Layout Suite XL

DATASHEET

VIRTUOSO LAYOUT SUITE XL

Virtuoso Layout Suite XL accelerates custom layout with a comprehensive set of user-configurable, easy-to-use pure polygon layout features within a fully hierarchical environment. Additional layout productivity is provided through optional parameterized cells (Pcells) and SKILL, a powerful scripting language that provides direct database access, tool configuration, and interoperability with other tools. Virtuoso Layout Suite XL has set the standard for layout productivity and changed the way custom block authoring is done. It is driven by a connectivity source from Virtuoso Schematic Editor or a netlist such as CDL or SPICE. A layout vs. schematic (LVS)-correct layout can then be created, ensuring correct-byconstruction layout, higher productivity, and shorter verification time. Virtuoso Layout Suite XL automates tedious design tasks such as device generation,
Part of the Cadence Virtuoso Layout Suite family of products, Virtuoso Layout Suite XL is a connectivity- and constraint-driven layout environment built on common design intent. It supports the physical implementation of analog, custom-digital, and mixed-signal designs at the device, cell, block, and chip level. Seamlessly integrated with the Virtuoso custom design platform and built on the OpenAccess database, Virtuoso Layout Suite XL ensures faster convergence on design goals and more efficient layout implementation.
Figure 1: The industry-standard Virtuoso Layout Suite user interface
placement, and routing. Users can crossprobe schematics and layout to highlight instances and devices, as well as quickly identify unconnected nets. In addition to being a fully featured connectivity-driven environment, Virtuoso Layout Suite XL is built upon the Virtuoso common constraint system. Topological constraints, electrical constraints, and/ or design-rule specific constraints can be specified and managed by Virtuoso Schematic Editor, Virtuoso Analog Design Environment, or Virtuoso Layout Suite. Once users set the constraints in Virtuoso Schematic Editor XL, Virtuoso Layout Suite XL can then be configured to either enforce the constraints while generating layout, or automatically flag and log constraint violations that be resolved in subsequent design reviews. Constraint- and connectivity-driven layout is a fundamental building block for realizing optimized, first-time correct silicon.
In addition to Virtuoso Layout Suite XL, the suite includes: Virtuoso Layout Suite L, a basic design-creation and implementation environment focused on layout productivity Virtuoso Layout Suite GXL, an extension to the XL tier, adds a robust set of advanced automated finishing tools to satisfy demanding physical design tasks such as floorplanning, placement, routing, and optimization; these technologies are the fundamental building blocks to rapidly realizing firsttime successful silicon
VIRTUOSO LAYOUT SUITE XL BENEFITS
The XL configuration includes all Virtuoso Layout Suite L features (see respective datasheet) and offers these additional benefits: Captures and drives common hierarchical design intent with Virtuoso Schematic Editorincluding connectivity, constraints, and power domains Enables interactive Pick-From-Schematic or automated Gen-From-Source device generation Enables automated SKILL Pcell-based device editing, including abutment, pin permutation, folding, chaining, and cloning Boosts designer productivity with rich set of assisted wire-editing functionality when creating custom interconnect Synchronous Copy command copies a group of physical objects that exist in the layout while maintaining synchronization among copied groups Includes menu-driven or programmable multi-part path (MPP) features for guard rings, slotting, etc. Features advanced synchronous cloning capabilities for generating and editing complex repeated layout patterns Enables easy configuration and visualization of large, complex designs using the configure physical hierarchy browser Addresses challenging next-generation design problems with common design intent using a connectivity- and constraint-driven environment Constraint-aware and designruledriven editing for correct-byconstruction layout Automatic design intent and constraint checking Automatic and dynamic design abstraction to handle more complex levels of design integration High-performance connectivitydriven binder to handle designs with schematic-to-layout name mismatches

VIRTUOSO CUSTOM DESIGN PLATFORM
The Virtuoso custom design platform integrates Virtuoso Schematic Editor, Virtuoso Analog Design Environment, Virtuoso Multi-Mode Simulation, and the Virtuoso Layout Suite to speed convergence on design goals at every step for front-to-back custom analog, digital, RF, and mixed-signal design flows. The platform is backed by the largest number of process design kits (PDKs) available from the worlds leading foundries, for process nodes everywhere from mature 0.35um to advanced 28nm. It is built on the OpenAccess database, engineered by Cadence for industry-wide interoperability. The Virtuoso custom design platform also interoperates with the Cadence Encounter digital implementation platform technologies via the OpenAccess database, providing a single, complete, coherent, and unified representation of design intent. This design intent is preserved throughout the entire physical implementation phase while operating with multiple levels of design abstractions (device, cell, block, chip), speeding design convergence to realize silicon for complex mixed-signal and system-on-chip designs.
VIRTUOSO LAYOUT SUITE FAMILY
The Virtuoso Layout Suite family of products comprises the layout environment of the industry-standard Virtuoso custom design platform, a complete solution for front-to-back custom analog, digital, RF, and mixedsignal design. The Virtuoso Layout Suite preserves design intent throughout the entire physical implementation process, while managing multiple levels of design abstractions from device, cell, and block levels through to the full-chip level. It provides the fastest path to design convergence for mature and advanced node silicon realization. The Virtuoso Layout Suite includes three tiers of increasing layout automation and designer productivity. By selectively automating aspects of custom-analog design and providing advanced technologies integrated on a common database, engineers can focus on precision-crafting their designs without sacrificing creativity to repetitive manual tasks.

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VIRTUOSO LAYOUT SUITE XL FEATURES
Hierarchical, multi-window, multi-tabbed editing environment
Virtuoso Layout Suite XL enables users to open multiple cells or blocks in a single editing session, or to open different views of the same design, ensuring consistency in complex designs. Users can also open and manage their designs more quickly by using tabs, bookmarks, and history similar to the functionality in todays popular web browsers. A tabbed approach to viewing layouts simplifies window management and provides fast access to multiple designs in an intuitive manner. This is particularly helpful when copying portions of a layout from one design to another, or when using a pre-existing design as a reference. Users can bookmark commonly accessed designs or view the history of opened designs. Bookmarks can be a single

cell or a group of cells that appear in individual tabs. A personal bookmarks toolbar makes accessing commonly used bookmarks extremely quick and easy. Virtuoso Layout Suite XL shares the same look and feel with Virtuoso Schematic Editor and Virtuoso Analog Design Environment. This consistent use model enables a fully featured, intuitive, frontto-back design flow.

Docked layout assistants

Docked assistants are user-interface widgets that surround the main layout editing canvas. Virtuoso Layout Suite XL includes a rich set of assistants, including a Design Navigator and Property Editor, Search, and World View Assistants that significantly increase layout productivity. Through the Design Navigator, users can quickly access specific cells that may be in a lower level of the design hierarchy via a tree browser built into the Design Navigator. Cells, nets, and pins can also be selected, sorted, and probed through
Figure 3: Docked layout assistants include a Design Navigator, Property Editor, and World View, which enhance layout productivity
the Design Navigator. This is a very effective feature when designing and debugging complex layouts. The Property Editor Assistant is a new twist on the traditional Edit Properties pop-up form. The streamlined interface improves the effective area of the layout canvas space while decreasing mouse clicks and wasteful pop-up dialog boxes. Through the Search Assistant, layout engineers have comprehensive search capabilities. The Search Assistant categorizes the found items into logical groups (cells, pin names, properties, etc.) and displays these items in a tree structure. This makes it very easy for users to find and access information within the design, the design libraries, menu commands, and even the SKILL manuals.
Figure 2: The Configure Physical Hierarchy browser enables easy configuration and visualization of large, complex designs
Context-sensitive menus and double-click operations allow for rapid operations on selected results. The World View Assistant is an intuitive navigational aid that allows users to always see the entire design, even while zoomed into a specific section of the layout. This Assistant is particularly useful when working with large layouts where users have to perform editing while zoomed in on a portion of the design. The ability to concentrate on a specific section of layout while still viewing the overall layout decreases the need for repetitive panning and zooming. This translates into fewer mouse clicks, which improves layout productivity.

Design-ruledriven editing
Virtuoso Layout Suite XL provides real-time design-ruledriven editing that flags violations and automatically enforces design rules while the layout is being created. This promotes correctby-construction layout, improving productivity and eliminating physical verification iterations. All technology file process rules are supported, including complex sub-32nm nodes.
charge orders (ECOs) that involve renaming of instances and terminals in the layout. The incremental nature of the connectivity binder also greatly improves the performance of a connectivity-driven layout flow.
Constraint- and design-rule driven functions
The Virtuoso platform is built upon a common constraint environment to ensure correct-by-construction layout, higher productivity, and fewer physical verification iterations. Topological constraints, electrical constraints, and/or design-rule specific constraints complete the design intent specified and managed in Virtuoso Schematic Editor, Virtuoso Analog Design Environment, or Virtuoso Layout Suite. Simply set the design intent constraints in Schematic Editor and Layout Suite can easily be configured to either enforce the constraints while generating layout or automatically flag and log constraint violations that can be discussed at subsequent design reviews. Integrated signoff constraint verification can be run and accessed from the docked annotation browser, simplifying the task of verifying that a design is meeting the design intent specification. Constraint verification can be done before, during, or after physical implementation of a design.
Advanced layout automation
Virtuoso Layout Suite XL simplifies and optimizes block authoring with advanced layout automation features that leverage the design-ruledriven functions and flow. Dynamic Measurement minimizes the need to manually measure geometries. Alignment speeds up the task of aligning instances, pins, and objects. Mark Net efficiently traverses the physical design hierarchy and performs continuity checking and highlighting.

Flexible SKILL Pcells

SKILL parameterized cells (Pcells) provide an advanced level of design automation to minimize tedious and repetitive layout tasks. Pcells support the changing of the size, shape, or contents of each cell instance without changing the original cell. They raise the level of abstraction to the component level, simplifying complex shapes and devices that can be generated, edited, and managed with variable settings. This results in faster design entry, accelerated layout, and fewer design-rule violations.

Connectivity-driven functions and flow
Virtuoso Layout Suite XL changes the way custom block authoring is done. Driven by schematic connectivity and constraint design intent established in Virtuoso Schematic Editor or a netlist source (such as CDL or SPICE), an LVS-correct layout can be done in real-time. This ensures correct-by-construction layout, higher productivity, and shorter verification time. Additionally, tedious design tasks can be automated, such as device generation, placement, and routing. Schematics and layout can be cross-probed to highlight instances and devices as well as quickly identify unconnected nets. In Virtuoso Layout Suite XL, a new incremental connectivity-driven binding technology has been introduced. This approach is far superior to traditional name-based schematic-to-layout binders, which had severe limitations when supporting schematic-to-layout name mismatches. The connectivity-driven binder enables better support of legacy layouts that have name mismatches, and also improves handling of engineering
Highly customizable editing features
The architecture and implementation of the Cadence Design Framework II and the OpenAccess database allow Virtuoso Layout Suite XL to offer a customizable layout-editing environment and useradded features. This is made possible through the support of the flexible, powerful, and industry-proven SKILL programming language, which gives users direct access to the design database and tools to meet the design requirements of any custom design methodology. Additionally, the OpenAccess database supports a C-based API and toolbox to allow for tool customization and tool interoperability.
Advanced assisted wire editing
Virtuoso Layout Suite XL has a robust set of constraint/design-ruledriven assisted wire-editing capabilities. This comprehensive, fully interactive wire editor is natively integrated into Virtuoso Layout Suite XL and supports advanced process nodes along with an array of custom specialty routing types such as bus/bundle, differential pair, matched length, and symmetric. In addition to driving the wire editor fully manually, users can also take advantage of the wire editors assisted capabilities. Commands such as point-topoint, finish wire, pushing and shoving of wires, along with guided routing on single nets and buses, are built upon the
OASIS format Cadence Chip Assembly Router database format

Design Output

OpenAccess database SKILL STREAM format OASIS format Cadence Chip Assembly Router database format

Platform/OS

Sun/Solaris HP-UX IBM AIX Linux
Figure 4: Robust assisted routing facilities include finish net, point-to-point routing, and guided routing
CADENCE SERVICES AND SUPPORT
Cadence application engineers can answer your technical questions by telephone, email, or Internetthey can also provide technical assistance and custom training Cadence certified instructors teach more than 70 courses and bring their real-world experience into the classroom More than 25 Internet Learning Series (iLS) online courses allow you the flexibility of training at your own computer via the Internet Cadence Online Support gives you 24x7 online access to a knowledgebase of the latest solutions, technical documentation, software downloads, and more

Virtuoso common constraint system and connectivity-driven layout. These features are productivity enablers for almost all layout engineers, who no longer need to generate complicated scripts to get desired results.
enable a single change in a member of a clone to update all partner clones. This capability greatly boosts productivity when working in a connectivity-driven environment.
Advanced editing with cloning
Virtuoso Layout Suite XL has a unique capability that allows users to clone portions of the layout without altering connectivity. What differentiates cloning from a more traditional copy of geometry is that cloning supports both a geometric copy and a connectivity update. This capability is essential in todays connectivity-driven methodologies. In addition to cloning, synchronous clones

SPECIFICATIONS

Third-Party Support
OpenAccess-compatible tools and functions PDKs (please contact your foundry provider for more information)

Design Input

OpenAccess database SKILL STREAM format
For more information contact Cadence sales at:

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