V irtu o s o S che m at i c Edit o r L and XL
Fast, easy to use design and constraint entry

DATASHEET

The Cadence Virtuoso Schematic Editor family of products comprises the design and constraint composition environment that establishes the design intent of the industry-standard Virtuoso custom design platform, the complete solution for frontto-back custom-analog, digital, RF, and mixed-signal designs.

Family overview

The Virtuoso Schematic Editor product family provides the most comprehensive and flexible array of design and constraint composition capabilities that speed design and constraint entry and establish the design intent for the rest of the design and implementation tools. From abstracted architectural definitions, using industry-standard hardware description languages such as Verilog and VHDL, to final structural schematic implementations at the transistor level, the Virtuoso Schematic Editor family helps designers implement each stage in their designs, while capturing and ensuring consistency of design intent with constraints. The Virtuoso Schematic Editor product family is integrated with the Virtuoso Analog Design Environment, Virtuoso Multi-Mode Simulation, and Virtuoso Layout Suite to facilitate design convergence of front-to-back customanalog, digital, RF, and mixed-signal design flows.
The Virtuoso Schematic Editor product family provides a flexible set of product performance levels, Virtuoso Schematic Editor L and Virtuoso Schematic Editor XL, to best suit your design flow needs. Virtuoso Schematic Editor L provides all the capabilities necessary to speed design entry on even the largest and most complex custom designs. Virtuoso Schematic Editor XL builds upon the L level, adding the first front-to-back unified common constraint environment as well as advanced features to facilitate design team collaboration.

Family benefits

New, fast, easy-to-learn, easy-to-use design and constraint entry sets the design intent in one location Supports design abstraction by seamlessly integrating transistor schematics with language modules Features tight integration with other Cadence tools to speed design convergence
Increases productivity with new unified front-to-back common design environment Significantly speeds design entry, visualization, access, and control Lowers cost of support and maintenance with unified front-to-back design environment Flexible set of product levels supports a variety of design flows and needs Built-in design and language rule checking enables design problems to be found early Enables easy configuration and visualization of large, complex hierarchical designs Reduces risk by maintaining design intent between design specification and implementation with unified common constraint environment
Family features at a glance:

Feature

Multi-tab, multi-view canvas Customizable workspaces World View Assistant Hierarchical schematics with support for Verilog, VHDL, and Verilog AMS Hierarchical cross-probing front to back Generate bookmarks and history Expanded Search Assistant Design Navigator Assistant Property Editor Assistant Updated common constraints Constraint Manager Assistant Automated constraint annotation on schematic Circuit Prospector Assistant Analog schematic generation from SPICE HTML Design Publisher Analog schematic generation from SPICE Schematic to CPF model generator for Cadence low-power design flow

L

XL
V irt uos o Schemat i c E di t o r L

Product Overview

Virtuoso Schematic Editor L is the design intent environment of the industrystandard Virtuoso custom design platform, the complete solution for front-to-back custom-analog, digital, RF, and mixedsignal design. Virtuoso Schematic Editor L, which is built upon the new unified Virtuoso custom design platform, utilizes the latest advances in user interfaces and design tool integration to bring unprecedented levels of productivity and integration to design creation. The new unified Virtuoso custom design platform includes new capabilities and design flow enhancements such as modern, familiar, and user-customizable toolbars, icons, pull-down menus, a
Figure 1: Virtuoso Schematic Editor L

www.ca de nce.com

Virtuoso Schematic Editor L and XL
multi-tab, multi-view design canvas, workspaces, bookmarks, history, and more (see Figure 1). Virtuoso Schematic Editor L provides the most comprehensive and flexible array of design composition capabilities that can speed design entry on even the largest and most complex custom designs. From architectural definition, using industrystandard hardware description languages such as Verilog and VHDL, to final structural schematic implementations at the transistor level, Virtuoso Schematic Editor L helps designers implement each stage in their designs. For larger and more complex block- and chip-level designs, Virtuoso Schematic Editor L not only supports multi-sheet designs but also provides the ability to design hierarchically with no limit on the number of levels used. The integrated Hierarchy Editor makes hierarchical designs easy to traverse, and automatically ensures that all connections are maintained accurately throughout the design. Well-defined component libraries from the industrys broadest selection of PDKs, originated by the worlds leading foundries, enable faster schematic design at both the gate and transistor levels for process nodes from 0.35um to 28nm and everything in between. Advanced wire routing capabilities further assist in connecting devices. Virtuoso Schematic Editor L is integrated with the Virtuoso Analog Design Environment, Virtuoso Multi-Mode Simulation, and Virtuoso Layout Suite to provide a complete solution for frontto-back custom-analog, digital, RF, and mixed-signal design flows. To better suit your design flow needs, Virtuoso Schematic Editor L also provides an easy path to the higher performance level and constraint composition capabilities of Virtuoso Schematic Editor XL.

Benefits

New, fast, easy-to-learn, easy-to-use design entry Increased productivity with new unified front-to-back common design environment Significant speed improvements in design entry, visualization, access, and control Lower cost of support and maintenance with unified front-to-back design environment Flexible set of product levels to support a variety of design flows and needs Design problems found early with built-in design and language rule checking Easy visualization and configuration of large, complex hierarchical designs Rapid command execution with userconfigurable bindkeys and menus Custom check tabs and associated rules checks Inherited connections limit the clutter associated with power and isolation connectivity nets Recognizes sophisticated device parameter interaction using Cadence SKILL callbacks
UNIFIED VIRTUOSO DESIGN TASK ASSISTANTS
The design task assistants can be docked or undocked, configured, and saved in multiple workspaces suited to each designers styles and needs depending on the task at hand. A native Navigator Assistant provides quick, efficient, and intuitive access to the complete design hierarchy and all design objects directly from within the schematic editing environment. A native Search Assistant provides quick, efficient, and comprehensive search engine capabilities directly within the schematic editing environment. The Search Assistant automatically categorizes search results into logical groups, displaying common items in a familiar tree structure. This makes it very easy for users to find and access information within the design, the design libraries, menu commands, and even the Cadence SKILL programming language. Context-sensitive menus and double-click operations allow for rapid operations on selected results. A modern Property Editor Assistant docked around the main schematic editing canvas, or undocked and placed anywhere on a users workstation, allows fast, efficient, and intuitive editing of multiple properties on a single design object or multiple design objects. New multi-color visual display and coding of property values rapidly identifies common and varying property settings.

Features

UNIFIED VIRTUOSO CUSTOM DESIGN PLATFORM
Virtuoso Schematic Editor L utilizes all of the new unified features of the Virtuoso custom design platform to facilitate fast and easy design entry. A modern common user cockpit for design creation is accompanied by familiar and user-customizable toolbars, icons, and pull-down menus. Location and content of toolbars are user-defined and saved in custom workspaces for the most efficient use of screen space depending on tasks. A multiwindow, multi-tabbed canvas, bookmarks, and history define an intuitive editing environment, which allows users to open multiple schematics, or different views of the same design, and consequently manage their designs more quickly and effectively.

FAST AND ACCURATE DESIGN ENTRY
Virtuoso Schematic Editor L has many features that facilitate fast and easy design entry. First among these capabilities, a well-defined component librarywhich is integrated with the productenables fast design at both the gate and transistor level. This feature is complemented with sophisticated wire routing capabilities to assist in connecting devices. For larger and more complex designs, Virtuoso Schematic Editor L supports both multi-sheet designs and the ability to design hierarchically, with no limit to the number of levels used. Hierarchical designs are easy to traverse using the Hierarchy Editor, and
Virtuoso Schematic Editor L ensures that all connections are maintained accurately throughout a design.
EXTENSIVE DESIGN CHECKING CAPABILITIES
User-configurable rule checks identify drawing and electrical rule violations, such as overlapping components, open or shorted connections, unconnected inputs and outputs, object consistency, and illegal names to ensure the accuracy of your design. It allows the designer to check connections throughout the entire design hierarchy for pin name matches, completion of wire connections, and proper wire labeling. The designer has the flexibility of checking individual pages of a design, or checking the entire design hierarchy with one command. Users can create custom tab and associated rules checks for schematic rules check.
COMPREHENSIVE INTEGRATION CROSS-APPLICATION CAPABILITIES
Virtuoso Schematic Editor L is the complete single source for all connectivity-driven design, verification, and implementation needs. In conjunction with Virtuoso Analog Design Environment, Virtuoso Multi-Mode Simulation, and Virtuoso Layout Suite, Virtuoso Schematic Editor L provides crossapplication hierarchical browsing, selection, and backannotation. Connectivity and device parameters are checked for correctness using construction layout implementation. Bi-directional incremental updates are provided for complete engineering change order (ECO) control.
DESIGN WITH INDUSTRY STANDARD LANGUAGES
Virtuoso Schematic Editor L is well suited for entering mixed-level designs, using descriptions based on the industrys two leading hardware description languages VHDL and Verilog HDL. It also supports the ability to use Verilog-AMS and VHDL-AMS mixed-signal languages, thereby providing a standard way of entering designs regardless of design type. In addition to entering these languages, the user has the ability to generate block representations from the HDL descriptions automatically, facilitating a system-level approach to IC design.

V irt uos o Schemat i c E di t o r XL
Virtuoso Schematic Editor XL is the new design and constraint composition environment of the industry-standard Virtuoso custom design platform, the complete solution for front-to-back custom-analog, digital, RF, and mixedsignal design. Built upon the new unified Virtuoso custom design platform, and utilizing the latest advances in user interface and design tool integration, Virtuoso Schematic Editor XL includes all of the updated capabilities and design flow enhancements of Virtuoso Schematic Editor L with the added unified common constraint composition environment, bringing even higher levels of productivity to design creation and design team communication. The new unified Virtuoso common constraint environment is the first to capture, manage, and visualize critical custom design constraints, as well as being the first to formalize communication between design, verification, and implementation teams. Electrical and physical constraints are captured directly alongside connectivity in schematics to fully define a designs intent, leading to the formation of a complete design specification. This formal specification is used side by side with schematic-driven design to complete the first constraint-driven design environment. Interactive, assisted, and automated modes also aid in the formal signoff of constraint specifications (see Figure 2). Virtuoso Schematic Editor XL also inherits from the L tier all the modern, familiar and user-customizable toolbars, icons, pull-down menus, multi-tab multiview canvas, workspaces, bookmarks, history, and more. It also delivers the most comprehensive and flexible array of design composition capabilities that can speed design entry on even the largest and most complex custom designs. From architectural definition, using industrystandard hardware description languages such as Verilog and VHDL, to final structural schematic implementations at the transistor level, Virtuoso Schematic Editor XL not only helps you implement each stage in your design, it also maintains design intent throughout your flow. Virtuoso Schematic Editor XL operates with the same well-defined component librariesfrom the industrys broadest selection of PDKs coming out of the worlds leading foundriesfor process nodes from 0.35um to 28nm and everything in between, allowing for faster schematic design at both the gate and transistor levels. Virtuoso Schematic Editor XL is integrated with Virtuoso Analog Design Environment, Virtuoso Multi-Mode Simulation, and Virtuoso Layout Suite for the complete solution for front-to-back schematic and constraint-driven custom-analog, digital, RF, and mixed-signal design flows.

New, fast, easy-to-learn, easy-to-use design and constraint entry CPF model generation to support the Cadence low-power design flow Design publishing to facilitate design reviews over the web Reduce risk by maintaining design intent between design specification and implementation Facilitate design reuse by capturing the design process as IP Easy design reviews with integral documentation, specifications, measurement results, and waveforms Easily communicate critical design constraints between multiple users and sites Formally manage, verify, and signoff critical design constraints Increased productivity and design quality with constraint- and design-rule driven features to automatically ensure design and process correctness in real time Increased productivity with new unified front-to-back common design environment Significant speed improvements in design entry, visualization, access, and control Lower cost of support and maintenance with unified front-to-back design environment Flexible set of product levels to support a variety of design flows and needs Design problems found early with built-in design and language rule checking Easy visualization and configuration of large, complex hierarchical designs Rapid command execution with userconfigurable bindkeys and menus Inherited connections limit the clutter associated with power and isolation connectivity nets Recognizes sophisticated device parameter interaction using Cadence SKILL callbacks
Figure 2: Virtuoso Schematic Editor XL common constraint environment
Virtuoso Schematic Editor XL uses all of the unified features of the Virtuoso custom design platform to facilitate fast and easy design entry. A modern common user cockpit for design creation is accompanied by familiar and usercustomizable toolbars, icons, and pulldown menus. The location and content of toolbars can be defined by the user and saved in custom user workspaces for the most efficient use of screen space, depending upon the particular tasks undertaken. A multi-window multi-tabbed canvas, bookmarks, and history define an intuitive editing environment, which allows users to open multiple schematics, or different views of the same design, and consequently manage their designs more quickly and effectively.
verification functionality. Interactive, assisted and automated circuit prospecting, constraint templates and constraint generation aid in speeding the formal capture and signoff of constraint specifications preserving and ensuring designers intent on critical designs. Common circuit structures and topologies are built-in for automatic identification or prospecting, as well user-definable circuit structures and topologies, which are easily added to create an expanded set of circuit structures and constraints. Additionally, as done with schematics, constraints are captured as design IP to facilitate reuse.

Virtuoso Schematic Editor XL includes a suite of new unified front-to-back custom design task assistants that speed common creation, editing, checking, browsing, search, and design traversal tasks by as much as 5x over Virtuoso Schematic Editor L. The design task assistants can be docked or undocked, configured, and saved in multiple workspaces suited to each designers styles and needs depending on the task at hand.
UNIFIED VIRTUOSO COMMON CONSTRAINT ENVIRONMENT
Virtuoso Schematic Editor XL introduces the first unified common constraint environment comprising of a comprehensive suite of constraint capture, editing, visualization, management, and
A native Navigator Assistant provides quick, efficient, and intuitive access to the complete design hierarchy and all design objects directly from within the schematic editing environment. A native Search Assistant provides quick, efficient, and comprehensive search engine capabilities directly within the schematic editing environment. The Search Assistant automatically categorizes search results into logical groups, displaying common items in a familiar tree structure, making it very easy for users to find and access information within the design, the design libraries, menu commands, and even the Cadence SKILL programming language. Context-sensitive menus and double-click operations allow for rapid operations on selected results. A modern Property Editor Assistant docked around the main schematic editing canvas, or undocked and placed anywhere on a users workstation, allows fast, efficient, and intuitive editing of multiple properties on a single design object or multiple design objects. New multi-color visual display and coding of property values rapidly identifies common and varying property settings. A new Annotation Browser brings an easy-to-use interface to design and design object browsing while debugging common schematic and connectivity error markers.
Hierarchical designs are easy to traverse using the Hierarchy Editor, and Virtuoso Schematic Editor XL ensures that all connections are maintained accurately throughout the design.
parameters are checked for correctness using construction layout implementation. Bi-directional incremental updates are provided for complete ECO control.
Virtuoso Schematic Editor XL is well suited for entering mixed-level designs, using descriptions based on the industrys two leading hardware description languages VHDL and Verilog HDL. It also supports the ability to use Verilog-AMS and VHDLAMS mixed-signal languages, thereby providing a standard way of entering designs regardless of design type. In addition to entering these languages, the user has the ability to generate block representations from the HDL descriptions automatically, facilitating a system-level approach to IC design.

Specifications

DESIGN COMPOSITION
Unlimited design hierarchy support Simplified automatic generation of an HDL template Support of multi-sheet schematics HTML publisher for schematics Power Intent Export Assistant, to specify power intent of the design User-configurable command bindkeys and label display Dynamic highlighting for easy design correction Automated interactive connection router User-configurable selection with filtering Comprehensive symbol creation and editing features User-configurable undo/redo levels Move, copy, stretch, rotate, and delete editing options Search and replace features Customizable tool environment using Cadence SKILL Online help system using HTML/PDF formatted publications
To ensure the accuracy of designs, user-configurable rule checks identify drawing and electrical rule violations, such as overlapping components, open or shorted connections, unconnected inputs and outputs, object consistency, and illegal names. This capability allows the designer to check connections throughout the entire design hierarchy for pin name matches, completion of wire connections, and proper wire labeling. The designer also has the flexibility of checking individual pages of the design, or checking the entire design hierarchy with one command.
Virtuoso Schematic Editor XL has many features that facilitate fast and easy design entry. These capabilities start with well-defined component librarieswhich are integrated with the productthat allow for fast design at both the gate and transistor levels. This feature is complemented with sophisticated wirerouting capabilities to assist in connecting devices. For larger and more complex designs, Virtuoso Schematic Editor XL supports both multi-sheet designs and the ability to design hierarchically, with no limit to the number of levels used.

DESIGN CHECKING

Schematic or symbol cell views checked individually Entire design hierarchy checked with one command Connectivity and consistency checks across pages and hierarchy Schematic rules checker (SRC) makes both logical and physical checks
Virtuoso Schematic Editor XL comprises the complete single source for all connectivity-driven design, verification, and implementation needs. In conjunction with Virtuoso Analog Design Environment, Virtuoso Multi-Mode Simulation, and Virtuoso Layout Suite, Virtuoso Schematic Editor XL provides cross-application hierarchical browsing, selection, and back annotation. Connectivity and device

DESIGN INPUTS

CDL netlist EDIF 0 netlist SPICE netlist
VHDL IEEE 1076-1993 Verilog IEEE 1364 Cadence SKILL
CADENCE SERVICES AND SUPPORT
Cadence application engineers can answer your technical questions by telephone, email, or Internetthey can also provide technical assistance and custom training Cadence certified instructors teach more than 70 courses and bring their real-world experience into the classroom More than 25 Internet Learning Series (iLS) online courses allow you the flexibility of training at your own computer via the Internet Cadence Online Support gives you 24x7 online access to a knowledgebase of the latest solutions, technical documentation, software downloads, and more

DESIGN OUTPUTS

CDL netlist EDIF 0 netlist SPICE netlist VHDL IEEE 1076-1993 Verilog IEEE 1364

HW/COMPUTING PLATFORM/OS

Sun/Solaris HP-UX IBM AIX Linux
For more information contact Cadence sales at:

+1.408.943.1234

or log on to:
www.cadence.com/ cadence/contact_us
2011 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Verilog, and Virtuoso are registered trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 21928 03/11 IW/MK/DM/PDF

VIRTUOSO CUSTOM DESIGN PLATFORM XL
Figure 1: All components of the Virtuoso platform work together to support fast, silicon-accurate differentiated custom silicon

G0007A

DATASHEET
The Virtuoso custom design platform comprises several advanced products.
The Cadence Virtuoso custom design platform XL family of products extends the L family to provide higher levels of design assistance to the end user. The platform includes Virtuoso Schematic Editor XL, Virtuoso Analog Design Environment XL, and Virtuoso Layout Suite XL.

PERFORMAN CE

PARA SI
Design Specification Multi-mode Simulation Accelerated Layout Silicon Analysis Chip Finishing
VIRTUOSO SCHEMATIC EDITOR XL
Virtuoso Schematic Editor XL delivers extended functionality through the addition of assistants that speed common tasks by as much as 5x over Virtuoso platform L methodologies. To maintain design consistency throughout the custom design flow, the user can use design constraints. These constraints, which cover needs such as matching and symmetry, are added to the schematic by the designer to guide the implementation tools to maintain thedesigners intent on critical pieces of the design.
Open Database Constraint Management

PDKs Customer IP

VIRTUOSO ANALOG DESIGN ENVIRONMENT XL
Virtuoso Analog Design Environment XL is the most advanced design and simulation environment for the Virtuoso platform. By supporting extensive exploration of multiple designs against their objective specifications, it sets the standard in fast and accurate design verification.

VIRTUOSO LAYOUT SUITE XL

Virtuoso Layout Suite XL is the high-end custom block authoring physical layout product of the Virtuoso platform. It supports both constraint- and schematicdriven physical implementation of customdigital, mixed-signal, and analog designs at the device, cell, and block levels (see Figure 2). As the design composition environment for the Virtuoso platform, Virtuoso Schematic Editor XL delivers an extensive set of tools for custom IC design entry. From architectural definition using industry-standard language representations (such as Verilog, VHDL, and C) to final structural implementations at the transistor level, it helps engineers implement each stage in a design. The concept of design constraints is introduced at the XL level. These constraints allow design intent to be stored electronically and adhered to throughout all the different tool interactions that occur in later parts of the design cycle. Virtuoso Analog Design Environment XL manages the exploration and v erification of multiple designs in one easy-to-use tool. Throughout the design and verification process, any circuit can be monitored against its objective s pecifications with fast pass/fail feedback. In addition, all sweeps, corners, Monte Carlo statistics, and measurements are managed and stored in one location for fast and accurate verification of a design. As a high-end custom block authoring physical layout tool, Virtuoso Layout Suite XL provides accelerated features beyond the basic polygon layout editing features of Virtuoso Layout Suite L. It supports
Figure 2: Virtuoso Schematic Editor XL
custom-digital, mixed-signal, and analog designs at the device, cell, and block levels. These accelerated features provide advanced connectivity, constraint- and design-ruledriven functionality combined with advanced automation to accelerate custom block authoring. Included are device generation and editing with parameterized cell (Pcell) and SKILL programming support (see Figure 3).
Improves verification throughput with simulation distribution and multi-test management Ensures quality through the standardization of design methodologies Provides constant visibility into the design status of multiple projects acrossmultiple sites Simplifies design reviews through integral documentation, specifications, measurement results, and waveforms Accelerates block authoring via connectivity-driven features and flows schematic or netlistwhich promotes correct-by-construction LVS-correct layout to reduce verification iterations Increases productivity and design quality with constraint- and design-ruledriven features to automatically ensure design and process correctness in real time Simplifies and optimizes device generation using a new menu-driven QuickCell feature or standard SKILL-programmable Pcells Express Pcells capability reduces data load time and manipulation response time of large designs

BENEFITS

Maintains design integrity by using design constraints throughout the XL tool flow Provides easy visualization of large, complex designs using the Hierarchy Editor Enables early discovery of design problems with built-in design and language rule checking Rapidly executes commands with userconfigurable bind keys and menus Reduces risk by maintaining agreement between design and specification as well as through managing validation ofdesign, process, and spec changes Eases design reuse through capturing the design process as IP

www.cadence.com

VIR TUOSO CUSTOM DESIGN PLATFORM XL
Environment XL supports sweeps, corners, and Monte Carlo analysis over one or more of the available tests. All results are automatically stored for validation against the objective specifications. Virtuoso Multi-Mode Simulation is fully integrated into the standard cockpit, as well as the majority of third-party simulation technologies.
CONNECTIVITY-DRIVEN FUNCTIONS AND FLOW ACCELERATE DESIGN COMPLETION
Virtuoso Layout Suite XL has set the standard in the industry and changed the way custom block authoring is done. Driven by a schematic connectivity source using Virtuoso Schematic Editor XL or a netlist source such as CDL or SPICE, designers can achieve an LVScorrect layout in real time. This approach promotes correct-by-construction layout, improves productivity, and reduces verification time. Additionally, it enables automation of tedious design tasks such as device generation, placement, and routing. Schematic and layout can be cross-probed to highlight instances and devices as well as to quickly identify unconnected nets (see Figure 4).
Figure 3: Virtuoso Analog Design Environment XL

FEATURES

FAST AND ACCURATE DESIGN ENTRY Virtuoso Schematic Editor XL provides many features that facilitate fast and easy design entry. In addition to all the features offered in the L configuration, XL adds assistants for search, property editing, viewing, and traversing the design hierarchy. These assistants provide up to a 5x increase in productivity when performing these common tasks. The XL configuration also offers new capabilities such as tabs, configurable workspaces, and new menu structures to mirror common features in Web browsers. More advanced users can quickly execute commands using user-programmable bind keys and object-sensitive pop-up menus, which display relevant operations for objects under the cursor, anticipate userrequirements, and present only pertinent choices.
unified cockpit. A specification consists of multiple tests, which are formed by combining test harnesses with specific measurements. Virtuoso Schematic Editor XL eases the development of multiple tests over multiple conditions to validate a designs performance against the target s pecification. Once created, the tests and the complete specifications can be shared and managed across multiple design groups to set standards of testing for specific types of designs. The project level provides access to all the tests, sweeps, corners, scripts, and documentation needed to completely validate a design against the target specification. An overview of all the tests within a project is available through the test assistant, which presents the status of all tests along with easy access to all the waveforms, measurements, and simulation files. From the assistant, all tests can be run individually or together for a complete design investigation and verification. The designer can use the parallel-processing options for efficient simulation management. In addition to standard SPICE and RF simulation analyses, Virtuoso Analog Design

CONSTRAINT- AND DESIGNRULEDRIVEN FUNCTIONS FOR IMPROVED PRODUCTIVITY
Virtuoso Layout Suite XL provides design constraint specification and management and design-ruledriven features that are automatically flagged when in violation or enforced in real time. This capability coupled with connectivity promotes correct-by-construction layout, improving productivity and reducing physical verification iterations and time. Device generation, placement, and routing function (both automatic and done manually with the wire editor) obey the constraints and all technology file process rules. All process nodes are supported, from classic analog at.25u all the way down to leading-edge 45nm processes.
SPECIFICATION-DRIVEN DESIGN
To accelerate design verification, Virtuoso Analog Design Environment XL combines specification entry and design management into a single
TIGHT INTEGRATION WITH THE VIRTUOSO PLATFORM
All of these features are an integral part of the Virtuoso custom design platform, connecting to all the other features of the platform. This integration provides a single environment to create, analyze, and implement multi-domain designs, including ASICs, programmable ICs, multi-chip modules, and digital, analog and mixed-signal ICs. The Virtuoso platform supports the industry-standard OpenAccess (OA) database, as well as the Cadence SKILL programming language, which facilitates customization of the environment and the encapsulation of proprietary design tools.
Dynamic highlighting for easy design correction Automated interactive connection router User-configurable selection with filtering Comprehensive symbol creation and editing features User-configurable undo/redo levels Move, copy, stretch, rotate, and delete editing options Search and replace features Customizable tool environment using Cadence SKILL Online help using HTML formatted publications
Specifications sheets to compare design to design, design to model, or process to process Projects can be shared among multiple users and sites Distributed processing Parallel analysis of multiple tests Creation and tracking of dependencies among tests Calculator, Ocean, MDL, and MATLAB measurement strategies Tests overview window with s pecification checking Integrated with Virtuoso Multi-Mode Simulation Cross-probing and annotation to schematics Integrated Wavescan waveform displayand waveform calculator for sophisticated analysis Integral documentation creation

SPECIFICATIONS

DESIGN COMPOSITION
Complete design hierarchy support Simplified automatic generation of an HDL template Support of multi-sheet schematics User-configurable command bindkeys and label display
DESIGN SIMULATION AND ANALYSIS
Design exploration with sweeps, corners, and Monte Carlo statistics Creation of specifications directly from simulation results

PHYSICAL IMPLEMENTATION

Automated device editing, including abutment, pin permutation, folding, chaining, and cloning Menu-driven or programmable multipart path (MPP) feature for guard rings, slotting, etc. Design-ruledriven editing with real-time notification or enforcement ofprocess rules Dynamic measurement Constraint-driven specification, management, and real-time notification or enforcement Automatic constraint- and design-rule driven placement of pins, devices, cells, and blocks Advanced shape-based constraint- and design-ruledriven interactive routing ECO support Legacy non-connectivity design importing and connectivity mapping
Figure 4: Virtuoso Layout Suite XL
Assura physical verification support

DESIGN INPUTS

OpenAccess data objects Cadence proprietary languages: Ocean and MDL SPICE netlists EDIF 0 netlist Circuit design language (CDL) SPICE VHDL IEEE 1076-1993 Verilog IEEE1364 SKILL STREAM format CDL and SPICE netlist format Verilog and VHDL AMS languages
VIRTUOSO CUSTOM DESIGN PLATFORM XL features
Virtuoso Schematic Editor XL
New Common Cockpit New Icon Style Multi-Tab Support Bookmarks & History Updated Pulldown Menus Window Config Support World View Assistant Search Assistant Property Editor Assistant y Navigator Assistant Constraint Browser Design Explorer Single Test-bench g Simple Parametric Analysis Device Checking g Global Variable Support Updated Wavescan New Calculator Simulation Support: Virtuoso Multi-mode Simulation, HSPICE Basic Polygon Editing Q-Cells DRD Editing Constraint Browser Search Assistant Property Editor Assistant

X X X X X X X X X X X X

Virtuoso Analog Design Environment XL

X X X X X X

Virtuoso Layout Suite XL
DESIGN OUTPUTS (VIRTUOSO SCHEMATIC EDITOR XL)
EDIF 0 netlist CDL SPICE OpenAccess SKILL STREAM format
X X X X X X X X X X X X X

THIRD-PARTY SUPPORT

Access to other third-party simulators from Synopsys, Mentor Graphics, Silvaco, Magma, Berkeley Design Associates, and in-house proprietary simulators are supported through the Virtuoso Analog Design Environment interface Supports MATLAB from Mathworks foradditional measurements and visualization
DESIGN OUTPUTS (VIRTUOSO ANALOG DESIGN ENVIRONMENT XL)
PSF waveform format SST2 waveform format Perl scripts PLATFORM/OS Sun/Solaris HP-UX Linux IBM AIX

SourceLink online customer support gives you answers to your technical questions24 hours a day, 7 days a weekincluding the latest in quarterly software rollups, product release i nformation, technical documentation, software updates, and more.
Cadence-certified instructors teach more than 80 courses and bring theirreal-world experience into the classroom. More than 25 Internet Learning Series (iLS) online courses allow you the flexibility of training at your own c omputer via the Internet.
CADENCE SERVICES AND SUPPORT
Cadence application engineers can answer your technical questions by telephone, email, or internetthey can also provide technical assistance and custom training.
For more information, Email us at

info@cadence.com

or visit
2008 Cadence Design Systems, Inc. All rights reserved. Cadence, Assura, Verilog, and Virtuoso are registered trademarks and the Cadence logo is a trademark of Cadence Design Systems, Inc. All others are properties of their respective holders. 20583/7021D 0408 KM /FLD /CS/PDF