Voltagestorm Power and Power Rail Verification

DATASHEET

ENCOUNTER PLATFORM
To release innovative products in narrow market windows, companies need to focus precious engineering resources on where they add the most valuedifferentiating their designs. The Cadence Encounter digital IC design platform offers a full spectrum of technologies for nanometer-scale SoC design, helping both logic design www. cadence.com/solutions/logic_design/ index.aspx and physical implementation www.cadence.com/solutions/digital_ implementation/index.aspx teams achieve high-quality silicon quickly. As an integrated RTL-to-GDSII design environment, the Encounter platform provides a complete flowfrom RTL synthesis and test design through silicon virtual prototyping and partitioning to final timing and manufacturing closure. It delivers the highest quality of silicon
The complexities associated with todays power-sensitive designs increases the risk that IR drop will be a cause of silicon failure. Design teams require comprehensive power and power rail analysis solutions that can accurately validate on-chip power delivery networks, from initial power planning through final signoff prior to tapeout. Within the Cadence Encounter digital IC design platform, VoltageStorm power verification helps you quickly validate and optimize your power networks using both static and dynamic analysis approaches.
(timing, area, and power with wires), accurate verification, signal-integrity aware routing, and the latest yield and low-power design capabilities that are critical for advanced 65nm designs. With Encounter technology, you can boost your productivity, manage complexity, and get your products to market faster. Encounter platform products are available in L, XL, and GXL offerings.
VOLTAGESTORM POWER AND POWER RAIL VERIFICATION
Delivering the accuracy, capacity, and performance to handle the most complex multi-million gate designs, the VoltageStorm hierarchical solution gives design teams the confidence that IR (voltage) drop and power rail electromigration are managed effectively.
VoltageStorm power verification has been proven to validate IR drop and power electromigration (EM) on thousands of designs. Initially used as an IR drop and power EM signoff solution prior to tapeout, VoltageStorm technology has evolved to become an integral component of design creation, which requires early and up-front power rail analysis to help create robust power networks during power planning. Employing parasitic extraction that is manufacturing aware, and using patented static and dynamic algorithms, VoltageStorm technology continues to deliver power estimation and power rail analysis functionality and automation that you can depend on to both analyze and optimize your power networks throughout the design flow.

BENEFITS

Enables efficient creation of on-chip power networks Power routing sizes De-coupling capacitance size and location Minimizes risk of power-related silicon failures Outputs comprehensive static and dynamic IR drop reports Enables IR drop-aware timing and SI noise analysis (requires Cadence Encounter Timing System or CeltIC NDC) Optimizes low-power designs Reports on-chip power density Allows tradeoff between de-coupling capacitance and leakage Validates power-switch sizes and power-up time Verifies impact of power-up rush current on surrounding logic Delivers an efficient, hierarchical analysis solution Uses power grid views to maximize accuracy, performance, and capacity Accurately models IP, custom digital, analog, and mixed-signal blocks Supported by major reference flows, ASIC and IP vendors, and IDMs Recommended by TSMC 7.0 Reference Flow Recommended by Starc ZD 3.0 Flow Library power grid views available directly from ARM and TSMC PowerMeter

.lib DEF DSPF SPEF

Figure 1: Example VoltageStorm plots (from left to right: IR drop, current density, and recommended de-coupling capacitance)

FEATURES

VoltageStorm power and power rail verification provides a comprehensive solution for power analysis and contains the functionality to accurately address the requirements associated with multiple design styles, including SoC, low-power, ASIC, and custom digital designs. Employing a combination of static and dynamic analysis approaches, VoltageStorm solutions can be used for power rail verification during the complete physical design creation flow, from early power planning through signoff prior to tapeout. To enable this comprehensive support, the VoltageStorm solution contains the functionality to calculate static and dynamic power consumption plus the functionality to perform both static and dynamic power rail analysis.
Power-driven design requirements
For design teams to manage power consumption effectively, they must understand the source of the power, typically either active power or leakage power. For design teams to create robust power networks, in addition to understanding the details of power consumption, they must understand how to optimize power rail routing and sizes and the size and location of power switches (low-power designs) and de-coupling capacitors. VoltageStorm technology contains all of the functionality required to help you with these power-driven design requirements.
PowerMeter power estimation
PowerMeter is the power estimation functionality within the hierarchical, cell-based VoltageStorm solution. PowerMeter allows you to calculate static power consumption and dynamic power Dynamic Power

Static Power

TWF SLEW SDC TFC/ VCD1 DSPF SPEF

TWF SLEW

PowerMeter
Instance-based Static Current
Instance-based Dynamic Current Waveform cell
1. Optional VCD input used to seed activity
Figure 2: PowerMeter data flow and usage
2. VCD required for vector-based analysis or to seed vectorless analysis

www.cadence.com

Voltagestorm
transients for all instances within a design. Optional VCD vectors can be used to seed the activity for static or vectorless dynamic power calculation. VCD vectors can also be used to directly drive PowerMeter for vector-based dynamic power calculation. PowerMeter uses a proprietary activity propagation algorithm that enables comprehensive nodal activity to always be generated, driven by default activity or seeded by partial activity information supplied by the designer.
VoltageStorm PE + DG Full-chip Analysis GDS/ DEF Boundary Voltages

IP or Memory

Power Grid View Library
LibGen Block Powergrid Views

Analog or AMS

IP or Memory Analog or AMS

VoltageStorm PE + DG Transistor Dynamic VAVO Transistor Dynamic Cell-based Dynamic Cell-based Static

VoltageStorm PE

VoltageStorm PE enables hierarchical static power estimation using PowerMeter and hierarchical static power rail analysis. A static approach to power rail verification helps you rapidly check that the power rails can supply the amount of power needed by the design, without creating high amounts of IR drop. Static analysis if often used for pre-tapeout signoff for process technologies at and above 130nm, where the amount of natural de-coupling capacitance diminishes the need for dynamic analysis. Static analysis is a necessary step prior to executing dynamic analysis, to ensure that the power rails are robust prior to finetuning with de-coupling capacitance incorrectly sized power routing cannot be fixed by adding de-coupling capacitance.

Block-level Analysis DEF

VoltageStorm DG
Figure 3: Hierarchical power rail analysis
level-shifting logic, voltage clamp circuitry, and the use of power switches to minimize leakage. VoltageStorm DG gives you additional insight on how fast a block powers up after it was powered down, and the IR drop impact of the block powering up on surrounding logic.
Automated de-coupling capacitance optimization
Once youve completed dynamic power rail analysis using VoltageStorm DG, the solution can calculate and recommend the amount of additional de-coupling capacitance necessary to limit the dynamic IR to user-specified limits. This recommended additional de-coupling capacitance can then drive an automated optimization flow within the SoC Encounter system, where filler cells are swapped with de-coupling capacitance cells.
Transistor-level analysis
With the VoltageStorm hierarchical analysis solution, you can use the technology at the transistor-level to perform power rail analysis for custom digital blocks. Using GDSII input and the Virtuoso UltraSim simulation engine, the VoltageStorm solution enables staticand vector-based dynamic analysis.
With hierarchical vectorless and vectorbased dynamic analysis, VoltageStorm DG extends the static analysis capabilities of VoltageStorm PE. At and below 90nm, high dynamic currents caused by simultaneously switching logic can cause high transients of dynamic IR drop on both power and ground rails. Using VoltageStorm DG, design teams can determine the dynamic power consumption created by simultaneous switching and the dynamic IR drop caused by these high currents. Both VoltageStorm PE and DG provide full support for low-power design methodologies that employ multiple voltage domains, multiple thresholds,

User IR Drop limit = 75mV
ECO File to Optimize de-caps SoC Encounter Analysis result after adding de-cap Worst-case IR < 63mV
Original analysis result Worst-case IR < 75mV (red)
1. IR drop before optimization

2. Recommended De-caps

3. IR drop after optimization
Figure 4: Automated de-coupling capacitance optimization flow
Impact of IR drop on timing and SI noise
While some design teams use IR drop margins to ensure that their designs will not suffer from IR drop issues, a more comprehensive approach is to fix IR drop issues that are shown to impact timing and SI noise. VoltageStorm technology calculates instance operating voltages during the timing (switching) windows associated with each instance, and provides this information to Encounter Timing System or CeltIC NDC, which calculate the impact of IR drop on delay- and SI-generated noise.

SPECIFICATIONS

System requirements
Specific requirements are design dependent 512MB (min) DRAM 2GB (min) swap space 50MB software disc space 2GB per 1M gates design disc space For more information, email us at info@cadence.com or visit

Platform/OS

Sun Solaris 8 or 9 (32-bit, 64-bit) HP-UX 11.0 (32-bit, 64-bit) Opteron Linux RHEL 3.0 (64-bit) Red Hat Linux RHEL 2.1 (32-bit) BM AIX 5.1 (32-bit, 64-bit)

VoltageStorm PE + DG

Power Consumption

Interface

OpenAccess 2.2
Chip & Package Design Creation or OpenAccess
Dynamic Instance -based Power

PowerStorm

De-cap ECO IR Drop & EM
Dynamic Instance Operation Voltage

Cadence QRC Extraction

Encouter Timing System SI-based Timing Analysis
Figure 5: Flow to analyze impact of IR drop on timing and SI noise
Cadence Design Systems, Inc.
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2006 Cadence Design Systems, Inc. Cadence, CeltIC, Encounter, Virtuoso, and VoltageStorm are registered trademarks, and the Cadence logo and SoC Encounter are trademarks of Cadence Design Systems, Inc. ARM is a registered trademark of ARM, Ltd. All others are properties of their respective holders. 7222 11/06 MK/MVC/JA/PDF

Using First Encounter and VoltageStorm to Optimize Peak IR drop or Power Mesh Area
Kevin Kelley Cadence Design Systems Arden Hills, Minnesota kevink@cadence.com

Abstract

The design of efficient power distribution meshes is increasingly subject to worst case IR drop, and the effect that IR drop will have on circuit timing. While power planning tools can optimize a power grid for a specified maximum IR drop, this level of detail omits two important factors from analysis. The first is whether the maximum IR drop threshold is correctly chosen. For example, if a number of critical timing paths pass through the area of maximum IR drop, and the reduced supply voltage causes those timing paths to experience setup or hold failures, then the maximum IR drop threshold may need to be lower. Likewise, if the power grid is over-designed, we may be able to gain area by reducing P/G wire width without worsening peak IR drop, and thereby improve critical path timing by freeing routing channels for more direct signal routing. This session will present an example that demonstrates the trade-offs between stripe width, peak IR drop, and worst case delay paths using Cadence SOC Encounter and VoltageStorm-PE.

Introduction

The optimal IC power distribution network is capable of delivering adequate current to the IP blocks, memories, and standard cells on the chip without consuming excessive routing resources. Because the power distribution network (rings, stripes, followpins) is a resistive network, Ohms Law states that there will be a reduction in voltage as current travels from the power pads into the core area, since V = I*R. Likewise, the resistive ground network will experience an increase in voltage as current travels through it, a behavior known as ground bounce. All the remarks made here about controlling IR drop also apply to ground bounce. The aim of the designer is to prevent IR drop or ground bounce from exceeding a specified threshold. A 10% reduction in VDD voltage is often used as a starting point for maximum IR drop, but the absolute maximum is highly design dependent. As VDD supply voltage scales down with new process nodes, the total IR drop budget also scales down. The main effects of IR drop and ground bounce are on timing and on signal integrity. Because a reduction in supply voltage will slow down a gate transition, IR drop and ground bounce affects setup and hold timing as well as clock skew. Cells in areas of the design with high IR drop are impacted more severely than others, so the timing of a clock or data path will depend on where the constituent cells are located on the chip. IR drop and ground bounce also increase the susceptibility of a signal to crosstalk noise, since a noise glitch of a given voltage represents a higher percentage of a nets noise threshold when the supply voltage on its receiver has been reduced by IR drop. In the worst case, the adverse effects on timing and crosstalk vulnerability can be severe enough to cause a functional failure. The maximum IR drop or ground bounce we can tolerate will depend (at least in part) on the circuit timing and layout. For example, a path that easily meets timing can tolerate more IR drop on its constituent cells, than a path with little or no slack.
IR drop and ground bounce can be reduced by increasing the width or number of power straps, since this reduces the total resistance of the power grid. But this will also reduce the amount of resources available for signal routing, increasing routing congestion and possibly creating or worsening timing and signal integrity violations. So the ideal power grid solution will both influence and depend upon circuit timing and congestion. Power rail analysis can highlight the magnitude of IR drop in different regions of the chip, telling the designer where the power network may need to be improved, or exposing where there are missing vias or other opens. But a designer should also have the ability to do congestion analysis and static timing analysis at the same time, so they can identify how best to trade-off between power and signal wiring. Fortunately, the means to analyze power grid, timing, and signal integrity trade-offs are available in todays generation of IC design tools. This paper presents an example with a 0.13um, six routing layer standard cell design of average size, analyzed using Cadence First Encounter and VoltageStorm-PE, though other combinations of tools are possible. A representative IR drop display from VoltageStorm-PE is shown here in the First Encounter GUI. The regions in red are the areas of unacceptably large IR drop:

Figure 1. IR drop display in First Encounter. Note that IR drop effects may become much worse with technology scaling. Researchers at USC (see reference #6) submitted a paper to the ISQED in 2003, exploring the relationship between technology scaling and IR drop effects. As geometries shrink, severe performance degradation results. For example, clock tree skew becomes much worse due to uneven IR drop effects across the chip. The degradation is caused by higher temperatures, resistivity increase of Cu interconnects due to electron surface scattering, finite barrier thickness and other factors.

Data Preparation

Libraries. For any given process technology and foundry, a significant amount of one-time data preparation is required for detailed power rail and signal integrity analysis. Apart from the usual timing libraries (dotlibs) and LEF libraries needed for place and route, the designer will also need libraries for crosstalk noise analysis and libraries for power rail analysis. In addition, process technology file(s) may be required for sign-off quality parasitic extraction and other analyses. The libraries may be prepared by an in-house library group, by an outside party, or by the designers themselves. However, these libraries are for the most part not design-specific and are reused whenever a new design is implemented in the same technology. A few such inputs for the Cadence SOC Encounter and VoltageStorm-PE flow are listed here: A process specific technology file is required for sign-off RC extraction as well as for VoltageStorm power rail analysis (which performs an extraction step on the power network). The starting point is an ASCII interconnect technology (ICT) file describing the process layer geometries, and any manufacturing effects that may affect these metals. It is processed by programs like icecaps or RCGen to create a binary technology file that is used for accurate extraction. The library of standard cell and block models for VoltageStorm is created with a utility called LibGen. LibGen starts from LEF, GDS, or both to create a view of the cell or blocks internal power grid. Such models can be very detailed, or simplified to save memory and processing time. The library of cell or block level noise models for CeltIC crosstalk analysis is created by a utility called make_cdb. Make_cdb combines dotlib and transistor level information about a cell to create a model which can be used for determining (for example) whether the cell will attenuate or amplify a noise glitch of some magnitude.

Place, Route, RC extract. For a given design, it is necessary to perform a place and route and parasitic extraction before timing and signal integrity analysis can be done. SOC Encounter has the choice of a quick and dirty router (trialRoute) and a sign-off signal router (NanoRoute). Likewise you can choose a quick and dirty RC extraction or a sign-off RC extraction. One uses the quick and dirty tools early on, in the so-called virtual prototyping phase of design. The sign-off tools are usually used only for final analysis and implementation. Power Planning. Besides place, route, and extraction, it is also necessary to have a basic power distribution network in place, and some kind of power dissipation information in order to perform power rail analysis. The latter may range from a rough top-level estimate of power dissipation across the chip, to very detailed net-by-net switching power calculated from a VCD file. Designing a power grid for a complex SoC may be very complex; however from the standpoint of the First Encounter tool the steps are reasonably simple. You can either create a power distribution network for a single chip using the Power Planning menus and commands, or alternately, you may create a power template which can be used on numerous chips. The latter would be instantiated onto a chip, and First Encounter will automatically adjust the model to the current floorplan arrangement. The basic steps of power planning are summarized below: The globalNetConnect command creates the connectivity between the special nets and cells/blocks which they supply. The cutCoreRow and displayCutRow commands cut away standard cell rows from the IP and memories, and then display the revised row area. Add power rings around the core, and block rings around blocks, row clusters, and power domains. The global power ring is customarily drawn on higher metal layers, since resistance is less compared to lower layers; because all supply current usually must pass through the global power ring, these wires are likely to have higher IR drop. Add power stripes within the overall design, within a specific area, or over specified blocks or power domains. There may be one or more local grids defined in addition to a global grid. Connect the ring pins using the SRoute form. The SRoute special router software routes power and ground nets to block pins, pad pins, standard cell pins, and any unconnected stripes.
Power Rail Analysis prerequisites. In order to perform power analysis, the designer must supply the location of the power pads, and define some means of estimating the switching activities of the instances. The ideal situation is to have a VCD file from a good, representative full chip simulation. Lacking that, one can use static or statistical mode, where the tool is given as much as possible about the clock domains, and the average toggle frequency within each. From this input, instance based power consumption can be estimated. Although power calculation and power rail analysis are technically two separate steps, they are accomplished with just one command: updatePower within First Encounter, or runVStorm when using PowerMeter and VoltageStorm-PE. Two Power Analysis Engines Available. First Encounter has its own power analysis engine, but the designer may also use PowerMeter, which is the power calculator supplied with the VoltageStorm-PE product. If one is working from the First Encounter GUI, there is no particular usability advantage of one over the other. Both calculators are easy to use from inside First Encounter, and both can work with incomplete information. PowerMeter can also be used in standalone mode for more detailed analysis. For the moment well look at how to set up power analysis in First Encounter. Power Pad Locations, Toggle Estimates. The objective of power and ground pad placement is to maximize voltage potential to current drain tap points on the global ring. The current brought in from the power pads should be distributed to minimize the current flowing in different segments of the global ring. This minimizes IR drop from the power/ground cells to current tap points; and thus the equivalent resistance seen from any power pad towards standard cell rails also decreases. The motto is: Maximum current encounters minimum resistance in the global power ring. Selecting VDD PAD locations in the Encounter GUI is simple (or you can use the Tcl command addPadLocation x y). savePadLocation -outfile VDD_locs.pp stores the list, which can be loaded back in future sessions with loadPadLocation -file VDD_locs.pp. You can create this list automatically if your power pad cells are properly defined with USE POWER and USE GROUND in LEF. This automatic pad location is done using the Auto Fetch feature. Likewise it is easy to make a rough start on the toggle estimates by going into Power > Analysis > Edit Net Toggle Probability. Use the "Get Clock" radio button to read the SDCs, and extract all the defined clocks and their frequencies. For example, for a clock defined by: create_clock [get_ports {clk2x}] -name my_clk_2x -period 6.0 -waveform {0 3.0} the software determines that the frequency is 166.667 MHz and assigns an average toggle probability of 0.2, meaning the average net (including clocks) in that domain toggle once in five clock periods: my_clk_2x 166.667 0.200 Toggle Count File (TCF). You can edit this probability if you like and make other changes before clicking "save" (or running saveToggleProbability) to store these into a simple ASCII file which can also be used later. There is also a button on the Edit Net Toggle Probability menu to "Generate Tcf" which runs writeTcf based on those toggle probabilities, but only for the primary inputs. You can add more information to the TCF file manually if desired. A short snippet of a TCF is shown here: tcffile () { tcfversion : "1.0"; generator : "First Encounter"; genversion : "06.10-p005_1"; date : "12:54:23 07/21/2006"; duration : "1.00000e+09"; unit : "ns"; instance () { net () { "clk" : "0.500000 166666000"; "clk2x" : "0.500000 333334000";

Now, you can choose between running Encounter power analysis in static mode, which is driven from the TCF, or in statistical mode, driven by the toggle probability file. The power analysis is easy to drive from the GUI; the Tcl command is updatePower. Static: updatePower -irDropAnalysis average -postCTS -tcf my.tcf -pad VDD_locs.pp -temperature 30 -mode floorplan VDD Statistical: updatePower -irDropAnalysis average -postCTS -toggleFile tgl_rate.tg -pad VDD_locs.pp -temperature 30 -mode floorplan VDD Different power estimation methods may not agree with each other. It is up to the designer to supply as much power switching information that is accurate as possible, recognizing that perfect information may not be available. Its particularly important to ensure power analysis knows what parts of the core consume more power relative to others. This will influence how much IR drop is seen across different areas of the design.
Evaluating IR drop vs. Routing Congestion
The key to making good tradeoffs between timing, IR drop thresholds, and congestion is the capability to view the results concurrently in the First Encounter GUI. Fortunately, this is fairly easy. Congestion maps can be turned on and off; critical timing paths can be highlighted, and color coded IR drop results can be displayed as well, as was seen in Figure 1. Figures 2 and 3 below show the congestion map for this same design. Only a few small areas of routing congestion between RAMs are observed in Figure 2. Routes are temporarily turned off to better display the congestion. Figure 3 shows a detail area from the congestion map.
Figure 2: Routing congestion.
Figure 3: Congestion detail. Designers cannot afford to over-design the power network in presence of congestion. One approach developed at IBM and the University of MN (reference #3) is to relax power grid congestion in crowded regions in two steps: 1. 2. Remove power/ground wires in non-critical regions (where IR drop is less) Upsize nearby P/G wires to maintain IR drop within limits
The power distribution network contains some dense grids; global wires compete for the same channels, and require the shortest path routes. It is not necessary for the power grid to be perfectly regular, as IR drop hotspots vary. The designer may display routing congestion by turning on visibility for the Hcongest and Vcongest layers in the Encounter layer selector (usually on the right of the GUI). IR drop results may be highlighted using the Power > Analysis > Display > Display Rail Analysis results menu, or with the command: displayRailAnalysisResults -net VDD -type ird -visibleLayer M6 M5 M4 M3 M2 M1 Wherever congestion is seen in an area with reasonable IR drop, we consider the power and ground stripes crossing that area as candidates for removal. But if congestion falls in an area where the IR drop is severe, we wont remove wires. In this case, floorplan refinements or area specific congestion optimization is our alternative. Note that whenever we can relive congestion well probably also improve signal integrity. The chief cause of crosstalk glitches (and noise-on-delay effects) is congestion, especially in the vicinity of clocks or other frequently switching signals.

Evaluating Timing in the presence of IR drop
Limitations in the flexibility of static timing analysis (STA) tools and the lack of a pressing need kept most timing analysis of digital circuits at a single voltage. If multiple voltages were used, it was in the context of best case/worst case analysis. At process nodes 0.13um and below, the effect of IR drop on instance timing becomes more important. Starting in First Encounter 5.2, it is possible to read the instance based voltages into the timing system, and have timing analysis account for the slowdown caused by reduced supply voltage. The command to use is setIrDropInstVoltage. Subsequent delays and slew calculated by the SignalStorm delay calculator will reflect the IR drop effects. Up to four different IR drop files can be read for early-max, early-min, late-max, and late-min analysis. For example: setIrDropInstVoltage -late -max -infile { latemax.ir } This can be used together with an extensive GUI for static timing analysis. The Timing Debug menu allows you to examine any timing path, or group of related paths, to examine the relevant SDC constraints, the amount of time spent in each logic stage, or the wires making up the path, as shown in Figure 4 below.
Figure 4: Timing Debug environment (partial view) showing worst path in GUI
Of course the timing path(s) may also be displayed together with rail analysis (IR drop) results, although they are not in this example for readability. One example of using the timing debug GUI would be to inspect a data path and its associated clock path. If they pass through areas of widely different IR drop, setup or hold problems that were not seen in the nominal voltage timing analysis may be seen. The GUI is not strictly needed here; you will see the results of IR drop in the regular timing reports. But the GUI may assist the designer in determining, for example, the cause of clock skew.

Summary

This paper presents a brief application example of some design considerations and possible analysis approaches to achieve efficient power distribution meshes. As processes scale down into the submicron area, IR drop effects become much worse and need to be considered during timing closure. An intertwined trade-off is between power grid robustness and signal congestion: the more real estate is given over to global and local power grids, the less there is available for signal routing, particularly global routes. Greater congestion leads to signal integrity issues, including increased delays due to crosstalk noise. IR drop analysis can help the designer understand where the power grid may be reduced to relieve congestion.

References

1. 2. 3. VoltageStorm Cell-Level Rail Analysis User Guide, Cadence Design Systems, 2006 Encounter User Guide, Cadence Design Systems, 2006 H. Su, J. Hu, S. Sapatnekar, S. R. Nassif. Congestion-driven Codesign of Power and Signal Networks. DAC 2002, June 10-14, 2002. Copyright 2002 ACM 1-581 13-461-4/02/0006. H. Su, J. Hu, S. Sapatnekar, S. R. Nassif. A Methodology for the Simultaneous Design of Supply and Signal Networks. IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, Vol. 23, No. 12, December 2004 M. Zhao, R. V. Panda, S. Sapatnekar, D. Blaauw. Hierarchical Analysis of Power Distribution Networks. IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, Vol. 21, No. 2, February 2002 H. Ajami, K. Banerjee, A. Mehrotra, M. Pedram. Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs. Proceedings of the Fourth International Symposium on Quality Electronic Design (ISQED03), 2003 IEEE Q. K. Zhu, D. Ayers. Power Grid Planning For Microprocessors And SOCs. Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED05), 2005 IEEE.