DMC VMEbus Pentium III Based Dual PMC Module Carrier Board

Users Manual

DMC Users Manual Rev. 1.00 June 2003

Dynatem

23263 Madero, Suite C Mission Viejo, CA 92691 Phone: (949) 855-3235 Fax: (949) 770-3481 www.dynatem.com

Table of Contents

1. 2. 3. 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 4. 4.1 4.2 4.3 4.4 4.5 4.6 Features Related Documents Hardware Description Overview Processor Intel 815E Chipset DRAM Intel 82559 Fast Ethernet Controller Tundra Universe IID CA91C142D PCI-VMEbus Interface PCI Mezzanine Card (PMC) Slot Winbond W823627HF/F Super I/O Device Real Time Clock and NVRAM Intels E82802AC Firmware Hub Clock Drivers Reset Circuitry Watchdog Timer Operation Interrupt Logic Installation Jumper Selectable Options CompactFlash Drive Installation PCI Mezzanine Card (PMC) Installation VMEbus Chassis Installation Front Panel Connections Front Panel Reset Switch and LEDs 24 24
DMC VMEbus Pentium Processor Board Users Manual
A. A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 B. B.1 B.2 B.3 B.4 B.5 C.
Connector Pin-outs JTAG Debug Port (J4) Floppy Drive Interface Connector (J8) External BIOS Connector Pin-out (J3) 10BaseT/100BaseTX Fast Ethernet Connector (J1) VGA Connector (J2-1) PS/2 Keyboard/Mouse Connector (J2-2) Primary IDE Interface Connector (J7) CompactFlash Interface Connector (J6) PCI Mezzanine Card (PMC) Connectors (JN1 and JN2) VMEbus Connectors (P0, P1, and P2) Address Maps, Interrupts, DMA Channels Memory Map PCI/AGP Configuration Space Map Interrupt Request Routing ISA DMA Channel Assignments PCI Bus Request/Grant Routing Power and Environmental Requirements

Chapter 1 Features

Features
The Dynatem DMC is a single-slot 6U VMEbus Single Board Computer (SBC). The DMC offers full PC performance with a Socket 370 processor and it also offer two Fast Ethernet ports and two PMC sites for greater expansion capability.
The DMC employs Intels embedded technology to assure long-term availability. The Socket 370 processor will track commercial product, however, for low cost and high performance. Features of the DMC include: Single-slot VMEbus operation with on-board CompactFlash disk for bootable mass storage and front panel connectors for Keyboard/Mouse, VGA, and 10/100BaseTX COM1/2, LPT1, PMC I/O, mouse/keyboard, a second 100BaseTX port, USB, Soundblaster, Game Port, IDE and FDC are routed out to the backplane via a five-row VME64 P2 connector and a P0 connector Socket 370 supports readily available processors from an 850 MHz Celeron to a 1.4 MHz Tualatin Pentium III
High-performance Intel 815E chipset with DRAM controller, PCI bus arbitration logic and interface, built-in video interface, Ultra ATA IDE interface, USB interface, RTC, NV-RAM, standard PC timers, and interrupt logic. An SO-DIMM socket supports up to 512 MB of SDRAM at 133 MHz Tundra Universe IID PCI-VMEbus Interface provides 64-bit VMEbus transfer rates over 30 MB/sec. Integral FIFOs permit write-posting to maximize available PCI and VMEbus bandwidth. Full Slot 1 (System Controller) functionality is provided Two Intels 82559 Fast Ethernet Controllers with 10/100BaseTX support Two PCI Mezzanine Cards (PMC) are supported with front panel I/O, while maintaining VMEbus single-slot form factor Primary Ultra DMA IDE Interface with improved transfer rates and PIO and Bus Master support Secondary IDE port for CompactFlash on-board booting for flash-based and mechanical storage General Softwares flash-based system BIOS Floppy drive controller with support for drives of up to 2.88 MB COM1 and COM2 serial ports, based on 16C550 compatible UARTs with 16-byte transmit and receive FIFOs LPT1 parallel port thats capable of standard, bidirectional, enhanced parallel port (EPP), and enhanced capabilities port (ECP) operation, with IEEE 1284 compliance. Programmable watchdog timer for system recovery. Operating System (OS) and driver support, including Windows NT, Embedded NT, QNX, VxWorks, Linux, Solaris, and pSOS+.
Chapter 2 Related Documents

Related Documents

Listed below are documents that describe the Pentium processor and chipset, and the peripheral components used on the DMC. Contact your local distributor for copies of these documents. For a data sheet on the Pentium III, go to: http://developer.intel.com/design/intarch/pentiumiii/pentiumiii.htm For a data sheet on the Celeron, go to: http://developer.intel.com/design/intarch/celeron/celeron.htm For Intel data, go to: http://developer.intel.com/design/litcentr/index.htm The Intel website is subject to change but the following documents should be available and downloadable: Pentium III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz ftp://download.intel.com/design/PentiumIII/datashts/24526408.pdf Intel Celeron Processor for the PGA370 Socket up to 1.40 GHz on 0.13 Micron Proces ftp://download.intel.com/design/celeron/datashts/29859604.pdf Intel 82801BA I/O ControllerHub 2 (ICH2) and Intel 82801BAMI/O Controller Hub 2 Mobile(ICH2-M) http://developer.intel.com/design/chipsets/datashts/290687.htm Intel Chipset Family: 82815 Graphics and Memory ControllerHub (GMCH) ftp://download.intel.com/design/chipsets/datashts/29068801.pdf 82559ER Fast Ethernet PCI Controller http://developer.intel.com/design/network/products/lan/controllers/82559er.htm VMEbus Interface Components Manual Tundra Semiconductor Corporation; Universe IID revisions are found at www.tundra.com Winbond W83627HF/F Super I/O Device Data Sheet Winbonds website is http://www.winbond.com.tw/e-winbondhtm/index.asp

The following documents provide information on the PC architecture: PCI Local Bus Specification, Revision 2.1 PCI Special Interest Group
The following documents cover topics relevant to the VMEbus and can be purchased through VITA: IEEE Std 1014-1987, IEEE Standard for a Versatile Backplane Bus: VMEbus The Institute of Electrical and Electronic Engineers 345 East 47th Street New York, NY 10017 (800) 678-4333 Wade D. Peterson, The VMEbus Handbook VITA 10229 North Scottsdale Road, Suite B Scottsdale, AZ 85253 (480) 951-8866
The following documents are the current draft standards for the PCI Mezzanine Card (PMC): IEEE Draft Std P1386/2.0, Draft Standard for a Common Mezzanine Card Family: CMC The Institute of Electrical and Electronic Engineers 345 East 47th Street New York, NY 10017 (800) 678-4333 IEEE Draft Std P1386.1/2.0, Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards: PMC The Institute of Electrical and Electronic Engineers 345 East 47th Street New York, NY 10017 (800) 678-4333
Chapter 3 Hardware Description

Hardware Description

Overview
The block diagram of the DMC is shown below. The sections that follow describe the major functional blocks of the DMC.
Socket 370 supports Tualatin PIII Processors and Celeron Processors
Integrated 3D Graphics Controller

VGA Port

133 MHz 64-bit GTL Bus
Graphics and Memory Controller Hub (GMCH)
64-bit Memory Bus @ up to 133 MHz
SO-DIMM Socket (J5) supports up to 512 MBytes of SDRAM

VMEbus

PCI Mezzanine Card #1

PCI Mezzanine Card #2

Intel 82559ER Fast Ethernet #1
Intel 82559ER Fast Ethernet #2
Tundra Universe IID VMEbus
5 Volt tolerant 33 MHz 32-bit PCIbus
I/O Controller Hub (ICH2)

Clock Drivers

Reset Circuitry

Interrupt Logic

USB, AC 97, IDE, & Compact Flash

BIOS/ Firmware Hub

Winbond W83627HF Super I/O
FDC, Mouse/Keyboard, LPT1, & COM1/2 Ports

Hub Interface

DMC Block Diagram

3.2 Processor

The DMC supports a Socket 370 processor. Both Tualatin Pentium IIIs and Celeron processors are supported. Processor System Bus (PSB) of up to 133 MHz. Built-in Level 1 instruction (code) and data caches of 16 KB each and up to 512 KB of on-die L2 cache. Integrated math co-processor. Power management, MMX, and backwards compatibility with Pentium class processors.

For further information on the Pentium processor, refer to Pentium Processors and Related Products, available from Intel Corporation. 3.3 Intel 815E Chipset
With the 2nd generation I/O Controller Hub (ICH2), the Intel 815E chipset offers greater platform flexibility and stability in Celeron and Pentium III processor-based PCs. The Intel 815E chipset consists of two devices: Graphics and Memory Controller Hub (GMCH) and the I/O Controller Hub (ICH2). The GMCH integrates the following functions into a single ball-grid array (BGA) package: Built-in graphics accelerator which supports VGA resolutions up to 1600 x 1200. 133 MHz DRAM controller supporting up to 512 MB of Synchronous DRAM (SDRAM) which are accessed from an on-board SO-DIMM connector. 133 MHz 64 bit front side processor bus.
The ICH2 integrates the following functions into a single ball-grid array (BGA) package: PCI 2.2 compliant, high-performance Processor-to-PCI buffered bridge with PCI bus arbitration logic. USB support and AC97 2.1 compliant link for audio and telephony codecs. Primary and secondary Ultra ATA/100/66/33 interfaces. The IDE signals are brought out to J7 and J6. The primary IDE port, J7, is a 44-pin dual-row 2-mm header on the PCB. The secondary port, J6, is a CompactFlash Type II connector. The pin-outs for these connectors are given in Appendix A. Enhanced DMA controller, interrupt controller, and timer functions.
For further information, see the documents referenced in Section 2. 3.4 DRAM
The DMC supports up to 512 MB of Synchronous DRAM (SDRAM) with a 144-pin SO-DIMM socket for additional 3.3 V PC100 SDRAM memory. When a processor with a front side bus of 133 MHz is populated in the DMCs socket 370, SO-DIMMs compliant with PC133 (133 MHz transfer rates) may be installed. Jumpers JP1 and JP2 determine the frequency of the front side bus and the SO-DIMMs DRAM interface. The SO-DIMM socket is J5 and it is located beneath the two PMC modules. While these SO-DIMMs are industry standard, we recommend ordering this DRAM from Dynatem as it will be tested at the factory for electronic and mechanical compatibility.
Intel 82559 Fast Ethernet Controller
The DMC provides two 82559 Fast Ethernet controllers. The Intel 82559 offers the following features: 10BaseT and 100BaseTX support with auto-negotiation. Independent 3 KB receive and transmit FIFOs. Powerful on-chip DMA minimizes CPU overhead with zero wait-state burst transfers to system memory. Built-in Phyceiver. Serial EEPROM for nonvolatile Ethernet address storage.
The 10BaseT/100BaseTX signals of one of the 82559 controllers are brought out to J1, an RJ-45 connector on the front panel. The pin-out for J1 is given in Appendix A. Three front panel LEDs are located below the front panel reset button and are controlled by the Ethernet circuitry: CR1 is closest to the RJ-45 connector (it is on when transferring at 100 Mb/sec, off when transferring at 10 Mb/sec), CR2 (active) is positioned next, and CR3 (link established) is the last indicator LED for the first Ethernet port. The DMCs second 82559 has its I/O lines routed to VMEbus connector P2. Both Dynatems rear I/O breakout card (model XMCPTB) and the 2nd-slot mass storage transition module (model XMCTB) run these lines through a transformer and out an RJ-45 connector. Indicator LEDs for the second LAN port are located next to those for the first port, below the reset button. These three LEDs follow the same pattern as those for the first port. The Intel 82559 contains several PCI configuration registers. It also contains a number of device registers for controlling the Ethernet operation that can be mapped to the memory space or the I/O space. The PCI signals specific to the DMCs first 82559 are shown below: Intel 82559 Signal IDSEL PREQ PGNT PIRQ PCI Bus Connection AD23 (PCI Device 0Ch) REQ2# (ICH2) GNT2# (ICH2) PIRQH# (ICH2)

The PCI signals specific to the DMCs second 82559 are shown below: Intel 82559 Signal IDSEL PREQ PGNT PIRQ PCI Bus Connection AD24 (PCI Device 0Ch) REQ3# (ICH2) GNT3# (ICH2) PIRQG# (ICH2)
For further information on the 82559, refer to 82559 Fast Ethernet Multifunction PCI/Cardbus Controller, available from Intel Corporation. Please go to the link at: http://developer.intel.com/design/network/products/lan/controllers/82559.htm
3.6 Tundra Universe IID CA91C142D PCI-VMEbus Interface
The PCI-VMEbus interface, based on the Tundra Universe IID CA91C142D, offers the following features: High-performance 64-bit VMEbus interface. Integral FIFOs for write-posting allow the Universe IID to quickly relinquish the bus. Programmable DMA controller with linked list support. Full VMEbus system controller functionality. Complete VMEbus address and data transfer modes: A32/A24/A16 master and slave D64 (MBLT)/D32/D16/D08 master and slave
Flexible register set, programmable from both the PCI bus and the VMEbus.
The block diagram of the PCI-VMEbus interface is shown below:

VMEbus Buffers

A24 A31

A01 A31, LWORD* PCI Bus

AD[31:0]

D00 D31

Buffers AS, DS0*, DS1*, Ctrl Buffers AM0* AM5* Buffers

D16 D31

AD27 C/BE[3:0], Ctrl
Universe IID CA91C142D LINT0# LINT1# PCI REQ4#, GNT4#
IRQx*, BRx* Buffers VMEbus P1 Connector VMEbus P0 Connector VMEbus P2 Connector

815E Chipset

PMC#2 I/O, COM2, USB, CODEC

IDE COM1 LPT1 PMC#1 I/O

P2 User Defined Pins
PCI-VMEbus Interface Block Diagram
As shown in the block diagram, several peripheral signals are routed to the user-defined pins of the VMEbus P2 connector. The VMEbus P1 and P2 connector pin-outs are given in Appendix A. The Universe IID CA91C142D can act as a PCI bus initiator (master) or target (slave), and a VMEbus master or slave. The Universe IID is capable of generating interrupts on the VMEbus, and can act as a VMEbus interrupt handler. The Universe IID provides full VMEbus system controller functionality. The DMC reset circuitry is tied to the Universe IID, since the DMC can generate the VMEbus SYSRESET* signal as well as be reset by another VMEbus board that asserts the SYSRESET* signal. The DMC reset circuitry is discussed in detail in Section 3.12. This section is intended to supplement the VME-to-PCI Bus Bridge Manual User Manual (downloadable from www.tundra.com), which contains comprehensive descriptions of the operation and programming of the Universe IID. In that manual, Chapter 1, Functional Overview, Chapter 5, Registers Overview, and Chapter 12, Registers, provide the necessary information to understand the operating modes of the Universe IID: DMC-initiated transfers (PCI slave, VMEbus master). Other VMEbus master-initiated transfers (PCI master, VMEbus slave). DMA controller transfers (PCI master, VMEbus master). VMEbus interrupt generation. VMEbus interrupt handling. System controller functionality. Register programming via the PCI bus and the VMEbus. Coupled and uncoupled transfers between the PCI bus and the VMEbus. 4 mailboxes and 8 semaphores. VMEbus arbitration.

The BS[23:19] and EN fields reset to all 0s, and the EN bit can be set by the VME64 Auto ID process. Thus, the CR/CSR method must be configured by accessing the Universe IID registers in the memory space. The PCI signals specific to the Tundra Universe IID CA91C142D are shown below: Tundra Universe IID CA91C142D Signal IDSEL REQ# GNT# LINT0# LINT1# PCI Bus Connection AD27 (PCI Device 10h) REQ4# (ICH2) GNT4# (ICH2) PIRQG# (ICH2) EXTSMI# (ICH2)
3.7 PCI Mezzanine Card (PMC) Slots
The DMC offers two PCI Mezzanine Card (PMC) sites for more flexible I/O expansion. The first PMC site (designated PMC #1) is closer to the Socket 370 processor and its heat sink. The PMC Slot offers the following characteristics: Conforms to IEEE draft standards 1386/2.0 and 1386.1/2.0. Accepts single-width 5V PMC boards with front panel I/O as well as backplane I/O. Provides 32-bit PCI support via connectors JN1 and JN2, and JN4 is available for routing PMC I/O to VMEbus connector P2. The two PMC sites do not offer JN3 connectors for 64-bit PCI support, but cards containing a PN3 connector are accommodated (that is, no components on the DMC interfere with a PMC PN3 connector).
The PCI signals specific to the two PMC Slots are shown below: PMC #1 Slot Signal IDSEL REQ# GNT# PMCINTA# PMCINTB# PMCINTC# PMCINTD# PCI Bus Connection AD16 (PCI Device 0Fh) REQ0# (ICH2) GNT0# (ICH2) PIRQA# (ICH2) PIRQB# (ICH2) PIRQC# (ICH2) PIRQD# (ICH2)
PMC #2 Slot Signal IDSEL REQ# GNT# PMCINTA# PMCINTB# PMCINTC# PMCINTD#
PCI Bus Connection AD17 (PCI Device 0Fh) REQ1# (ICH2) GNT1# (ICH2) PIRQB# (ICH2) PIRQC# (ICH2) PIRQD# (ICH2) PIRQA# (ICH2)
The DMC routes most of the JN4 I/O pins of the two PMC sites to the VMEbus backplane. With PMC #1, pins 1 through 46 of its JN4 I/O connector are routed to the P2 VMEbus connector. With PMC #2, pins 1 through 60 of its JN4 I/O connector are routed to the P0 VMEbus connector. Depending on whether the integrators I/O will be routed to the backplane, on how many of those JN4 I/O pins are needed, and whether a VME64 Extensions backplane (with P0 support) is used, care should be taken regarding site assignment. Appendix A has the pinouts for VMEbus backplane connectors P0 and P2. For further information on the PMC specification, refer to PCI Local Bus Specification, Revision 2.2, available from the PCI Special Interest Group (www.pcisig.com), IEEE Draft Std P1386-2001, IEEE Standard for a Common Mezzanine Card Family: CMC, and IEEE Draft Std P1386.1-2001, IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards: PMC, both available from the Institute of Electrical and Electronic Engineers.
3.8 Winbond W83627HF/F Super I/O Device
The Winbond W83627HF/F provides the following standard PC peripherals: Floppy drive controller with support for drives up to 2.88 MB with a 2Mbps transfer rate. COM1 and COM2 serial ports, based on 16C550 compatible UARTs with 16-byte transmit and receive FIFOs. LPT1 parallel port thats capable of standard, bidirectional, enhanced parallel port (EPP), and enhanced capabilities port (ECP) operation, with IEEE 1284 compliance. Infrared port that supports IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps

There are eight ways to perform a hard reset of the DMC: The DS1232 senses that the +5 VDC supply has dropped too low, which asserts a PWROK signal to the ICH2, the Super I/O, and to the Universe IID. This signal resets the processor and the Chipset and, ultimately, all PCI peripherals. The front panel reset switch is pressed, which also asserts a PWROK signal and resets the DMC. Another VMEbus board asserts SYSRESET*, which asserts the Universe IID VRSYSRST# input and, if switch SW1-2 is closed, will reset the DMC via the DS1232. The SW_SYSRST bit in the MISC_CTL register of the Universe IID is set by code running on the DMC processor. This leads to the assertion of the VMEbus SYSRESET* signal, if SW1-3 is closed. The SW_LRST bit in the MISC_CTL register of the Universe IID is set by code running on the DMC processor. This performs a local hard reset of the DMC board circuitry, if SW1-2 is closed, without asserting the VMEbus SYSRESET* signal. Another VMEbus master sets the RESET bit in the VCSR_SET register of the Universe IID over the VMEbus. In this case the LRST# signals remains asserted until the RESET bit of the VCSR_CLR register of the Universe IID is set by another VMEbus master over the VMEbus. The Reset Control Register in the ICH2 can be set appropriately by code running on the DMC processor. Let the watchdog timer time out; see Section 3.13 below.
For further information on the peripherals that play a part in the reset circuitry, refer to Intel 82801BA I/O ControllerHub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile (ICH2-M) from Intel Corporation, Document Number 290687-002, and Intel815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH), also available from Intel Corporation at www.intel.com. 3.13 Watchdog Timer Operation
The DMCs DS1232 is used to reset the entire board through the push button accessed through the front panel, through the modules 5 VDC supply being sensed as dropping to 4.75 VDC, through a VMEbus reset if jumper SW1-2 is closed, or if the watchdog timer is enabled and it times out. The DMCs watchdog timer is controlled by one general-purpose output line (GPO19) that is asserted by the ICH2. The DS1232 has a strobe input pin which must see an active clock. If no clock pulse is generated to the pin within 500 milliseconds, the entire DMC board will be reset. As long as GPO19 is high, a 25 MHz clock will be present at the strobe input. To use the watchdog timer, drive GPO19 low, thereby turning off the 25 MHz clock to the DS1232s strobe input, but write a software routine that will bring GPO19 high before 500 milliseconds elapses. GPO19 is controlled by bit 19 in the ICH2s GP_LVL register. GPO19 reflects the status of bit 19: GPO19 is high if bit 19 is a logic 1 and it is low of bit 19 is at logic 0. GPO19 is high at reset so the watchdog timer will only be activated when the user drives bit 19 of the GP_LVL register low.

Appendix A Connector Pin-outs

Connector Pin-outs

The locations of the DMC connectors are shown below. The connectors that do not go to the front panel have their pin 1 location designated accordingly. The numbering conventions for PMC site #1 connectors are given below. PMC site #2 connectors are to the right and they follow the same convention as site #1

Fast Ethernet J1

VGA, KYBD & Mouse J2 Off-board BIOS J3 JTAG Connector J4

Primary IDE J7

CompactFlash J6
144-Pin SO-DIMM Module J5

Floppy Drive J8

PMC1 JN4 VMEbus P2 PMC1 JN2 PMC1 JN1 VMEbus P0 VMEbus P1

A.1 JTAG Debug Port (J4)

This JTAG debug connector permits in-circuit emulation for system debugging. Pin 29 Signal GND GND GND TDI TDO TRST# N/C PREQ0# PRDY0# N/C N/C N/C N/C N/C N/C Pin 30 Signal RESET# DBRESET# TCX TMS POWERON N/C GND GND GND GND GND GND GND GND ITPCLK

JTAG Connector (J4)

A.2 Floppy Drive Interface Connector (J8)
For details on the Floppy Drive Interface signals, refer to the Winbond W83627HFManual. Pin +5 VDC INDEX# +5 VDC DS0# +5 VDC DSKCHG# No connection No connection No connection MTR0# No connection DIR# No connection STEP# GND WDATA# GND WGATE# GND TRK0# GND WRTPRT# GND RDATA# GND HDSEL# Signal Description
Floppy Drive Interface Connector (J8) 1.00mm ZIF Flex Circuit Connector
A.3 External BIOS Connector Pin-out (J3)
Connector J3 is a 16-pin Dual In-Line connector. J3 is used to route the DMCs firmware hub interface to an external BIOS for in-factory testing and development. This port should be of no use to the customer and the connector is not populated on the DMC. The following table shows J3s pin-out: Pin Signal SMB Clock SMB Data LAD0 LAD1 LAD2 PCI Reset No Connect DBRESET# Pin Signal 3.3 VDC PCLK_8 LAD3 LFRAME# Ground No Connect No Connect Ground
External BIOS (J3) 16-pin Dual-row 0.1 Header
10BaseT/100BaseTX Fast Ethernet Connector (J1) Pin Signal Description Transmit Data + (TX+) Transmit Data - (TX-) Receive Data + (RX+) Transmit Center Tap 1 (CTTX1) Transmit Center Tap 2 (CTTX2) Receive Data - (RX-) Receive Center Tap 1 (CTRX1) Receive Center Tap 2 (CTRX2)
10BaseT/100BaseTX Fast Ethernet Connector (J1) Front Panel RJ-45 Connector. The metal shell of the connector goes to chassis ground.
A.5 VGA Connector (J2-1) Pin 15 Signal Description Red Output Green Output Blue Output No connection HSYNC/VSYNC Return (GND) Red Return (GND) Green Return (GND) Blue Return (GND) +5 VDC HSYNC/VSYNC Return (GND) No connection DDCDAT Horizontal Sync (HSYNC) Output Vertical Sync (VSYNC) Output DDCCLK
VGA Connector (J2-1) Front Panel MDSM Connector. The metal shell of the connector goes to chassis ground. Connector J2-1 is the upper half of a stacked ITT Cannon MDSM-30 connector. It will be the half that is furthest to the right when viewing the DMC while it is inserted into a VMEbus chassis. The PS/2 mouse/keyboard connector will be the other, lower, part to its left. While the pinout is the same as with an industry standard VGA connector, mechanically it is too small and incompatible so Dynatem provides an adapter cable for the MDSM termination that will mate with a VGA monitors cable.

PS/2 Keyboard/Mouse Connector (J2-2) Pin B11 B3 B10, B12 B2, B4 B9 B1 Signal Description Keyboard Data Mouse Data GND +5 VDC (via 1 amp self-resetting fuse F1) Keyboard Clock Mouse Clock
Keyboard/Mouse Connector (J2-2) Front Panel Mini-DIN Receptacle. The metal shell of the connector goes to chassis ground. Connector J2-2 is the lower half of a stacked ITT Cannon MDSM-30 connector. It will be the half that is closer to the DMCs Printed Circuit Board (PCB). The VGA connector will be the other, upper, part. Dynatem provides a Y-splitter adapter cable for the MDSM termination that connects with PS/2 mouse and keyboard devices.
A.7 Primary IDE Interface Connector (J7) Pin Signal RST# D7 D6 D5 D4 D3 D2 D1 D0 GND DMARQ0 IOW# IOR# IORDY DMAACK0 IRQ14 DA1 DA0 CS1Fx LED Control +5 VDC GND Pin Signal GND D8 D9 D10 D11 D12 D13 D14 D15 No connection GND GND GND 470-ohm pull-down GND No connection P66 Detect DA2 CS3Fx GND +5 VDC No connection
Primary IDE Interface Connector (J7) 44-pin Dual-row 2-mm Header
A.8 CompactFlash Interface Connector (J6) Pin 25 Signal GND D3 D4 D5 D6 D7 CS1# GND GND GND GND GND +5 VDC GND GND GND GND DA2 DA1 DA0 D0 D1 D2 No connection No connection Pin 50 Signal CMPFLASHDET D11 D12 D13 D14 D15 CS3# No connection DIOR# DIOW# +5 VDC DIRQ (IRQ15) +5 VDC GND (master) No connection IDERESET DIORDY No connection +5 VDC No connection Pull-up to +5 VDC D8 D9 D10 GND
CompactFlash Type II Interface Connector (J6)
PCI Mezzanine Card (PMC) Connectors (JN1 and JN2)
This section has the pin-outs for both PMC sites. PMC site #1 is further away from the socket 370 processor and closer to the lower edge of the module while PMC site #2 is located in the middle of the module. The JN4 pin-outs will not be given here as the signals on these connectors are routed to VMEbus connectors P2 and P0, for PMC sites 1 and 2 respectively. Please refer to section A.10 for these pin-outs. Pin Signal 5.6K pull-down GND PIRQ#B No connection PIRQ#D GND PCI CLK GND PCI REQ0# +5 VDC (VI/O) AD28 AD25 GND AD22 AD19 +5 VDC (VI/O) FRAME# GND DEVSEL# GND SDONE PAR +5 VDC (VI/O) AD12 AD9 GND AD6 AD4 +5 VDC (VI/O) AD2 AD0 GND Pin Signal -12 VDC PIRQ#A PIRQ#C +5 VDC No connection No connection GND PCI GNT0# +5 VDC AD31 AD27 GND C/BE3# AD21 +5 VDC AD17 GND IRDY# +5 VDC LOCK# SBO GND AD15 AD11 +5 VDC C/BE0# AD5 GND AD3 AD1 +5 VDC REQ64 (2.7K pull-up)

PCI Mezzanine Card (PMC) Site #1 Connector (P1JN1) Molex 52763-0649

Pin 61 63

Signal +12 VDC TMS (pulled up) TDI (pulled up) GND No connection +5 VDC PCI RST# +3.3 VDC No connection AD30 GND AD24 AD16 (IDSEL) +3.3 VDC AD18 AD16 GND TRDY# GND PERR# +3.3 VDC C/BE1# AD14 GND AD8 AD7 +3.3 VDC No connection No connection GND ACK64 (2.7K pull-up) GND

Pin 62 64

Signal TRST (pulled down) No connection GND No connection No connection +3.3 VDC GND GND GND AD29 AD26 +3.3 VDC AD23 AD20 GND C/BE2# No connection +3.3 VDC STOP# GND SERR# GND AD13 AD10 +3.3 VDC No connection No connection GND No connection No connection +3.3 VDC No connection
PCI Mezzanine Card (PMC) Site #1 Connector (P1JN2) Molex 52763-0649 Note: PMC Connector P1JN4 is strictly for I/O routing so there is no defined pin-out assignment. Section A.10, on the following pages, shows how the P1JN4 lines are routed to the outer rows of VME64 Extensions connector P2 (some of these lines are shared with an optional FDC routing to P2).
Signal 5.6K pull-down GND PIRQ#C No connection PIRQ#A GND PCI CLK GND PCI REQ1# +5 VDC (VI/O) AD28 AD25 GND AD22 AD19 +5 VDC (VI/O) FRAME# GND DEVSEL# GND SDONE PAR +5 VDC (VI/O) AD12 AD9 GND AD6 AD4 +5 VDC (VI/O) AD2 AD0 GND
Signal -12 VDC PIRQ#B PIRQ#D +5 VDC No connection No connection GND PCI GNT1# +5 VDC AD31 AD27 GND C/BE3# AD21 +5 VDC AD17 GND IRDY# +5 VDC LOCK# SBO GND AD15 AD11 +5 VDC C/BE0# AD5 GND AD3 AD1 +5 VDC REQ64 (2.7K pull-up)
PCI Mezzanine Card (PMC) Site #2 Connector (P2JN1) Molex 52763-0649
Signal +12 VDC TMS (pulled up) TDI (pulled up) GND No connection +5 VDC PCI RST# +3.3 VDC No connection AD30 GND AD24 AD17 (IDSEL) +3.3 VDC AD18 AD16 GND TRDY# GND PERR# +3.3 VDC C/BE1# AD14 GND AD8 AD7 +3.3 VDC No connection No connection GND ACK64 (2.7K pull-up) GND
PCI Mezzanine Card (PMC) Site #2 Connector (P2JN2) Molex 52763-0649 Note: PMC Connector P2JN4 is strictly for I/O routing so there is no defined pin-out assignment. Section A.10, on the following pages, shows how the P2JN4 lines are routed to the VME64 Extensions connector P0.
A.10 Pin A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 VMEbus Connectors (P0, P1, and P2) Signal D00 D01 D02 D03 D04 D05 D06 D07 GND SYSCLK GND DS1* DS0* WRITE* GND DTACK* GND AS* GND IACK* IACKIN* IACKOUT* AM4 A07 A06 A05 A04 A03 A02 A01 -12 VDC +5 VDC Pin B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 Signal BBSY* BCLR* ACFAIL* BG0IN* BG0OUT* BG1IN* BG1OUT* BG2IN* BG2OUT* BG3IN* BG3OUT* BR0* BR1* BR2* BR3* AM0 AM1 AM2 AM3 GND No connection (NC) No connection (NC) GND IRQ7* IRQ6* IRQ5* IRQ4* IRQ3* IRQ2* IRQ1* +5 VDC Standby (NC) +5 VDC Pin C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 Signal D08 D09 D10 D11 D12 D13 D14 D15 GND SYSFAIL* BERR* SYSRESET* LWORD* AM5 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 +12 VDC +5 VDC

VMEbus Connector (P1) DIN 41612 96-pin (3 rows x 32 pins)
The JN4 lines from PMC site #1 are routed to the P2 connector but the Floppy Disk Controller (FDC) signals may also be routed to rows D & Z of P2 by shunting jumpers JP5 through JP16. Be careful that these lines dont overlap. The XMCPTB rear plug-in expansion module supports P2 FDC expansion with an FDC connector. The optional FDC signals (only routed to the backplane when JP5 through JP16 are closed) are in bold and the corresponding P1JN4 pin numbers are in parentheses (always routed to the backplane). One difference between the P2 routing of the DMC and previous Dynatem cards, that expanded through the adjacent slot transition module (the TB) or the rear plug-in card (XPC2PTB), is that the DMC routes the second Ethernet port out through P2. So pins A16 and A17 used to be tied together on the XPC2PTB for SCSI power, pin C12 used to be used for ground, and C13 used to be used for an optional battery voltage. Now all four of these pins are used for the 2nd Ethernet port. Care must be taken to use an XMCPTB or the TBM with the DMC. Please call Dynatem for support if you wish to use earlier versions of these transition modules (for the DRC1 and the DPC2) with the DMC. Pin
Z01 Z02 Z03 Z04 Z05 Z06 Z07 Z08 Z09 Z10 Z11 Z12 Z13 Z14 Z15 Z16 Z17 Z18 Z19 Z20 Z21 Z22 Z23 Z24 Z25 Z26 Z27 Z28 Z29 Z30 Z31 Z32

Signal

P1JN4-pin2 GND P1JN4-5 GND P1JN4-8 GND P1JN4-11 GND P1JN4-14 GND P1JN4-17 GND P1JN4-20 GND P1JN4-23 GND P1JN4-26 GND P1JN4-29 GND P1JN4-32 GND Hdsel# (35) GND Trk0# (38) GND Step# (41) GND Dskchg# (44) GND Index# (46) GND
A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32
IDE PDREQ IDE PDIOW# IDE PDIOR# IDE PDIORDY IDE PDDACK# IDE PDIRQ IDE PDA1 IDE PDA0 IDE PDCS1# IDE RSTDRV# IDE PDA2 IDE PDCS3# IDE PDD7 IDE PDD6 GND LAN2TDP LAN2TDN IDE PDD15*** IDE PDD5 GND IDE PDD4 IDE PDD3 IDE PDD2 IDE PDD1 IDE PDD0 IDE PDD8 IDE PDD9 IDE PDD10 IDE PDD11 IDE PDD12 IDE PDD13 IDE PDD14
B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
+5 VDC GND No Connect A24 A25 A26 A27 A28 A29 A30 A31 GND +5 VDC D16 D17 D18 D19 D20 D21 D22 D23 GND D24 D25 D26 D27 D28 D29 D30 D31 GND +5 VDC
C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32

COM1 TxD COM1 RxD COM1 RTS COM1 CTS COM1 DTR COM1 DSR COM1 DCD COM1 RI P1JN4-28 Speaker Output +5 VDC LAN2RDP LAN2RDN IDE LED# P1JN4-30 LPT1 STROBE# LPT1 AUTOFD# LPT1 PD0 LPT1 ERR# LPT1 PD1 LPT1 INIT# LPT1 PD2 LPT1 SLCTIN# LPT1 PD3 LPT1 PD4 LPT1 PD5 LPT1 PD6 LPT1 PD7 LPT1 ACK# LPT1 BUSY LPT1 PE LPT1 SLCT
D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 C17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32
P1JN4-pin1 P1JN4-3 P1JN4-4 P1JN4-6 P1JN4-7 P1JN4-9 P1JN4-10 P1JN4-12 P1JN4-13 P1JN4-15 P1JN4-16 P1JN4-18 P1JN4-19 P1JN4-21 P1JN4-22 P1JN4-24 P1JN4-25 P1JN4-27 P1JN4-28 P1JN4-30 P1JN4-31 P1JN4-33 P1JN4-34 Rdata# (36) Wpt# (37) Wgate# (39) Wdata# (40) Dir# (42) Motr0# (43) Drvs0# (45) GND +5 VDC
VMEbus Connector (P2) 160-pin (5 rows x 32 pins)
A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
P2JN4-56 P2JN4-51 P2JN4-46 P2JN4-41 P2JN4-36 P2JN4-31 P2JN4-26 P2JN4-21 P2JN4-16 P2JN4-11 P2JN4-6 P2JN4-1 COM2 CTS COM2 DCD USB Over A MIDI In MIDI Out AC 97 Clock InfraRed RxD
B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19
P2JN4-57 P2JN4-52 P2JN4-47 P2JN4-42 P2JN4-37 P2JN4-32 P2JN4-27 P2JN4-22 P2JN4-17 P2JN4-12 P2JN4-7 P2JN4-2 COM2 DTR COM2 DSR USB #0 N Kybd Data Joy2 Y Joy1 Button1 InfraRed TxD
C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
P2JN4-58 P2JN4-53 P2JN4-48 P2JN4-43 P2JN4-38 P2JN4-33 P2JN4-28 P2JN4-23 P2JN4-18 P2JN4-13 P2JN4-8 P2JN4-3 COM2 RI COM2 RxD USB #0 P Kybd Clock Joy1 Y Joy2 Button1 AC 97 Reset
D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19
P2JN4-59 P2JN4-54 P2JN4-49 P2JN4-44 P2JN4-39 P2JN4-34 P2JN4-29 P2JN4-24 P2JN4-19 P2JN4-14 P2JN4-9 P2JN4-4 COM2 RTS USB #1 N Mouse Data Joy2 Button2 Joy1 X AC 97 Data In AC 97 Data Out
E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19
P2JN4-60 P2JN4-55 P2JN4-50 P2JN4-45 P2JN4-40 P2JN4-35 P2JN4-30 P2JN4-25 P2JN4-20 P2JN4-15 P2JN4-10 P2JN4-5 No Connect COM2 TxD USB #1 P Mouse Clock Joy1 Button2 Joy2 X AC 97 SYNC
VME64 Extensions Bus Connector (P0)
Appendix B Address Maps, Interrupts, DMA Channels
Address Maps, Interrupts, DMA Channels
Tables of the DMCs address maps, interrupt request assignments, and DMA channel usage are given in the following sections. All addresses are shown in hexadecimal notation. B.1 Memory Map

The DMCs memory map is shown below: Address Range Description
00000000 - 0009FFFF DOS area main memory (640 KB) 000A0000 000BFFFF Std PCI/ISA Video Memory (128 KB) 000C0000 000FFFFF BIOS Region 00100000 1FFFFFFF DRAM (up to 512 MB) 01000000 FFFFFFFF: PCI Memory Address Range breaks as: FEC00000 - FECFFFFF, FEE00000 - FEEFFFFF APIC Configuration Area (unused on DMC) FFFC0000 - FFFFFFFF High BIOS Area For further details on the DMC memory space map, refer to Section 4.1.1 in Intel 815E Chipset Family:82815 Graphics and Memory Controller Hub (GMCH) data sheet, available from Intel Corporation. B.2 PCI Configuration Space Map
The PCI configuration space map is shown below. The Vendor ID and Device ID in hex for the PMC slot are shown as xxxx, since they depend on the type of device installed in the PMC slot. IDSEL Bus Dev Fcn VenID DevID Description
1130 GMCH Host Bridge/Controller 244E 82801BA PCI-ISA Bridge 2440 82801BA Low Pin Count (LPC) Interface 2440 82801BA DMA Operation 2440 82801BA Timers 2440 82801BA Interrupt Controllers (PIC) 2440 82801BA Advanced Interrupt Controllers (APIC) 2440 82801BA Real Time Clock (PIC) 2440 82801BA Power Mgmt & DMC Watchdog 244b 82801BA PCI-IDE Interface 2,2442 82801BA PCI-USB Interface AD82559 Fast Ethernet Controller #1 AD82559 Fast Ethernet Controller #2 ADxxxx xxxx PCI Mezzanine Card (PMC) Slot #1 ADxxxx xxxx PCI Mezzanine Card (PMC) Slot #2 AD10EUniverse IID CA91C142D PCI-VMEbus Interface For further details refer to Intel 82801BA I/O Controller Hub 2(ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile (ICH2-M) data sheet, available from Intel Corporation.
B.3 Interrupt Request Routing
The ISA interrupt request routing is shown below: IRQ 6 *15 Description Timer 0 (ICH2) Keyboard (W83627HFs keyboard/mouse controller) Cascade Interrupt from slave PIC (ICH2) COM2/COM4 (W83627HF) COM1/COM3 (W83627HF) Assigned to a PCI IRQ by the BIOS Floppy Drive (W83627HF) LPT1 (W83627HF) Real Time Clock (ICH2) Assigned to a PCI IRQ by the BIOS Assigned to a PCI IRQ by the BIOS Assigned to a PCI IRQ by the BIOS Mouse (W83627HFs keyboard/mouse controller) Math Coprocessor (ICH2) Primary IDE Interface (ICH2) Secondary IDE Interface (ICH2, via MIRQ0)
The PCI interrupt request routing to the Intel 82801BA PCI-ISA Bridge (ICH2) is shown below: ICH2 PCI IRQ See Section A.9 See Section A.9 PIRQH# PIRQG# PIRQF# Description PMC Site #1 INTA#, INTB#, INTC#, INTD# PMC Site #2 INTB#, INTC#, INTD#, INTA# Intel 82559 #1 Intel 82559 #2 Tundra Universe IID CA91C142D LINT0#
For further details on interrupts, refer to the documentation for the various peripherals that generate interrupts, as well as Intel 82801BA I/O Controller Hub 2(ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile (ICH2-M) data sheet, available from Intel Corporation. Note: the DMC uses the ICH2 and not the ICH2-M.