MEMORANDUM CIRCULAR No. 2004- 06 March 4, 2004 TO: All Chairpersons and Members of the Professional Regulatory Boards All PRC Officials and Employees in the Central Office and Regional Offices SUBJECT: UPDATED LIST OF NON-PROGRAMMABLE CALCULATORS ALLOWED TO BE USED IN LICENSURE EXAMINATIONS The Commission issued Memorandum Circular No. 2002-24 dated September 27, 2002 listing the brands and models of non-programmable calculators that are allowed to be used in licensure examinations. It has been observed during the conduct of examinations that there are still other brands and models that are non-programmable that are not included in the list of those allowed to be used. In order to properly guide the examinees and examination personnel, the following is the Updated List of NonProgrammable Calculators that shall be allowed to be used in the examinations after verification with the distributors and identification of knowledgeable persons. Accordingly, the examinees shall be allowed to bring in and use ONLY any of the following calculators that were identified as non-programmable:
CASIO STANDARD/DESK TOP SCIENTIFIC CALCULATORS CASIO 530 CASIO 20V CASIO 470LA CASIO D-20M CASIO D-60M CASIO D-100V CASIO D-208H CASIO D-120TE CASIO DM-1600 CASIO DS-208H CASIO DS-881 CASIO DF100 CASIO DN 858A CASIO DS1800S CASIO EL310-A Fx65 Fx75 Fx82 Fx95 Fx260 Fx401 Fx580 Fx824 Fx901 CASIO FX82C CASIO FX82LP CASIO FX85B CASIO FX85SA CASIO FX220 CASIO FX250HC CASIO FX350D CASIO FX350W CASIO FX570W CASIO HC100 CASIO HL-821 CASIO HL-122L CASIO J-120TE CASIO JS-10LA CASIO JS-20LA Fx82 Super Fx95MS Fx100D Fx100S Fx100W Fx115D Fx115S Fx115W Fx122s CASIO JS 40LA CASIO JS-140 CASIO JS-SC CASIO LC-401B CASIO LC-1000T CASIO-LC 403LD CASIO M-7LB CASIO MJ-100 CASIO MS 115 CASIO MS 373 CASIO MS-350 CASIO MS-470 CASIO MS 240T CASIO MS-808V CASIO MS-812V Fx509G Fx520G Fx546D Fx546L Fx570S Fx570W Fx580D Fx825X Fx911W CASIO MS-100TE CASIO MS 120TE CASIO MS 170LA CASIO MS-270LA CASIO MS-470LA CASIO MS-10V CASIO MS-10TE CASIO MS-80TE CASIO MS-8T CASIO MS-20/V CASIO MS-1002 CASIO O-40M CASIO SL-320V CASIO SL-305TE CASIO ELECT. D-20M Fx115MS Fx300SA Fx350TL Fx350HA Fx350HB Fx531GH Fx531LH Fx570AD Fx570MS
Fx991N Fx85S Fx82LB Fx82MS Fx82SX Fx82TL
Fx300W Fx451M Fx500A Fx506G Fx506M Fx509D
Fx991H Fx991S Fx991W Fx992S Fx992s Fx100MS

Fx991MS Fx992VB Fx350TLG

SHARP NON-PROGRAMMABLE CALCULATORS EL-233S EL-501V EL-510R EL-240S EL-501V (BK) EL-520G EL-242M EL-506P EL-520V EL-250S EL 506R EL-520V (BK) EL-310A EL-506V EL-520VA EL-310A-GR EL-506V (BK) EL-531GH EL-327S EL-509D EL 531RH EL-331A EL-509G EL-531VH EL-376S EL 509R EL-531VH (BK) EL-378S EL-509V EL-531VH (BL)
EL-546L EL-546VA EL 556G EL-771C EL-2125 EL-6053 EL-6750 EL-6810 EL-6850
CITIZEN NON-PROGRAMMABLE CALCULATORS CITIZEN TL-780 CITIZEN SDC 8610 CITIZEN SLD-742N CITIZEN SDC-8620A CITIZEN STL-795 CITIZEN SOC-8610A CITIZEN SDC-8560 OLYMPIA NON-PROGRAMMBLE CALCULATORS OLYMPIA HL 88L OLYMPIA HL 110 OLYMPIA SD-81H OLYMPIA SD-100H OLYMPIA SD-100V OLYMPIA SD-100HW OLYMPIA SD-805M OLYMPIA SD-828 OLYMPIA SD-835
CANON NON-PROGRAMMABLE CALCULATORS CANON F-604 CANON F-720 CANON LC 210HI CANON LS-39H CANON LS-154H CANON LS-566H CANON LS 120H CANON LS 82Z CANON LS-120V
AURORA NON-PROGRAMMBLE CALCULATORS AURORA DT 393 AURORA EB 964 AURORA MS 270LA AURORA DT 394 AURORA HL 125 AURORA SC 120 OTHER BRANDS CEBAR CD402 DAL 506X LIFELONG

AURORA 2512

KARCE-833 KARCE KC 250 KARCE KC 539
PORPO YH-105 PORPO YH-106 TIME BIRD SJC-122
TAKSUN TS-217 TAKSUN TS-128B

TL 30XS

TEXAS TI 30

TAKSUN TS-128

Other brands of desk top calculators may be allowed to be used in the CPA licensure examinations subject to inspection by the room watchers. The Board Secretaries of the various Professional Regulatory Boards are directed to update in accordance with the list herein provided, the List of Calculators printed at the back of the Program/Schedule of Examinations. This Memorandum Circular supersedes Memorandum Circular No. 2002-24 dated September 27, 2002. Please be guided accordingly.

Connector Pin# 43 Pin Name VSS COMOUT VSS VCOM VSS V13 V7 V6 VDD CLK V0 VSS D20 D21 D22 D23 D24 D25 D10 D11 D12 D13 D14 D15 D00 D01 D02 D03 D04 D05 VSS AVDD HSYNC VGL DE VGH VSYNC VSS YU XR YD XL VSS Pin Description GND Rectangular wave output for common driver GND Common driver signal GND Gamma generation reference for negative side Gamma generation reference for negative side Gamma generation reference for positive side VDD (Logic) 3.0V0.3V Dot clock Gamma generation reference for positive side GND RED data signal (LSB) RED data signal RED data signal RED data signal RED data signal RED data signal (MSB) GREEN data signal (LSB) GREEN data signal GREEN data signal GREEN data signal GREEN data signal GREEN data signal (MSB) BLUE data signal (LSB) BLUE data signal BLUE data signal BLUE data signal BLUE data signal BLUE data signal (MSB) GND VDD (analog) 5.0V0.2V Horizontal synchronous signal Power for gate driver (-) -15V1.0V Input data enable (Hi-active) Power for gate driver (+) +15V1.0V Vertical synchronous signal GND OPEN OPEN OPEN OPEN GND EPSON 3

Connector Pin# 44 45

Pin Name BLL BLH LED driver power (cathode side) LED driver power (anode side)

Pin Description

Note The recommended connector is a FH23-45S-0.3SHW(0.5) from Hirose Electric Co., Ltd. The connector is a 0.3mm pitch 45-pin FPC connector (13.8mm x 0.2mm gold plate).

3.2 Connection Examples

The information in this section provides connection examples for the S1D13513, S1D13706, and S1D13A05 display controllers. For the S1D13513 and S1D13A05, the display controller is available in two packages. The connection information differs for each package and is listed separately. In addition to the pin connections for the selected display controller, the COM27T2984 requires the following power supplies. VDD AVDD VGH VGL +3.0V (0.3V) +5.0V (0.2V) +15V (1.0V) -15V (1.0V)
For VDD, select a voltage within the supportable range of the Display Controller. For further details on the COM27T2984, such as power consumption and absolute maximum ratings, please contact your Casio representative.
3.2.1 Connecting the COM27T2984 to the S1D13513 The following diagram shows an example implementation of the COM27T2984 panel connected to the S1D13513.

LCD Panel Connecto r Pin# LCD Panel Pin Name LCD Panel Pin Description S1D13A05 QFP Pin# S1D13A05 PFBGA Ball# S1D13A05 Pin Name
VSS COMOUT VSS VCOM VSS V13 V7 V6 VDD CLK V0 VSS D20
GND Rectangular wave output for common driver GND Common driver signal GND Gamma generation reference for negative side Gamma generation reference for negative side GND Rectangular wave output for common driver GND Common driver signal GND Gamma generation reference for negative
Note Note Note 3,4,17,33, 52,69,Note 55
Note Note Note L2,G4,H6, L9,A10,F11 H10 Note E10
VSS VSS VSS IOVDD FPSHIFT VSS FPDAT11
LCD Panel Connecto r Pin#

S1D13A05 QFP Pin#

S1D13A05 PFBGA Ball#

S1D13A05 Pin Name

D21 D22 D23 D24 D25 D10 D11 D12 D13 D14 D15 D00 D01 D02 D03 D04 D05 VSS AVDD HSYNC VGL DE VGH VSYNC VSS YU XR YD XL VSS BLL BLH
side Gamma generation reference for negative side Gamma generation reference for positive side VDD (Logic) 3.0V0.3V Dot clock Gamma generation reference for positive side GND RED data signal (LSB) RED data signal RED data signal RED data signal RED data signal RED data signal (MSB) GREEN data signal (LSB) GREEN data signal GREEN data signal GREEN data signal GREEN data signal GREEN data signal (MSB) BLUE data signal (LSB) BLUE data signal BLUE data signal BLUE data signal BLUE data signal BLUE data signal (MSB) GND VDD (analog) 5.0V0.2V Horizontal synchronous signal Power for gate driver (-) -15V1.0V Input data enable (Hi-active) Power for gate driver (+) +15V1.0V Vertical synchronous signal GND

49 Note 40 Note Note -

E11 E8 G9 G8 H11 D11 D8 E9 G7 G11 G10 C10 D9 D10 F7 F10 F8 Note H9 K9 J9 Note Note -
FPDAT10 FPDAT9 FPDAT2 FPDAT1 FPDAT0 FPDAT14 FPDAT13 FPDAT12 FPDAT5 FPDAT4 FPDAT3 FPDAT17 FPDAT16 FPDAT15 FPDAT8 FPDAT7 FPDAT6 VSS FPLINE DRDY FPFRAME VSS VSS -
S1D13A05 IOVDD and COM27T2984 VDD must be configured between +3.0V to +3.3V. Note Allocation of VSS pin for each packages are as follows. QFP: 1,13,35,50,65,101,114 BGA: B2,F2,K2,G5,F9,B10,K10
3.3 Example Register Settings

Connector Pin#

Pin Name
VSYNC HSYNC CLK VSS MODE POCB NC RVDD COMDC NC VSREF C1P C1M C2M C2P VDD COMOUT VDD2 VSS VSS VSS C3M C3P C4M C4P VVCOM NC NC VGH C5P C5M VGL BLL2 BLH2 NC NC BLH1 BLL1
24bit mode: Vertical synchronous signal 18bit mode: Vertical synchronous signal (Negative) 24bit mode: Horizontal synchronous signal 18bit mode: Horizontal synchronous signal (Negative) 24bit mode: Dot clock 18bit mode: Dot clock (Capture at the falling edge) GND Input mode select, Lo: 24bit, Hi: 18bit Power on clear input (Lo-active) OPEN Internal power Common driver DC output OPEN Internal DAC reference power For charge pump capacitor connection For charge pump capacitor connection For charge pump capacitor connection For charge pump capacitor connection Power +3.0V(+2.7VVDD+3.6V Rectangular wave output for common driver Internal power GND GND GND For charge pump capacitor connection For charge pump capacitor connection For charge pump capacitor connection For charge pump capacitor connection COMOUT power output OPEN OPEN Gate driver power(+) For charge pump capacitor connection For charge pump capacitor connection Gate driver power(-) LED drive power2(cathode) LED drive power2(anode) OPEN OPEN LED drive power1(anode) LED drive power1(cathode)
Note The recommended connectors are FH26G-67S-0.3SHBW(0.5) from Hirose Electric Co., Ltd. or 04-6281-267-2X2-846+ from Kyocera elco. The connector is a 0.3mm pitch 67-pin FPC connector (20.8mm x 0.2mm gold plate).

4.2 Connection Examples

The information in this section provides connection examples for the S1D13513, S1D13719, and S1D13748 display controllers. Each display controller is available in two packages. The connection information differs for each package and is listed separately. In addition to the pin connections for the selected display controller, the COM41T4148 requires the following power supply. VDD +3.0V (2.7V VDD 3.6V)
For VDD, select a voltage within the supportable range of the Display Controller. For further details on the COM41T4148, such as power consumption, absolute maximum ratings, and charge pump capacitor connections (see pins 41-44, 51-54, 59-60), please contact your Casio representative. 4.2.1 Connecting the COM41T4148 to the S1D13513 The following diagram shows an example implementation of the COM41T4148 panel connected to the S1D13513. This example is for the setting of 18-bit panel mode (MODE=VDD) on COM41T4148.

Vertical synchronous signal (Negative) Horizontal synchronous signal (Negative) Dot clock (Capture at the falling edge) GND Input mode select, Lo: 24bit, Hi: 18bit Power on clear input (Lo-active) OPEN Internal power Common driver DC output OPEN Internal DAC reference power For charge pump capacitor connection For charge pump capacitor connection For charge pump capacitor connection For charge pump capacitor connection Power +3.0V(+2.7VVDD+3.6V Rectangular wave output for common driver Internal power GND GND GND For charge pump capacitor connection For charge pump capacitor connection For charge pump capacitor connection For charge pump capacitor connection COMOUT power output OPEN OPEN Gate driver power(+) For charge pump capacitor connection For charge pump capacitor connection Gate driver power(-) LED drive power2(cathode) LED drive power2(anode) OPEN OPEN LED drive power1(anode) LED drive power1(cathode)

77 Note 1 57,65,75

T8 R8 P8 Note 1 L5,L8,T6
FPFRAME FPLINE FPSHIFT VSS HVDD2

57,65,75

L5,L8,T6

Note 1 Note 1 Note 1

VSS VSS VSS
4.2.2 Connecting the COM41T4148 to the S1D13719 The following diagram shows an example implementation of the COM41T4148 panel connected to the S1D13719. This example is for the setting of 18-bit panel mode (MODE=VDD) on COM41T4148.

S1D13719

PIOVDD FPDAT[6:8] FPDAT[15:17]
The following diagram shows an example implementation of the COM41T4148 panel connected to the S1D13719. This example is for the setting of 24-bit panel mode (MODE=VSS) on COM41T4148.
COM41T4148 VDD D[27:25] (B) D[24:22] (B) D[21:20] (B) D[17:15] (G) D[14:12] (G) D[11:10] (G) D[7:5] (R) D[4:2] (R) D[1:0] (R) HSYNC VSYNC CLK CS DI SCK MODE VSS VSS 3.0V S1D13719
HVDD2 FPDAT[6:8] FPDAT[15:17] FPDAT[22:23] FPDAT[3:5] FPDAT[12:14] FPDAT[20:21] FPDAT[0:2] FPDAT[9:11] FPDAT[18:19] FPLINE FPFRAME FPSHIFT GPIO0 GPIO3 GPIO1
The following table provides a detailed pin listing for the required connections between the COM41T4148 and the S1D13719. This table is for the setting of 18-bit panel mode (MODE=VDD) on COM41T4148. Pin mappings are shown for both S1D13719 package types.
Connecting the COM41T4148 to the S1D13719 (18-bit panel mode (MODE=VDD))
LCD Panel Connector Pin# LCD Pane Pin Name LCD Panel Pin Description S1D13719 S1D13719 S1D13719 PFBGA Pin# FCBGA Ball# QFP Pin# S1D13719 Pin Name -
Common driver signal BLUE data signal (MSB) BLUE data signal BLUE data signal BLUE data signal BLUE data signal BLUE data signal (LSB) Connect to VSS Connect to VSS GREEN data signal (MSB) GREEN data signal GREEN data signal GREEN data signal EPSON

Note The recommended connector is a FH23-39S-0.3SHW(0.5) from Hirose Electric Co., Ltd. The connector is a 0.3mm pitch 39-pin FPC connector (12.0mm x 0.2mm gold plate).
36 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00)

5.2 Connection Examples

The information in this section provides connection examples for the S1D13513 and S1D13748 display controllers. For the S1D13513 and S1D13748, the display controller is available in two packages. The connection information differs for each package and is listed separately. In addition to the pin connections for the selected display controller, the COM35H3827 requires the following power supplies. VDD +3.0V (2.7V VDD 3.6V)
For VDD, select a voltage within the supportable range of the Display Controller. For further details on the COM35H3827, such as power consumption and absolute maximum ratings, please contact your Casio representative. 5.2.1 Connecting the COM35H3827 to the S1D13513 The following diagram shows an example implementation of the COM35H3827 panel connected to the S1D13513.
3.0V COM35H3827 VDD STBYB DE D[25:23] (R) D[22:20] (R) D[15:13] (G) D[12:10] (G) D[5:3] (B) D[2:0] (B) HSYNC VSYNC CLK FPDRDY FPDAT[0:2] FPDAT[9:11] FPDAT[3:5] FPDAT[12:14] FPDAT[6:8] FPDAT[15:17] FPLINE FPFRAME FPSHIFT S1D13513 HVDD2

TEST1 TEST2 VSS VSS

The following table provides a detailed pin listing for the required connections between the COM35H3827 and the S1D13513. Pin mappings are shown for both S1D13513 package types.
Connecting the COM35H3827 to the S1D13513
VSS VSS VDD VDD VSS RESETB HSYNC VSYNC CLK VSS D00 D01 D02 D03 D04 D05 D10 D11 D12 D13 D14 D15 D20 D21 D22 D23 D24 D25 VSS DE STBYB TEST1 NC NC NC NC TEST2 BLH BLL
GND GND Power supply for logic +2.7V+3.6V Power supply for logic +2.7V+3.6V GND RESET(Lo-active) Horizontal synchronous signal (Negative) Vertical synchronous signal (Negative) Dot clock (Capture at the falling edge) GND BLUE data signal (LSB) BLUE data signal BLUE data signal BLUE data signal BLUE data signal BLUE data signal (MSB) GREEN data signal (LSB) GREEN data signal GREEN data signal GREEN data signal GREEN data signal GREEN data signal (MSB) RED data signal (LSB) RED data signal RED data signal RED data signal RED data signal RED data signal (MSB) GND Input data enable (Hi-active) Display control signal Lo:Standby, Hi:Normal Connect to GND OPEN OPEN OPEN OPEN Connect to GND Power supply for back light LED(anode) Power supply for back light LED(cathode)
Note Note 57,65,75 57,65,75 Note 77 Note Note 80 57,65,75 Note Note -
Note Note L5,L8,T6 L5,L8,T6 Note R8 T8 P8 Note N4 P4 T2 R6 K6 M6 R4 T4 T5 L7 P7 R7 N5 M5 P6 T7 N7 M7 Note M8 L5,L8,T6 Note Note -
VSS VSS HVDD2 HVDD2 VSS FPLINE FPFRAME FPSHIFT VSS FPDAT17 FPDAT16 FPDAT15 FPDAT8 FPDAT7 FPDAT6 FPDAT14 FPDAT13 FPDAT12 FPDAT5 FPDAT4 FPDAT3 FPDAT11 FPDAT10 FPDAT9 FPDAT2 FPDAT1 FPDAT0 VSS FPDRDY HVDD2 VSS VSS -

Note P8 M8 R8 T8 Note N5 M5 P6 T7 N7 M7 R4 T4 T5 L7 P7 R7 N4 P4 T2 R6 K6 M6 Note Note
VSS FPSHIFT FPDRDY FPLINE FPFRAME VSS FPDAT11 FPDAT10 FPDAT9 FPDAT2 FPDAT1 FPDAT0 FPDAT14 FPDAT13 FPDAT12 FPDAT5 FPDAT4 FPDAT3 FPDAT17 FPDAT16 FPDAT15 FPDAT8 FPDAT7 FPDAT6 VSS VSS
57,65,75 57,65,75 Note Note Note Note Note -
L5,L8,T6 L5,L8,T6 Note Note Note Note Note -
HVDD2 HVDD2 VSS VSS VSS VSS VSS -
Note Allocation of VSS pin for each packages are as follows. QFP: 10,20,38,58,66,76,92,99,106,120,133,139,151,163,169,175,184,197 BGA: A1,A16,D4,D8,D13,G7-G10,G13,H7-H10,J1,J7-J10,K2,K7-K10,K13,N3,N6,N9,N13,T1,T16
6.2.2 Connecting the COM55T5108 to the S1D13706 The following diagram shows an example implementation of the COM55T5108 panel connected to the S1D13706.
COM55T5108 VDD STBYB DE D[25:23] (R) D[22:20] (R) D[15:13] (G) D[12:10] (G) D[5:3] (B) D[2:0] (B) HSYNC VSYNC CLK

3.3V S1D13706 NIOVDD

FPDRDY FPDAT[0:2] FPDAT[9:11] FPDAT[3:5] FPDAT[12:14] FPDAT[6:8] FPDAT[15:17] FPLINE FPFRAM FPSHIFT
The following table provides a detailed pin listing for the required connections between the COM55T5108 and the S1D13706. Connecting the COM55T5108 to the S1D13706
VSS CLK DE HSYNC VSYNC VSS D20 D21 D22 D23 D24 D25 D10 D11 D12 D13 D14 D15 D00 D01 D02 D03 D04 D05 VSS REV VDD STBYB VSS PDM VSS_B VSS_B VSS_B VBL VBL VBL VSS
GND for digital Dot clock (Capture at the falling edge) Input data enable (Hi-active) Horizontal synchronous signal Vertical synchronous signal GND for digital RED data signal (LSB) RED data signal RED data signal RED data signal RED data signal RED data signal (MSB) GREEN data signal (LSB) GREEN data signal GREEN data signal GREEN data signal GREEN data signal GREEN data signal (MSB) BLUE data signal (LSB) BLUE data signal BLUE data signal BLUE data signal BLUE data signal BLUE data signal (MSB) GND for digital Vertical and Horizontal reverse control signal input (Lo: Normal, Hi:Reverse) Power +3.3V(+3.0VVDD+3.6V Standby control signal input (Lo: Normal, Hi: Standby) GND for analog Back light dimmer control pulse input (Lo:100%, Hi:0%(Back light off)) GND for back light GND for back light GND for back light Power supply for back light Power supply for back light Power supply for back light GND for digital
Note Note Note Note 37,49,63,76 37,49,63,76 Note Note Note Note Note Note
VSS FPSHIFT FPDRDY FPLINE FPFRAME VSS FPDAT11 FPDAT10 FPDAT9 FPDAT2 FPDAT1 FPDAT0 FPDAT14 FPDAT13 FPDAT12 FPDAT5 FPDAT4 FPDAT3 FPDAT17 FPDAT16 FPDAT15 FPDAT8 FPDAT7 FPDAT6 VSS VSS NIOVDD NIOVDD VSS VSS VSS VSS VSS VSS

Note Note Note Note Note Note Note 57,65,75 57,65,75 57,65,75 Note 80 Note
N4 P4 T2 R6 K6 M6 Note Note Note R4 T4 T5 L7 P7 R7 Note Note Note N5 M5 P6 T7 N7 M7 Note L5,L8,T6 L5,L8,T6 L5,L8,T6 Note M8 Note
FPDAT17 FPDAT16 FPDAT15 FPDAT8 FPDAT7 FPDAT6 VSS VSS VSS FPDAT14 FPDAT13 FPDAT12 FPDAT5 FPDAT4 FPDAT3 VSS VSS VSS FPDAT11 FPDAT10 FPDAT9 FPDAT2 FPDAT1 FPDAT0 VSS HVDD2 HVDD2 HVDD2 VSS FPDRDY VSS
REV VSS VBL VBL PDM VSS VSS

Note 57,65,75 Note Note

Note L5,L8,T6 Note Note

VSS HVDD2 VSS VSS

Note Allocation of VSS pin for each packages are as follows. QFP: 10,20,38,58,66,76,92,99,106,120,133,139,151,163,169,175,184,197 BGA: A1,A16,D4,D8,D13,G7-G10,G13,H7-H10,J1,J7-J10,K2,K7-K10,K13,N3,N6,N9,N13,T1,T16 The following table provides a detailed pin listing for the required connections between the COM57T5120 and the S1D13513. This table is for the setting of 24-bit panel mode (MODE=VSS) on COM57T5120. Pin mappings are shown for both S1D13513 package types.
Connecting the COM57T5120 to the S1D13513 (24-bit panel mode (MODE=VSS))
VSS CLK VSS HSYNC VSYNC VSS D20 D21 D22 D23 D24 D25 D26 D27 VSS D10 D11 D12 D13 D14 D15 D16 D17 VSS D00 D01 D02 D03 D04 D05 D06 D07 VSS MODE VDD VDD STBY DE
GND Dot clock (Capture at the falling edge) GND Horizontal synchronous signal (Negative) Vertical synchronous signal (Negative) GND Connect to VSS Connect to VSS BLUE data signal (LSB) BLUE data signal BLUE data signal BLUE data signal BLUE data signal BLUE data signal (MSB) GND Connect to VSS Connect to VSS GREEN data signal (LSB) GREEN data signal GREEN data signal GREEN data signal GREEN data signal GREEN data signal (MSB) GND Connect to VSS Connect to VSS RED data signal (LSB) RED data signal RED data signal RED data signal RED data signal RED data signal (MSB) GND Input mode select. Lo: 24bit, Hi: 18bit Power supply for logic+3.3V0.3V Power supply for logic+3.3V0.3V Standby control signal input (Lo: Normal, Hi: Standby) Input data enable (Hi-active) Vertical and Horizontal reverse control signal input (Lo: Normal, Hi:Reverse) GND Power supply for back light+12V1.2V Power supply for back light+12V1.2V Back light pulse input. Lo: OFF0%, Hi: ON100% GND GND

Note Note 78 Note 1 Note 2 Note 68 Note 1 Note 2 Note 71 Note 1 Note 2 Note 74 Note 1 Note 1 57,65,75 57,65,82 84
Note 1 P8 Note 1 R8 T8 Note 1 K4 R3 N4 P4 T2 R6 K6 M6 Note 1 T3 P5 R4 T4 T5 L7 P7 R7 Note 1 K5 R5 N5 M5 P6 T7 N7 M7 Note 1 Note 1 L5,L8,T6 L5,L8,T6 L9 T9 P9
VSS FPSHIFT VSS FPLINE FPFRAME VSS FPDAT23 FPDAT22 FPDAT17 FPDAT16 FPDAT15 FPDAT8 FPDAT7 FPDAT6 VSS FPDAT21 FPDAT20 FPDAT14 FPDAT13 FPDAT12 FPDAT5 FPDAT4 FPDAT3 VSS FPDAT19 FPDAT18 FPDAT11 FPDAT10 FPDAT9 FPDAT2 FPDAT1 FPDAT0 VSS VSS HVDD2 HVDD2 CS# SO SCK

Note 1

57,65,75 Note 1 Note 1

L5,L8,T6 Note 1 Note 1

HVDD2 VSS VSS
Note 1 Allocation of VSS pin for each packages are as follows.
QFP: 10,20,38,58,66,76,92,99,106,120,133,139,151,163,169,175,184,197 BGA: A1,A16,D4,D8,D13,G7-G10,G13,H7-H10,J1,J7-J10,K2,K7-K10,K13,N3,N6,N9,N13,T1,T16 Note 2 For QFP package, please connect to S1D13513 VSS pin.
7.2.2 Connecting the COM57T5120 to the S1D13748 The following diagram shows an example implementation of the COM57T5120 panel connected to the S1D13748. This example is for the setting of 18-bit panel mode (MODE=VDD) on COM57T5120.
3.3V COM57T5120 VDD MODE CS/STBY PDM DI/DE D[27:25] (B) D[24:22] (B) D[17:15] (G) D[14:12] (G) D[7:5] (R) D[4:2] (R) HSYNC VSYNC CLK D[21:20] D[11:10] D[1:0] SCK/REV VSS VSS FPDRDY FPDAT[6:8] FPDAT[15:17] FPDAT[3:5] FPDAT[12:14] FPDAT[0:2] FPDAT[9:11] FPLINE FPFRAME FPSHIFT S1D13748 PIOVDD
The following diagram shows an example implementation of the COM57T5120 panel connected to the S1D13748. This example is for the setting of 24-bit panel mode (MODE=VSS) on COM57T5120.
COM57T5120 VDD MODE CS/STBY PDM DI/DE D[27:25] (B) D[24:22] (B) D[21:20] (B) D[17:15] (G) D[14:12] (G) D[11:10] (G) D[7:5] (R) D[4:2] (R) D[1:0] (R) HSYNC VSYNC CLK FPSO FPDAT[6:8] FPDAT[15:17] FPDAT[22:23] FPDAT[3:5] FPDAT[12:14] FPDAT[20:21] FPDAT[0:2] FPDAT[9:11] FPDAT[18:19] FPLINE FPFRAME FPSHIFT FPCS1# S1D13748 PIOVDD

SCK/REV VSS

FPSCK VSS
The following table provides a detailed pin listing for the required connections between the COM57T5120 and the S1D13748. This table is for the setting of 18-bit panel mode (MODE=VDD) on COM57T5120. Pin mappings are shown for both S1D13748 package types. Connecting the COM57T5120 to the S1D13748 (18-bit panel mode (MODE=VDD))
LCD Panel Connector Pin# LCD Panel Pin Name S1D13748 QFP Pin# S1D13748 PFBGA Ball# S1D13748 Pin Name
GND Dot clock (Capture at the falling edge) GND Horizontal synchronous signal (Negative) Vertical synchronous signal (Negative) GND Connect to VSS Connect to VSS EPSON

Note 75 Note Note Note Note
Note J11 Note H10 J10 Note Note Note
D22 D23 D24 D25 D26 D27 VSS D10 D11 D12 D13 D14 D15 D16 D17 VSS D00 D01 D02 D03 D04 D05 D06 D07 VSS MODE
BLUE data signal (LSB) BLUE data signal BLUE data signal BLUE data signal BLUE data signal BLUE data signal (MSB) GND Connect to VSS Connect to VSS GREEN data signal (LSB) GREEN data signal GREEN data signal GREEN data signal GREEN data signal GREEN data signal (MSB) GND Connect to VSS Connect to VSS RED data signal (LSB) RED data signal RED data signal RED data signal RED data signal RED data signal (MSB) GND Input mode select. Lo: 24bit, Hi: 18bit
Power supply for logic+3.3V0.3V
Power supply for logic+3.3V0.3V Standby control signal input (Lo: Normal, Hi: Standby) Input data enable (Hi-active) Vertical and Horizontal reverse control signal input (Lo: Normal, Hi:Reverse) GND Power supply for back light+12V1.2V Power supply for back light+12V1.2V Back light pulse input. Lo: OFF0%, Hi: ON100% GND GND
Note Note Note Note Note Note Note 19,26,35, 40,46,55, 67,73,83, 87 19,26,35, 40,46,55, 67,73,83, 87 19,26,35, 40,46,55, 67,73,83, 87 Note 78 Note Note
J9 K10 L10 K7 J7 L7 Note Note Note H8 K9 L9 L6 J6 H6 Note Note Note L8 J8 K8 K5 L5 J5 Note E8,F4, H7,J4
FPDAT17 FPDAT16 FPDAT15 FPDAT8 FPDAT7 FPDAT6 VSS VSS VSS FPDAT14 FPDAT13 FPDAT12 FPDAT5 FPDAT4 FPDAT3 VSS VSS VSS FPDAT11 FPDAT10 FPDAT9 FPDAT2 FPDAT1 FPDAT0 VSS PIOVDD
STBY DE REV VSS VBL VBL PDM VSS VSS

Note G7 Note Note

VSS FPDRDY VSS VSS
19,26,35, 40,46,55,67 ,73,83,87 Note Note

E8,F4,H7 ,J4 Note Note

PIOVDD VSS VSS
Note Allocation of VSS pin for each packages are as follows.
PFBGA: B1,C4,C8,D10,E6,F2,F8,G4,K6,K11 QFP: 6,13,20,31,36,39,47,56,66,74,82,91,97,102,108,115,129,138,144
The following table provides a detailed pin listing for the required connections between the COM57T5120 and the S1D13748. This table is for the setting of 24-bit panel mode (MODE=VSS) on COM57T5120. Pin mappings are shown for both S1D13748 package types. Connecting the COM57T5120 to the S1D13748 (24-bit panel mode (MODE=VSS))
LCD Panel Connector Pin# LCD Panel Pin Name LCD Panel Pin Description S1D13748 QFP Pin# S1D13748 PFBGA Ball#

VSS CLK VSS HSYNC VSYNC VSS D20 D21 D22 D23 D24 D25 D26 D27 VSS D10 D11 D12 D13 D14 D15 D16 D17 VSS D00 D01 D02 D03
GND Dot clock GND Horizontal synchronous signal Vertical synchronous signal GND BLUE data signal (LSB) BLUE data signal BLUE data signal BLUE data signal BLUE data signal BLUE data signal BLUE data signal BLUE data signal (MSB) GND GREEN data signal (LSB) GREEN data signal GREEN data signal GREEN data signal GREEN data signal GREEN data signal GREEN data signal GREEN data signal (MSB) GND RED data signal (LSB) RED data signal RED data signal RED data signal
Note 75 Note Note Note Note 63 62
Note J11 Note H10 J10 Note H5 L4 J9 K10 L10 K7 J7 L7 Note G6 K4 H8 K9 L9 L6 J6 H6 Note L3 K3 L8 JE
VSS FPSHIFT VSS FPLINE FPFRAM VSS FPDAT2 FPDATFPDATFPDATFPDATFPDAT8 FPDAT7 FPDAT6 VSS FPDAT2 FPDATFPDATFPDATFPDATFPDAT5 FPDAT4 FPDAT3 VSS FPDAT1 FPDATFPDATFPDAT1
D04 D05 D06 D07 VSS MODE VDD RED data signal RED data signal RED data signal RED data signal (MSB) GND Input mode select, Lo: 24bit, Hi: 18bit Power supply for logic+3.3V0.3V Note Note 19,26,35, 40,46,55,67 ,73,83,87 19,26,35, 40,46,55,67 ,73,83,Note
K8 K5 L5 J5 Note Note E8,F4,H7 ,J4 E8,F4,H7 ,J4 G9 G11 H11 Note
FPDAT9 FPDAT2 FPDAT1 FPDAT0 VSS VSS PIOVDD
VDD CS DI SCK VSS VBL VBL PDM VSS VSS
Power supply for logic+3.3V0.3V Serial chip select (Lo-active) Serial data input Serial clock GND Power supply for back light+12V1.2V Power supply for back light+12V1.2V Back light pulse input, Lo:OFF0%, Hi:ON100% GND GND
PIOVDD FPCS1# FPSO FPSCK VSS
7.3 Example Register Settings
In addition to the pin connections, the S1D13513/S1D13748 internal registers must be configured appropriately for the COM57T5120 LCD panel. The following tables provide example settings for each display controller. However, these values are for reference only and may differ according to each specific implementation. For details on configuring the S1D13513 register values, see the S1D13513 Hardware Functional Specification, document number X78B-A-001-xx. For details on configuring the S1D13748 register values, see the S1D13748 Hardware Functional Specification, document number X80A-A-001-xx. Also included in the table is an example clock configuration designed to achieve a 50Hz or greater LCD refresh. Example Register Settings for the S1D13513
Register Index and Name REG[0800h] LCD Panel Type Select Register REG[0802h] LCD Horizontal Total Register REG[0804h] LCD Horizontal Display Period Register REG[0806h] LCD Horizontal Display Period Start Position Register REG[0808h] LCD Horizontal Pulse Width REG[080Ah] LCD Horizontal Pulse Start Position REG[080Ch] LCD Vertical Total Register REG[080Eh] LCD Vertical Display Period Resister REG[0810h] Vertical Display Period Start Position Register REG[0812h] LCD Vertical Pulse Width REG[0814h] LCD Vertical Pulse Start Position PLL2 output frequency in MHz REG[0446h] LCD Clock Control Register FPSHIFT in MHz LCD Refresh in Hz 11

N4 P4 T2 R6 K6 M6

R4 T4 T5 L7 P7 R7

N5 M5 P6 T7 N7 M7

VSS FPSHIFT VSS FPLINE FPFRAME VSS VSS VSS FPDAT17 FPDAT16 FPDAT15 FPDAT8 FPDAT7 FPDAT6 VSS VSS VSS FPDAT14 FPDAT13 FPDAT12 FPDAT5 FPDAT4 FPDAT3 VSS VSS VSS FPDAT11 FPDAT10 FPDAT9 FPDAT2 FPDAT1 FPDAT0 VSS HVDD2 HVDD2 HVDD2 HVDD2 FPDRDY VSS VSS
57,65,75 57,65,75 57,65,75 57,65,75 80
L5,L8,T6 L5,L8,T6 L5,L8,T6 L5,L8,T6 M8
Connecting the COM65T6111 to the S1D13742
The following diagram shows an example implementation of the COM65T6111 panel connected to the S1D13742.
3.3V COM65T6111 VDD RL DISP PDM DE D[27:22] (B) D[17:12] (G) D[7:2] (R) DE VD[5:0] VD[11:6] VD[17:12] S1D13742 PIOVDD

HSYNC VSYNC CLK

HS VS PCLK

TEST[1:6] UD VSS VSS

The following table provides a detailed pin listing for the required connections between the COM65T6111 and the S1D13742. Connecting the COM65T6111 to the S1D13742
VSS CLK VSS HSYNC VSYNC VSS TEST1 TEST2 D20 D21 D22 D23 D24 D25 VSS TEST3 TEST4 D10 D11 D12 D13 D14 D15 VSS TEST5 TEST6 D00 D01 D02 D03 D04 D05 VSS RL
GND Dot clock GND Horizontal synchronous signal (Negative) Vertical synchronous signal (Negative) GND Connect to VSS Connect to VSS BLUE data signal (LSB) BLUE data signal BLUE data signal BLUE data signal BLUE data signal BLUE data signal (MSB) GND Connect to VSS Connect to VSS GREEN data signal (LSB) GREEN data signal GREEN data signal GREEN data signal GREEN data signal GREEN data signal (MSB) GND Connect to VSS Connect to VSS RED data signal (LSB) RED data signal RED data signal RED data signal RED data signal RED data signal (MSB) GND Horizontal reverse display control (Lo: Reverse, Hi: Normal) Power supply for logic+3.3V0.3V
VSS PCLK VSS HS VS VSS VSS VSS VD0 VD1 VD2 VD3 VD4 VD5 VSS VSS VSS VD6 VD7 VD8 VD9 VD10 VD11 VSS VSS VSS VD12 VD13 VD14 VD15 VD16 VD17 VSS PIOVDD

D9 D10

L9 L8 L7 L6 L5 L4

L3 K10 K9 K8 K7 K6

K5 K4 J11 J10 J9 J8

DISP DE UD

Display control signal Lo:OFF, Hi:ON Input data enable (Hi-active) Vertical reverse display control
4,17,20, 33,38,52,5 5,69 4,17,20, 33,38,52,5 5,69 4,17,20, 33,38,52,5 5,69 4,17,20, 33,38,52,5 5,69 8
E8,G4,H5 ,H7 E8,G4,H5 ,H7 E8,G4,H5 ,H7 E8,G4,H5 ,H7 C11

PIOVDD DE VSS

LCD Panel Pin Name LCD Panel Pin Description

S1D13742 QFP Pin#

S1D13742 FCBGA Ball# -

S1D13742 Pin Name

VSS VBL VBL PDM VSS VSS
(Lo: Normal, Hi: Reverse) GND Power supply for +12V1.2V Power supply for +12V1.2V

back back

light light
Back light dimmer control pulse input (Lo: 0%(Back light off), Hi:100%) GND GND

4,17,20, 33,38,52,5 5,69

Connector Pin# Pin Name VSS CLK HSYNC VSYNC VSS D20 D21 D22 D23 D24 D25 VSS D10 D11 D12 D13 D14 D15 VSS D00 D01 D02 D03 D04 D05 VSS DE PDM NC RL UD VSS Pin Description GND CLK HSYNC VSYNC GND Red D02 Red D03 Red D04 Red D05 Red D06 Red D07 GND Green D12 Green D13 Green D14 Green D15 Green D16 Green D17 GND Blue D02 Blue D03 Blue D04 Blue D05 Blue D06 Blue D07 GND DE Back light pulse input Low: 100% bright, High: 0% bright (back light off) Horizontal reverse display control Low: Reverse, High: Normal Vertical reverse display control Low: Reverse, High: Normal GND
Note The recommended connector is a Molex 52559-3252. The connector is a 0.5mm pitch 32-pin FPC connector (16.5mm x 0.3mm gold plate).
COM80T8102 Pin Mapping (Power Supply Connector)
Connector Pin# Pin Name VDD GND Pin Description +12.0V (1.2V) GND
Note The recommended connectors are: Mounting Side: B2B-PH-SM4TBT(LF) Cable Side: PHR-2 (housing) and SPH-002T-P0.5 or SPH-004T-P0.5 (contact)

9.2 Connection Examples

The information in this section provides a connection example for the S1D13513 display controller. The S1D13513 display controller is available in two packages. The connection information differs for each package and is listed separately. In addition to the pin connections for the selected display controller, the COM80T8102 requires the following power supplies. VDD +12.0V(1.2V)
The COM80T8102 generates 3.3V logic voltage internally. Therefore, the display controller VDD must be configured within the range of 3.3V0.3V. For further details on the COM80T8102, such as power consumption and absolute maximum ratings, please contact your Casio representative.
9.2.1 Connecting the COM80T8102 to the S1D13513 The following diagram shows an example implementation of the COM80T8102 panel connected to the S1D13513.
COM80T8102 RL UD DE FPDRDY 3.3V S1D13513 HVDD2
D[25:23] (R) D[22:20] (R) D[15:13] (G) D[12:10] (G) D[5:3] (B) D[2:0] (B)
FPDAT[0:2] FPDAT[9:11] FPDAT[3:5] FPDAT[12:14] FPDAT[6:8] FPDAT[15:17]

HSYNC VSYNC CLK PDM VSS

FPLINE FPFRAM FPSHIFT
The following table provides a detailed pin listing for the required connections between the COM80T8102 and the S1D13513. Pin mappings are shown for both S1D13513 package types. Connecting the COM80T8102 to the S1D13513 (Signal Connector)
LCD Panel Connector Pin# LCD Panel Pin Name VSS CLK HSYNC VSYNC VSS D20 D21 D22 D23 D24 D25 VSS D10 D11 D12 D13 D14 D15 VSS D00 D01 D02 D03 D04 D05 VSS DE PDM NC RL UD VSS LCD Panel Pin Description GND CLK HSYNC VSYNC GND Red D02 Red D03 Red D04 Red D05 Red D06 Red D07 GND Green D12 Green D13 Green D14 Green D15 Green D16 Green D17 GND Blue D02 Blue D03 Blue D04 Blue D05 Blue D06 Blue D07 GND DE Back light pulse input Low: 100% bright, High: 0% bright (back light off) Horizontal reverse display contro Low: Reverse, High: Normal l Vertical reverse display control Low: Reverse, High: Normal GND S1D13513 QFP Pin# S1D13513 PBGA Ball# J11 H10 J10 L8 J8 K8 K5 L5 J5 H8 K9 L9 L6 J6 H6 J9 K10 L10 K7 J7 L7 G7 S1D13513 Pin Name VSS FPSHIFT FPLINE FPFRAME VSS FPDAT11 FPDAT10 FPDAT9 FPDAT2 FPDAT1 FPDAT0 VSS FPDAT14 FPDAT13 FPDAT12 FPDAT5 FPDAT4 FPDAT3 VSS FPDAT17 FPDAT16 FPDAT15 FPDAT8 FPDAT7 FPDAT6 VSS FPDRDY VSS HVDD2 HVDD2 VSS