Power Output Modem analog regulated supply output RF Control Output Modem bias voltage/control signal for RF external components

CT_Bias

RFIN_M RFIN_P NC
RF Input (Output) RF Input (Output)
Modem RF input/output negative Modem RF input/output positive Not used
Pin # 38 Pin Name PAO_P Type RF Output Description Functionality
Modem power amplifier RF Open drain. Connect to VDDA through a bias output positive network when used with external balun. Not used when internal T/R switch is used. Modem power amplifier RF Open drain. Connect to VDDA through a bias output negative network when used with external balun. Not used when internal T/R switch is used. Test Mode pin General Purpose Input/Output 4. Modem General Purpose Input/Output 3 Must be grounded for normal operation See Footnote 1 See Footnote 1

RF Output

SM GPIO41 GPIO31 GPIO2
Input Digital Input/ Output Digital Input/Output Test Point
MCU Port E Bit 6 / Modem Internally connected pins. When gpio_alt_en, General Purpose Register 9, Bit 7 = 1, GPIO2 functions as a CRC Input/Output 2 Valid indicator. MCU Port E Bit 7 / Modem Internally connected pins. When gpio_alt_en, General Purpose Register 9, Bit 7 = 1, GPIO1 functions as an Out of Input/Output 1 Idle indicator. MCU main power supply Active Low Attention. Transitions IC from either Hibernate or Doze Modes to Idle. MCU Port D Bit 2 / TPM1 Channel 2 MCU Port D Bit 4 / TPM2 Channel 1 MCU Port D Bit 5 / TPM2 Channel 2 MCU Port D Bit 6 / TPM2 Channel 3 MCU Port D Bit 7 / TPM2 Channel 4 MCU Port B Bit 0 / ATD analogChannel 0 MCU Port B Bit 1 / ATD analog Channel 1 MCU Port B Bit 2 / ATD analog Channel 2 MCU Port B Bit 3 / ATD analog Channel 3 MCU Port B Bit 4 / ATD analog Channel 4 Decouple to ground. See Footnote 2

Test Point

VDD ATTN2
Power Input Digital Input
PTD2/TPM1CH2 PTD4/TPM2CH1 PTD5/TPM2CH2 PTD6/TPM2CH3 PTD7/TPM2CH4 PTB0/AD1P0 PTB1/AD1P1 PTB2/AD1P2 PTB3/AD1P3 PTB4/AD1P4
Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 11
Pin # 65 Pin Name PTB5/AD1P5 PTB6/AD1P6 PTB7/AD1P7 VREFH VREFL PTA0/KBI1P0 PTA1/KBI1P1 PTA2/KBI1P2 PTE5/SPSCK1 Type Input/Output Input/Output Input/Output Input Input Digital Input/Output Digital Input/Output Digital Input/Output SPICLK Description MCU Port B Bit 5 / ATD analog Channel 5 MCU Port B Bit 6 / ATD analog Channel 6 MCU Port B Bit 7 / ATD analog Channel 7 MCU high reference voltage for ATD MCU low reference voltage for ATD MCU Port A Bit 0 / Keyboard Input Bit 0 MCU Port A Bit 1 / Keyboard Input Bit 1 MCU Port A Bit 2 / Keyboard Input Bit 2 MCU SPI master SPI clock Normally factory test. Do not connect output drives modem SPICLK slave clock input. MCU SPI master MOSI Normally factory test. Do not connect output drives modem slave MOSI input Modem SPI slave MISO Normally factory test. Do not connect output drives MCU master MISO input MCU SPI master SS Normally factory test. Do not connect output drives modem slave CE input Modem interrupt request Normally factory test. Do not connect M_IRQ output drives MCU IRQ input MCU Port D Bit 1 drives Normally factory test. Do not connect the RXTXEN input to the modem to enable TX or RX or CCA operations. MCU Port D Bit 3 drives the reset M_RST input to the modem. External package flag. Common VSS Normally factory test. Do not connect Functionality

SiP Level SPI Pin Connections
The SiP level SPI pin connections are all internal to the device. Figure 4 shows the SiP interconnections with the SPI bus highlighted.

MC1321x 43

M_RST M_IRQ ATTN RXTXEN MODEM GPIO1/Out_of_Idle GPIO2/CRC_Valid MOSI MISO SPICLK CE
PTD3 IRQ PTD0 PTD1 PTE7 PTE6 PTE4/MOSI1 PTE3/MISO1 PTE5/SPSCK1 PTE2/SS1 MCU
Figure 4. MC1321x Internal Interconnects Highlighting SPI Bus Table 4. MC1321x Internal SPI Connections
MCU Signal PTE5/SPSCK1 PTE4/MOSI1 PTE3/MISO1 PTE2/SS1 Modem Signal SPICLK MOSI MISO CE Description MCU SPI master SPI clock output drives modem SPICLK slave clock input. MCU SPI master MOSI output drives modem slave MOSI input Modem SPI slave MISO output drives MCU master MISO input MCU SPI master SS output drives modem slave CE input

SPI Features

MCU bus master Modem bus slave Programmable SPI clock rate; maximum rate is 8 MHz Double-buffered transmit and receive at MCU Serial clock phase and polarity must meet modem requirements (MCU control bits Slave select programmed to meet modem protocol

SPI System Block Diagram

MCU (MASTER) MOS1 SPI SHIFTER MISO1 MISO MOSI SPI SHIFTER MODEM (SLAVE)
Figure 5 shows the SPI system level diagram.

SPSCK1

SPICLK

CLOCK GENERATOR

Figure 5. SPI System Block Diagram
Figure 5 shows the SPI modules of the MCU and modem in the master-slave arrangement. The MCU (master) initiates all SPI transfers. During a transfer, the master shifts data out (on the MOSI pin) to the slave while simultaneously shifting data in (on the MISO pin) from the slave. Although the SPI interface supports simultaneous data exchange between master and slave, the modem SPI protocol only uses data exchange in one direction at a time. The SPSCK signal is a clock output from the master and an input to the slave. The slave device must be selected by a low level on the slave select input (SS1 pin).
MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 15

802.15.4 Standard Modem

Block Diagram

Symbol Synch & Det

Correlator
1st IF Mix er LNA IF = 65 MHz
2nd IF Mix er IF = 1 MHz PMA
Decimation Baseband Matched Filter Mix er Filter Packet Processor
Analog Regulator Pow er-Up Control Logic Digital Regulator L Digital Regulator H Cry stal Regulator

VDDA VBATT VDDINT VDDD

RFIN_P (PAO_P) RFIN_M (PAO_M) T/ R AGC

Receiv e Packet RAM

Receiv e RAM Arbiter Sequence Manager (Control Logic)

VCO Regulator

CT_Bias VDDLO2

256 MHz

Programmable Prescaler

24 Bit Ev ent Timer

XTAL1 XTAL2

Crystal Oscillator

16 MHz
SERIAL PERIPHERAL INTERFACE (SPI)
4 Programmable Timer Comparators
CE MOSI MISO SPICLK ATTN RST

Synthesizer

Transmit Packet RAM 2 Transmit Packet RAM 1
GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 Transmit RAM Arbiter Sy mbol Generation IRQ Arbiter IRQ

2.45 GHz VCO

PAO_P PAO_M

Phase Shift Modulator

FCS Generation

Header Generation

Figure 6. 802.15.4 Standard Modem Block Diagram

Data Transfer Modes

The 802.15.4 modem has two data transfer modes: 1. Packet Mode Data is buffered in on-chip RAM 2. Streaming Mode Data is processed word-by-word The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer. For proprietary applications, packet mode can be used to conserve MCU resources.

Packet Structure

Figure 7 shows the packet structure of the 802.15.4 modem. Payloads of up to 125 bytes are supported. The 802.15.4 modem adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A Frame Check Sequence (FCS) is calculated and appended to the end of the data.
4 bytes Preamble 1 byte SFD 1 byte FLI 125 bytes maximum Payload Data 2 bytes FCS
Figure 7. 802.15.4 modem Packet Structure

Receive Path Description

In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon the baseband energy integrated over a specific time interval. The digital back end performs Differential Chip Detection (DCD), the correlator de-spreads the Direct Sequence Spread Spectrum (DSSS) Offset QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data. The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS (which are stored in RAM in Packet Mode). A two-byte FCS is calculated on the received data and compared to the FCS value appended to the transmitted data, which generates a Cyclical Redundancy Check (CRC) result. A parameter of received energy during the reception called the Link Quality Indicator is measured over a 64 s period after the packet preamble and stored in an SPI register. If the 802.15.4 modem is in Packet Mode, the data is stored in RAM and processed as an entire packet. The MCU is notified that an entire packet has been received via an interrupt. If the 802.15.4 modem is in streaming mode, the MCU is notified by a recurring interrupt on a word-by-word basis. Figure 8 shows CCA reported power level versus input power. Note that CCA reported power saturates at about -57 dBm input power which is well above 802.15.4 Standard requirements.

MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 17
NOTE For both graphs, the required 802.15.4 Standard accuracy and range limits are shown. A 3.5 dBm offset has been programmed into the CCA reporting level to center the level over temperature in the graphs.
Reported Power Level (dBm)
802.15.4 Ac curac y and range Requirements

-100 -90

-70 Input Pow er (dBm)
Figure 8. Reported Power Level versus Input Power in Clear Channel Assessment Mode
Figure 9 shows energy detection/LQI reported level versus input power.
-15 -25 Reported Power Level (dBm) -35 -45 -55 -65 -75 -85 -85 -75 -65 -55 -45 -35 -25 -15 802.15.4 Accuracy and Range Requirements
Figure 9. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator
Transmit Path Description
For the transmit path, the TX data that was previously written to the internal RAM is retrieved (packet mode) or the TX data is clocked in via the SPI (stream mode), formed into packets per the 802.15.4 PHY, spread, and then up-converted to the transmit frequency. If the 802.15.4 modem is in packet mode, data is processed as an entire packet. The data is first loaded into the TX buffer. The MCU then requests that the modem transmit the data. The MCU is notified via an interrupt when the whole packet has successfully been transmitted. In streaming mode, the data is fed to the 802.15.4 modem on a word-by-word basis with an interrupt serving as a notification that the 802.15.4 modem is ready for more data. This continues until the whole packet is transmitted. In both modes, a two-byte FCS is calculated in hardware from the payload data and appended to the packet. This done without intervention from the user.

Functional Description

The following sections provide a detailed description of the MC1321x functionality including the operating modes and the Serial Peripheral Interface (SPI).
802.15.4 Modem Operational Modes
The 802.15.4 modem has a number of operational modes that allow for low-current operation. Transition from the Off to Idle mode occurs when M_RST is negated. Once in Idle, the SPI is active and is used to control the IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are summarized, along with the transition times, in Table 5. Current drain in the various modes is listed in Table 8, DC Electrical Characteristics.
Table 5. 802.15.4 Modem Mode Definitions and Transition Times
Mode Off Hibernate Doze Definition All IC functions Off, Leakage only. M_RST asserted. Digital outputs are tri-stated including IRQ Transition Time To or From Idle 10 - 25 ms to Idle
Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data 7 - 20 ms to Idle is retained. Crystal Reference Oscillator On but CLKO output available only if Register 7, Bit 9 (300 + 1/CLKO) s to Idle = 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to ATTN and can be programmed to enter Idle Mode through an internal timer comparator. Crystal Reference Oscillator On with CLKO output available. SPI active. Crystal Reference Oscillator On. Receiver On. Crystal Reference Oscillator On. Transmitter On. 144 s from Idle 144 s from Idle

RFIN_P (PAO_P) Balun L1 RFIN_M (PAO_M)
R F IN _ M (P A O _ M ) A nt Sw L NA B a lun L1 RF IN_ P (P A O _ P )

CT_Bias Bypass PAO_P

B yp a ss

M C 1321x

C T_ B ia s (A nt S w C tl) PA O_P
B a lun P A O_M B yp a s s
14A) Using Onboard T/R Switch 14B) Using External Antenna Switch With LNA

RX Antenna

RFIN_P (PAO_P)

RFIN_M (PAO_M)

TX Antenna Bypass VDDA Bypass

14C) Using Dual Antennae

Figure 14. Using the MC1321x with External RF Components

MCU Block Diagram

MCU CORE INTERNAL BUS PORT A

DEBUG MODULE (DBG)

PTA7/KBI1P7 PTA0/KBI1P0
MCU SYSTEM CONTROL RESET RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT
8-BIT KEYBOARD INTERRUPT MODULE (KBI1)

PORT B

8 PTB7/AD1P7 PTB0/AD1P0
IIC MODULE (IIC) PORT C RTI IRQ COP LVD SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) USER FLASH (61,268 BYTES MAX)
PTC7 PTC6 PTC5 PTC4 PTC3/SCL1 PTC2/SDA1 PTC1/RxD2 PTC0/TxD2 PTD7/TPM2CH4 PTD6/TPM2CH3 PTD5/TPM2CH2 PTD4/TPM2CH1 PTD3 PTD2/TPM1CH2 PTD1 PTD0 PTE7 PTE6 PTE5/SPSCK PTE4/MOSI PTE3/MISO PTE2/SS PTE1/RxD1 PTE0/TxD1
USER RAM (4096 BYTES MAX)
1-CHANNEL TIMER/PWM MODULE (TPM1)

VREFH VREFL

10-BIT ANALOG-TO-DIGITAL CONVERTER (ATD1)

MODULE (TPM2)

PORT F PORT G
INTERNAL CLOCK GENERATOR (ICG) LOW-POWER OSCILLATOR
DEDICATED SERIAL PERIPHERAL INTERFACE MODULE (SPI)

PORT E

VDDAD VSSAD

4-CHANNEL TIMER/PWM

PORT D
SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2)

See Note 1.

VDD VSS

VOLTAGE REGULATOR

Notes 1. All Port F and Port G signals are present on the MCU, but only the signals used by the MC1321x are designated. For lowest power operation, all unused I/O should be programmed as outputs during initialization. 2. Timer channels are limited as noted due to use of Port D I/O for internal signals.
PTG2/EXTAL PTG1/XTAL PTG0/BKGD/MS
Figure 15. MCU Block Diagram (HCS08, Version A)
MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 25

MCU Modes of Operation

The MCU has multiple operational modes to facilitate maximum system performance while also providing low-power modes. In the MC1321x, the MCU can use the following modes: Run Wait Stop2 Stop3
NOTE The MCU can also be programmed for Stop1 mode, but this mode IS NOT USABLE. The reset to the modem function is controlled by an MCU GPIO and the GPIO state must be maintained during the MCU stop condition. Stop1 mode does not control I/O states as required during modem power down condition. To attain specified Stop2 and Stop3 currents, all unused port signals must be programmed to a known state (recommended as outputs in the low state)

5.7.6.2

IIC Modes of Operation
The IIC functions the same in normal and monitor modes. A brief description of the IIC in the various MCU modes is given here. Run mode This is the basic mode of operation. To conserve power in this mode, disable the module. Wait mode The module will continue to operate while the MCU is in wait mode and can provide a wake-up interrupt. Stop mode The IIC is inactive in Stop3 Mode for reduced power consumption. The STOP instruction does not affect IIC register states. Stop1 and Stop2 will reset the register contents.
MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 41

5.7.6.3

IIC Block Diagram
Figure 24 shows a block diagram of the IIC module.
ADDRESS INTERRUPT ADDR_DECODE DATA_MUX DATA BUS

CTRL_REG

FREQ_REG

ADDR_REG

STATUS_REG

DATA_REG

INPUT SYNC START STOP ARBITRATION CONTROL CLOCK CONTROL ADDRESS COMPARE IN/OUT DATA SHIFT REGISTER
Figure 24. IIC Functional Block Diagram
Analog-to-Digital (ATD) Module
The HCS08 provides one 8-channel analog-to-digital (ATD) module. The eight ATD channels share Port B. Each channel individually can be configured for general-purpose I/O or for ATD functionality.

5.7.7.1

ATD Features
8-/10-bit resolution 14.0 sec, 10-bit single conversion time at a conversion frequency of 2 MHz Left-/right-justified result data Left-justified signed data mode Conversion complete flag or conversion complete interrupt generation Analog input multiplexer for up to eight analog input channels Single or continuous conversion mode

5.7.7.2

ATD Modes of Operation
The ATD has two modes for low power 1. Stop mode 2. Power-down mode

5.7.7.2.1

ATD Stop Mode
When the MCU goes into Stop Mode, the MCU stops the clocks and the ATD analog circuitry is turned off, placing the module into a low-power state. Once in stop mode, the ATD module aborts any single or continuous conversion in progress. Upon exiting stop mode, no conversions occur and the registers have their previous values. As long as the ATDPU bit is set prior to entering stop mode, the module is reactivated coming out of stop.

5.7.7.2.2

ATD Power Down Mode
Clearing the ATDPU bit in register ATD1C also places the ATD module in a low-power state. The ATD conversion clock is disabled and the analog circuitry is turned off, placing the module in power-down mode. (This mode does not remove power to the ATD module.) Once in power-down mode, the ATD module aborts any conversion in progress. Upon setting the ATDPU bit, the module is reactivated. During power-down mode, the ATD registers are still accessible.
NOTE The reset state of the ATDPU bit is zero. Therefore, the module is reset into the power-down state.
MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 43

5.7.7.3

ATD Block Diagram
Figure 25 shows the functional structure of the ATD module.
CONTROL INTERRUPT ADDRESS R/W DATA CONTROL AND STATUS REGISTERS DATA JUSTIFICATION SAR_REG <9:0> RESULT REGISTERS

VDD PRESCALER VSS STATUS

CTL BUSCLK CLOCK PRESCALER CONVERSION MODE CONTROL BLOCK STATE MACHINE
CONVERSION CLOCK DIGITAL ANALOG POWERDOWN VREFH VREFL VDDAD VSSAD SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER (ATD) BLOCK AD1P0 AD1P1 AD1P2 AD1P3 INPUT AD1P4 AD1P5 AD1P6 AD1P7 = INTERNAL PINS = CHIP PADS MUX CTL
Figure 25. ATD Block Diagram

CONVERSION REGISTER

Development Support
Development support systems in the include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip FLASH and other non-volatile memories. The BDC is also the primary debug interface for development and allows non-intrusive access to memory data and traditional debug features such as CPU register modify, breakpoints, and single instruction trace commands. Address and data bus signals are not available on external pins (not even in test modes). Debug is done through commands fed into the MCU via the single-wire background debug interface. The debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external access to the address and data signals. The alternate BDC clock source for HCS08 is the ICGLCLK.

5.7.8.1

Development Support Features
Features of the background debug controller (BDC) include: Single pin for mode selection and background communications BDC registers are not located in the memory map SYNC command to determine target communications rate Non-intrusive commands for memory access Active background mode commands for CPU register access GO and TRACE1 commands BACKGROUND command can wake CPU from stop or wait modes One hardware address breakpoint built into BDC Oscillator runs in stop mode, if BDC enabled COP watchdog disabled while in active background mode Features of the debug module (DBG) include: Two trigger comparators: Two address + read/write (R/W) or One full address + data + R/W Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information: Change-of-flow addresses or Event-only data Two types of breakpoints: Tag breakpoints for instruction opcodes Force breakpoints for any address access Nine trigger modes:
MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 45
A-only A OR B A then B A AND B data (full mode) A AND NOT B data (full mode) Event-only B (store data) A then event-only B (store data) Inside range (A address B) Outside range (address < A or address > B)
System Electrical Specification
This section details maximum ratings for the 71 pin LGA package and recommended operating conditions, DC characteristics, and AC characteristics for the modem, and the MCU.
SiP LGA Package Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maximum rating is not guaranteed. Stress beyond the limits specified in Table 6 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. Table 6 shows the maximum ratings for the 71 Pin LGA package.
Table 6. LGA Package Maximum Ratings
Rating Maximum Junction Temperature Storage Temperature Range Power Supply Voltage Digital Input Voltage RF Input Power Maximum Current into VDD Instantaneous Maximum Current (Single Pin Limit)1, 2, 3 Symbol TJ Tstg VBATT, VDDINT Vin Pmax IDD ID Value 125 -55 to 125 -0.3 to 3.6 -0.3 to (VDDINT + 0.3) 25 dBm mA mA Unit C C Vdc

MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 53

Num 1 2

MCU ATD Characteristics
Table 14. MCU ATD Electrical Characteristics (Operating)
Characteristic ATD supply1 ATD supply current Enabled Disabled (ATDPU = 0 or STOP) Condition Symbol VDDAD IDDADrun IDDADstop Min 1.80 Typical 0.7 0.02 Max 3.6 1.2 0.6 Unit V mA A
Differential supply voltage Differential ground voltage Reference potential, low Reference potential, high

VDDVDDAD VSSVSSAD

|VDDLT| |VSDLT |VREFL|

2.08 VDDAD

200 <0.01
VSSAD VDDAD VDDAD 300 0.02

mV mV V V

2.08V < VDDAD < 3.6V 1.80V < VDDAD < 2.08V
Reference supply current (VREFH to VREFL)
Enabled Disabled (ATDPU = 0 or STOP)

IREF IREF

Analog input voltage2

VSSAD 0.3

VDDAD + 0.3
VDDAD must be at same potential as VDD. Maximum electrical operating range, not valid conversion range.
Table 15. ATD Timing/Performance Characteristics1
Num 1 Characteristic ATD conversion clock frequency Conversion cycles (continuous convert)2 Conversion time Symbol fATDCLK Condition 2.08V < VDDAD < 3.6V 1.80V < VDDAD < 2.08V CCP Tconv 2.08V < VDDAD < 3.6V 1.80V < VDDAD < 2.08V 6 Source impedance at input3 Analog Input Voltage4 Ideal resolution (1 LSB)5 RAS VAIN RES 2.08V < VDDAD < 3.6V 1.80V < VDDAD < 2.08V 11 12
Min 0.5 0.14.0 28.0 VREFL 2.031 1.758

Typ 28

Max 2.0 1.0 <30 60.0 60.VREFH

Unit MHz

ATDCLK cycles S

k V mV

+0.5 +0.5 +0.4 +0.4 +0.05 +1.1
3.516 2.031 +1.0 +1.0 +1.0 +1.0 +5 +2.5
Differential non-linearity6 Integral non-linearity7 Zero-scale error8 Full-scale error9 Input leakage error 10 Total unadjusted error11

DNL INL EZS EFS EIL ETU

1.80V < VDDAD < 3.6V 1.80 V < VDDAD < 3.6V 1.80V < VDDAD < 3.6V 1.80V < VDDAD < 3.6V 1.80V < VDDAD < 3.6V 1.80V < VDDAD < 3.6V

LSB LSB LSB LSB LSB LSB

All ACCURACY numbers are based on processor and system being in WAIT state (very little activity and no IO switching) and that adequate low-pass filtering is present on analog input pins (filter with 0.01 F to 0.1 F capacitor between analog input and VREFL). Failure to observe these guidelines may result in system or microcontroller noise causing accuracy errors which will vary based on board layout and the type and magnitude of the activity. 2 This is the conversion time for subsequent conversions in continuous convert mode. Actual conversion time for single conversions or the first conversion in continuous mode is extended by one ATD clock cycle and 2 bus cycles due to starting the conversion and setting the CCF flag. The total conversion time in Bus Cycles for a conversion is: SC Bus Cycles = ((PRS+1)*2) * (28+1) + 2 CC Bus Cycles = ((PRS+1)*2) * (28) 3 RAS is the real portion of the impedance of the network driving the analog input pin. Values greater than this amount may not fully charge the input circuitry of the ATD resulting in accuracy error. 4 Analog input must be between V REFL and VREFH for valid conversion. Values greater than VREFH will convert to $3FF less the full scale error (EFS). 5 The resolution is the ideal step size or 1LSB = (V REFHVREFL)/Differential non-linearity is the difference between the current code width and the ideal code width (1LSB). The current code width is the difference in the transition voltages to and from the current code. 7 Integral non-linearity is the difference between the transition voltage to the current code and the adjusted ideal transition voltage for the current code. The adjusted ideal transition voltage is (Current Code1/2)*(1/((VREFH+EFS)(VREFL+EZS))). 8 Zero-scale error is the difference between the transition to the first valid code and the ideal transition to that code. The Ideal transition voltage to a given code is (Code1/2)*(1/(VREFHVREFL)). 9 Full-scale error is the difference between the transition to the last valid code and the ideal transition to that code. The ideal transition voltage to a given code is (Code1/2)*(1/(VREFHVREFL)). 10 Input leakage error is error due to input leakage across the real portion of the impedance of the network driving the analog pin. Reducing the impedance of the network reduces this error.

40 fICGDCLKma

MHz MHz MHz MHz kHz

fSelf fSelf_reset fLOR

fICGDCLKmin 5.50 8

10.500 1.5

fLOD 0.5

MHz ms ms

4*N 2*N

4*N 2*N
tLockl tLockh nUnlock nLock

counts counts

MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 57
Table 17. MCU ICG Frequency Specifications (continued) (VDDA = VDDA (min) to VDDA (max), Temperature Range = 40 to 85C Ambient)
Characteristic ICGOUT period jitter, 4, 7 measured at fICGOUT Max Long term jitter (averaged over 2 ms interval) Internal oscillator deviation from trimmed frequency VDD = 1.8 3.6 V, (constant temperature) VDD = 3.0 V 10%, 40 C to 85 C

Symbol CJitter

Typical
% fICG ACCint 0.5 0.5 0.2 % 2 2
Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop. Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked mode if it is not in the desired range. Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external mode (if an external reference exists) if it is not in the desired range. This parameter is characterized before qualification rather than 100% tested. Proper PC board layout procedures must be followed to achieve specifications. This specification applies to the period of time required for the FLL to lock after entering FLL engaged internal or external modes. If a crystal/resonator is being used as the reference, this specification assumes it is already running. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fICGOUT. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDDA and VSSA and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.
MCU AC Peripheral Characteristics
This section describes ac timing characteristics for each peripheral system.

MCU Control Timing

System SPI Timing

Table 20. SPI Timing
Table 20 describes the timing requirements for the SPI system.
Function Operating frequency Master

Symbol fop

Unit Hz
fBus/2048 tSCK 2 tLead 1/2 tLag 1/2 tWSCK 62.5 tSU 15 tHI 0 tv tHO 0 tRI tRO tFI tFO
fBus/2 = 8 MHz 2048 1024 tcyc 25 tcyc tcyc tcyc tSCK tSCK ns ns ns ns ns ns ns ns ns
SCK period Master Enable lead time Master Enable lag time Master Clock (SCK) high or low time Master Data setup time (inputs) Master Data hold time (inputs) Master Data valid (after SCK edge) Master Data hold time (outputs) Master Rise time Input Output Fall time Input Output

SS1 (OUTPUT)

SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT)

MISO (INPUT)

MSB IN2 BIT 6. 1 LSB IN

MOSI (OUTPUT) MSB OUT2

BIT 6. 1 LSB OUT
Figure 33. SPI Master Timing (CPHA = 0)
MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor 61

FLASH Specifications

This section provides details about program/erase times and program-erase endurance for the FLASH memory. Program and erase operations do not require any special power sources other than the normal VDD supply.
Table 21. FLASH Characteristics
Characteristic Supply voltage for program/erase Supply voltage for read operation 0 < fBus < 8 MHz 0 < fBus < 20 MHz Internal FCLK frequency1 Internal FCLK period (1/FCLK) Byte program time (random location)(2) Byte program time (burst Page erase time2 Mass erase time(2) mode)(2) Symbol Vprog/erase VRead 1.8 2.08 fFCLK tFcyc tprog tBurst tPage tMass 10,000 100,000 tD_ret 4000 20,000 years 3.6 3.6.67 kHz s tFcyc tFcyc tFcyc tFcyc cycles Min 2.1 Typical Max 3.6 Unit V V
Program/erase endurance3 TL to TH = 40C to + 85C T = 25C Data retention4
The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 Typical endurance for FLASH was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 4 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Non-volatile Memory.

Application Considerations
Crystal Oscillator Reference Frequency
The following sections describe crystal requirements and RF port options for end user applications.
The 802.15.4 Standard requires that several frequency tolerances be kept within 40 ppm accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. The MC1321x transceiver provides onboard crystal trim capacitors to assist in meeting this performance. The primary determining factor in meeting the 802.15.4 Standard, is the tolerance of the crystal oscillator reference frequency. A number of factors can contribute to this tolerance and a crystal specification will quantify each of them: 1. The initial (or make) tolerance of the crystal resonant frequency itself. 2. The variation of the crystal resonant frequency with temperature. 3. The variation of the crystal resonant frequency with time, also commonly known as aging. 4. The variation of the crystal resonant frequency with load capacitance, also commonly known as pulling. This is affected by: a) The external load capacitor values - initial tolerance and variation with temperature. b) The internal trim capacitor values - initial tolerance and variation with temperature. c) Stray capacitance on the crystal pin nodes - including stray on-chip capacitance, stray package capacitance and stray board capacitance; and its initial tolerance and variation with temperature. 5. Whether or not a frequency trim step will be performed in production
Crystal Oscillator Design Considerations
Freescale requires that a 16 MHz crystal with a <9 pF load capacitance is used. The MC1321x does not contain a reference divider, so 16 MHz is the only frequency that can be used. A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its performance. The crystal manufacturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal. The oscillator amplifier configuration used in the MC1321x requires two balanced load capacitors from each terminal of the crystal to ground. As such, the capacitors are seen to be in series by the crystal, so each must be <18 pF for proper loading. In the Figure 34 crystal reference schematic, the external load capacitors are shown as 6.8 pF each, used in conjunction with a crystal that requires an 8 pF load capacitance. The default internal trim capacitor value (2.4 pF) and stray capacitance total value (6.8 pF) sum up to 9.2 pF giving a total of 16 pF. The value for the stray capacitance was determined empirically assuming the default internal trim capacitor value and for a specific board layout. A different board layout may require a different external load capacitor value. The on-chip trim capability may be used to determine the closest standard value by adjusting the trim value via the SPI and observing the frequency at CLKO. Each internal trim load capacitor has a trim range of approximately 5 pF in 20 fF steps. Initial tolerance for the internal trim capacitance is approximately 15%.

Freescale Semiconductor Application Note
Document Number: AN3232 Rev. 1.1, 03/2008
Accelerometer Demonstration
With the 13213-SRB (Sensor Reference Board)

Introduction

Contents
Introduction. 1 SRB Hardware Overview. 2 Triax Demonstration Overview. 2 Triax Graphical User Interface (GUI). 3 Accelerometer Quick Start Guide. 17 Loading Embedded Applications to New Hardware Triax Demonstration Theory and Implementation 21
This application note describes how Freescales accelerometer technology is used in conjunction with the Freescale MC13213 device. The MC13213 is Freescales second-generation ZigBee platform which incorporates a low power 2.4 GHz radio frequency transceiver and an 8-bit microcontroller into a single 9x9x1 mm 71-pin LGA package. The MC13213 RF transceiver is an IEEE 802.15.4-compliant radio that operates in the 2.4 GHz ISM frequency band. The MC13213 microcontroller is based on the HCS08 Family of Microcontroller Units (MCU) and provides 60K of flash and 4KB of RAM and is also intended for use with the Freescale fully compliant 802.15.4 MAC where larger memory is required. In addition, the MC13213 can support ZigBee applications that use a stack from 3rd party vendors. For more details about the MC13213, refer to the MC13211/212/213/214 ZigBee- Compliant Platform - 2.4 GHz Low Power Transceiver for the IEEE 802.15.4 Standard plus Microcontroller Data Sheet, document number MC1321x.
Freescale Semiconductor, Inc., 2006, 2007, 2008. All rights reserved.
Using micro machining and integrated circuit technology, Freescale produces highly reliable, capacitive, acceleration sensors. Freescale's sensor technology can be used in a number of applications including medical, appliance, consumer, and industrial areas such as washing machines, gaming, LCD projectors, tracking boards, and robotics. This application note outlines how the Triax demonstration application is written and configured. Basic demonstration program operating instructions can be found in AN3230, MC1321x Accelerometer Demonstration Program Quick Start Guide.

SRB Hardware Overview

The SRB introduces users to the MC13213 2.4 GHz wireless data transceiver and low power, low cost 8-bit MCU integrated into a single package. The SRB includes a USB port configured as a virtual communications port, background debug module (BDM) for in-circuit hardware debug and programming, switches, LEDs, 3-axis accelerometers and a buzzer. This provides users with a small, low-cost development platform for establishing wireless data networks. The SRB is a 2 inch by 3 inch reference board that can be configured as a network node that contains the MC13213 transceiver/MCU System in a Package (SiP), a 16 MHz crystal, and a printed circuit antenna. Also included is a Freescale MMA7260QR2 3-axis accelerometer that has four g-force settings: +/- 1.5 +/- 2.0 +/- 4.0 +/- 6.0 The accelerometer also has a power saving enable pin. See the MMA7260Q Data Sheet for more details. Four switches and four LEDs are available for application and user interaction. The SRB derives its power from either the USB port or a 2.1 mm power connector that allows an input supply voltage range of 5 to 9 VDC. For a more in-depth description of the SRB, refer to the MC13213-EVK User's Guide (MC13213EVKUG).
Triax Demonstration Overview
The Triax demonstration is a collection of hardware and software that contains the following: Two SRBs (one SRB used as a PC_Radio Board and the other used as an Accelerometer Board) A USB cable to provide serial communication between the PC and the PC_Radio application running on the PC_Radio Board A power supply for the Accelerometer application running on the Accelerometer Board The standalone Triax Software PC application The embedded application that runs on both the PC_Radio Board and the Accelerometer Board A Serial Command Protocol that is implemented on both the Triax Software PC application and the PC_Radio Board An RF command set that communicates between the Accelerometer Board and the PC_Radio Board over-the-air using the Simplified Media Access Controller (SMAC)
Accelerometer Demonstration Application Note, Rev. 1.Freescale Semiconductor
NOTE ANSI C Source code is provided for the embedded applications so users are able to see how a basic SMAC application is written and debugged. Figure 1 shows the basic functional blocks of the Accelerometer Demonstration and serves as a guide that describes how all of the blocks communicate to build a working Accelerometer Demonstration application.

T ia p r xA p ( C P )

P Rd Ap C a io p ( 31- R) 3S B
A c le o e r c e r m te ( 31- R) 3S B
R c m a ds t fo R d F o m n e r a io T eS r l C m a dPo c l h e ia o m n r to o C m u ic tio o e th a o m n a n v r e ir R n in o e th U Bc n e tio un g vr e S onc n Figure 1. General Triax Demonstration System Overview
NOTE It is important to understand the names and functions of all the devices shown in Figure 1 because applications and demonstration described later in this note refer to their meaning.
Triax Graphical User Interface (GUI)
The Triax demonstration GUI shown in Figure 2 was built to show wireless sensor examples that use the on-board accelerometer on the SRBs. The Triax GUI is a collection of applets that show some basic accelerometer applications. Two different types of applets are available: Table 1 lists a set of applets that are PC-based and require the PC_Radio board to be connected to the PC for graphical output Table 2 lists a set of applets that are embedded, standalone applications that do not require connection to a PC
Table 1. Accelerometer Applications That Require a PC Connection
Applet Name Tilt Description Shows analogue gauges for X, Y, and Z axes applications.
PDA Scrolling Provides a virtual PDA that shows menu scrolling via X axis tilting. Digitally Filtered Tilt Shows X and Y axis, XY line plots as well as a scrolling histrogram of the X and Y axis data.
Shipping and Provides a log of X, Y, and Z axes movement over a specified accelerometer threshold in the X, Y, and Z axes. Handling Also provides an indicator that shows if the SRB has been turned upside down. The Shipping and Handling applet simulates a shipping acceleration monitor for tracking sensitive packages.
Accelerometer Demonstration Application Note, Rev. 1.1 Freescale Semiconductor 3
Applet Name Raw Data XYZ Scope Load Imbalance Description Shows the X,Y, and Z axes raw A/D data, the interpolated voltage, as well as the associated acceleration reading measured in gs. Shows either a 2-dimensional projection of the current X and Y axis readings or a 3-dimensional projection of the X, Y, and Z axes. A running chart of the X, Y, and Z axes readings on a traditional scope background. Load imbalance shows the lateral movement in the X and Y plane and determines if an unbalanced condition exists in a simulated washing machine application.

Table 2. Standalone Accelerometer Applications
Application Name PC_Radio Accel Freefall Application Number 3 Description The application that communicates with the PC GUI. The remote application that communicates to the PC_Radio. Detects when the Z axis accelerometer is measuring approximately 0gs. If a freefall is detected, the accelerometer packet buzzer is turned on and a packet is sent from the Accelerometer application on the Accelerometer board to the PC_Radio application on the PC_Radio board. When the PC_Radio board receives the freefall indication from the Accelerometer Board, the PC_Radio boards buzzer and LED4 are turned on. Detects movement in any of the X, Y, or Z axes. On movement, the following occurs on the Accelerometer Board: For movement detected in the X axis, LED1 blinks once and the buzzer chirps once. For movement detected in the Y axis LED1 blinks twice and the buzzer chirps twice. For movement detected in the Z axis, LED1 blinks three times and the buzzer chirps three times. On movement in any axis, the Accelerometer Board sends a data packet to the PC_Radio Board and the following occurs on the PC_Radio Board: LED4 blinks once and the buzzer chirps once to indicate X axis movement. LED4 blinks twice and the buzzer chirps twice to indicate Y axis movement. LED4 blinks three times and the buzzer chirps three times to indicate Z axis movement. If the Accelerometer Board is tilted more than 15 degrees off of the default center position, the buzzer is turned on and a data packet is sent to the PC_Radio Board which will then turn on its buzzer and LED4. The Battery Saver application shows how an application can take advantage of an accelerometer being used as a power saving component on a battery operated board. The Accelerometer Board simulates a board that is powered up by turning on its buzzer. When the Accelerometer Board is not moved for at least 5 seconds, the board simulates powering down by turning off its buzzer. Once the Accelerometer Board detects movement, the board simulates a power up and the buzzer is again turned on. This is a good demonstration for a remote control board.

Shock Detection

Anti-Theft

Battery Save

Figure 2. Triax Main Window
NOTE For optimal viewing, the display settings should be set to 96 DPI and the resolution set to 1280x1024.

Sensor Data View

To accurately map the output of the MMA7260QR2 accelerometer to the Raw Data applet in the Triax application while the SRB is laying flat, the raw values should read approximately 0,0 for the X and Y axes. This is because the SRB is not moving in either axis. However, the Z axis should read approximately 1 because gravity is pushing down on the device at approximately 1g. If a user were to stand still while holding the SRB flat (component side up) gravity would be pushing down on the accelerometer and the user should see the Z axis value at approximately 1g. Users can turn the SRB upside down (component side down) and the accelerometer Z axis value should be approximately -1g. Figure 3 shows the axes orientations.

Accelerometer Demonstration Application Note, Rev. 1.1 Freescale Semiconductor 5
Figure 3. SRB X, Y, and Z Axes Orientation
The sensor data view displays the raw data being sent from the accelerometers after the analog data from each accelerometer has been sampled by the 10-bit A/D converter in the MCU and converted to the corresponding digital value. The application then displays the X, Y, and Z accelerometer outputs in the following three formats: Volts 10-bit A/D readings (0-255) Each axis value converted into g's This data is displayed as shown in Figure 4.
Figure 4. Raw Data Demonstration Application
NOTE To improve accuracy of the accelerometer readings, refer to Section 4.9, Setting Up the Calibration Application.
XYZ Demonstration Application
The XYZ Demonstration application can be used for a gaming board application such as a race car game. Instead of using buttons and joysticks, the application uses the sensors and relative location to move the car based on the motion of the controller. The only buttons required for the board are the accelerator and the brake. The XYZ Demonstration application displays the location of the PC_Radio board based on the movement of the Accelerometer board. The boxes on the display represent the X, Y, and Z axes. The XYZ Demonstration application uses the raw data sent from the accelerometers and processed by the MCU. It uses the converted data to move to the corresponding location on the display as shown in Figure 5 (2-D) and Figure 6 (3-D).
Figure 5. XYZ Application (2-D)
Figure 6. XYZ Application (3-D)
Accelerometer Demonstration Application Note, Rev. 1.1 Freescale Semiconductor 7

Tilt Module

The Tilt Module translates the g readings of each axis to an angle of rotation. It displays the current physical angle of the transmitter board on the X, Y, and Z axes as shown in Figure 7. Use cases could include medical applications that incorporate a tilt range in physical therapy boards or medical equipment monitoring. In these cases, the accelerometers could be used to ensure that the equipment is used properly. For example, wrist mounted heartbeat monitors will obtain the most accurate measurement if the blood pressure sensing board is at the same elevation as the heart. By using an accelerometer to measure the angle of the arm, the monitor can guide users to the correct arm position before taking the measurement. The accuracy and repeatability of the blood pressure measurement is greatly increased by using the tilt information to tell users exactly where to position their arm. In addition, the accelerometer would be constantly sensing motion and position and be able to stop a measurement if a user's arm shifts out of the proper position. Through software, the monitor would be able to monitor the patients arm for movement, identify the angle of the patients arm, and determine if the angle of the patients arm has changed.

Figure 7. Tilt Module

Shipping and Handling Application
The Shipping and Handling application can record shock levels experienced during the transportation of fragile products. This information would allow shipping and handling companies to track incidents during package shipment. If the company were accused of mistreating a package, the company can view the log of the Shipping and Handling Application to verify if the product was mistreated or not. The Shipping and Handling application uses the low-g accelerometers to detect shock and on which axis the shock occurred. As shown in Figure 8, this application time stamps every time a predetermined shock threshold is violated or when the accelerometer is turned upside down.
Figure 8. Shipping and Handling Application
Accelerometer Demonstration Application Note, Rev. 1.1 Freescale Semiconductor 9
Load Imbalance Application
The Load Imbalance application simulates the imbalance that can occur in a washing machine. The Load Imbalance application displays the movement of the washing machine and calculates the Rotations Per Minute (RPM) and deflection of the washing machine. The graph displays the X and Y axes accelerometer data and shows the center of the orbit denoted by a green + symbol as shown in Figure 9. The application then calculates the RPM and the diameter of the deflection. If the diameter of the deflection is greater than 0.5 inches, then a simulated unbalanced condition is present and the data points are drawn in red. If a simulated unbalanced condition is not present, then the data points are drawn in blue.
Figure 9. Load Imbalance Application
PDA Scrolling Application
The PDA Scrolling application provides users a unique method of selecting menu items in a PDA. An accelerometer can be integrated into a hand-held device, such as a PDA with a GUI interface, that can be controlled by the angle of the hand-held device itself. By tilting the hand-held device front to back or back to front, users could make menu selections and operate their device with only one hand. PDA menu item selection item is in the X axis direction. By tilting the SRB front to back or back to front, users can change the highlighted item in the PDA menu as shown in Figure 10.
Figure 10. Triax PDA Scroll Application
Accelerometer Demonstration Application Note, Rev. 1.1 Freescale Semiconductor 11

Digitally Filtered Tilt

The Digitally Filtered Tilt application operates in the X and Y axes and has two views within the applet. Figure 11 shows the scope view which shows the X and Y axes readings over the last 500 samples in raw format.

Figure 11. Triax Digitally Filtered Tilt (Raw Format)
Figure 12 displays the moving average over the last 100 samples in the X and Y axes. Where appropriate, it may be advantageous for an application to do post processing on a PC rather than an embedded device. However, PC post processing can make the over-the-air packets larger and more frequent which uses more power and renders the channel active if the application is busy. If more preprocessing is done at the sensor, then the network may be less impacted to allow better node density, throughput, and more efficient power usage. To reduce RF traffic from the accelerometer to the PC_Radio embedded applications, the Accelerometer application only updates the PC_Radio when the X, Y, and Z axes readings have deviated from the previous values. Application choices can affect the way a wireless system performs.
Figure 12. Triax Digitally Filtered Tilt (XY Scope View)
Figure 13 displays the Digitally Filtered Tilt XY Filtered view with a 100 point moving average of the X and Y axes readings.
Figure 13. Triax Digitally Filtered Tilt (Moving Average)
Accelerometer Demonstration Application Note, Rev. 1.1 Freescale Semiconductor 13

Standalone Applications

The embedded applications described in this section do not require a PC and run on both the PC_Radio Board and Accelerometer Board. The status and functionality are monitored using the LEDs on the boards.
Setting Up the Freefall Application
1. Press the Reset button once on the PC_Radio Board. (Out of reset the PC Application is running.) 2. Press the Reset button once on the Accelerometer Board. 3. Press SW1 twice on the Accelerometer Board, pausing between each button press until LED3 and LED4 are lit. LED3 and LED4 indicate that Application Three (Freefall) is running. Pick up the Accelerometer Board and while holding on to the board, perform a dropping motion to simulate a freefall. A buzzer sounds on the Accelerometer Board and sends a packet to the PC_Radio Board to indicate a freefall. The PC_Radio Board then sounds its buzzer and sets LED4.
Setting up the Shock Detection Application
1. Press the Reset button once on the PC_Radio Board. (Out of reset the PC application is running.) 2. Press the Reset button once on the Accelerometer Board. 3. Press SW1 three times on the Accelerometer Board, pausing between each button press until LED2 is lit. LED2 indicates that Application Four (Shock Detection) is running. 4. When moved in the X direction, the following occurs: a) Accelerometer Board blinks LED1 once, sounds its buzzer once, then sends a packet to the PC_Radio Board. b) The PC_Radio Board blinks LED4 once and sounds its buzzer once. 5. When moved in the Y direction, the following occurs: a) Accelerometer Board blinks LED1 twice, sounds its buzzer twice, then sends a packet to the PC_Radio Board. b) The PC_Radio Board blinks LED4 twice and sounds its buzzer twice. 6. When moved in the Z direction, the following occurs: c) Accelerometer Board blinks LED1 three times, sounds its buzzer three times, then sends a packet to the PC_Radio Board. d) The PC_Radio Board blinks LED4 three times and sounds its buzzer three times.

Setting Up the Anti Theft Alarm Application
1. Press the Reset button once on the PC_Radio Board. (Out of reset the PC application is running.) 2. Press the Reset button once on the Accelerometer Board. 3. Press SW1 four times on the Accelerometer Board, pausing between each button press until LED2 and LED4 are lit. LED2 and LED4 indicate that Application Five (Anti Theft Alarm) is running. 4. If the Accelerometer Board is tilted 15 degrees past nominal, the buzzer sounds on both the PC_Radio and the Accelerometer Board.
Setting Up the Battery Saver Application
1. Press the Reset button once on the PC_Radio Board. (Out of reset the PC application is running.) 2. Press the Reset button once on the Accelerometer Board. 3. Press SW1 five times on the Accelerometer Board, pausing between each button press until LED2 and LED3 are lit. LED2 and LED3 indicate that Application Six (Battery Saver) is running. 4. If the Accelerometer Board is not moved for more than 5 seconds, a packet is sent to the PC_Radio Board and its buzzer and LED4 are turned off. Once the Accelerometer Board is moved again, the PC_Radio Board turns on its buzzer and sets LED4.
Setting Up the Calibration Application
In order to verify and visualize the calibration procedure, the Triax.exe PC GUI must be running, but it is not required. 1. Press the Reset button once on the PC_Radio Board. (Out of reset, the PC application is running.) 2. Press the Reset button once on the Accelerometer Board. 3. Place the Accelerometer Board on a flat surface (component side up). 4. Press SW1 once on the Accelerometer Board to advance the application to the Accelerometer Mode (Application Two). LED3 momentarily lights to indicate that Application Two is running. The Accelerometer Board sends out a ping packet every two (2) seconds and updates the data on the XYZ Demo PC application each time the board is moved. 5. If the data points for the X, Y, and Z axes shown on the PC GUI are not near the origin of the graph, then continue to Step 6. 6. Press SW4 once on the Accelerometer Board until all LEDs are lit. This shows that the calibration is being performed. 7. Verify that the Accelerometer Board is calibrated by viewing the X, Y, and Z axes on the PC GUI. The squares on the display should be approximately at axis point 0,0. If the calibration is still incorrect, repeat the calibration process until the data points are nominally at axis point 0,0. 8. Exit the application in the GUI and press the Reset button once on both boards. Press SW1 once on the Accelerometer Board to return to main application functionality.

Changing the Channel

In there is an interference issue, the RF channel can be changed by pressing SW2 on both the PC_Radio and the Accelerometer Board. Only four (4) frequencies are available: 2405 GHz 2430 GHz 2455 GHz 2480 GHz For example, out of reset, LED4 is set to indicate that the first channel (2.405 GHz) is being used. To change channels, press SW2 on the Accelerometer Board. The buzzer chirps and LED3 is set to indicate
Accelerometer Demonstration Application Note, Rev. 1.1 Freescale Semiconductor 15
that the second channel (2.430 GHz) is now being used. Press SW2 on the PC_Radio board which will set LED3 and thus match channels with the Accelerometer Board. The PC_Radio and the Accelerometer Boards are required to be on the same channel to work correctly. If communication problems exist, it is possible that one of the boards is on a different channel. Reset both boards to ensure that both are on the first channel (2.405 GHz), or push button SW2 until both boards LEDs match. NOTE There is no reason to change channels unless the system encounters an interference issue or users want to simultaneously run multiple demonstrations.
Changing the Application Number
To switch between applications, press SW1 once on the Accelerometer Board. The buzzer chirps and the LEDs momentarily display the current application number on the LEDs. For example, if the Accelerometer Board is running Application One (default) and SW1 is pressed, the buzzer on the Accelerometer Board chirps and the LEDs show that Application Two is running by setting the LEDs as follows: LED1 OFF LED2 OFF LED3 ON LED4 OFF To switch from Application Two to Application Three press SW1 again. The buzzer on the Accelerometer Board chirps and the LEDs are set as follows: LED1 OFF LED2 OFF LED3 ON LED4 ON
This process continues until users reach Application Six. The application then rolls back over to Application 1 and the process continues. No changes are required to the PC_Radio to switch between applications.
Accelerometer Quick Start Guide
AN3230, Accelerometer Demonstration Quick Start Guide, contains the start up procedures and assumes that one SRB has been programmed with the appropriate PC_Radio code and another SRB has been Flashed with the Accelerometer code. AN3230 also contains the default start up procedures for the Triax Demonstration software. NOTE If the Accelerometer Demonstration behavior becomes erratic when using batteries as the SRB power source, replace the batteries.
Loading Embedded Applications to New Hardware
When using the procedure described in this section, it is assumed that either no code was Flashed to the SRBs or that the code was altered and then Flashed to the SRBs.
Setting Up the SRBs for Programming
1. To program the SRB, users must have a P&E Background Debug Module (BDM) Multilink cable. The P&E BDM Multilink cable is used with CodeWarrior Development Studio for the HCS08 to program the MCU and is available from Freescale. The red lead of the BDM cable must align to pin 1 of J101. If using the parallel port version of the BDM cable, the BDM pod should be powered with a 2-5 VDC, negative center contact power supply or the SRB should be powered by a power supply through J106. The battery is not capable of sourcing the current required by the parallel BDM pod during programming. 2. Connect a 5 - 9 VDC power supply to the SRB power supply connector. If using the P&E BDM-Multilink cable the following should occur: The blue LED on the P&E Multilink turns on if the connection to the PC is functioning. The yellow LED on the P&E Multilink turns on if the cable is properly connected to the target.

Accelerometer Demonstration Application Note, Rev. 1.1 Freescale Semiconductor 17

Programming the SRBs

1. Select CodeWarrior and open the Accelerometer V3.mcp file. 2. Select SRB from the drop down menu in the project.
Figure 14. Loading the SRB Accelerometer Embedded Application from CodeWarrior
3. To choose debug, select one these two options: a) Select the Project/Debug button.

5. 6. 7.

b) Press Ctrl + F5. If the debug window is unable to make a connection, ensure that the following options are set: a) LPT1 Parallel Port 1(Address $0378) is selected in the drop down menu of the Connection Port of the personal computer. b) HCS08 Processor Autodetect is selected in the drop down menu of the CPU type. c) Then click on the Reset and Retry buttons. To run the program on the SRB, click on the green arrow on the toolbar. Close the Debug window and detach the P&E BDM Multilink cable from the SRB. To program the next SRB, repeat the steps shown in Section 6.1, Setting Up the SRBs for Programming.

PC_Radio Application

1. Apply power to the SRB being used as the PC_Radio Board. This can be accomplished by either connecting the included 9 VDC power supply to the 2.1mm power supply connector, the USB cable from the PC to the PC-Radio Board, or by inserting batteries in the PC_Radio Board. The following list shows the advantages of each connection: Batteries are truly portable, but without a USB connection only the standalone applications can run. Using the USB connection means that both the DC power supply and the UART connection are in one cable so all of the applications can run. Using the DC power supply along with the USB connection means no current draw through the USB bus. Not drawing current through the USB bus is beneficial if the system is running on a non-powered USB hub. 2. After connecting power to the PC_Radio Board with either the batteries, USB cable, or the DC power supply, set the Power Switch (S100) to the ON position. 3. Press the Reset button once on the PC_Radio Board. The PC_Radio Board is now in receive mode.
Accelerometer Application
1. Connect power to the SRB being used as the Accelerometer Board. The same power options exist for the Accelerometer Board as the PC_Radio board. 2. After connecting power to the Accelerometer Board with either the batteries, USB cable, or the DC power supply, set the Power Switch (S100) to the ON position. 3. Press the Reset and SW1 buttons once. LED3 momentarily lights to indicate that the Accelerometer Application is now running on the Accelerometer Board. 4. The Accelerometer Board sends a ping packet to the PC_Radio Board every two (2) seconds as indicated by LED2. 5. The Accelerometer Board detects when the SRB is moved and quickly toggles LED1 and sends a packet to the PC_Radio Board with an updated reading.

Verifying Accelerometer Application Operation
To verify if the Accelerometer application is running on the Accelerometer Board, monitor the LEDs as follows: Watch LED2 on the Accelerometer Board. LED2 will blink every two (2) seconds to indicate each time it sends a ping packet to the PC_Radio Board Watch LED1 on the Accelerometer Board. LED1 will blink every time the Accelerometer Board is moved. Each time the Accelerometer Board is moved, it sends a data packet to the PC_Radio Board that tells the PC_Radio Board that the position and or orientation of the Accelerometer Board has changed
Accelerometer Demonstration Application Note, Rev. 1.1 Freescale Semiconductor 19
Verifying PC_Radio Application Operation
To verify if the PC_Radio Application is running on the PC_Radio Board, monitor the LEDs as follows: Watch LED1 on the PC_Radio Board. LED1 activity indicates physical movement of the Accelerometer Board Watch LED2 on the PC_Radio Board. LED2 activity indicates ping packets sent from the Accelerometer Board

PC Setup

1. If the Evaluation Kit tools are already installed, then users can run the Triax software by navigating to the link using the Start menu. 2. From Windows, select Start->Programs->Freescale BeeKit->Triax->Triax. a) If the Triax application does not exist, go to Step 3 to install it. If users do not have a CD, download the BeeKit installer from www.freescale.com/zigbee b) If the application is in the Start Menu, go to Step 6. 3. To run only the Triax application, insert the CD supplied with the kit into the PC CD-ROM drive. 4. If autorun is not enabled on the PC, browse to the CD-Drive and execute the BeeKitSetup.exe file. 5. Once the BeeKit installer launches, follow the steps as directed to install the Triax PC application. 6. The Triax application is set up to run on COM ports 1-10. To check which COM port is being used by the USB, perform the following tasks: a) Open the System Properties window by clicking on Start->Settings->Control Panel->System. b) Select the Hardware tab, and click the Device Manager button. The Device Manager window appears as shown in Figure 15. c) Scroll to the Ports label and expand the tree by clicking the + sign to show the COM ports in the system. d) The COM Port selected by the system is titled Freescale ZigBee/802.15.4 MAC COM Device (COM5) as shown in Figure 15.

Figure 15. COM Port Determination in Device Manager
7. If the COM port chosen for Freescale Zigbee/802.15.4 MAC COM Device is not a port within Ports 1-10, then perform the following tasks: a) Double click on Freescale Zigbee/802.15.4 MAC COM Device in the Device Manager window and the Properties window will appear. b) Select the Port Settings tab and then click the Advanced button. c) Go to the Com Port Number drop down menu and select a COM port between 1-10 that is not in use.

Viewing Data

The data being sent from the Accelerometer Board can be viewed in three formats using the Raw Data application. See AN3231, MC1320x/MC1321x Demonstration Operation, Running the Basic Packet Error Rate, Wireless UART, Accelerometer, Range, Test Mode, and Lighting Demonstration Applications for more information about the Raw Data application. The Raw Data application presents the raw data sent from the accelerometers and processed by the MCU as follows: X, Y, and Z axes accelerometer output in volts 8-bit A/D readings (0-255) The output of each axes converted to g's. NOTE If the Accelerometer Demonstration behavior becomes erratic when using batteries as the SRB power source, replace the batteries.
Triax Demonstration Theory and Implementation

Serial Command Protocol

This section highlights the basic serial commands sent between the Triax application and the embedded PC_Radio application.
Table 3. Serial Interface Between PC_Radio and Triax Applications
PC Generates R V K k C rsp with k + 6 cal bytes c Accelerometer Response N xNyNzN Description Starts the handshake to show a valid serial connection PC asks for the current accelerometer reading PC sends cal string (Not Yet Implemented) PC asks for current cal values (Not Yet Implemented) PC asks PC_Radio for current Channel (Not Yet Implemented)
Accelerometer Demonstration Application Note, Rev. 1.1 Freescale Semiconductor 21

RF Command Interface

Table 4 shows the over-the-air packet format for all of the embedded applications. Currently, the PC_Radio Board is always listening and does not perform direct communication back to the Accelerometer Board, but this feature may be added at a later time.
Table 4. RF commands sent by the Accelerometer App to the PC_Radio
Name Ping Packet Length 11 Format Description The Accelerometer application sends a periodic ping to ensure that communication between the Accelerometer application and the PC_Radio application is still present. 'P' gi8AppStatus options; P ping gi8App Status Current Application number Options For example, allows the accelerometer to turn the buzzer on and off.

gu16msTimer (high byte); gu16msTimers Makes the PC_Radio application aware of the Accelerometer gu16msTimer(low byte); applications timebase sCalValues.NxOff; sCalValues.NxMax; sCalValues.NyOff; sCalValues.NyMax; sCalValues.NzOff; sCalValues.NzMax; Event Packet 2 gi8AppStatus; options Cal Values are sent periodically in the event that they have to change.
The Event Packet is Application Number Specific. The gi8AppStatus tells the PC_Radio which application number is sending the event. The options format defines which event is occurring.
Accelerometer Demonstration Application Note, Rev. 1.1 Freescale Semiconductor 23
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