means pin 4 is held below the reference level of pin 5 until the mains supply is interrupted or the set is switched off at which time pin 4 rises above pin 5 and the output pin 2 is pulled low. This low is sensed by the micro. In normal operation pin 2 is held high by pull up resistor R990 from the 5V supply. The protection line (pin 14) is held high under normal running conditions by R971 from the 5V supply, this high is applied to the protection line to the micro. When the protection line is pulled low the set goes into standby mode, the set can be restarted by the usual methods of bringing the set out of standby, but until the cause of the protection circuit operation is removed the set will return to its standby state. The over current for the 16V audio supply uses comparator 1, a reference voltage is set up on pin 6 by resistors R967, and R964. The voltage being compared is fed to pin 7 using the potential divider R968 and R966 which is supplied from the output side of the current sense resistor R974. Should the voltage on pin 7 fall below that of pin 6, pin 1 will be pulled low, thus pulling the protection line low via D958 putting the set into standby. Comparator 3 is used to protect against a layer short within the FBT, it will also act as protection for a short on the secondary outputs of the FBT. I903 is supplied with approximately 16V via D960 to pin 3, from this supply a reference voltage is fed to pin 9 using potential divider R972/R969, fed via Z948 supply. Pin 8 is supplied by another potential divider this time made up of three resistors R973/R970 and R760 samples the current flowing through Q752, should this increase, the voltage drop across R760 will increase and raise the voltage of pin 8, when it exceeds pin 9, pin 14 will be pulled low, putting the set into standby. Comparator 4 is used for EHT/over voltage protection, as all the FBT secondary voltages are proportional, the 200V supply to the CRT base is used to generate the voltage to be used in comparison, this is done by using a potential divider made up of R718, R749 and R719. Z708 monitors the voltage at the junction of R718 and R749, if this exceeds 36V, the Zener diode conducts, applying a high on pin 10 of I903, this is compared with the reference voltage on pin 11, which also uses the 2.5V set up by I905. When pin 10 is higher than 2.5V, pin 13 is pulled low, in turn pulling the protection line low via D957, putting the set into standby. The LT lines are given protection using diodes D931, D932 and D930, these are connected in reverse bias from the prot sense line to the 8V and 5V. The +5V standby link is protected by D986, pulling the reference Z950 low if a short is seen on the output of 2
I952. The +16V phono out has a diode back to I903 pin 5 in case of short. If the +B or audio supply lines become short circuit to ground before the protection on the secondary of the power supply, the primary over current protection (I900 pin 3) will operate, turning off the drive output from I900 pin 6. A latch circuit Q955/R998/RP01/C964, will operate to turn the power supply into standby (under fault condition) if the software fails to act on I903 pin 14 low. Delay before latch set by C964/R994. The +B is given protection from overvoltage via Z907, Z907 goes short circuit if the +B voltage rises above 180V DC.

The tuner U100, is a frequency synthesis type with an unbalanced input and IF of 38.9MHz, powered from the +5V rail while the tuning voltage is supplied by the +33V rail, supplied from the horizontal deflection circuit. Direct frequency access, channel selection, AGC and AFC functions are controlled via 2 the I C bus. AGC, AFC and Offset controls may be selected by entering the service menu and selecting the tuner option. Pin 1, AGC is taken from pin 62 of TDA9320/9321 (I200). The balanced IF output is taken from pins 10 and 11 arriving at both inputs of the vision and sound SAW filters (pins 1 and 2). The outputs from X200 5
and X202 (pins 4 and 5 respectively) pass through to pins 2 and 3 and pins 63 and 64 of I200, where they are demodulated.

RGB PROCESSOR (TDA9330)

VERTICAL DEFLECTION AND GEOMETRY CONTROLS
The drive circuit for the vertical and E-W deflection circuits are generated by means of a vertical divider which gets its clock from the line oscillator. The divider is synchronised by the incoming vertical pulse generated by the input processor (50Hz models) or the feature box. The vertical drive is realised by means of a differential output current. The outputs (100Hz/progressive scan models) must be DC coupled to the vertical output stage. The vertical 2 geometry can be adjusted by I C control via the service menu. 1.8.2 HORIZONTAL SYNCHRONISATION AND DRIVE CIRCUIT The horizontal drive signal is obtained from an internal VCO which is running at a frequency of 13.75MHz. This oscillator is stabilised to this frequency by means of a resonant oscillator 12MHz. The internal VCO is synchronised to the incoming horizontal HD pulse by means of a PLL with an internal time constant. The horizontal drive signal generated by means of a second control loop which compares the phase of the reference signal from the internal VCO with the flyback pulse. The time constant loop is internal. The IC has a dynamic horizontal phase correction input which can be used to compensate phase shifts which are caused by beam current variations. Additional settings of the horizontal deflection which are realised via the second loop are the horizontal shift and the parallelogram correction. The horizontal drive signal is switched on and off via the so called soft-start/soft-stop procedure. This function is realised by means of a variation to the Ton of the horizontal drive pulse. For EHT generators without bleeder the IC can be set in a fixed beam current mode. In that case the picture tube capacitance is discharged with a current of about 1mA which is determined by the black current feedback loop. With the fixed beam current option activated it is still possible to have a black screen during switch-off. This can be realised by placing the vertical deflection in an overscan position.

1.11 DOLBY DECODER (Prologic Models)
The Dolby decoding is provided by IF01 (YSS241). The signals which are sent to this device from I400 in the I2S format are: SD0 (Pin 13 Of I400) - the Left and Right channel data (before Dolby decoding) SCK (Pin 11 Of I400) - the system or bit clock WS (Pin 12 Of I400) - the word select line, provides selection between the Left and Right samples on the SDO Line. IFO1 is provided with an 18.432MHz clock via pin of I400 (SYSCLK), a reset line from pin 4 and is I C controlled. The Pro-logic signals that the device decodes are provided in I2S form at pins 40 and 41 (DACS1 and DALR). These signals are in a 32bit per channel format (The MSP4310D uses 16 bit) and must therefore pass through a conversion IC IF02. This IC also takes a Bit clock DABC from pin 36 of IF01. IF02 then provides the 16 bit pro-logic I2S channels as SDI1 and SDI2 on pins 14 and 20 of I400. I400 then passes these signals through DACs so that the Left, Right, Centre and Surround signals appear at pins 29, 28, 26 and 25 as Pre-L, Pre-R,
SM00025 Service Manual 1.12.3 MUTING The DACs IS06, IS07 and IS08 are muted via pin 34 of IS01 going low. Additional mute lines are provided for the Amplifier board on pins 41, 42 and 43 via the three way header PS08. In either case, the mute 2 lines are activated via I C commands. 1.12.4 MODES OF OPERATION Although described as the Digital Audio Decoder board, this board in fact provides audio in both the Analogue and Digital Audio modes. The following is a description of this board operation in the two different modes. ANALOGUE MODE This mode is used when either a SCART, Phono or RF signal provides the Audio source. In analogue mode, the analogue signal, be it RF or from a SCART/Phono source, is first processed by I400, the MSP3410D on the main board. This device converts the signal to 16 bit I2S format consisting of a Word Select (pin 12), Data (pin 13) and Bit Clock line (pin11). The signals arrive at PS04 on the decoder board via the 9 way lead described above. The 18.432MHz clock signal from pin 1 of the MSP3410D is connected to a two way header E28. From here it is passed via a shielded lead to PS01 on the decoder board. The signal is then passed through a buffer amplifier stage formed by QS11 and QS12 before being transformed to a 8.192MHz Clock by IS15. On the Decoder Board, Analogue mode is selected 2 by instructing IS01 via an I C command to take pin 28 of IS01 (the SPDIF select line) high. This signal is then inverted by QS01 thus pulling pin 1 of IS10 low. This Multiplexer then switches the Word Select, Data, Bit Clock and 8.192MHz clock mentioned earlier to the DSP56362 (IS01). The 8.192MHz clock is also passed to the DACs IS06, IS07 and IS08. The output of QS01 is also fed to pin 23 of the DACs, thus switching the devices to 16 bit. (leaving the device in 24 bit results in distorted sound). The DSP carries out either Stereo or Pro Logic decoding of the signal, setting the volume and Graphic Equaliser to the level selected by the user and also the channel outputs to their desired settings (i.e. if no centre has been selected in the speaker setup menu and the device is in the Pro Logic mode, 9

IS09 12C 3v3/5v Level translator And 1.024 MHz Clock buffer IS06, IS07, IS08 Digital to Analogue Converters Format line selects whether 16 or 24 bit.

12C 5v side (Main Board)

E408 Coaxial input

IS02, IS03, IS04 SRAM

IS12 EEPROM (Holds DTS Coefficients)
I408, I409, I410 Operational Amplifiers = 6dB gain Main Channels = 9.5dB gain LFE Channel
To read Phono sockets and power amplifiers
I2S Data for Centre, Front Left and Right, And rear Left and Right channels.

Denotes Amplifier Board

1.14 DEFLECTION
1.14.1 100HZ HORIZONTAL DEFLECTION STAGE The 2H output from UQ01 (the feature box) from pin 30 is fed via RZB7 to pin 24 of IZ04 TDA9330 the "HOP". The horizontal drive is then output from pin 8 is passed through an emitter follower stage (QZ18) to the gate of Q701B. A MOSFET is used to sharpen the switching edges and reduce the temperature of the power transistor Q751. The drain of Q701B is fed from the +B via R701 and the primary of the drive transformer T702. The secondary of the transformer drives the base of the power transistor Q751, the collector of which is supplied from the +B via R751, L700 and the primary of the FBT. The emitter is connected to ground via R760 a 1Ohm 10W resistor (R760 should be kept away from Q751 heatsink to reduce heat transfer) which is a sense resistor for the protection circuit. The capacitive divider network C717 and C708 produce a line pulse which is sampled by Z704 and clamped by D713 and D714 this is then returned to pin 13 of IZ04. 1.14.2 50HZ HORIZONTAL DEFLECTION STAGE The HA OUT from pin 60 of I200 TDA9320 the "HIP" is fed via RZB7 to pin 24 of IZ04 TDA9330 the "HOP". The horizontal drive is then output from pin 8 is fed to the base of Q701. The collector of Q701 is supplied from the +B via R701 and the primary of the drive transformer T702. The secondary of T702 drives the base of the power transistor Q751. The collector of Q751 is supplied from the +B via R751, L700 and the primary of the FBT. The emitter is connected to ground via R760 which is a sense resistor for the protection circuit. The capacitive divider network C717 and C708 produce a line pulse which is sampled by Z704 and clamped by D713 and D714 this is then returned to pin 13 of IZ04. 1.14.3 VERTICAL DEFLECTION On the 50Hz the vertical drive pulse come from pin 61 (VA OUT) of I200 and on the 100Hz it comes from pin 31 of UQ01. This is fed via RZB8 to pin 23 of IZ04. The vertical sawtooth waveforms are output from pins 1 and 2 of IZ04 and fed to pins 11 and 12 14

SM00025 Service Manual Scart Disable Output Pin 39 is used to route the AV/diagnostic link between pin 10 of AV1 or pin 10 of AV2 Mute Output Pin 40 is the mute output for the on-board audio amplifiers. This output is HIGH when the amplifiers are in the mute condition (e.g. Standby). If the user has chosen to use the internal speakers, then under normal operating conditions, this output will be LOW. When powering down, this output will quickly rise to mute the speakers, to prevent any unwanted popping noises from being heard. Green LED Output Pin 41 is the green LED output, which is only used on the digital chassis fitted with a DTT module. This output is high when the green led is ON. When the DTT module is in the partial standby state or when recording a digital terrestrial program, then this LED will be ON and will be mixed with the red LED to produce an amber colour. When the DTT module is connected via the telephone line and receives mail, then this LED will flash periodically to indicate this condition. When the TV first has power applied to it, then the green LED will be ON. Soon after, though, this LED should extinguish to indicate that the TV is operating correctly. NOTE: This is one of the easiest ways to check that the microcontroller is running the program code correctly in the EPROM/MTP. If the green led remains ON, then the microcontroller or EPROM/MTP has a fault preventing the code from being executed correctly. Red LED Output Pin 42 is the red LED output, which is used to indicate the standby state and when an IR command has been successfully received and decoded. When the TV is in the standby state, this output will be HIGH to ensure that the red LED is brightly lit. When the TV is not in standby, then this output will be low, but the red LED will remain dimly lit through resistor R081. When an IR command has been successfully received, then the LED will flash briefly, to inform the user that the button on the handset was pressed correctly. I C Connections Pin 23 is the I C bus data input/output for 2 transferring data between other I C peripherals/devices. This line is only connected to the EEPROM (I005) when in the standby state or 17
General Output Connections:
74HC595 Shift Register Outputs Storage-Register Clock Output (RCLK) Pin 20 of the microcontroller is connected to the rising edge (positive triggered) input (pin 12) of I006. This line is normally low when not communicating with the device or when shifting data into it. Once the full 8-bits have been shifted in, the RCLK line rises in order to latch the data to the devices outputs. EEPROM Write Enable Output Pin 22 is the E2 write enable output line, which is connected to pin 7 of the EEPROM (E2). When this output is HIGH (approx. +5V), the E2 cannot be written to (write disable) but data from the device can be read. When this output is low (0V), then data can be written to the E2. This hardware line helps to protect the E2 from inadvertent write operations, which could occur under abnormal circumstances. On/Off Output Pin 43 is the On/Off line which turns On (LOW) /Off (HIGH) the secondary supplies (+B, +16V audio rail, +8V and +5V). The standby +5V and+10V rails are unaffected when this output is HIGH (TV in the standby state). Under normal operating conditions, this output will be low when the TV is NOT in the standby condition. On/Off 2 Output Pin 29 is the On/Off 2 line which turns On (LOW) / Off (HIGH) the DTT/ASW sub-power supply. I C Disable Output Pin 33 is the I C disable output which prevents the 2 main chassis I C bus from being connected to the 2 I C bus of the microcontroller (I001) and E2 (I002). This line is normally HIGH when the TV is in the standby state. This output is inverted using the 74HC04 hex inverter IC (I004) and in connected to pins 5 and 6 of I007. In the standby condition, pins 5 and 6 of I007 (74HC4066) are low and the M.SDA and M.SCL (microcontroller) lines are disconnected 2 from the SDA and SCL (main chassis) I C lines. 2 When writing to the E2, the I C disable output is also pulled high, to ensure that successful writing of the data has occurred (e.g. to log fault diagnostics when 2 the TV fails to power-up and the main chassis I C bus is low).

SM00025 Service Manual Write Disable Connection Pin 7 is the I C write enable/disable input. When this 2 input is HIGH (+5V), all I C writes to the device are denied. When the pin is pulled low by the microcontroller (pin 22 E2RD), data can be written to the device. In this manner, inadvertent write 2 operations can prevent the I C data from being corrupted. 1.15.6 74HC595 SHIFT REGISTER (I006) 1.15.5 EEPROM (I005) The ST24C16 EEPROM, or E2 as it is commonly known, is a 16Kbit (2Kbyte) device that holds nonvolatile data when power is removed from the TV. This device can hold information for 100 programs, such as the name, frequency, standard, AV setting, speaker language setting and Teletext favourite pages. The EEPROM also holds diagnostic fault codes used to help identify previous faults with the chassis (see separate section that deals explicitly with this). The E2 also holds factory aligned parameters, such as the geometry, white balance, tuner AFC/AGC, model type, cathode level, etc. The E2 also holds the users preferential settings, such as the volume, balance, contrast, brightness, etc. Data is written to/read from the device using the 2 standard Philips I C protocols. Supply/Ground Connections Pins 8 and 4 are the +5V supply and ground (0V) connections respectively. The EEPROM is powered from the +5V standby rail so that it always has power to it, even when the TV is in standby. I C Connections Pin 5 is the I C Data line needed to transfer serial data between the microcontroller and itself. Data is changed when the clock line is low and latched on 2 the rising edge of the I C clock. Pin 6 is the I C clock line needed to synchronise the 2 I C data transfer. 9 clock pulses are needed for the 2 8-bit data and an acknowledge bit. The I C master clock originates from the microcontroller and operates at a frequency around 100KHz. Address Connections Pins 1 to 3 are the address lines used to select the 2 I C slave address of the device. On the ST24C16 device, these lines must be connected to ground in order to access the device properly.
line is HIGH. This signal must be inverted to disable the microcontrollers I C bus from the I C bus of the rest of the chassis. SCART Select Connection Pin 13 is the SCART select input from pin 39 of the microcontroller. This input is inverted and output at pin 12, which is then connected to pins 12 and 13 of the analogue switch (I007).

Pin 7 (PD4) is the velocity modulation (VM) out line. Link KZ05 connects these two together allowing the main micro to use the VM line if there is no autowidescreen micro. The main micro sends the 2 requested state of this line via the I C bus. Sync and luminance comparator connections Pin 11 (PD6) connects to the vertical sync. This signal is taken from pin 61 of the input processor I200. Pin 12 (PB0/AIN0) connects to the reference voltage. Pin 13 (PB1/AIN1) connects to the horizontal sync. This signal is taken from pin 60 of I200 the input processor TDA9320. Pin 8 (PD4) connects to the output of comparator IZ03. Pin 15 (PB3) is the least significant pin controlling the reference voltage. It is connected via RZ63. Pin 16 (PB4) is the second pin controlling the reference voltage. It is connected via RZ70. Pin 17 (PB5) is the most significant pin controlling the reference voltage. It is connected via RZ71. Other pins Pins 1, 17, 18 and 19 are used for programming the device while in circuit. These connect to connectors PZ01 and PZ07. Pins 3 and 14 are currently unused.
SM00025 Service Manual Receive an L signals by selecting program 14 via the remote control handset. Receive a signal level of +60 dBmV at 63.75MHz (CH4) by direct frequency entry under the CH option. In the tuner menu select L IF AFC and press < or > on the remote control. If the bar goes to either end then returns to centre, adjust L201 one turn and then return to step 3, continue this until the indicator bar no longer jumps back to the centre. Because the set up procedures are interactive, it is necessary to repeat all procedures from "STANDARD AFC ALIGNMENT" above until no adjustment of L201 is required. AGC ALIGNMENT To reduce the influence of circuit temperature drift, let the television warm up by leaving it operating normally for more than two minutes. Receive channel 40 (623.25MHz) at +60dBmV. Adjust AGC takeover option (Service >> Tuner) to maximum:.00 (XX) Max. AGC Voltage

2 SERVICE

BOARD ADJUSTMEMT

FOR SIGNAL

PREPARATION ADJUSTMENT +B adj. Set R982 to centre position Set screen pot T701 (FBT) fully anti-clockwise Turn on set. Adjust +B to approximately 152V. (Pre adjustment only) If flaring is observed, adjust L501 until a clean video signal is seen on the oscilloscope video out port. For Models with a flash device fitted, ensure the service information reads: FLASH: x.x instead of Code: x.x for the software version. The batch and serial number must be programmed into the EEPROM at locations: 0635-0644 inclusive using the diagnostic interface. The data is to be programmed in ASCII format. STANDARD AFC ALIGNMENT To reduce the influence of circuit temperature drift, let the television warm up by leaving it operating normally for more than two minutes. Receive a PAL I signals by selecting program 3 via the remote control handset. Receive a signal level of +60 dBmV at 623.25MHz (CH40) by direct frequency entry under the CH option. Set AFC offset (in service options) to the centre position. In the tuner menu select standard IF AFC and press either < or > on the remote control to activate the automatic AFC setting procedure. If the indicator goes either end of spectrum, then returns to the centre, adjust L201 one turn and then return to step 3, continue this until the indicator bar no longer jumps back to the centre. L AFC ALIGNMENT (for export models only) To reduce the influence of circuit temperature drift, let the television warm up by leaving it operating normally for more than two minutes. 24

RAIL 3.3V 5.1V 9V 12V +17V -17V 30V Audio (A8) Not Used Not Used Not Used Not Used 2.5A 2.5A Not Used DTT (D8) 2.7A 1.5A 400mA 10mA 2.5A 2.5A 10mA
High voltage limiter circuit jig:

R718 240K

2 470K

R749 4.7K

PROTECTION

R719 47K

ANODE/FOCUS SHORT-CIRCUIT TEST PROTECTION CIRCUIT CHECK Add a DC voltage to R760 until set trips. The DC level should be equivalent to DC level = 1.7 * (+B current peak value) 0.6 VDC R760 SET SHOULD NOT TRIP 1.6 VDC R760 SET SHOULD TRIP FINAL ANODE VOLTAGE LEVEL CHECK Check on all 100Hz models that the final anode voltage does not exceed the voltages listed below.
28 16:16:16:9 33KV 33.5KV 34KV
DTT +5V SETTING Set VR1 to approx. centre position (10K). Turn power on applying external load, see table. Adjust VR1 making sure +5.2V rail is within 0.05V. SUB-BOARD MUST BE BEAB TESTED IN A SET OR CONSOLE STAND Adjust R9055 until +17V is across C9046 at full load of 2.5A. During no load condition 17.5 to 18V should appear across C9046. HIGH VOLTAGE LIMITER CIRCUIT CHECK Mount the PCB to the set and adjust normally.
This test should be carried out in AV Mode (No signal). 2.1.3 FEATURE BOX (100HZ/PROGRESSIVE SCAN) +5V & +8V SHORT CIRCUIT CHECK USING FEATURE BOX BOARD Measure the resistance between 5V (EU11, pin1) and GND (EU11, pin3) using multi-meter. If the meter shows 62.5W 4W, The FEATURE BOX is OK. Measure the resistance between 8V (EU11, pin6) and GND (EU11, pin3) using multi-meter. If the meter shows 1.29KW 0.1KW, The FEATURE BOX is OK. 26
Receive the circle test pattern. Set the Contrast and brightness to maximum. Add R=470KW in parallel with R718 and R718A. Check that picture and sound disappear when R is added.
SM00025 Service Manual FEATURE BOX OPERATION CHECK Fit FEATURE BOX into main board. Receiving circle test pattern (PAL), check the picture quality.
Check: Horizontal line is stable (see horizontal line).

Picture Condition

Adjust control so that the centre of the picture is as in the diagram below.
Upper: Extends Lower: Shrinks Standard Upper: Shrinks Lower: Extends
White part of picture is pure white (see diagram).
Size Adjust until upper castillations disappear Adjust until both castillations disappear Adjust until lower castillations disappear
Colour bar Horizontal line Greyscale (small)
Note: The picture should be exaggerated as to create a barrel type picture at the vertical edges. The compensation to achieve this barrel picture should be 3 steps passed the straight vertical edge position. This is to compensate for the pincushion effect noticeable on OSDs. TILT PARABOLA WIDTH Allow 5 minutes warm up time before adjustment.

Check the Progressive Scan/100Hz operation by handset. Change sharpness, CTI, compression (14:9, 4:3 & zoom), noise reduction (Auto, low, mid & high) by handset. Check the total performance. Whenever digital noise appears on the picture, or mis-operation occurs, reject the feature box. Receive an NTSC signal and repeat "FEATURE BOX OPERATION CHECK" section above again.
Receive circle test pattern. Set Brightness and Contrast to nominal. The set should face North or South. AC input source should be 230V 5V 50Hz. Adjust software so that the vertical lines at the outside edges of the screen are adjusted to be roughly vertical. Adjust the software so that the (approximately) vertical lines at the sides of the screen are adjusted as vertical as the centre of the screen. Adjust the software so that the castillations at the sides of the picture are not quite visible. Reduce the brightness and contrast to make sure that the picture width has not reduced so that you can see beyond the castillations. You may have to repeat stages 6 and 7 again. Note: For all 16:9 receivers the picture should be first set up in 16:9 mode, then final adjustment for parabola and corner correction only to be carried out in 4:3 mode. 27
FINAL ALIGNMENT (by Software)

PICTURE POSITION/SHAPE

HORIZONTAL PHASE VERTICAL CENTRE VERTICAL AMPLITUDE Wait 5 minutes minimum, after switching on the mains before adjustment. Receive circle test pattern. Set Brightness and Contrast to maximum. The set should face North or South. AC input should be 230 5V 50Hz. Adjust software control (using PC / HAND SET)
SM00025 Service Manual BOW (only for N2 version TDA9330 IZ04) U CORNER L CORNER TIMING Allow 5 minutes warm up time before adjustment. Receive circle test pattern Set Brightness and Contrast to nominal. The set should face North or South. AC input source should be 230 5V 50Hz. Select SERVICE HORIZONTAL and scroll down to BOW. Adjust BOW in software menu until vertical lines across the entire screen are approximately straight and vertical. Scroll up and adjust U CORNER until vertical lines at top corners of the screen are vertical. Adjust L CORNER until vertical lines at bottom of the screen are vertical. If there is any fold over at right hand edge of the screen, increase TIMING until it disappears. Note: (U CORNER and L CORNER adjustment) Best results may be obtained when altered in conjunction with PARABOLA. 2.2.2 FOCUS ADJUSTMENT Receive circle test pattern. Receive circle test pattern. PICTURE MORE COMBFILTER by handset Adjust after Horizontal/Vertical has been adjusted. Switch the received signal to the crosshatch signal. Turn the static focus pot (middle pot) gradually clockwise starting from the full anti-clockwise position. The vertical line furthest to the right should be focused for the best result (Contrast Max, Brightness nominal). Turn the dynamic focus pot (top pot) gradually clockwise starting from the full anti-clockwise position. Focus of the horizontal line at the top of the picture for the best results (Contrast Max, Brightness nominal). Ensure the Comb Filter software option is ON using handset, watching the multi-burst section of the test card, ensuring there is no Cross Colour interference as shown.

SM00025 Service Manual Rear Left Channel Apply 1KHz, 1Vrms signal to E414 Pin 4. Check that an output of approximately 2Vrms is seen at E401 Pin 8 (White). Check that an output of approximately 9Vrms at E405 Pins 8. Disconnect supply to E418 Pin 2/ E409 Pin 16 (Rear Off) both waveforms should disappear. Supply 5V to E407 Pin 1/ E409 Pin 14 (Mute) both waveforms should disappear. Supply 5V to E409 Pin 13 (Vmute2) both waveforms should disappear. Front Right Channel Apply 1KHz, 1Vrms signal to E414 Pin 7. Check that an output of approximately 2Vrms is seen at E401 Pin 1 (Red). Disconnect supply to E418 Pin 2/ E409 Pin 16 (Rear Off) both waveforms should disappear. Supply 5V to E407 Pin 1/ E409 Pin 14 (Mute) waveform should disappear. Supply 5V to E409 Pin 13 (Vmute2) waveform should disappear. Front Left Channel Apply 1KHz, 1Vrms signal to E414 Pin 8. Check that an output of approximately 2Vrms is seen at E401 Pin 6 (White). Supply 5V to E407 Pin 1/ E409 Pin 14 (Mute) waveform should disappear. Supply 5V to E409 Pin 13 (Vmute2) waveform should disappear. Centre Channel Apply 1KHz, 1Vrms signal to E414 Pin 6. Check that an output of approximately 2Vrms is seen at E401 Pin 4 (Green). Check that an output of approximately 9Vrms at: E404 Pin 1 PTV. E403 Pin CTV. E405 Pin CTV. Disconnect supply to E418 Pin 3/ E409 Pin 17 (Centre Off) both waveforms should disappear. Supply 5V to E407 Pin 1/ E409 Pin 14 (Mute) both waveforms should disappear. Supply 5V to E409 Pin 13 (Vmute2) both waveforms should disappear. 30 Woofer Channel Apply 1KHz, 1Vrms signal to E414 Pin 5. Check that an output of approximately 2Vrms is seen at E401 Pin 3 (Blue). Check that an output of approximately 9Vrms at: E402 Pin 1 &E406 Pin 1 PTV. E411 Pin CTV. E405 Pin CTV. Disconnect supply to E418 Pin 1/ E409 Pin 15 (Woofer Off) both waveforms should disappear. Supply 5V to E407 Pin 1/ E409 Pin 14 (Mute) both waveforms should disappear. Supply 5V to E409 Pin 13 (Vmute2) both waveforms should disappear. 2.3.2 DOLBY DIGITAL DECODER BOARD

1KHz signal between 2Vrms and 2.1Vrms
At this point, it is normal that the woofer channel will show clipping. Turn the main volume down and check that you can achieve at least 3Vrms / 8.5 Vpp without clipping. Remove the input to E408 and apply the optical input from the DVD player to I407. Check the symbol Dolby D 3/2.1 appears (Press recall/info if it doesnt) Repeat the test from **). DTS Select track 15 on the DTS test DVD. Set the player for repeat play. Apply the coaxial output of the player to E408 on the audio amplifier board. ****Set the master volume control to maximum. Check the OSD indicates DTS 3/2.1. If it doesnt appear, press the recall/info button on the handset. Check for an undistorted continuous*** sine wave can be seen at the following level on all channels at the phono socket E401. 31
1KHz signal between 2Vrms and 2.1Vrms 1KHz signal between 2Vrms and 2.1Vrms 1KHz signal between 1.41Vrms and 1.5Vrms 1KHz signal between 1.4Vrms and 1.5Vrms
Put the master volume to mid way and un-mute the amplifiers via the speaker setup menu.
SHIPPING SPEC DATA SHEETS
SERVICE DATA SETTINGS - This is the data set in SERVICE mode for various models. Model No. Contrast Brightness Colour Sharpness Hue 1* C28WF523N 311 50Hz 85%* 50% 2* C32WF523N 311 50Hz 85%* 50% 3* C32WF720N - 311 85%* 50% 4* C32WF810N - 311 85%* 50% 5* D32WF815N - 311 85%* 50% 6 C36WF810N - 311 100% 50% 7 D36WF815TN - 311 100% 50% 8* CL28WF720AN 300 85%* 50% 9* CL32WF720TAN - 300 85%* 50% 10* CL32WF810AN 300 85%* 50% 11 CL36WF810AN - 300 100% 50% * Set contrast to 9 steps down from maximum. 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 65% 65% 65% 65% 65% 65% 65% 65% 65% 65% 65% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50%
Noise Reduction Auto Auto Auto Auto Auto Auto Auto Auto Auto Auto Auto
Comb Filter N/A N/A On On On On On On On On On
CTI On On On On On On On On On On On
VM On On On On On On On On On On On
White Point Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal
Black Stretch On On Off Off Off Off Off Off Off Off Off
SERVICE DATA SETTINGS - This is the data set in SERVICE mode for various models. Model No. Volume Loudness Balance LFE Mode 11 C28WF523N 311 50Hz C32WF523N 311 50Hz C32WF720N - 311 C32WF810N - 311 D32WF815N - 311 C36WF810N - 311 D36WF815TN - 311 CL28WF720AN 300 CL32WF720TAN - 300 CL32WF810AN 300 CL36WF810AN - 300 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% Off Off Off N/A N/A N/A N/A Off Off N/A N/A 50% 50% 50% N/A N/A N/A N/A 50% 50% N/A N/A N/A N/A N/A 50% 50% 50% 50% N/A N/A 50% 50% 1

3 SCHEMATIC DIAGRAMS

4 PCB LAYOUT DIAGRAMS

5 PARTS LIST

THE UPDATED PARTS LIST FOR THIS MODEL IS AVAILABLE ON ESTA
Hitachi, Ltd. Tokyo, Japan International Sales Division THE HITACHI ATAGO BUILDING, No. Nishi Shinbashi, 2 Chome, Minato- Ku, Tokyo 105-8430, Japan. Tel: HITACHI EUROPE LTD, Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA UNITED KINGDOM Tel: Fax: Email: consumer -service@hitachi-eu.com HITACHI EUROPE S.A. 364 Kifissias Ave. & 1, Delfon Str. Chalandri Athens GREECE Tel: 1-6837200 Fax: 1-6835964 Email: service.hellas@hitachi-eu.com
HITACHI EUROPE GmbH Munich Office Dornacher Strasse 3 D-85622 Feldkirchen bei Mnchen GERMANY Tel: +49-89-991 80-0 Fax: +49- 89-991 80-224 Hotline: +49-180-51 (12ct/min) Email: HSE- DUS.service@hitachi-eu.com
HITACHI EUROPE S.A. Gran Via Carlos III, 86, planta 5 Edificios Trade - Torre Este 08028 Barcelona SPAIN Tel: 2550 Fax: 3513 Email: atencion.cliente@hitachi-eu.com
HITACHI EUROPE srl Via Tommaso Gulli N.39, 20147 Milano, Italia ITALY Tel: +487861 Tel: +38073415 Servizio Clienti Fax: +48786381/2 Email: customerservice.italy@hitachi-eu.com
HITACHI Europe AB Box 77 S-Kista SWEDEN Tel: +46 (0) Fax: +46 (0) Email: csgswe@hitachi-eu.com
HITACHI EUROPE S.A.S Lyon Office B.P. 45, 69671 BRON CEDEX FRANCE Tel: 70 Fax: 99 Email: france.consommateur@hitachi-eu.com
HITACHI EUROPE LTD (Norway) AB STRANDVEIEN Lysaker NORWAY Tel: 30 Fax: 32 Email: csgnor@hitachi-eu.com
HITACH EUROPE AB Egebkgrd Egebkvej 98 DK-2850 Nrum DENMARK Tel: +Fax: +Email: csgnor@hitachi-eu.com
HITACHI EUROPE AB Neopoli / Niemenkatu 73 FIN-15140 Lahti FINLAND Tel : +Fax: +Email: csgnor@hitachi-eu.com
Hitachi Europe Ltd Bergensesteenweg Sint- Pieters-Leeuw BELGIUM Tel: +01 Fax: +00 Email: sofie.van.bom@hitachi-eu.com
HITACHI EUROPE LTD Na Sychrove 975/27 Pr aha 10 Bohdalec CZECH REPUBLIC Tel: +Fax: +Email: csgnor@hitachi-eu.com
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Model: CL28WF720AN Condition: Symptom: Intermittently No switch-on from standby
Tip: The set will not start. Intermittent Earth-problem on main board & Signal Processor PCB. Remove and resolder all yellow marked soldering. MAIN BOARD Figure 1 Main Board Solder Side
Main board A: Jumper K2 B: Jumper K465 C: Jumper K426 & K427 (x2) D: Jumper K451 E: FB45 F: Jumper K455 G: K182 (Component side, green cable to pin 1 at IZ02, Signal Processor PCB) H: C015 I: Jumper K166
J: Jumper K10 K: Jumper K151 L: Jumper L208 M: Jumper K162 (x2) N: Jumper K56 O: Jumper K223 & K348 P: Jumper K132 & K459 1: Only Components side
Figure 2 Main Board Solder Side (1)
Figure 3 Main Board Solder Side (2)

Figure 4 Feature Box MSP

Component side of main board. Figure 5 Tuner and Underside of Signal Processor PCB
Component side of main board.
SIGNAL PROCESSOR PCB Remove the Signal Processor PCB to reach the J, K, L, N points. Resolder all yellow-marked solder. Figure 6 Signal Processor PCB (Solder side)
Figure 7 Signal Processor PCB (Component side)
Q: Jumper KZ19 R: Jumper KZ20 S: Jumper KZ14 T: Jumper KZ16 (Observe the green-cable between KZ16/CZ68 & CZ34) Section: Defect: Repair: CHA T D Chassis Bad contact, connection Resoldering
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