HD44780U (LCD-II)

(Dot Matrix Liquid Crystal Display Controller/Driver)
ADE-207-272(Z) '99.9 Rev. 0.0 Description
The HD44780U dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. Since all the functions such as display RAM, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. A single HD44780U can display up to one 8-character line or two 8-character lines. The HD44780U has pin function compatibility with the HD44780S which allows the user to easily replace an LCD-II with an HD44780U. The HD44780U character generator ROM is extended to generate 8 dot character fonts and 10 dot character fonts for a total of 240 different character fonts. The low power supply (2.7V to 5.5V) of the HD44780U is suitable for any portable battery-driven product requiring low power dissipation.

Features

and dot matrix possible Low power operation support: 2.7 to 5.5V Wide range of liquid crystal display driver power 3.0 to 11V Liquid crystal drive waveform A (One line frequency AC waveform) Correspond to high speed MPU bus interface 2 MHz (when VCC = 5V) 4-bit or 8-bit MPU interface enabled 80 8-bit display RAM (80 characters max.) 9,920-bit character generator ROM for a total of 240 character fonts 208 character fonts (dot) 32 character fonts (dot)

HD44780U

64 8-bit character generator RAM 8 character fonts (dot) 4 character fonts (dot) 16-common 40-segment liquid crystal display driver Programmable duty cycles 1/8 for one line of dots with cursor 1/11 for one line of dots with cursor 1/16 for two lines of dots with cursor Wide range of instruction functions: Display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift Pin function compatibility with HD44780S Automatic reset circuit that initializes the controller/driver after power on Internal oscillator with external resistors Low power consumption

Ordering Information

Type No. HD44780UA00FS HCD44780UA00 HD44780UA00TF HD44780UA02FS HCD44780UA02 HD44780UA02TF HD44780UBxxFS HCD44780UBxx HD44780UBxxTF Note: xx: ROM code No. Package FP-80B Chip TFP-80F FP-80B Chip TFP-80F FP-80B Chip TFP-80F CGROM Japanese standard font

European standard font

Custom font

HD44780U Block Diagram

OSC1 OSC2 CL1 CL2 M CPG Instruction register (IR)

Reset circuit ACL

Timing generator

RS R/W E

MPU interface

Instruction decoder

Display data RAM (DDRAM) bits

16-bit shift register

Common signal driver

COM1 to COM16

Address counter DB4 to DB7 DB0 to DB3 Input/ output buffer

40-bit shift register

40-bit latch circuit

Segment signal driver

SEG1 to SEG40

Data register (DR)

Busy flag Character generator RAM (CGRAM) 64 bytes
LCD drive voltage selector
Character generator ROM (CGROM) 9,920 bits
Cursor and blink controller
Parallel/serial converter and attribute circuit VCC V1 V2 V3 V4 V5
HD44780U Pin Arrangement (FP-80B)
SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38
SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC1

FP-80B (Top view)

SEG39 SEG40 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DB7 DB6 DB5 DB4 DB3 DB2

OSC2 V1 V2 V3 V4 V5 CL1 CL2 VCC M D RS R/W E DB0 DB1
HD44780U Pin Arrangement (TFP-80F)
SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40
SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1

TFP-80F (Top view)

COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DB7 DB6 DB5 DB4
GND OSC1 OSC2 V1 V2 V3 V4 V5 CL1 CL2 VCC M D RS R/W E DB0 DB1 DB2 DB3

HD44780U Pad Arrangement

Chip size: 4.90 4.90 mm2
Coordinate: Pad center (m) Origin: Pad size: 80 Chip center m2 63

Type code

HCD44780U Pad Location Coordinates
Pad No. Function SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC1 OSC2 V1 V2 V3 V4 V5 CL1 CL2 VCC M D RS R/W E DB0 DB1 Coordinate X (um) Y (um) Pad No. Function DB2 DB3 DB4 DB5 DB6 DB7 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 Coordinate X (um) Y (um) 1617 2313

Pin Functions

Signal RS No. of Lines 1 I/O I Device Interfaced with MPU Function Selects registers. 0: Instruction register (for write) Busy flag: address counter (for read) 1: Data register (for write and read) Selects read or write. 0: Write 1: Read Starts data read/write. Four high order bidirectional tristate data bus pins. Used for data transfer and receive between the MPU and the HD44780U. DB7 can be used as a busy flag. Four low order bidirectional tristate data bus pins. Used for data transfer and receive between the MPU and the HD44780U. These pins are not used during 4-bit operation. Clock to latch serial data D sent to the extension driver Clock to shift serial data D Switch signal for converting the liquid crystal drive waveform to AC Character pattern data corresponding to each segment signal Common signals that are not used are changed to non-selection waveforms. COM9 to COM16 are non-selection waveforms at 1/8 duty factor and COM12 to COM16 are non-selection waveforms at 1/11 duty factor. Segment signals Power supply for LCD drive VCC V5 = 11 V (max) VCC: 2.7V to 5.5V, GND: 0V When crystal oscillation is performed, a resistor must be connected externally. When the pin input is an external clock, it must be input to OSC1.

E DB4 to DB7

MPU MPU

DB0 to DB3

CL1 CL2 M D

O O O O O

Extension driver Extension driver Extension driver Extension driver LCD

COM1 to COM16 16

SEG1 to SEGV1 to V5 VCC, GND OSC1, OSC2 2
LCD Power supply Power supply Oscillation resistor clock

Function Description

Registers The HD44780U has two 8-bit registers, an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator RAM (CGRAM). The IR can only be written from the MPU. The DR temporarily stores data to be written into DDRAM or CGRAM and temporarily stores data to be read from DDRAM or CGRAM. Data written into the DR from the MPU is automatically written into DDRAM or CGRAM by an internal operation. The DR is also used for data storage when reading data from DDRAM or CGRAM. When address information is written into the IR, data is read and then stored into the DR from DDRAM or CGRAM by an internal operation. Data transfer between the MPU is then completed when the MPU reads the DR. After the read, data in DDRAM or CGRAM at the next address is sent to the DR for the next read from the MPU. By the register selector (RS) signal, these two registers can be selected (Table 1). Busy Flag (BF) When the busy flag is 1, the HD44780U is in the internal operation mode, and the next instruction will not be accepted. When RS = 0 and R/W = 1 (Table 1), the busy flag is output to DB7. The next instruction must be written after ensuring that the busy flag is 0. Address Counter (AC) The address counter (AC) assigns addresses to both DDRAM and CGRAM. When an address of an instruction is written into the IR, the address information is sent from the IR to the AC. Selection of either DDRAM or CGRAM is also determined concurrently by the instruction. After writing into (reading from) DDRAM or CGRAM, the AC is automatically incremented by 1 (decremented by 1). The AC contents are then output to DB0 to DB6 when RS = 0 and R/W = 1 (Table 1). Table 1

RS 1 1

Register Selection
R/W Operation IR write as an internal operation (display clear, etc.) Read busy flag (DB7) and address counter (DB0 to DB6) DR write as an internal operation (DR to DDRAM or CGRAM) DR read as an internal operation (DDRAM or CGRAM to DR)

Display Data RAM (DDRAM) Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid crystal display. The DDRAM address (ADD ) is set in the address counter (AC) as hexadecimal. 1-line display (N = 0) (Figure 2) When there are fewer than 80 display characters, the display begins at the head position. For example, if using only the HD44780, 8 characters are displayed. See Figure 3. When the display shift operation is performed, the DDRAM address shifts. See Figure 3.
High order bits Low order bits
Example: DDRAM address 4E 0
AC (hexadecimal) AC6 AC5 AC4 AC3 AC2 AC1 AC0

Figure 1 DDRAM Address

Display position (digit)
DDRAM address (hexadecimal)

Figure 2 1-Line Display

Display position DDRAM address For shift left

For shift right 4F 06

Figure 3 1-Line by 8-Character Display Example
2-line display (N = 1) (Figure 4) Case 1: When the number of display characters is less than lines, the two lines are displayed from the head. Note that the first line end address and the second line start address are not consecutive. For example, when just the HD44780 is used, 8 characters 2 lines are displayed. See Figure 5. When display shift operation is performed, the DDRAM address shifts. See Figure 5.

Display position

DDRAM address (hexadecimal) 40 41

Figure 4 2-Line Display

Display position DDRAM address

For shift left

For shift right 45 46
Figure 5 2-Line by 8-Character Display Example
Case 2: For a 16-character 2-line display, the HD44780 can be extended using one 40-output extension driver. See Figure 6. When display shift operation is performed, the DDRAM address shifts. See Figure 6.
0A 0B 0C 0D 0E 0F 4A 4B 4C 4D 4E 4F

HD44780U display

Extension driver display
09 0A 0B 0C 0D 0E 0F 4A 4B 4C 4D 4E 4F 50
09 0A 0B 0C 0D 0E For shift right 49 4A 4B 4C 4D 4E
Figure 6 2-Line by 16-Character Display Example
Character Generator ROM (CGROM) The character generator ROM generates dot or dot character patterns from 8-bit character codes (Table 4). It can generate 8 dot character patterns and 10 dot character patterns. Userdefined character patterns are also available by mask-programmed ROM. Character Generator RAM (CGRAM) In the character generator RAM, the user can rewrite character patterns by program. For dots, eight character patterns can be written, and for dots, four character patterns can be written. Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character patterns stored in CGRAM. See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used for display can be used as general data RAM. Modifying Character Patterns Character pattern development procedure The following operations correspond to the numbers listed in Figure 7: 1. Determine the correspondence between character codes and character patterns. 2. Create a listing indicating the correspondence between EPROM addresses and data. 3. Program the character patterns into the EPROM. 4. Send the EPROM to Hitachi. 5. Computer processing on the EPROM is performed at Hitachi to create a character pattern listing, which is sent to the user. 6. If there are no problems within the character pattern listing, a trial LSI is created at Hitachi and samples are sent to the user for evaluation. When it is confirmed by the user that the character patterns are correctly written, mass production of the LSI proceeds at Hitachi.

Hitachi User Start

Computer processing Create character pattern listing Evaluate character patterns No
Determine character patterns Create EPROM address data listing

Write EPROM

EPROM Hitachi OK? Yes Art work

Masking

Sample

Sample evaluation

OK? Yes Mass production
Note: For a description of the numbers used in this figure, refer to the preceding page.
Figure 7 Character Pattern Development Procedure
Programming character patterns This section explains the correspondence between addresses and data used to program character patterns in EPROM. The HD44780U character generator ROM can generate 8 dot character patterns and 10 dot character patterns for a total of 240 different character patterns. Character patterns EPROM address data and character pattern data correspond with each other to form a or dot character pattern (Tables 2 and 3). Table 2 Example of Correspondence between EPROM Address Data and Character Pattern (Dots)

EPROM Address Data

LSB A 1 1A A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O 4 O3 O2 O1 O1 Character code Notes: 1. 2. 3. 4. 5. 6. Cursor position

Line position

EPROM addresses A11 to A4 correspond to a character code. EPROM addresses A3 to A0 specify a line position of the character pattern. EPROM data O4 to O0 correspond to character pattern data. EPROM data O5 to O7 must be specified as 0. A lit display position (black) corresponds to a 1. Line 9 and the following lines must be blanked with 0s for a dot character fonts.
Handling unused character patterns 1. EPROM data outside the character pattern area: Always input 0s. 2. EPROM data in CGRAM area: Always input 0s. (Input 0s to EPROM addresses 00H to FFH.) 3. EPROM data used when the user does not use any HD44780U character pattern: According to the user application, handled in one of the two ways listed as follows. a. When unused character patterns are not programmed: If an unused character code is written into DDRAM, all its dots are lit. By not programing a character pattern, all of its bits become lit. (This is due to the EPROM being filled with 1s after it is erased.) b. When unused character patterns are programmed as 0s: Nothing is displayed even if unused character codes are written into DDRAM. (This is equivalent to a space.) Table 3 Example of Correspondence between EPROM Address Data and Character Pattern (Dots)
LSB A 1 1A A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O 4 O3 O2 O1 O1 Character code Cursor position

Notes: 1. 2. 3. 4. 5. 6.

EPROM addresses A11 to A3 correspond to a character code. EPROM addresses A3 to A0 specify a line position of the character pattern. EPROM data O4 to O0 correspond to character pattern data. EPROM data O5 to O7 must be specified as 0. A lit display position (black) corresponds to a 1. Line 11 and the following lines must be blanked with 0s for a dot character fonts.

Table 4

Lower 4 Bits Upper 4 Bits
Correspondence between Character Codes and Character Patterns (ROM Code: A00)

CG RAM (1)

xxxx0000

xxxx0001

xxxx0010

(3) (4)

xxxx0011

xxxx0100

(5) (6)

xxxx0101

xxxx0110

(7) (8)

xxxx0111

xxxx1000

xxxx1001

(2) (3)

xxxx1010

xxxx1011

(4) (5)

xxxx1100

xxxx1101

xxxx1110

xxxx1111
Note: The user can specify any pattern for character-generator RAM.
Correspondence between Character Codes and Character Patterns (ROM Code: A02)

1110 1111

Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character Patterns (CGRAM Data)
For dot character patterns Character Codes (DDRAM data) High Low CGRAM Address High Low Character Patterns (CGRAM data) High * * * Low 0 0

Character pattern (1)

* * * * * *

Cursor position

Character pattern (2)
Notes: 1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types). 2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line regardless of the cursor presence. 3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left). 4. As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are all 0. However, since character code bit 3 has no effect, the R display example above can be selected by either character code 00H or 08H. 5. 1 for CGRAM data corresponds to display selection and 0 to non-selection. * Indicates no effect.
Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character Patterns (CGRAM Data) (cont)
For dot character patterns Character Codes (DDRAM data) High Low CGRAM Address High Low Character Patterns (CGRAM data) High * * * 0 * 0 * 0 * Low 0 * 0 *

Character pattern

* * * * *
Notes: 1. Character code bits 1 and 2 correspond to CGRAM address bits 4 and 5 (2 bits: 4 types). 2. CGRAM address bits 0 to 3 designate the character pattern line position. The 11th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 11th line data corresponding to the cursor display positon at 0 as the cursor display. If the 11th line data is 1, 1 bits will light up the 11th line regardless of the cursor presence. Since lines 12 to 16 are not used for display, they can be used for general data RAM. 3. Character pattern row positions are the same as dot character pattern positions. 4. CGRAM character patterns are selected when character code bits 4 to 7 are all 0. However, since character code bits 0 and 3 have no effect, the P display example above can be selected by character codes 00H, 01H, 08H, and 09H. 5. 1 for CGRAM data corresponds to display selection and 0 to non-selection. * Indicates no effect.

Interfacing to the MPU

The HD44780U can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4- or 8-bit MPUs. For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3 are disabled. The data transfer between the HD44780U and the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then transfer the busy flag and address counter data. For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.

DB7 DB6 DB5 DB4

IR7 IR6 IR5 IR4

IR3 IR2 IR1 IR0

BF AC6 AC5 AC4

AC3 AC2 AC1 AC0

DR7 DR6 DR5 DR4

DR3 DR2 DR1 DR0

Instruction register (IR) write
Busy flag (BF) and address counter (AC) read

Data register (DR) read

Figure 9 4-Bit Transfer Example

Reset Function

Initializing by Internal Reset Circuit An internal reset circuit automatically initializes the HD44780U when the power is turned on. The following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state until the initialization ends (BF = 1). The busy state lasts for 10 ms after VCC rises to 4.5 V. 1. Display clear 2. Function set: DL = 1; 8-bit interface data N = 0; 1-line display F = 0; dot character font 3. Display on/off control: D = 0; Display off C = 0; Cursor off B = 0; Blinking off 4. Entry mode set: I/D = 1; Increment by 1 S = 0; No shift Note: If the electrical characteristics conditions listed under the table Power Supply Conditions Using Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the HD44780U. For such a case, initial-ization must be performed by the MPU as explained in the section, Initializing by Instruction.

Instructions

Outline Only the instruction register (IR) and the data register (DR) of the HD44780U can be controlled by the MPU. Before starting the internal operation of the HD44780U, control information is temporarily stored into these registers to allow interfacing with various MPUs, which operate at different speeds, or various peripheral control devices. The internal operation of the HD44780U is determined by signals sent from the MPU. These signals, which include register selection signal (RS), read/ write signal (R/W), and the data bus (DB0 to DB7), make up the HD44780U instructions (Table 6). There are four categories of instructions that: Designate HD44780U functions, such as display format, data length, etc. Set internal RAM addresses Perform data transfer with internal RAM Perform miscellaneous functions

Read data 1 from CG or DDRAM I/D I/D S S/C S/C R/L R/L DL N F BF BF

Read data

= 1: = 0: = 1: = 1: = 0: = 1: = 0: = 1: = 1: = 1: = 1: = 0:
Increment Decrement Accompanies display shift Display shift Cursor move Shift to the right Shift to the left 8 bits, DL = 0: 4 bits 2 lines, N = 0: 1 line dots, F = 0: dots Internally operating Instructions acceptable
indicates no effect. * After execution of the CGRAM/DDRAM data write or read instruction, the RAM address counter is incremented or decremented by 1. The RAM address counter is updated after the busy flag turns off. In Figure 10, tADD is the time elapsed after the busy flag turns off until the address counter is updated.

Busy signal (DB7 pin)

Busy state
Address counter (DB0 to DB6 pins)

A t ADD

Note: t ADD depends on the operation frequency t ADD = 1.5/(f cp or f OSC ) seconds
Figure 10 Address Counter Update

Instruction Description

Clear Display Clear display writes space code 20H (character pattern for character code 20H must be a blank pattern) into all DDRAM addresses. It then sets DDRAM address 0 into the address counter, and returns the display to its original status if it was shifted. In other words, the display disappears and the cursor or blinking goes to the left edge of the display (in the first line if 2 lines are displayed). It also sets I/D to 1 (increment mode) in entry mode. S of entry mode does not change. Return Home Return home sets DDRAM address 0 into the address counter, and returns the display to its original status if it was shifted. The DDRAM contents do not change. The cursor or blinking go to the left edge of the display (in the first line if 2 lines are displayed). Entry Mode Set I/D: Increments (I/D = 1) or decrements (I/D = 0) the DDRAM address by 1 when a character code is written into or read from DDRAM. The cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1. The same applies to writing and reading of CGRAM. S: Shifts the entire display either to the right (I/D = 0) or to the left (I/D = 1) when S is 1. The display does not shift if S is 0. If S is 1, it will seem as if the cursor does not move but the display does. The display does not shift when reading from DDRAM. Also, writing into or reading out from CGRAM does not shift the display. Display On/Off Control D: The display is on when D is 1 and off when D is 0. When off, the display data remains in DDRAM, but can be displayed instantly by setting D to 1. C: The cursor is displayed when C is 1 and not displayed when C is 0. Even if the cursor disappears, the function of I/D or other specifications will not change during display data write. The cursor is displayed using 5 dots in the 8th line for dot character font selection and in the 11th line for the dot character font selection (Figure 13). B: The character indicated by the cursor blinks when B is 1 (Figure 13). The blinking is displayed as switching between all blank dots and displayed characters at a speed of 409.6-ms intervals when fcp or f OSC is 250 kHz. The cursor and blinking can be set to display simultaneously. (The blinking frequency changes according to f OSC or the reciprocal of f cp. For example, when fcp is 270 kHz, 409.6 250/270 = 379.2 ms.)

Cursor or Display Shift Cursor or display shift shifts the cursor position or display to the right or left without writing or reading display data (Table 7). This function is used to correct or search the display. In a 2-line display, the cursor moves to the second line when it passes the 40th digit of the first line. Note that the first and second line displays will shift at the same time. When the displayed data is shifted repeatedly each line moves only horizontally. The second line display does not shift into the first line position. The address counter (AC) contents will not change if the only action performed is a display shift. Function Set DL: Sets the interface data length. Data is sent or received in 8-bit lengths (DB7 to DB0) when DL is 1, and in 4-bit lengths (DB7 to DB4) when DL is 0.When 4-bit length is selected, data must be sent or received twice. N: Sets the number of display lines. F: Sets the character font. Note: Perform the function at the head of the program before executing any instructions (except for the read busy flag and address instruction). From this point, the function set instruction cannot be executed unless the interface data length is changed. Set CGRAM Address Set CGRAM address sets the CGRAM address binary AAAAAA into the address counter. Data is then written to or read from the MPU for CGRAM.
RS Clear display Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1

RS Return home Code 0

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB1 * Note: * Dont care.

RS Entry mode set Code 0

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBI/D S
RS Display on/off control Code 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB1 D C B
RS Cursor or display shift Code 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBS/C R/L * * Note: * Dont care.

RS Function set Code 0

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB1 DL N F * *
RS Set CGRAM address Code 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBA A A A A A

Higher order bit

Lower order bit
Figure 11 Instruction (1)
Set DDRAM Address Set DDRAM address sets the DDRAM address binary AAAAAAA into the address counter. Data is then written to or read from the MPU for DDRAM. However, when N is 0 (1-line display), AAAAAAA can be 00H to 4FH. When N is 1 (2-line display), AAAAAAA can be 00H to 27H for the first line, and 40H to 67H for the second line. Read Busy Flag and Address Read busy flag and address reads the busy flag (BF) indicating that the system is now internally operating on a previously received instruction. If BF is 1, the internal operation is in progress. The next instruction will not be accepted until BF is reset to 0. Check the BF status before the next write operation. At the same time, the value of the address counter in binary AAAAAAA is read out. This address counter is used by both CG and DDRAM addresses, and its value is determined by the previous instruction. The address contents are the same as for instructions set CGRAM address and set DDRAM address. Table 7

Figure 19 Liquid Crystal Display and HD44780 Connections
Since five segment signal lines can display one digit, one HD44780U can display up to 8 digits for a 1-line display and 16 digits for a 2-line display. The examples in Figure 19 have unused common signal pins, which always output non-selection waveforms. When the liquid crystal display panel has unused extra scanning lines, connect the extra scanning lines to these common signal pins to avoid any undesirable effects due to crosstalk during the floating state.

COM8 COM9

SEG40 Example of a dot, 8-character 2-line display (1/5 bias, 1/16 duty cycle)
Figure 19 Liquid Crystal Display and HD44780 Connections (cont)
Connection of Changed Matrix Layout: In the preceding examples, the number of lines correspond to the scanning lines. However, the following display examples (Figure 20) are made possible by altering the matrix layout of the liquid crystal display panel. In either case, the only change is the layout. The display characteristics and the number of liquid crystal display characters depend on the number of common signals or on duty factor. Note that the display data RAM (DDRAM) addresses for 4 characters 2 lines and for 16 characters 1 line are the same as in Figure 19.

SEG40 COM9

COM8 dot, 16-character 1-line display (1/5 bias, 1/16 duty cycle)
Figure 20 Changed Matrix Layout Displays
Power Supply for Liquid Crystal Display Drive
Various voltage levels must be applied to pins V1 to V5 of the HD44780U to obtain the liquid crystal display drive waveforms. The voltages must be changed according to the duty factor (Table 10). VLCD is the peak value for the liquid crystal display drive waveforms, and resistance dividing provides voltages V1 to V5 (Figure 21). Table 10 Duty Factor and Power Supply for Liquid Crystal Display Drive
Duty Factor 1/8, 1/11 1/16 Bias Power Supply V1 V2 V3 V4 V5 1/4 VCC1/4 VLCD VCC1/2 VLCD VCC1/2 VLCD VCC3/4 VLCD VCCVLCD 1/5 VCC1/5 VLCD VCC2/5 VLCD VCC3/5 VLCD VCC4/5 VLCD VCCVLCD
VCC (+5 V) VCC R V1 V2 V3 V4 R V5 VR 5 V 1/4 bias (1/8, 1/11 duty cycle) 1/5 bias (1/16, duty cycle) R VLCD R VCC V1

Power supply on (the HD44780U is initialized by the internal reset circuit) Function set 1 0

Function set 0 0

Display on/off control Entry mode set 0 1
The control is the same as for 8-bit operation beyond step #6.

Table 13

Step No. RS 1
8-Bit Operation, 8-Digit 2-Line Display Example with Internal Reset
Instruction R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Operation Initialized. No display.
Power supply on (the HD44780U is initialized by the internal reset circuit) Function set 0
Sets to 8-bit operation and selects 2-line display and dot character font. _ Turns on display and cursor. All display is in space mode because of initialization. Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the DD/CGRAM. Display is not shifted. Writes H. DDRAM has already been selected by initialization when the power was turned on. The cursor is incremented by one and shifted to the right.
Write data to CGRAM/DDRAM Set DDRAM address 0 1

HITACHI_

Writes I.

HITACHI _

Sets DDRAM address so that the cursor is positioned at the head of the second line.

Step No. RS 9

8-Bit Operation, 8-Digit 2-Line Display Example with Internal Reset (cont)
Instruction R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display HITACHI M_ HITACHI MICROCO_ HITACHI MICROCO_ ITACHI ICROCOM_ Writes O. Operation Writes M.
Write data to CGRAM/DDRAM Write data to CGRAM/DDRAM Entry mode set 0
Sets mode to shift display at the time of write. Writes M. Display is shifted to the left. The first and second lines both shift at the same time.

Return home 1 0

HITACHI _ MICROCOM Returns both display and cursor to the original position (address 0).
Initializing by Instruction
If the power supply conditions for correctly operating the internal reset circuit are not met, initialization by instructions becomes necessary. Refer to Figures 23 and 24 for the procedures on 8-bit and 4-bit initializations, respectively.

AC Characteristics (VCC = 4.5 to 5.5 V, Ta = 30 to +75C*3)
Item External External clock frequency clock External clock duty operation External clock rise time External clock fall time Symbol Min f cp Duty t rcp t fcp 190 Typ 270 Max 0.2 0.Unit kHz % s s kHz Rf = 91 k VCC = 5.0 V Test Condition Notes* 12
Item Enable cycle time Enable pulse width (high level) Enable rise/fall time Symbol t cycE PWEH t Er, t Ef Min Typ Max 20 Unit ns Test Condition Figure 25
Item Enable cycle time Enable pulse width (high level) Enable rise/fall time Symbol t cycE PWEH t Er, t Ef Min 5 Typ Max 20 160 Unit ns Test Condition Figure 26
Item Power supply rise time Power supply off time Symbol t rCC t OFF Min 0.Typ Max 10 Unit ms Test Condition Figure 28
Electrical Characteristics Notes
1. All voltage values are referred to GND = 0 V.
VCC B V1 A V5 A = VCC V5 B = VCC V1 A 1.5 V B 0.25 A The conditions of V1 and V5 voltages are for proper operation of the LSI and not for the LCD output level. The LCD drive voltage condition for the LCD output level is specified as LCD voltage VLCD.

2. 3. 4. 5.

VCC V1 V2 V3 V4 V5 must be maintained. For die products, specified at 75C. For die products, specified by the die shipment specification. The following four circuits are I/O pin configurations except for liquid crystal display output.
Input pin Pin: E (MOS without pull-up) Output pin Pins: CL1, CL2, M, D VCC PMOS PMOS
Pins: RS, R/W (MOS with pull-up) VCC VCC PMOS
(pull up MOS) NMOS NMOS NMOS
I/O Pin Pins: DB0 DB7 (MOS with pull-up)

VCC PMOS

VCC (input circuit) PMOS Input enable

(pull-up MOS)

NMOS VCC NMOS PMOS

Output enable Data

NMOS (output circuit) (tristate)
6. Applies to input pins and I/O pins, excluding the OSC1 pin. 7. Applies to I/O pins. 8. Applies to output pins. 9. Current flowing through pullup MOSs, excluding output drive MOSs. 10. Input/output current is excluded. When input is at an intermediate level with CMOS, the excessive current flows through the input circuit to the power supply. To avoid this from happening, the input level must be fixed high or low. 11. Applies only to external clock operation.
Th Oscillator OSC1 0.7 VCC 0.5 VCC 0.3 VCC Tl
t rcp Duty = Th 100% Th + Tl
12. Applies only to the internal oscillator operation using oscillation resistor Rf.
R f : 75 k 2% (when VCC = 3 V) R f : 91 k 2% (when VCC = 5 V) Since the oscillation frequency varies depending on the OSC1 and OSC2 pin capacitance, the wiring length to these pins should be minimized.

OSC1 Rf OSC2

VCC = 5 V 500 500

VCC = 3 V

400 f OSC (kHz) f OSC (kHz)
max. 200 typ. min. 100 50

(91) 100

max. 200 typ. 100 50

min. 150

R f (k )
13. RCOM is the resistance between the power supply pins (VCC, V1, V4, V5) and each common signal pin (COM1 to COM16). RSEG is the resistance between the power supply pins (VCC, V2, V3, V5) and each segment signal pin (SEG1 to SEG40). 14. The following graphs show the relationship between operation frequency and current consumption.
VCC = 5 V 1.8 1.6 1.4 1.2 ICC (mA) 1.0 0.8 0.6 0.4 0.2 0.500 typ. ICC (mA) max. 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.500 typ. max. VCC = 3 V

fOSC or fcp (kHz)

15. Applies to the OSC1 pin. 16. Each COM and SEG output voltage is within 0.15 V of the LCD voltage (V CC, V1, V2, V3, V4, V5) when there is no load.

Load Circuits

Data Bus DB0 to DB7
VCC = 5 V For VCC = 4.5 to 5.5 V 3.9 k Test point 90 pF 11 k IS2074 H diodes Test point 50 pF For VCC = 2.7 to 4.5 V
External Driver Control Signals: CL1, CL2, D, M

Test point 30 pF

Timing Characteristics
VIH1 VIL1 tAS tAH VIH1 VIL1

VIL1 PWEH tAH tEf

VIH1 VIL1 tEr tDSW

VIH1 VIL1 tH

VIH1 VIL1

Valid data tcycE

Figure 25 Write Operation

VIH1 VIL1 tAS tAH

VIH1 PWEH tAH tEf

VIH1 VIL1 tEr tDDR

VIH1 VIL1 tDHR

VOH1 VOL1 *

VOH1 * VOL1
* VOL1 is assumed to be 0.8 V at 2 MHz operation.

Figure 26 Read Operation

tct CL1 VOH2 VOH2 tCWH tCSU CL2 VOL2 tCSU tCWH VOH2 tCWL tct VOH2 VOL2 tDH tSU M VOH2 t DM VOL2
Figure 27 Interface Timing with External Driver

2.7 V/4.5 V*2

trcc 0.1 ms trcc 10 ms

tOFF*1 tOFF 1 ms

Notes: 1. tOFF compensates for the power oscillation period caused by momentary power supply oscillations. 2. Specified at 4.5 V for 5-V operation, and at 2.7 V for 3-V operation. 3. For if 4.5 V is not reached during 5-V operation, the internal reset circuit will not operate normally. In this case, the LSI must be initialized by software. (Refer to the Initializing by Instruction section.)
Figure 28 Internal Power Supply Reset

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachis sales office for any questions regarding this document or Hitachi semiconductor products.

HD44780U (LCD-II)

(Dot Matrix Liquid Crystal Display Controller/Driver)

Description

The HD44780U dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. Since all the functions such as display RAM, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. A single HD44780U can display up to one 8-character line or two 8-character lines. The HD44780U has pin function compatibility with the HD44780S which allows the user to easily replace an LCD-II with an HD44780U. The HD44780U character generator ROM is extended to generate 8 dot character fonts and 10 dot character fonts for a total of 240 different character fonts. The low power supply (2.7V to 5.5V) of the HD44780U is suitable for any portable battery-driven product requiring low power dissipation.

Features

and dot matrix possible Low power operation support: 2.7 to 5.5V Wide range of liquid crystal display driver power 3.0 to 11V Liquid crystal drive waveform A (One line frequency AC waveform) Correspond to high speed MPU bus interface 2 MHz (when VCC = 5V) 4-bit or 8-bit MPU interface enabled 80 8-bit display RAM (80 characters max.) 9,920-bit character generator ROM for a total of 240 character fonts 208 character fonts (dot) 32 character fonts (dot)

HD44780U

64 8-bit character generator RAM 8 character fonts (dot) 4 character fonts (dot) 16-common 40-segment liquid crystal display driver Programmable duty cycles 1/8 for one line of dots with cursor 1/11 for one line of dots with cursor 1/16 for two lines of dots with cursor Wide range of instruction functions: Display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift Pin function compatibility with HD44780S Automatic reset circuit that initializes the controller/driver after power on Internal oscillator with external resistors Low power consumption

Ordering Information

Type No. HD44780UA00FS HCD44780UA00 HD44780UA00TF HD44780UA02FS HCD44780UA02 HD44780UA02TF HD44780UBxxFS HCD44780UBxx HD44780UBxxTF Note: xx: ROM code No. Package FP-80B Chip TFP-80F FP-80B Chip TFP-80F FP-80B Chip TFP-80F CGROM Japanese standard font

European standard font

Custom font

HD44780U Block Diagram

OSC1 OSC2 CL1 CL2 M CPG Instruction register (IR)

Reset circuit ACL

Timing generator

RS R/W E

MPU interface

Instruction decoder

Display data RAM (DDRAM) bits

16-bit shift register

Common signal driver

COM1 to COM16

Address counter DB4 to DB7 DB0 to DB3 Input/ output buffer

40-bit shift register

40-bit latch circuit

Segment signal driver

SEG1 to SEG40

Data register (DR)

Busy flag Character generator RAM (CGRAM) 64 bytes
LCD drive voltage selector
Character generator ROM (CGROM) 9,920 bits
Cursor and blink controller
Parallel/serial converter and attribute circuit VCC V1 V2 V3 V4 V5

LCD-II Family Comparison

Item Power supply voltage Liquid crystal drive voltage VLCD Maximum display digits per chip Display duty cycle CGROM 1/4 bias 1/5 bias HD44780S 5 V 10% 3.0 to 11.0V 4.6 to 11.0V 16 digits (8 digits 2 lines) 1/8, 1/11, and 1/16 7,200 bits (160 character fonts for dot and 32 character fonts for dot) 64 bytes 80 bytes A External resistor, external ceramic filter, or external clock 270 kHz 30% (59 to 110 Hz for 1/8 and 1/16 duty cycles; 43 to 80 Hz for 1/11 duty cycle) 91 k 2% HD44780U 2.7 to 5.5 V 3.0 to 11.0V 3.0 to 11.0V 16 digits (8 digits 2 lines) 1/8, 1/11, and 1/16 9,920 bits (208 character fonts for dot and 32 character fonts for dot) 64 bytes 80 bytes A External resistor or external clock 270 kHz 30% (59 to 110 Hz for 1/8 and1/16 duty cycles; 43 to 80 Hz for 1/11 duty cycle) 91 k 2% (when VCC = 5V) 75 k 2% (when VCC = 3V) 1 MHz (when VCC = 3V) 2 MHz (when VCC = 5V) FP-80B TFP-80F
CGRAM DDRAM Segment signals Common signals Liquid crystal drive waveform Oscillator Clock source
Rf oscillation frequency (frame frequency) Rf resistance Instructions CPU bus timing Package
Fully compatible within the HD44780S 1 MHz FP-80 FP-80A
HD44780U Pin Arrangement (FP-80B)
SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38
SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC1

FP-80B (Top view)

SEG39 SEG40 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DB7 DB6 DB5 DB4 DB3 DB2
OSC2 V1 V2 V3 V4 V5 CL1 CL2 VCC M D RS R/W E DB0 DB1
HD44780U Pin Arrangement (TFP-80F)
SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40
SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1

TFP-80F (Top view)

COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DB7 DB6 DB5 DB4
GND OSC1 OSC2 V1 V2 V3 V4 V5 CL1 CL2 VCC M D RS R/W E DB0 DB1 DB2 DB3

HD44780U Pad Arrangement

Chip size: 4.90 4.90 mm2
Coordinate: Pad center (m) Origin: Pad size: 80 Chip center m2 63

Type code

HCD44780U Pad Location Coordinates
Pad No. Function SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC1 OSC2 V1 V2 V3 V4 V5 CL1 CL2 VCC M D RS R/ E DB0 DB1 Coordinate X (um) Y (um) Pad No. Function DB2 DB3 DB4 DB5 DB6 DB7 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 Coordinate X (um) Y (um) 1617 2313

09 0A 0B 0C 0D 0E 0F 4A 4B 4C 4D 4E 4F 50
09 0A 0B 0C 0D 0E For shift right 49 4A 4B 4C 4D 4E
Figure 6 2-Line by 16-Character Display Example
Character Generator ROM (CGROM) The character generator ROM generates dot or dot character patterns from 8-bit character codes (Table 4). It can generate 8 dot character patterns and 10 dot character patterns. User-defined character patterns are also available by mask-programmed ROM. Character Generator RAM (CGRAM) In the character generator RAM, the user can rewrite character patterns by program. For dots, eight character patterns can be written, and for dots, four character patterns can be written. Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character patterns stored in CGRAM. See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used for display can be used as general data RAM. Modifying Character Patterns Character pattern development procedure The following operations correspond to the numbers listed in Figure 7: 1. 2. 3. 4. 5. Determine the correspondence between character codes and character patterns. Create a listing indicating the correspondence between EPROM addresses and data. Program the character patterns into the EPROM. Send the EPROM to Hitachi. Computer processing on the EPROM is performed at Hitachi to create a character pattern listing, which is sent to the user. 6. If there are no problems within the character pattern listing, a trial LSI is created at Hitachi and samples are sent to the user for evaluation. When it is confirmed by the user that the character patterns are correctly written, mass production of the LSI proceeds at Hitachi.

Hitachi User Start

Computer processing Create character pattern listing Evaluate character patterns No
Determine character patterns Create EPROM address data listing

Write EPROM

EPROM Hitachi OK? Yes Art work

Masking

Sample

Sample evaluation

OK? Yes Mass production
Note: For a description of the numbers used in this figure, refer to the preceding page.

Figure 7 Character Pattern Development Procedure
Programming character patterns This section explains the correspondence between addresses and data used to program character patterns in EPROM. The HD44780U character generator ROM can generate 8 dot character patterns and 10 dot character patterns for a total of 240 different character patterns. Character patterns EPROM address data and character pattern data correspond with each other to form a or dot character pattern (Tables 2 and 3). Table 2 Example of Correspondence between EPROM Address Data and Character Pattern (Dots)

EPROM Address Data

LSB A 1 1A A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O 4 O3 O2 O1 O1 Character code Cursor position

Line position

Notes: 1. 2. 3. 4. 5. 6.
EPROM addresses A11 to A4 correspond to a character code. EPROM addresses A3 to A0 specify a line position of the character pattern. EPROM data O4 to O0 correspond to character pattern data. EPROM data O5 to O7 must be specified as 0. A lit display position (black) corresponds to a 1. Line 9 and the following lines must be blanked with 0s for a dot character fonts.
Handling unused character patterns 1. EPROM data outside the character pattern area: Always input 0s. 2. EPROM data in CGRAM area: Always input 0s. (Input 0s to EPROM addresses 00H to FFH.) 3. EPROM data used when the user does not use any HD44780U character pattern: According to the user application, handled in one of the two ways listed as follows. a. When unused character patterns are not programmed: If an unused character code is written into DDRAM, all its dots are lit. By not programing a character pattern, all of its bits become lit. (This is due to the EPROM being filled with 1s after it is erased.) b. When unused character patterns are programmed as 0s: Nothing is displayed even if unused character codes are written into DDRAM. (This is equivalent to a space.) Table 3 Example of Correspondence between EPROM Address Data and Character Pattern (Dots)
EPROM addresses A11 to A3 correspond to a character code. EPROM addresses A3 to A0 specify a line position of the character pattern. EPROM data O4 to O0 correspond to character pattern data. EPROM data O5 to O7 must be specified as 0. A lit display position (black) corresponds to a 1. Line 11 and the following lines must be blanked with 0s for a dot character fonts.
Table 4 Correspondence between Character Codes and Character Patterns (ROM Code: A00)

Upper 4 Bits

Lower 4 Bits

CG RAM (1)

xxxx0000

xxxx0001

xxxx0010

(3) (4)

xxxx0011

xxxx0100

(5) (6)

xxxx0101

xxxx0110

(7) (8)

xxxx0111

xxxx1000

xxxx1001

(2) (3)

xxxx1010

xxxx1011

(4) (5)

xxxx1100

xxxx1101

xxxx1110

xxxx1111
Note: The user can specify any pattern for character-generator RAM.
Table 4 Correspondence between Character Codes and Character Patterns (ROM Code: A02)

1110 1111

Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character Patterns (CGRAM Data)
For dot character patterns Character Codes (DDRAM data) High Low CGRAM Address High Low Character Patterns (CGRAM data) High * * * Low 0 0

Character pattern (1)

* * * * * *

Cursor position

Character pattern (2)
Notes: 1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types). 2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line regardless of the cursor presence. 3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left). 4. As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are all 0. However, since character code bit 3 has no effect, the R display example above can be selected by either character code 00H or 08H. 5. 1 for CGRAM data corresponds to display selection and 0 to non-selection. * Indicates no effect.
Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character Patterns (CGRAM Data) (cont)
For dot character patterns Character Codes (DDRAM data) High Low CGRAM Address High Low Character Patterns (CGRAM data) High * * * 0 * 0 * 0 * Low 0 * 0 *

Character pattern

* * * * *
Notes: 1. Character code bits 1 and 2 correspond to CGRAM address bits 4 and 5 (2 bits: 4 types). 2. CGRAM address bits 0 to 3 designate the character pattern line position. The 11th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 11th line data corresponding to the cursor display positon at 0 as the cursor display. If the 11th line data is 1, 1 bits will light up the 11th line regardless of the cursor presence. Since lines 12 to 16 are not used for display, they can be used for general data RAM. 3. Character pattern row positions are the same as dot character pattern positions. 4. CGRAM character patterns are selected when character code bits 4 to 7 are all 0. However, since character code bits 0 and 3 have no effect, the P display example above can be selected by character codes 00H, 01H, 08H, and 09H. 5. 1 for CGRAM data corresponds to display selection and 0 to non-selection. * Indicates no effect.

Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interferences, such as flickering, in areas other than the display area. Liquid Crystal Display Driver Circuit The liquid crystal display driver circuit consists of 16 common signal drivers and 40 segment signal drivers. When the character font and number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output non-selection waveforms. Sending serial data always starts at the display data character pattern corresponding to the last address of the display data RAM (DDRAM). Since serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register, the HD44780U drives from the head display. Cursor/Blink Control Circuit The cursor/blink control circuit generates the cursor or character blinking. The cursor or the blinking will appear with the digit located at the display data RAM (DDRAM) address set in the address counter (AC). For example (Figure 8), when the address counter is 08H, the cursor position is displayed at DDRAM address 08H.
AC6 AC5 AC4 AC3 AC2 AC1 AC0 AC For a 1-line display Display position DDRAM address (hexadecimal) 11 0A 0
For a 2-line display Display position DDRAM address (hexadecimal) 46

cursor position 0A 4A

cursor position Note: The cursor or blinking appears when the address counter (AC) selects the character generator RAM (CGRAM). However, the cursor and blinking become meaningless. The cursor or blinking is displayed in the meaningless position when the AC is a CGRAM address.
Figure 8 Cursor/Blink Display Example

Interfacing to the MPU

The HD44780U can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4- or 8-bit MPUs. For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3 are disabled. The data transfer between the HD44780U and the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then transfer the busy flag and address counter data. For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.

S/C R/L Shifts the cursor position to the left. (AC is decremented by one.) Shifts the cursor position to the right. (AC is incremented by one.) Shifts the entire display to the left. The cursor follows the display shift. Shifts the entire display to the right. The cursor follows the display shift.

Shift Function

Table 8

Function Set

No. of Display Lines 2 Duty Factor 1/8 1/11 1/16 Cannot display two lines for dot character font

N 1 Note:

Character Font dots dots dots

Remarks

Indicates dont care.
Cursor dot character font dot character font Alternating display Blink display example

Cursor display example

Figure 13 Cursor and Blinking
RS Set DDRAM address Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB1 A A A A A A A
RS Read busy flag and address Code 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBBF A A A A A A A

Figure 14

Write Data to CG or DDRAM Write data to CG or DDRAM writes 8-bit binary data DDDDDDDD to CG or DDRAM. To write into CG or DDRAM is determined by the previous specification of the CGRAM or DDRAM address setting. After a write, the address is automatically incremented or decremented by 1 according to the entry mode. The entry mode also determines the display shift. Read Data from CG or DDRAM Read data from CG or DDRAM reads 8-bit binary data DDDDDDDD from CG or DDRAM. The previous designation determines whether CG or DDRAM is to be read. Before entering this read instruction, either CGRAM or DDRAM address set instruction must be executed. If not executed, the first read data will be invalid. When serially executing read instructions, the next address data is normally read from the second read. The address set instructions need not be executed just before this read instruction when shifting the cursor by the cursor shift instruction (when reading out DDRAM). The operation of the cursor shift instruction is the same as the set DDRAM address instruction. After a read, the entry mode automatically increases or decreases the address by 1. However, display shift is not executed regardless of the entry mode. Note: The address counter (AC) is automatically incremented or decremented by 1 after the write instructions to CGRAM or DDRAM are executed. The RAM data selected by the AC cannot be read out at this time even if read instructions are executed. Therefore, to correctly read data, execute either the address set instruction or cursor shift instruction (only with DDRAM), then just before reading the desired data, execute the read instruction from the second time the read instruction is sent.

Character Font dots + cursor dots + cursor dots + cursor Number of Common Signals 16 Duty Factor 1/8 1/11 1/16

Number of Lines 2

HD44780 COM1

COM8 SEG1

SEG40 Example of a dot, 8-character 1-line display (1/4 bias, 1/8 duty cycle) HD44780 COM1
SEG40 Example of a dot, 8-character 1-line display (1/4 bias, 1/11 duty cycle)
Figure 20 Liquid Crystal Display and HD44780 Connections
Since five segment signal lines can display one digit, one HD44780U can display up to 8 digits for a 1line display and 16 digits for a 2-line display. The examples in Figure 20 have unused common signal pins, which always output non-selection waveforms. When the liquid crystal display panel has unused extra scanning lines, connect the extra scanning lines to these common signal pins to avoid any undesirable effects due to crosstalk during the floating state (Figure 21).

COM8 COM9

SEG40 Example of a dot, 8-character 2-line display (1/5 bias, 1/16 duty cycle)
Figure 20 Liquid Crystal Display and HD44780 Connections (cont)
Figure 21 Using COM9 to Avoid Crosstalk on Unneeded Scanning Line
Connection of Changed Matrix Layout: In the preceding examples, the number of lines correspond to the scanning lines. However, the following display examples (Figure 22) are made possible by altering the matrix layout of the liquid crystal display panel. In either case, the only change is the layout. The display characteristics and the number of liquid crystal display characters depend on the number of common signals or on duty factor. Note that the display data RAM (DDRAM) addresses for 4 characters 2 lines and for 16 characters 1 line are the same as in Figure 20.
Figure 22 Changed Matrix Layout Displays
Power Supply for Liquid Crystal Display Drive
Various voltage levels must be applied to pins V1 to V5 of the HD44780U to obtain the liquid crystal display drive waveforms. The voltages must be changed according to the duty factor (Table 10). VLCD is the peak value for the liquid crystal display drive waveforms, and resistance dividing provides voltages V1 to V5 (Figure 23). Table 10 Duty Factor and Power Supply for Liquid Crystal Display Drive
Duty Factor 1/8, 1/11 1/16 Bias Power Supply V1 V2 V3 V4 V5 1/4 VCC1/4 VLCD VCC1/2 VLCD VCC1/2 VLCD VCC3/4 VLCD VCCVLCD 1/5 VCC1/5 VLCD VCC2/5 VLCD VCC3/5 VLCD VCC4/5 VLCD VCCVLCD
VCC (+5 V) VCC R V1 V2 V3 V4 R V5 VR 5 V 1/4 bias (1/8, 1/11 duty cycle) 1/5 bias (1/16, duty cycle) R VLCD R VCC V1

VCC (+5 V)

V2 R V3 R V4 R V5 VR 5 V
Figure 23 Drive Voltage Supply Example

Relationship between Oscillation Frequency and Liquid Crystal Display Frame Frequency
The liquid crystal display frame frequencies of Figure 24 apply only when the oscillation frequency is 270 kHz (one clock pulse of 3.7 s).
1/8 duty cycle COM1 VCC V1 V2 (V3) V4 Vframe 1 frame = 3.7 s = 11850 s = 11.9 ms 1 Frame frequency = = 84.3 Hz 11.9 ms 1/11 duty cycle COM1 VCC V1 V2 (V3) V4 Vframe 1 frame = 3.7 s = 16300 s = 16.3 ms 1 Frame frequency = = 61.4 Hz 16.3 ms 1/16 duty cycle COM1 VCC V1 V2 V3 V4 Vframe 1 frame = 3.7 s = 11850 s = 11.9 ms 1 Frame frequency = = 84.3 Hz 11.9 ms 200 clocks 2

400 clocks 2

Figure 24 Frame Frequency
Instruction and Display Correspondence
8-bit operation, 8-digit 1-line display with internal reset Refer to Table 11 for an example of an 8-digit 1-line display in 8-bit operation. The HD44780U functions must be set by the function set instruction prior to the display. Since the display data RAM can store data for 80 characters, as explained before, the RAM can be used for displays such as for advertising when combined with the display shift operation. Since the display shift operation changes only the display position with DDRAM contents unchanged, the first display data entered into DDRAM can be output when the return home operation is performed. 4-bit operation, 8-digit 1-line display with internal reset The program must set all functions prior to the 4-bit operation (Table 12). When the power is turned on, 8-bit operation is automatically selected and the first write is performed as an 8-bit operation. Since DB0 to DB3 are not connected, a rewrite is then required. However, since one operation is completed in two accesses for 4-bit operation, a rewrite is needed to set the functions (see Table 12). Thus, DB4 to DB7 of the function set instruction is written twice. 8-bit operation, 8-digit 2-line display For a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be again set after the 8th character is completed. (See Table 13.) Note that the display shift operation is performed for the first and second lines. In the example of Table 13, the display shift is performed when the cursor is on the second line. However, if the shift operation is performed when the cursor is on the first line, both the first and second lines move together. If the shift is repeated, the display of the second line will not move to the first line. The same display will only shift within its own line for the number of times the shift is repeated. Note: When using the internal reset, the electrical characteristics in the Power Supply Conditions Using Internal Reset Circuit table must be satisfied. If not, the HD44780U must be initialized by instructions. See the section, Initializing by Instruction.

Table 11

Step No. RS 1 2
8-Bit Operation, 8-Digit 1-Line Display Example with Internal Reset

Instruction R/

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display
Operation Initialized. No display. Sets to 8-bit operation and selects 1-line display and dot character font. (Number of display lines and character fonts cannot be changed after step #2.)
Power supply on (the HD44780U is initialized by the internal reset circuit) Function set * *
Display on/off control Entry mode set 0
Turns on display and cursor. Entire display is in space mode because of initialization. Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the DD/CGRAM. Display is not shifted. Writes H. DDRAM has already been selected by initialization when the power was turned on. The cursor is incremented by one and shifted to the right. Writes I.
Write data to CGRAM/DDRAM 0 0
Write data to CGRAM/DDRAM Write data to CGRAM/DDRAM Entry mode set 0 0

HITACHI_

Writes I. Sets mode to shift display at the time of write. Writes a space.
Write data to CGRAM/DDRAM 1 0

ITACHI _

Step No. RS 11
8-Bit Operation, 8-Digit 1-Line Display Example with Internal Reset (cont)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display 0 1

Operation Writes M.

Write data to CGRAM/DDRAM Write data to CGRAM/DDRAM Cursor or display shift Cursor or display shift 1 1

1 * * 1 * * * * 1 * * 1

MICROKO_
Writes O. Shifts only the cursor position to the left. Shifts only the cursor position to the left. Writes C over K. The display moves to the left. Shifts the display and cursor position to the right. Shifts the display and cursor position to the right. Writes M.

MICROKO _

Write data to CGRAM/DDRAM Cursor or display shift Cursor or display shift 1 1

ICROCO _

MICROCO _

MICROCO_

Clock oscillation frequency fOSC Rf oscillation Note: *
Item Enable cycle time Enable pulse width (high level) Enable rise/fall time Address set-up time (RS, R/ Address hold time Data set-up time Data hold time Symbol tcycE PWEH tEr, tEf tAS tAH tDSW tH Min Typ Max 20 Unit ns Test Condition Figure 27
Item Enable cycle time Enable pulse width (high level) Enable rise/fall time Address set-up time (RS, R/ Address hold time Data delay time Data hold time Symbol tcycE PWEH tEr, tEf tAS tAH tDDR tDHR Min 5 Typ Max 20 160 Unit ns Test Condition Figure 28
Item Power supply rise time Power supply off time Symbol trCC tOFF Min 0.Typ Max 10 Unit ms Test Condition Figure 30
Electrical Characteristics Notes
1. All voltage values are referred to GND = 0 V.
VCC B V1 A V5 A = VCC V5 B = VCC V1 A 1.5 V B 0.25 A The conditions of V1 and V5 voltages are for proper operation of the LSI and not for the LCD output level. The LCD drive voltage condition for the LCD output level is specified as LCD voltage VLCD.

2. 3. 4. 5.

VCC V1 V2 V3 V4V5 must be maintained. For die products, specified up to 75C. For die products, specified by the die shipment specification. The following four circuits are I/O pin configurations except for liquid crystal display output.
Input pin Pin: E (MOS without pull-up) Pins: RS, R/W (MOS with pull-up) VCC PMOS PMOS VCC PMOS Output pin Pins: CL1, CL2, M, D VCC PMOS
(pull up MOS) NMOS NMOS NMOS
I/O Pin Pins: DB0 DB7 (MOS with pull-up)

VCC PMOS

VCC (input circuit) PMOS Input enable

(pull-up MOS)

NMOS VCC NMOS PMOS

Output enable Data

NMOS (output circuit) (tristate)
6. Applies to input pins and I/O pins, excluding the OSC1 pin. 7. Applies to I/O pins. 8. Applies to output pins. 9. Current flowing through pullup MOSs, excluding output drive MOSs. 10. Input/output current is excluded. When input is at an intermediate level with CMOS, the excessive current flows through the input circuit to the power supply. To avoid this from happening, the input level must be fixed high or low. 11. Applies only to external clock operation.
Th Oscillator OSC1 0.7 VCC 0.5 VCC 0.3 VCC Tl
t rcp Duty = Th 100% Th + Tl
12. Applies only to the internal oscillator operation using oscillation resistor Rf.
OSC1 Rf OSC2 R f : 75 k 2% (when VCC = 3 V) R f : 91 k 2% (when VCC = 5 V) Since the oscillation frequency varies depending on the OSC1 and OSC2 pin capacitance, the wiring length to these pins should be minimized.

VCC = 5 V 500 500

VCC = 3 V
400 f OSC (kHz) f OSC (kHz)
max. 200 typ. min. 100 50

(91) 100

max. 200 typ. 100 50

min. 150

R f (k )
13. RCOM is the resistance between the power supply pins (VCC, V1, V4, V5) and each common signal pin (COM1 to COM16). RSEG is the resistance between the power supply pins (VCC, V2, V3, V5) and each segment signal pin (SEG1 to SEG40). 14. The following graphs show the relationship between operation frequency and current consumption.
VCC = 5 V 1.8 1.6 1.4 1.2 ICC (mA) 1.0 0.8 0.6 0.4 0.2 0.500 typ. ICC (mA) max. 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.500 typ. max. VCC = 3 V

fOSC or fcp (kHz)

15. Applies to the OSC1 pin. 16. Each COM and SEG output voltage is within 0.15 V of the LCD voltage (VCC, V1, V2, V3, V4, V5) when there is no load.

Load Circuits

Data Bus DB0 to DB7
VCC = 5 V For VCC = 4.5 to 5.5 V 3.9 k Test point 90 pF 11 k IS2074 H diodes Test point 50 pF For VCC = 2.7 to 4.5 V
External Driver Control Signals: CL1, CL2, D, M

Test point 30 pF

Timing Characteristics
RS VIH1 VIL1 tAS tAH VIH1 VIL1

VIL1 PWEH tAH tEf

VIH1 VIL1 tEr tDSW

VIH1 VIL1 tH

VIH1 VIL1

Valid data tcycE

Figure 27 Write Operation
VIH1 VIL1 tAS tAH VIH1 VIL1

VIH1 PWEH tAH tEf

VIH1 VIL1 tEr tDDR

VIH1 VIL1 tDHR

VOH1 VOL1 *

VOH1 * VOL1

* VOL1 is assumed to be 0.8 V at 2 MHz operation.

Figure 28 Read Operation

tct CL1 VOH2 VOH2 tCWH tCSU CL2 VOL2 tCSU tCWH VOH2 tCWL tct VOH2 VOL2 tDH tSU M VOH2 t DM VOL2
Figure 29 Interface Timing with External Driver

2.7 V/4.5 V*2

trcc 0.1 ms trcc 10 ms

tOFF*1 tOFF 1 ms

Notes: 1. tOFF compensates for the power oscillation period caused by momentary power supply oscillations. 2. Specified at 4.5 V for 5-V operation, and at 2.7 V for 3-V operation. 3. For if 4.5 V is not reached during 5-V operation, the internal reset circuit will not operate normally. In this case, the LSI must be initialized by software. (Refer to the Initializing by Instruction section.)
Figure 30 Internal Power Supply Reset