Technologies for the ProLiant ML570 G4 and ProLiant DL580 G4 servers

technology brief

Abstract..... 3 Introduction..... 3 Processor architecture..... 3 64-bit architecture.... 3 Dual-core architecture.... 4 Xeon dual-core processors..... 4 Memory architecture.... 5 Background: memory banks and ranks.... 5 Intel E8501 chipset.... 6 Partitioning for electrical isolation.... 6 Maximum memory configurations.... 7 High-performance memory.... 7 DDR-2 memory..... 7 Memory interleaving.... 8 Errors in memory.... 11 High-availability memory technologies.... 11 Supported Advanced Memory Protection technologies.. 11 Architecture trade-offs with a large memory footprint... 12 Updated I/O technologies.... 12 Serial Attached SCSI..... 12 Small Form Factor hard drives.... 13 The Smart Array SAS P400 Controller.... 13 Expansion slot options.... 14 Updated networking technologies.... 14 TCP Offload Engine.... 14 Receive Side Scaling (RSS).... 15 iSCSI..... 15 Improved manageability through iLO 2... 15 Mechanical design for serviceability.... 16 Common components.... 16 ProLiant ML570 G4.... 18
ProLiant DL580 G4.... 19 Conclusion..... 21 For more information.... 21 Call to action.... 22

Abstract

The fourth generation of HP ProLiant 500 series serversthe HP ProLiant ML570 G4 and the HP ProLiant DL580 G4 serverscan transition easily from 32-bit to 64-bit x86 processing. The architecture for these servers uses the Intel 64-bit Xeon dual-core processor designed to operate in either 32-bit or 64-bit mode, depending on the application and operating system (OS) used. This architecture brings enhanced performance not only through dual-core 64-bit architecture but also through the use of fast DDR-2 memory, large memory footprints, and dual front-side buses. To complement this high-performing architecture, the Intel E8501 chipset supports high-availability memory technologies such as Online Spare, Hot Plug Mirrored memory, and Hot Plug RAID memory. This paper is written with the assumption that readers are familiar with HP ProLiant server technology.

Introduction

The ProLiant ML570 G4 and the ProLiant DL580 G4 servers bring a new level of high-performance and high-availability technologies to 4-way, industry-standard servers. Many of these technologies were previously available only in 8-way x86 servers or servers using other processor architectures. This paper addresses the following key technologies within the ProLiant ML570 G4 and DL580 G4 platforms: Dual-core processor configurations High-availability technologies including Advanced Memory Protection technologies and larger memory footprints Updated I/O technologies Updated networking technologies Highly serviceable mechanical designs For complete specifications of each server, see the HP website at www.hp.com/go/ProLiant.

Processor architecture

In October of 2005 Intel began shipping the first dual-core Xeon processors. The ProLiant ML570 G4 and the ProLiant DL580 G4 offer the choice of either the dual-core 64-bit Intel Xeon 7100 sequence processors (previously referred to by the code name Tulsa) or the Xeon 7000 sequence processors (previously referred to by the code name Paxville).

64-bit architecture

A 64-bit architecture has a much larger amount of directly addressable (flat) memory space than a 32-bit processor. The use of EM64T allows the OS to access a flat memory address space greater than 4 GB without enabling Physical Address Extensions (PAE) and incurring the overhead of PAE. This can result in performance advantages for the 64-bit architectures because of their ability to use large amounts of memory, such as with intensive floating-point calculations used in scientific and engineering modeling programs. For additional information about 64-bit extensions and architecture, see the technology brief titled Characterizing x86 processors for industry-standard servers: AMD Opteron and Intel Xeon. 1
Available at this URL: www.hp.com/servers/technology

Dual-core architecture

Dual-core processors are two separate microprocessors on the same physical die. When combined with Intel Hyper-Threading technology, each dual-core processor has the ability to execute four simultaneous threads. By increasing the number of processors available to the operating system, multiple threads can be executed more efficiently. In addition, a dual-core processor uses less power than two equivalent single-core processors and therefore produces less heat.
Xeon dual-core processors
The ProLiant ML570 G4 and DL580 G4 platforms support the following processors: Xeon Xeon Xeon Xeon Xeon Xeon 7140M 3.4 GHz/16MB L3 cache 7130M 3.2 GHz/8MB L3 cache 7120M 3.0 GHz/4MB L3 cache 7110M 2.6 GHz/4MB L3 cache 7030 2.8 GHz/2 x 1MB L2 cache GHz/2 x 2MB L2 cache

The 7100 sequence processors are built using 65-nanometer (nm) process technology and use a 200-MHz front side bus which is quad-pumped to 800 MHz, providing up to 6.4 GB/s data transfer rates. The 65-nm technology uses 65-nm-wide circuits on the chip, allowing for high processor speeds and more circuits per chip than earlier 90-nm technology. A quad-pumped bus performs four data transfers per clock cycle, effectively quadrupling the data throughput for the bus. The processors feature an L3 cache that is shared between cores and supports IA-32 and the EMT64 instruction set for running 64-bit applications and operating systems. The 7000 sequence processors are built on 90-nanometer technology. The 64-bit Xeon processor uses the NetBurst architecture with Hyper-Threading technology and HyperPipelined technology. It includes support for Enhanced Intel Speed-Step Technology and Intel Execute Disable Bit technology. 2 As server and rack densities have increased, power and heat management have become increasingly important. In response, Intel developed Enhanced Intel Speed-Step technology, which exposes power state registers in the processor. With the appropriate ROM or OS interface, these registers can be used to switch the processor between different power states, changing the operating frequency and voltage of the processor. This, in turn, lowers the power usage and heat production of the processor. Demand-based switching is the OS implementation of power management using the Enhanced SpeedStep technology. It is supported by some new operating systems including Microsoft Windows Server 2003 SP1, Red Hat Enterprise Linux 4 Update 1, and SUSE Linux Enterprise Server 9 SP1. HP Power Regulator 3 for ProLiant is an OS-independent power management feature of HP ProLiant servers that uses Enhanced Intel Speed-Step technology. HP Power Regulator supports both dynamic and static modes. With HP Static Low Power Mode, the processors are configured to run continuously in a lower power state. This is useful for customers with power-constrained data centers who require a guaranteed maximum power usage for each server. For servers that operate in moderately or minimally loaded environments, there will be little, if any, performance degradation. HP Dynamic Power Savings Mode lowers overall power usage of the server without affecting system performance. When this mode is enabled, the System ROM will dynamically modify the frequency and voltage of each processor, based on the processor workload. The processor operates in a high power state only when needed, thus reducing the overall system power usage.

For information about these Intel technologies, visit the Intel website at www.intel.com. Available online at http://h18013.www1.hp.com/products/servers/management/ilo/power-regulator.html
Intel first released the Execute Disable Bit functionality with the Itanium processor family. The technology allows the processor to classify areas of memory that cannot execute application code. When combined with OS support, this helps to prevent certain classes of malicious buffer overflow attacks. Intel Execute Disable bit is supported by Microsoft Windows Server 2003 SP1, Microsoft Windows XP SP2, SuSe Linux Enterprise Server 9.2, or Red Hat Enterprise Linux 3 Update 3. For additional information about these processors, see the Intel website or the HP technology brief titled The Intel processor roadmap for industry-standard servers. 4

Memory architecture

The ProLiant ML570 G4 and the ProLiant DL580 G4 both use the Intel E8501 chipset architecture; therefore, they have the same core technologies for the memory subsystem. However, they differ in their I/O implementation to meet diverse customer requirements.
Background: memory banks and ranks
The term memory bank has been used to refer to more than one concept. For this paper, a memory bank refers to a pair of DIMMs that are located in the same order in two parallel memory channels (Figure 1). The DIMMs may be single-rank or dual-rank, which affects memory capacity and how memory is interleaved for performance. The ProLiant ML570 G4 has three memory banks; the ProLiant DL580 G4 has two. Either model will accept single-rank or dual-rank DIMMs. For

Figure 1. Memory banks

A single-rank DIMM is a DIMM in which all of the memory chips contribute to a single data set of 64 bits (plus the ECC bits) and are activated by the same chip-select signals. To increase memory density, memory suppliers are producing dual-rank DIMMs. Typically, a dualrank DIMM is made by stacking a second set of memory chips directly on top of the first set of memory chips. A dual-rank DIMM produces a second data set of 64 bits (plus ECC bits) and requires two chip-selects with different signals to differentiate between the two sets of memory chips. Although physically taking up the space of a single DIMM, a dual-rank DIMM acts as if it were two separate DIMMs and is considered two electrical loads by the chipset.

Available at http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00164255/c00164255.pdf

Intel E8501 chipset

The E8501 chipset has a high-availability memory subsystem that consists of the north bridge [TNB] and the XMB memory controller. The E8501 chipset supports dual-core versions of Intel processors and has the important feature of using two separate front side buses to connect to the processors (Figure 2). Each north bridge can connect to up to four memory boards, and each memory board includes an XMB memory controller chip. The north bridge connects to each XMB memory controller using a high-speed serial interconnect (the IMI bus) that allows 6.4 GB/s inbound (for read data signals from the XMB) and 3.2 GB/s outbound (for write data signals to the XMB). The north bridge uses an in-order (FIFO) queue to maintain coherency across the dual front-side buses while processing read/write requests.
Figure 2. Block diagram of Xeon MP architecture used in the ProLiant ML570 G4 and DL580 G4 platforms
Each XMB memory controller chip supports two channels of DDR-2 memory. The DDR-2 memory on each channel operates in lockstep at 400 MHz. The ProLiant ML570 G4 supports six DIMMs per memory board (three per channel). The ProLiant DL580 supports four DIMMs per memory board (two per channel), due to physical constraints of the 4U system. For both servers, the maximum memory supported is 64 GB with 4-GB DIMMs. Partitioning for electrical isolation One of the features of a well-designed chipset is the degree to which the silicon is partitioned to allow different signal areas to be electrically isolated. The E8501 chipset is partitioned so that the front-side bus interconnects to a partitioned area for the left CPU, the right CPU, and each memory board (Figure 3). The XMB is similarly partitioned so that each internal memory controller is isolated electrically from the other to avoid power noise and crosstalk issues. Avoiding crosstalk and other
noise is increasingly important as bus speeds increase and bus signals become more susceptible to slight differences in voltages.
Figure 3. Partitioning of the TNB and XMB chips to reduce power noise and crosstalk issues
Maximum memory configurations Each XMB memory controller supports eight electrical loads. A single-rank DIMM is considered one electrical load; a dual-rank DIMM is two electrical loads. Therefore, the ProLiant ML570 G4 supports the following maximum DIMM configurations per memory board: Six single-rank DIMMs (three per memory channel) Four dual-rank DIMMs (two per memory channel) Two dual-rank DIMMs and four single-rank DIMMs Four 4-GB dual-rank DIMMs per memory board provide the maximum memory of 64 GB for the ProLiant ML570 G4. The ProLiant DL580 G4 also supports a maximum of 64 GB of memory using four dual-rank, 4-GB DIMMs per memory board. The ProLiant DL580 G4 can support a maximum of four DIMMs per memory board, using either single-rank DIMMs, dual-rank DIMMs, or a combination of the two. In either system, DIMMs must be installed in pairs on the memory board. Each DIMM pair must be identical, with the same capacity, technology, and density. Refer to the applicable server user guide for valid memory configurations when combining single-rank and dual-rank DIMMs.

High-performance memory

Processor performance has kept pace fairly consistently with Moores law of doubling performance every two years. On the other hand, memory bandwidth doubles roughly every three years. To keep pace, designers are challenged to make memory subsystems that are faster. The ProLiant ML570 G4 and the ProLiant DL580 G4 use DDR2-400 memory and interleaving to improve memory performance and decrease this performance gap. DDR-2 memory DDR-2 SDRAM is the second generation of DDR SDRAM. In contrast to the first generation of DDR memory, DDR-2 memory operates at an even lower voltage (1.8V) to further reduce power consumption. DDR-2 memory also uses higher clock frequencies to increase data transfer rates and uses on-die termination control to improve signal quality. At 200 MHz (double-clocked to an effective 400 MHz), DDR-2 increases memory bandwidth to 3.2 GB/s.
In DDR memory, an external termination resistor is added to the system board to improve signal quality and reduce noise for the memory signals. This reduces the likelihood of a signal reflecting, or bouncing back, toward the driving source. DDR-2 memory, on the other hand, moves this resistor into the silicon of the memory itself. This reduces signal reflection and therefore improves signal quality (Figure 4). For additional information about DDR-2 memory technology, refer to the HP technology brief titled Memory technology evolution: an overview of system memory technologies. 5
Figure 4. Comparison of on-die termination of DDR and DDR-2 memory
Memory interleaving To reduce latencies and improve performance, there are three different types of memory interleaving within the ProLiant ML570 G4 and DL580 G4 servers: two-way (dual-channel) interleaving, interleaving within the XMB memory controller, and interleaving across multiple XMB memory controllers. To simplify the descriptions, the following sections describe how interleaving works when using single-rank DIMMs. The same concepts apply for dual-rank DIMMs. Two-way interleaving Like previous ProLiant servers, the ProLiant ML570 G4 and the ProLiant DL580 G4 servers use two-way, or dual-channel, interleaving. Two-way interleaving works by dividing memory into 64-bit blocks that can be accessed two at a time through the two memory channels in an XMB controller (Figure 5). This allows twice the amount of data to be obtained in a single memory access and reduces the required number of memory accesses. Because the data is split into the two separate memory channels and accessed simultaneously, DIMMs must be installed in pairs in the ML570 G4 and DL580 G4 servers, and the pairs must contain identical DIMMs.

Figure 5. Interleaving between the two channels of memory: 64-bits go to memory controller (channel) 1, the next 64 bits to go to memory controller 2, and so on.
XMB rank interleaving Rank interleaving within the XMB groups several ranks of memory together so that cache lines are sequentially read or written across the entire group. For example, suppose that bank A and bank B are interleaved together. (In this example, all contain single-rank DIMMs, so bank A is equivalent to a rank.) The first requested cache line would come from bank A DIMMs, the next cache line would come from bank B DIMMs, the next from bank A DIMMs, and so on (Figure 6). XMB interleaving is done on 2, 4, or 8 ranks at a time. While bank A is undergoing its refresh cycle, bank B is accessing memory, and then when bank B is undergoing its refresh cycle, bank A is accessing memory. In this way, the refresh cycles occur while memory is being accessed. XMB rank interleaving reduces latencies by allowing multiple memory pages to be open at the same time, rather than waiting for several cache lines to be read from a single bank.
Figure 6. Rank interleaving: Cache lines are split across a group of memory ranks.
Interleaving across XMB memory controllers Because there are up to four XMB memory controllers (one per memory board), the north bridge device also splits requested cache lines among all memory controllers. This type of interleaving is automatically enabled when using more than one memory board (if hot-add is disabled). For example, if an application requires 40 cache lines of data and the server contains four memory boards, the north bridge will split those 40 cache lines across the four memory boards in a sequential fashion: Cache line 1 comes from memory board 1, cache line 2 comes from memory board 2, and so on (Figure 7). Assuming that rank interleaving is also enabled, the memory controller will read the fifth cache line from the second rank of DIMMs on memory board 1. Distributing the memory reads and writes across multiple controllers reduces memory access times for individual controllers and reduces the likelihood of processors waiting on data. The north bridge has no mechanism for updating the interleaving scheme on the fly if new memory boards are added. Therefore, if hot-add memory is enabled, interleaving cannot be done across memory controllers and it will be disabled. 6
Figure 7. Interleaving across XMB memory controllers: The north bridge interleaves the cache lines among the memory board subsystems (moving down vertically in the schematic). Rank interleaving would then interleave cache lines horizontally, as depicted with cache line 5.
The one exception is if all four memory boards are installed and hot-add is enabled: Because the system is already fully populated with memory boards, the north bridge controller can interleave memory across the XMB memory controllers.

Errors in memory

As memory capacity grows, it becomes statistically more likely that memory errors will occur: both hard and soft errors. Errors can be categorized as either correctable or uncorrectable. In the ProLiant ML570 G4 and the DL580 G4 servers, the memory controller calculates check bits every time it writes to memory. When memory is read, it re-calculates those check bits from the data stored in the DRAM devices and compares the re-calculated check bits to the stored check bits. If the two sets of check bits are different, the error can be corrected if it is a: Single-bit error in a DRAM device (correctable by standard ECC) Multi-bit error in a DRAM device (correctable by advanced ECC) If multi-bit failures occur in different DRAM devices, they are not correctable. The uncorrectable error will return bad data unless the customer has enabled Advanced Memory Protection techniques such as Hot Plug RAID or Hot Plug Mirrored Memory. For more information about the types and causes of memory errors, refer to the HP technology brief titled HP Advanced Memory Protection technologies. 7
High-availability memory technologies
The ML570 G4 and DL580 G4 servers offer three levels of Advanced Memory Protection that provide increased fault tolerance for applications requiring higher levels of availability: Online Spare, Hot Plug Mirrored Memory, and Hot Plug RAID.
Supported Advanced Memory Protection technologies
Customers have four options to consider for memory protection in the ML570 G4 and the DL580 G4 servers: Advanced ECC , Online Spare, Hot Plug Mirroring, and Hot Plug RAID. Generally, as the level of memory availability (redundancy) increases, the amount of installed memory available for use by the OS decreases. Advanced ECC provides the most available memory, as all installed memory is available to the OS and applications. Advanced ECC mode protects against correctable memory errors. However, Advanced ECC mode does not protect against uncorrectable errors and does not provide any capability of replacing failed or degraded DIMMs without shutting down the server. Online Spare memory reduces the likelihood of uncorrectable memory errors but does not protect against uncorrectable memory errors. Like advanced ECC, Online Spare provides no capability of replacing failed or degraded DIMMs without shutting down the server. The amount of memory reserved for the Online Spare rank will vary from one system configuration to the next. The exact percentage of memory available to the OS when using Online Spare mode depends on the number and size of DIMMs populated per memory board. Hot Plug Mirrored Memory provides protection against both correctable and uncorrectable memory errors. Hot Plug Mirrored Memory also allows replacing failed or degraded DIMMs while the system is operating. However, this mode uses half of the installed memory for redundancy. Hot Plug RAID memory often provides the most economical and effective memory protection. Like Hot Plug Mirrored Memory, it protects against correctable and uncorrectable memory errors, but it does so while allowing 75 percent of the installed memory to be available to the OS. Hot Plug RAID memory also allows replacing failed or degraded DIMMs while the system is operating. Table 1 summarizes differences in functionality among the levels of memory protection.

The Smart Array SAS P400 Controller
Both the ML570 G4 and the DL580 G4 include a Smart Array P400 Controller in a PCI Express slot. This controller offers the benefits of SAS storage and a rich feature set. Some configurations of the ML570 G4 and the DL580 G4 come with a battery-backed write cache (BBWC) on the P400 controller. For models that do not come with the BBWC, it is available as an option. This cache buffers disk writes so that disk I/O can be handled efficiently. The battery is needed in case of an unexpected shutdown of the system, so that information in the buffer will not be lost. In the case of a complete system failure, the controller and disks can be moved to a different server, where the controller will flush out the cache to the disks after power has been restored. In the case of a controller failure, the cache module and disks can be removed from the failed controller and moved to a working controller, where the cache will be flushed out to the disks. The battery will last two days without receiving any power from the computer. The Smart Array P400 supports RAID levels 0, 1, 1+0, and 5. RAID 6 (double parity) is available and does require the BBWC. Mirror splitting is available for RAID 1 arrays. This functionality allows the user to split a RAID 1 mirror into two separate RAID 0 arrays (breaking the mirror). Mirror recombining is the oppositecombining two RAID 0 arrays into a RAID 1 mirror. The battery-backed write cache is not required for this feature. For detailed information about RAID, refer to the HP technology brief titled RAID 6 with HP Advanced Data Guarding technology: a cost-effective, fault-tolerant solution. 9 The battery-backed write cache is required for capacity expansion, which allows the user to add a physical disk to an existing array. The controller then recalculates parity and balances the data across the disks. During the expansion, data and logical structures on the array are preserved. The P400 controller supports a recovery ROM which allows for failing back to the previous good ROM, in the event of a failed attempt to flash the controllers ROM. Online Drive Flashing is also supported. With Online Drive Flashing, disk drive firmware updates can be pre-loaded onto the controller; and then at the next reboot, the controller will flash the firmware on the hard drives.
Available at this URL: www.hp.com/servers/technology Available at this URL: www.hp.com/servers/technology

Expansion slot options

The ML570 G4 is optimized for expansion, and the DL580 G4 is optimized for efficient use of space in a server rack. Because of the different design goals, the two servers offer different expansion slot configurations. The ML570 G4 has the following expansion slots: Four 64-bit/100-MHz PCI-X slots Six PCI Express x4 slots

An x4-x8 PCI Express bus expander is available for converting two PCI Express x4 slots into one PCI Express x8 slot. When installed in a PCI Express x4 slot, the expander converts the adjacent slot into a PCI Express x8 slot. The ML570 G4 can support up to three x4-x8 PCI Express bus expander cards. Expander cards can be installed only in slots 6, 8, and 10. The DL580 G4 features the following expansion slots on all models: One 64-bit/133-MHz PCI-X slot Four PCI Express x4 slots
In addition, the DL580 G4 has a mezzanine option that can be ordered in one of the following configurations: The PCI-X mezzanine option adds two 64-bit/133-MHz PCI-X slots. The PCI Express x4 mezzanine option adds two PCI Express x4 slots. The PCI Express x8 mezzanine option adds one PCI Express x8 slot.
The x4-x8 PCI Express bus expander is also available for the DL580 G4. It can only be installed in slots 5 and 7.
Updated networking technologies
The ProLiant ML570 G4 and the ProLiant DL580 G4 include an embedded, dual-port, NC371i multifunction, gigabit Ethernet network adapter. Technologies enabled by the NC371i include TCP Offload Engine (TOE), Receive Side Scaling (RSS), and iSCSI (internet SCSI).

TCP Offload Engine

Network bandwidth has improved steadily since the early days of TCP/IP networking, and along with this improvement in speed has come increased demand for CPU cycles to manage the network protocol stack. A busy, full-duplex gigabit Ethernet connection can consume the available computing power of a 1-GHz Pentium 4 processor. Unfortunately, this means that even a modern, high-powered CPU will show degraded performance in processing application instructions while data is being transferred onto or off of the network. Computers most susceptible to this problem are application, web, and file servers that have a high number of concurrent connections. To reduce this burden on the CPU, the embedded NC371i network controller in both the ML570 G4 and the DL580 G4 is designed with TOE (TCP Offload Engine) capabilities. TOE NICs (network interface cards) are designed with on-board logic to process common and repetitive tasks of TCP network traffic. Because the CPU does not have to devote cycles to processing these tasks, it can be used more efficiently to significantly increase application performance on servers attached to gigabit Ethernet networks. TOE is supported on Microsoft Windows Server 2003 with the Scalable Networking Pack installed.

Receive Side Scaling (RSS)
The Network Driver Interface Specifications (NDIS) define a common Application Programming Interface for network interface cards on Microsoft operating systems. Early versions of NDIS did not differentiate between computers with single or multiple CPUs. The result was that one CPU was forced to handle the entire network processing load. NDIS v6.0 includes support for multiple processors. With NDIS v6.0, RSS can dynamically balance the processing of received network packets across multiple processors. The Scalable Networking Pack for Windows Server 2003 is required for RSS support. By installing the Scalable Networking Pack for Windows Server 2003, administrators can balance the processing load between multiple CPUs on the ML570 G4 and DL580 G4 servers
iSCSI is a standard that implements the SCSI protocol for interacting with storage devices over a TCP/IP network. While iSCSI can be implemented over any TCP/IP network, the most common implementation is over gigabit Ethernet. iSCSI serves the same purpose as Fibre Channel in building storage area networks (SANs), but avoids the cost, complexity, and compatibility issues associated with Fibre Channel SANs. In iSCSi terminology, initiators are devices that access storage resources through the iSCSI protocol. A target is the device that the initiator accesses. While the target is usually a hard drive enclosure or another computer, it can also be any other storage device that supports the iSCSI protocol, such as a tape drive. Initiators can be divided into two categories: software initiators and Host Bus Adapters (HBAs). Software initiators implement the iSCSI protocol in software, and CPU resources are used to manage the protocol stack. A more efficient approach is to offload the management of the protocol to the network adapter. Adapters that implement the iSCSI protocol are known as iSCSI HBAs. These devices appear to the operating system to be a SCSI HBA. The NC371i is an iSCSI HBA and appears to the operating system as a SCSI HBA. The ML570 G4 and DL580 G4 servers both offer the ability to use either network interface as an iSCSI HBA. For more information about iSCSI, refer to the HP technology brief titled iSCSI technology: A convergence of networking and storage. 10

Improved manageability through iLO 2
Integrated Lights-Out 2 (iLO 2) is the fourth generation of Lights-Out remote management for HP servers. iLO 2 is hardware and firmware integrated into most ProLiant servers that provides remote management capabilities over Ethernet. iLO 2 is most useful in situations that require remote management of servers, and it is active even when the OS not operating. The iLO2 management processor obtains its power from the auxiliary power plane of the server, so it is always available when the server is plugged into a power source. There are three levels of licensing for iLO 2: iLO 2 Standard, iLO 2 Select Packs, and iLO 2 Advanced Packs. Each offers different levels of remote access capabilities. The ML570 G4 and DL580 G4 servers both offer the ability to connect to iLO 2 through a dedicated Ethernet port. This port can connect to a dedicated management network that is out of the data path for the server and that can be highly secured. In addition, iLO 2 on these platforms can assign an additional MAC and IP address to one of the standard embedded network interfaces and share that
port with normal traffic. This shared arrangement eliminates the need for an extra network connection for iLO 2. For more information about iLO 2, refer to the HP technology brief titled Integrated Lights-Out technology: enhancing the manageability of ProLiant servers. 11
Mechanical design for serviceability
The ProLiant ML570 G4 and DL580 G4 servers follow the well-established tradition of excellent mechanical design in ProLiant servers. The designs improve thermal efficiencies, improve the ability to withstand mechanical shocks, and provide easy-to-service components.

Common components

Both servers share the same processor heat sink design, hot-plug redundant fans, hot-plug redundant power supply design, universal rail design, and the same cable management arms. Use of the same parts allows customers to keep fewer spare parts in stock and greatly simplifies ordering and storage of replacement parts. The processor heat sink design includes three guiding pins and a special locking lever mechanism to reduce the likelihood of damaging the processor when inserting the heat sink (Figure 10). The lever, which is extended out for easy access, has to be in the proper position before it can lock the processor.
Figure 10. Processor heat-sink in the ML570 G4 and the DL580 G4 servers
The ML570 G4 and the DL580 G4 use a single, redundant, hot-plug fan form factor throughout the servers. Both servers support six hot-plug fans. Both servers ship with tool-free, snap-in, sliding rails and a cable management system for simple deployment in HP and third-party racks and for in-rack server access. The rail system is ambidextrous; that is, the same rail can be used on either side of the rack with minor adjustments to the rail system. The rail system accommodates a much broader range of rack designs than previous rail systems. It provides tool-free support for square-hole, round-hole, and threaded-hole racks and for adjusting to rack depths of 23.75 to 35 inches (603.25 to 889.00 millimeters). The cable management arms are also ambidextrous and independent of the hole design in the racks. The ambidextrous cable management arms allow customers to choose whether to put all the cables down one side of the rack or to switch sides from one server to the next.

Figure 15. Front view of the ProLiant DL580 G4 server. Memory, processors, and disk drives are easily accessible from the front.
The memory modules in the ML580 G4 use the same intuitive locking mechanism as the ML570 G4 to prevent a user from inserting or removing a memory board when it is in the hot, or active, state (Figure 16).
Figure 16. Memory modules have a simple locking mechanism that shows whether the memory board can be removed.

Locking mechanism

The four processors are all housed in a processor cage that is accessible from the front. This eliminates the need to remove the server from the rack to replace or install a processor. The processor cage uses a unique double-locking latch mechanism: Administrators use the blue touchpoint latch to remove the processor cage from the server chassis and then use this same blue touchpoint latch to open the top sheet metal cover to the processor cage (Figure 17).
Figure 17. Double-locking latch on the processor cage

Conclusion

The ProLiant ML570 G4 and the ProLiant DL580 G4 servers continue to build on the success of their G3 predecessors, offering both high performance and reliability. The server designs share a common processor and memory architecture that optimizes performance through the use of the latest Intel 64-bit Xeon dual-core processors, fast DDR-memory, and multiple layers of memory interleaving to reduce latencies in the memory subsystem. The servers are capable of supporting a large memory footprint to complement the 64-bit capabilities of the Intel 64-bit Xeon dual-core processor. Advanced Memory Protection techniques protect against correctable memory errors (advanced ECC), reduce the risk of uncorrectable errors (Online Spare memory), and protect against uncorrectable errors (Hot Plug Mirrored Memory and Hot Plug RAID). The servers support Serial Attached SCSI for increased performance, density, and scalability. They offer a multifunction network controller that is capable of supporting TOE, RSS, and iSCSI. iLO 2 provides improved remote management capabilities. The server chassis design of both the rack-optimized ProLiant DL580 G4 and the expansion-optimized ProLiant ML570 G4 delivers a combination of performance, flexibility, and serviceability.

Product environmental attributes - IT Eco Declaration 2004
Brand Manufacturer Manufacturers representative Contact person Postal address Postal code /City/ Country Telephone (incl. country code) Mobile phone (incl. country code) Fax (incl. country code) Internet site Additional information Hewlett-Packard Hewlett-Packard Name: e-mail: Name: e-mail: itecodeclaration.ww@hp.com Hans Wendschlag , HP Sweden Logo
+ + + http://www.hp.se/environment Latest version of this document can be found at: www.hp.se/itecodeclarations. The company environmental profile, which is issued for the company and isn't product related, can also be found at the same website. Check Item 14 for explanatory information regarding specific item responses.
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HP ProLiant ML570G4

Issue date 2006-05-18 Guideline document (Version of Guideline document used for completion of this declaration (month, year)) This IT Eco Declaration consists of three documents: Company environmental profile: Product environmental attributes: Divided into two sections, legal and market requirements Divided into two sections, legal and market requirements
Guideline document with extensive clarifications, comments and references.
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document this declaration has been completed.
This version of the IT Eco Declaration is adjusted to the document Product-related Environmental Attributes, issued by the European
Association for Standardizing Information and Communication Systems (ECMA), TR/70, version 1999.
This version of the IT Eco Declaration meets the basic principles of ISO14021:1999, Environmental labels and declarations Self-
declared environmental claims (Type II environmental labelling).
When references are given to standards like ISO, IEC and EN, the latest version should always be referred to.
For telecommunication products, use eco declaration for telecommunication products.
This IT Eco Declaration version can be used from October and shall be used for products announced after December 1 2003.
The IT Eco Declaration is a system for declaration of environmental aspects of IT and telecom products, developed by the Nordic IT organisations, IT-Fretagen in Sweden, ITB in Denmark, IKT-Norge in Norway and TTK ry in Finland. This IT Eco Declaration may only be used after having signed a contract with at least one of these organisations.
Association of the Swedish IT and Telecom Industry www.itforetagen.se
Norwegian IT-companies Organisation www.ikt-norge.no
IT-Brancheforeningen Kontor & Data www.itb.dk
Finnish Association of Office Technology Traders www.ttkry.com

Version June 2004

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Copyright Association of the Swedish IT and Telecom Industry 2000. Reproduction of this form without permission is prohibited by the copyright law 1960:729. The prohibition includes any kind of reproduction, by electronic or any other means.
Product identity Issue date
2006-05-18 Logo Requirement met Yes No n.a.
Product environmental attributes - Legal requirements
Item P1 P1.1 P1.2 P1.3 P1.4 P1.5 Additional information regarding each item may be found under P14. Environmental conscious design Product parts are free from, i.e. less than 0.1% by weight (b.w.), CFCs & HCFCs, asbestos, PCB & PCT (3093/94/EEC, 76/769/EEC, 6th amendment, 99/77/EEC, 82/828/EEC) Components are free from, i.e. less than 0.1% b.w., mercury (Hg), except for small amounts of mercury which are allowed in light sources. (SE SFS 1998:944) Cadmium (Cd) content of colorants, stabilizers, and surface treatments does not exceed, 0.01% b.w., as specified in 76/769/EEC, 10th amendment, 1991/338/EEC. Paints are free from lead (Pb), i.e. less than 0.1% b.w., (76/769/EEC, 8th amendment, 89/677/EEC) Paints, coatings, plastics, rubbers and seals are free from flame retardants and/or plasticizers containing Short Chain Chlorinated Paraffines (SCCPs) with more than 0,1% by weight, 10-13 carbon atoms, minimum 48% chlorine by weight, CAS number 63449-39-8 (NO MVD regulation 1544, 2000.12.13 and FI 416/2003). If the product is intended for direct and prolonged skin contact, the surfaces do not release nickel (Ni) above levels specified in (76/769/EEC, 8th amendment, 94/27/EEC) Batteries If hazardous batteries are used in the product, they are labelled. (93/86/EEC). If batteries are used in the product they are free (<0.0005% by weight) from mercury (Hg) (98/101/EC) Electrical safety, EMC and connection to the telephone network The product meets the Low Voltage Directive (LVD) regarding electrical safety (73/23/EEC & 93/68/EEC) The product meets the EMC Directive regarding electromagnetic compatibility (89/336/EEC) If product is intended for connection to a public telecom network or contains a radio transmitter, it meets the EU R&TTE Directive (1999/5/EC) The product is CE-marked (93/68/EEC) Consumable materials If a photo conductor (drum, belt etc.) is used in the product, it is free (<0.01% by mass) from cadmium (Cd) (76/769/EEC and 91/338/EEC) If an ink is used in the product, it is free (<0.01% by mass) from cadmium (Cd) (91/338/EEC) If toner/ink (or corresponding) are used in the product, they are classified and if required labelled in accordance with EU directives Packaging materials The sum of the concentration levels of lead, cadmium, mercury, and hexavalent chromium present in packaging or packaging components does not exceed 0.01% by weight (100 ppm). (94/62/EC). The product packaging material is free from CFC/HCFC.

P1.6 P2 P2.1 P2.2 P3 P3.1 P3.2 P3.3 P3.4 P4 P4.1 P4.2 P4.3 P5 P5.1 P5.2
This product meets above listed legal requirements

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Product Identity Issue date
Product environmental attributes - Market requirements
Item P6 V = Voluntary to answer. Additional information regarding each item may be found under P14. Environmental conscious design Disassembly, recycling P6.1 Gluing/welding of different material has been avoided. P6.2 P6.3 P6.4 P6.6 P6.7 P6.8 P6.9 Plastic materials in covers/housing are free from surface coating. Mechanical plastic parts >100g, consist of one material or of easily separable materials. Plastic parts >25g, have material codes according to ISO 11469. If labels are required they should be separable. (This requirement does not apply to safety labels). Product lifetime Upgrading of the product can be done with commonly available tools Processor, memory and cards of various types can be changed/upgraded. Hard disk, CD/DVD drives and / or floppy drive can be changed/upgraded.
P6.5 V Plastic parts are free from metal inlays or have inlays that can be removed with commonly available tools.
P6.10 V Spare parts are available after end of production for: P6.11 Material requirements Plastic parts >25g are free from PBB/PBDE, i.e less than 0.1% b.w.

5 years

P6.12 V Plastic parts >25g are free from flame retardant substances/preparations above 0.1% classified as R45/46, R50/51/52/53 and R60/61 (67/548/EEC) P6.13 Chemical specification of flame retardants in plastic parts >25g according to ISO 1043-4 declared below: Product cover/ housing: FR(40) Printed circuit boards: FR(16) V Other plastic parts: P6.14 P6.15 P6.16 V P6.17 V P6.18 V P7 P7.1 P7.2 V P8 P8.1 V Product cover/housing material type, specified according to ISO 1043-1 Material type PC+ABS Material type PC Electrical cable insulation material specification Light sources are free from mercury, i.e less than 0.1% b.w. If mercury is used specify: Number of lamps & max. mercury per lamp Mechanical plastic parts > 25g are free from lead (Pb), i.e. less than 0.1% b.w. Batteries Product is free from batteries defined as hazardous (91/157/EEC) Batteries are used that meet the European eco-label (EU Flower) criteria (2001/687/EC & 2001/686/EC) Energy consumption n.a. Maximum power W V Operation Low power mode W Off mode Sleep mode W Deep sleep mode If the product is in Stand by mode, it reverts to: Low power mode in min Sleep mode in Deep sleep mode in min V Off mode in 2-sided printing/copying (duplex) from 1-sided originals is an integrated product function. n.a. W W W min min Material type PVC mg
Product parts are free from beryllium (Be) and beryllium oxide (BeO), i.e. less than 0.1% b.w.

V P8.2 P8.3

Information about the energy save function is given in the user documentation. (Not applicable when no instruction is needed to operate the energy save function, i.e. the energy save function cannot be adjusted or inhibited by the user.) The product meets the requirements of ENERGY STAR.
P8.5 V The product meets the requirements of GEEA. P8.6 V Display meets the energy save requirements of the European eco-label (EU Flower) (2001/686/EC & 2001/687/EC). V Desktop or portable computer meets the energy save requirements of the European eco-label (EU Flower) (2001/686/EC & 2001/687/EC)

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Product environmental attributes - Market requirements (continued)
Item P9 P9.1 P9.2 V V = Voluntary to answer. Additional information regarding each item may be found under P14. Noise characteristics (Measured and declared according to ISO 7779 and ISO 9296) Declared A-Weighted Sound Power Level, LWAd (1B = 10 dB) Operating mode: LWAd : 7.7 B Idling mode: LWAd : 7.7 B The product meets the acoustic noise requirement of:
TCO Blue Angel European eco-label (EU Flower) Nordic Swan
P9.3 V Declared A-Weighted Sound Pressure Level, LpAm (measured at the operator position if applicable; otherwise measured at the 1m bystander positions). Operating mode: LpAm: 60 dB Idling mode: LpAm: 60 dB Test position: LpAm: Operator position Bystander positions
Test position for PC tower LpAm:
Table top Floor standing P10 Emissions P10.1 , other standard , specify:
Chemical emission test performed according to RAL-UZ The test covers: Dust
Ozone Styrene TVOC Benzene P10.2 V The product meets the requirement for chemical emission in: TCO Blue Angel Nordic Swan P10.3 Display/monitor/portable computer meets the requirement for low frequency electromagnetic fields in: MPR-II TCO prEN50279- A , -B , -C Consumable materials The photo conductor is free from selenium. If the photo conductor contains selenium there is a system for waste recovery.

P11 P11.1 P11.2

P11.3 V Safety Data Sheet/Material Safety Data Sheet (SDS/MSDS) is available for toner/ink (99/45/EC & 2001/58/EC) P11.4 V Paper containing recycled fibres and meeting requirements of ENV12281 can be used in the product. P12 P12.1 P12.2 P12.3 P13 P13.1 P13.2 V Ergonomics The computer system meets the ergonomic requirements of EN 29241-3, -7, -8 for CRT displays and EN-ISO 13406-2 for flat panel displays. The product keyboard meets the requirements of ISO 9995 and EN 29241-4. The computer input device meets the requirements of ISO 9241-9. Packaging and documentation Product packaging: material type(s): Carton - Corrugated Paper weight (kg): 7.660 kg Cushion - PE-E 1.560 kg Plastic packaging material is marked according to DIN 6120, ISO 11469 or ISO 1043, 1-4.

P13.3 V Product plastic packaging is free from chlorine P13.4 V User and product documentation are free from chlorine bleached paper P14 Additional information "The IT Eco Declaration covers the product base model only. If optional items with moving parts are added, like extra hard disks or graphic cards with fans etc, these can change energy and acoustics values for which HP can take no responsibility." Energy consumption for specific system configurations can be determined using the HP Enterprise Configurator at http://h30099.www3.hp.com/configurator/

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