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Contents

Preface. Conventions. Bibliography.

iii iii iv

1 System Overview Package. 10

Minitower Package. 11

Specifications and Characteristic Data. 12
Physical Characteristics. Environmental Specification. Electrical Specification. 13

Documentation. 15

Where to Find the Information. 16
2 System Board System Board and Backplane Boards. 18 Architectural View. 20 Chip-Set. 21
The PMC, PL/PCI Bridge Chip (82441 FX). The DBX, Data Bus Accelerator Chip (82442 FX). The PIIX3, PCI/ISA Bridge Chip (82371SB). The SIO, Super I/O Controller (NS 87308). 23 24
Devices on the Processor-Local Bus. 26
Intel Pentium II Microprocessor. Cache Memory. 26 27
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Main Memory.

Devices on the PCI Bus. 29
Integrated Drive Electronics (IDE). Universal Serial Bus (USB) Controller. 29 30
Devices on the ISA Bus. 31
Super I/O Controller. Little Ben. Other PCI and ISA Accessory Devices Under Plug and Play. 35
3 Interface Devices and Mass-Storage Drives Cirrus 5446 Graphics Controller Chip. 38
Connectors. Video Memory. Video Modes. Available Video Resolutions. 39 42
Matrox MGA Millennium II Graphics Controller Board. 44
Connectors. Video Memory. Available Video Resolutions. Video BIOS. 45 47
Audio Controller. 48 Mass-Storage Drives. 50
Hard Disk Drives. Flexible Disk Drives. CD-ROM Drives. 50
Connectors and Sockets. 51
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4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS Summary. 58 Setup Program. 60
Main Menu. Configuration Menu. Security Menu. Power Menu. 62 62
Power Saving and Ergonometry. 63
Power-On from Space-Bar. Soft Power Down. 63 63

BIOS Addresses. 64

System Memory Map. Product Identification. HP I/O Port Map (I/O Addresses Used by the System). 65

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Where to Find the Information
The following table summarizes the availability of information within the HP Vectra VL 6/xxx Series 6 PC documentation set.
Familiarization Guide Service Handbook Technical Reference Manual Key features

User Guide

User Online
Product features Product model numbers

Key features

Introducing the computer Exploring New features
Exploded view Parts list Product range CPL dates
Using the computer Connecting cables and turning on Finding on-line information Environmental Formal documents Keyboard, mouse, display, network, printer, power Finding READ.MEs and online documentation Working in comfort S/w license agreement Upgrading the computer Opening the computer Supported accessories Replacing accessories Configuring devices Fields and their options within Setup Troubleshooting Technical information System board Basic Basic Jumpers, switches and connectors Basic details Key error codes and suggestions for corrective action Repairing the computer New symptoms Detailed Jumpers, switches and connectors How to replace Upgrading Service notes Jumpers, switches and connectors Full details Some part number details How to install Configuring peripherals Full PN details New procedures Problem fixes Key fields System overview
Software license agreement Warranty information
Advanced Advanced Jumpers, switches and connectors Chip-set details Technical details Memory maps Order of tests Complete list
BIOS Power-On Self-Test routines (POST)
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System Board

The next chapter describes the graphics, disk and audio devices which are supplied with the computer. This chapter describes the components of the system board, taking in turn the components of the Processor-Local Bus, the Peripheral Component Interconnect (PCI) bus and the Industry Standard Architecture (ISA) bus.
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2 System Board System Board and Backplane Boards
System Board and Backplane Boards
Most desktop and minitower models are supplied with a Matrox graphics controller on a PCI board, and do not have the integrated graphics controller loaded on the system board.

The PMC, PL/PCI Bridge Chip (82441 FX)
This forms the bridge between the Processor Local Bus (PL Bus) and the PCI Bus.

PL Bus Interface

The PMC chip monitors each cycle that is initiated by the processor, and forwards those to the PCI bus that are not targeted at the local memory. It translates PL bus cycles into PCI bus cycles. The chip supports the SMM mode of the Pentium processor, the CPU stop clock hardware function, and the keyboard lock function. These are used by the LittleBen chip, as described on page 34.

PCI Bus Interface

Sequential PL-to-PCI memory write cycles are translated into PCI zero wait state burst cycles. The maximum PCI burst transfer can be between 256 bytes and 4 KB. The chip supports advanced snooping for PCI master bursting, and provides a pre-fetch mechanism dedicated for IDE read. The PCI arbiter supports PCI bus arbitration for up to four masters using a rotating priority mechanism. Its hidden arbitration scheme minimizes arbitration overhead.
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Main Memory Controller The main memory controller supports up to 512 MB of dynamic random
access memory (DRAM), arranged in banks of any mixture of memory capacities, provided that each bank contains a pair of identical single interline memory modules (SIMMs). With the 32 MB module from HP, the three banks on these PCs gives a total capacity of 192 MB. With a 64 MB module from HP, it will give a total capacity of 384 MB.

DBX Interface

The DBX chip, described next, is controlled by the PMC chip.
The DBX, Data Bus Accelerator Chip (82442 FX) PMC Interface
The DBX chip implements a 64-bit data path (not interleaved) between the Processor-Local bus and main memory modules. This unit takes the data from the Processor Local bus that is to be written to the memory, and takes the data out to the Processor Local bus that has been read from the memory. Storage elements are provided for bidirectional data buffering among the 64-bit PL data bus, the 64/32-bit memory data bus, and the 32-bit PCI address/data bus. There are three FIFO (first-in first-out) queues, and one read buffer for the paths between the PL, PCI, and Memory buses. This buffering is used, partly, to smooth the differences in bandwidths between the three buses, thereby improving the overall system performance. During bus operations between the PL, PCI and Memory buses, the chip receives control signals from the PMC, performs functions such as data latching, data forwarding to the destination bus, and data assemble and disassemble. Whilst accesses to the local memory are in progress, whether it be from the PL or PCI bus, the PMC maintains control of the secondary cache, DRAMs, and the datapath.

Data Path

DRAM Interface
In the case of 66 MHz PL bus operation, memory accesses have a timing pattern of 5-2-2-2 for a page-hit. This degrades to 8-2-2-2 for a row-miss, and to 11-2-2-2 for a page-miss. When the banks have been filled in an arbitrary order, back-to-back burst reads keep to the 5-2-2-2,5-2-2-2 timing
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pattern. When the banks have been filled contiguously (bank A, then bank B, then bank C), back-to-back burst reads are improved to a 5-2-2-2,3-2-2-2 timing pattern. The controller supports relocation of system management memory. It supports a read cycle power saving mode, and a CAS before RAS Intelligent Refresh mode of operation, with a CAS# driving current that is programmable. The controller is fully configurable for the characteristics of the shadow RAM (640 KB to 1 MB). It supports concurrent write back.
The PIIX3, PCI/ISA Bridge Chip (82371SB)
This chip is encapsulated in a 208 pin plastic quad flat pack (PQFP) package.
This part of the chip is responsible for transferring data between the PCI bus and the ISA expansion bus. It performs PCI-to-ISA, and ISA-to-PCI bus cycle translation. It supports the Plug-and-Play mechanism. Data buffers are provided, to isolate the PCI and ISA buses. As well as accepting cycles from the PCI bus interface, and translating them for the ISA bus, the ISA bus interface also requests the PCI master bridge to generate PCI cycles on behalf of a DMA or ISA master. The ISA bus interface contains a standard ISA bus controller and data buffering logic. It can directly support six ISA slots without external data or address buffering. The PCI master/slave IDE controller, supporting four devices, two on each of two channels, is described on page 29. The PCI USB controller, supporting two connectors, is described on page 30. The seven channel DMA controller incorporates the functionality of two 82C37 DMA controllers. Channels 0 to 3 are for 8-bit DMA devices, while channels 5 to 7 are for 16-bit devices (see page 67). The channels can be programmed for any of the four transfer modes: the three active modes (single, demand, block), can perform three different types of transfer: read, write and verify. The address generation circuitry supports a 24-bit address for DMA devices.

These processors are not available for these models of HP Vectra PC at the time of printing. This information is provided for completeness only.
The computer may execute erratically, if at all, or may overheat, if it is configured to operate at a higher processor speed than the processor is capable of supporting. This can cause damage to the computer. Setting the switches to operate at a slower speed, than the processor is capable of supporting, can still cause erratic behavior in some cases, and would reduce the instruction throughput in others.

Cache Memory

The level-2 cache memory is pre-packaged in the processor module. The level-1 cache memory is fabricated on the Pentium II processor chip. Each bank of level-1 cache memory (I-cache and D-cache) has a capacity of 16 KB. The level-2 cache memory has a capacity of 256 KB or 512 KB. The amount of both types of cache memory is set at the time of manufacture, so cannot be changed. Data is stored in lines of 32-bytes (256 bits). Thus four consecutive 64-bit transfers with the main memory are involved for each transaction.
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Main Memory

There are six main memory module sockets, arranged in three banks (A to C). One bank is already occupied by the pair of single interline memory modules (SIMMs) that contain the 16 MB or 32 MB of memory that is supplied with the computer. Different banks can have different capacities (8, 16, 32 or 64 MB), but must be composed of identical pairs of modules (2!4, 2!8, 2!16 or 2!32 MB). By installing a pair of 32 MB SIMMs in every bank, first removing the memory modules that were supplied with the computer, the maximum capacity of 192 MB of main memory can be attained. The banks can be filled, or left empty, in any order. However, there is a performance advantage to filling the banks in the order A, B, C. Each bank that is used must contain a pair of identical modules: the same speed (60 or 70 ns), the same width (32-bit or 36-bit), and the same technology (extended data out, EDO, or fast page mode, FPM). Different banks can contain different speed modules (but the computer will work at the speed of the slowest bank). Different banks can contain different technology modules. The following table indicates the recommended capacities of main memory.
Operating System Windows 3.11 Windows 95 Windows NT OS/2 Minimum Memory Capacity 4 to 8 MB 8 MB 12 MB 4 to 8 MB Recommended Memory Capacity 12 to 16 MB 16 to 24 MB 24 to 32 MB 16 MB

Cylinders per Device CHS ECHS LBA Heads per Cylinder Sectors per Track 256 M (=228) Bytes per Sector 512 Bytes per Device 528 M 8.4 G 137 G
Universal Serial Bus (USB) Controller
The OpenHCI (for USB release 1.0) USB controller is implemented as part of the PIIX3 chip (the PCI/ISA bridge). It is driven from the PCI bus, and provides support for the two stacked USB connectors on the back panel. Over-current detection and protection is provided, but shared between the two ports. USB works only if the USB interface has been enabled within the HP Setup program. Currently, only the Microsoft Windows 95 operating system provides support for the USB. The Microsoft Supplement 2.1 software, which provides support of the Universal Serial Bus, can be obtained from the Hewlett-Packard World Wide Web site: http://www.hp.com/go/vectrasupport/
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2 System Board Devices on the ISA Bus

Devices on the ISA Bus

ISA Device Super I/O Little Ben (HP ASIC) Index 15Ch 496h Data 15Dh 497h

Super I/O Controller

The Super I/O chip (NS 87308) is part of the chip set, and is described on page 24. The computer is supplied with a Logitech 2-button mouse, and a C3758A keyboard with the following features: Space bar power on, to start the computer from the Off state (if power on from keyboard is enabled in the Setup program). keys), which has the same effect as Windows key (next to the clicking the Start button on the Windows 95 task bar. key), which has the same effect as Pull-down key (next to the right clicking the right mouse button.
The computer uses 4 Kbit of Serial EEPROM implemented within a single 512 K ! 8-bit ROM chip. Serial EEPROM is ROM in which one byte at a time can be returned to its unprogrammed state by the application of appropriate electrical signals. In effect, it can be made to behave like very slow, nonvolatile RAM. It is used for storing the tatoo string, the serial number, and the parameter settings for the Setup program. When installing a new system board, the Serial EEPROM will have a blank serial number field. This will be detected automatically by the BIOS, which will then prompt the user to enter the serial number which is printed on the identification label on the back of the computer.
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Flash EEPROM (the System ROM)
The computer uses 256 KB of Flash EEPROM implemented within a single 256 K ! 8-bit ROM chip (or in two 128 K ! 8-bit chips). Flash EEPROM is ROM in which the whole memory can be returned to its unprogrammed state by the application of appropriate electrical signals to its pins. It can then be reprogrammed with the latest firmware. The System ROM contains: 64 KB of system BIOS (including the boot code, the ISA and PCI initialization, DMI, the Setup program and the Power-On Self-Test routines, plus their error messages); 32 KB of video BIOS; 32 KB of Plug-and-Play code; and 32 KB of power management code. The functions of these are summarized in Chapters 4 and 5.

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Updating the BIOS Before Considering Replacing the System Board
If the computer is faulty, but it starts up correctly, and the fault is not clearly due to the system board hardware, then it is advisable to check the BIOS version number. The BIOS version number can be found from the summary screen, or the Setup program, obtained by pressing or , respectively, when the computer has just been restarted, as described in Chapter 4. If it is not the current version of the BIOS, the System ROM should be flashed with the new version, as described on the previous page. The computer should then be re-run to see if this has cleared the problem.

Little Ben

Little Ben is an HP application specific integrated circuit (ASIC), designed to be a companion to the Super I/O chip. It interfaces between the chip-set and the processor, and contains the following: BIOS timer hardware wired 50 ms long 880 Hz beep module. automatic blinker that feeds the LEDs module with a 1 Hz oscillator signal. security protection (access, flash and anti-virus protection) For 128, 256 or 512 KB Flash EEPROMs. For the Super I/O space: the Serial EEPROM, serial ports, parallel port and mass storage drives (disable write on Flexible Disk Drive, disable boot on any drive, disable use of any embedded drive) hard and soft control for the power supply (available with Windows NT and Windows 95, but not with OS/2) Advanced power management (APM) version 1.2 (available with Windows 95 and OS/2, but not with Windows NT) glue logic (such as programmable chip selects) The computer can be turned on by typing the space-bar on the keyboard, or when it receives an external signal from a network board. When VccState and PowerGood pins are both low, all output pins are in tri-state mode, except for RemoteOnBen which continues to be driven. The power consumption has been kept as low as possible. This allows the computer to be powered from the standby power supply, and to be restarted even after a power loss has occurred.
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When the user requests a ShutDown from the operating system, the environment is first cleared. Any request to turn off the computer, from the control panel, or from the operating system, can only be granted if the computer is not locked by Little Bens lock bit (otherwise the power remains on, a red light is illuminated, and the buzzer is sounded).

Other PCI and ISA Accessory Devices Under Plug and Play
Plug and Play is an industry standard for automatically configuring the computers hardware. When you start the computer, the Plug and Play system BIOS can detect automatically which hardware resources (IRQs, DMAs, memory ranges, and I/O addresses) are used by the system-based components. All PCI accessory boards are Plug and Play, although not all ISA boards are. Check the accessory boards documentation if you are unsure. The computer is PCI 2.1 compliant, and PnP 1.1 compliant. Accessory boards which are Plug and Play are automatically configured by the BIOS. In general, in a Plug and Play configuration, resources for an ISA board have to be reserved first, and then you can plug in your board. If you want to install an ISA board when running a non Plug-and-Play operating system, such as Windows for Workgroups, you have to reserve the resources for the board using the ICU (ISA configuration utility). Failure to do so may lead to resource conflicts.
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Interface Devices and Mass-Storage Drives
This chapter describes the graphics, mass storage and audio devices which are supplied with the computer. It also summarizes the pin connections on the internal and external connectors.
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3 Interface Devices and Mass-Storage Drives Cirrus 5446 Graphics Controller Chip
Cirrus 5446 Graphics Controller Chip
Some models are supplied with a graphics controller chip integrated on the system board (all other models are supplied with a Matrox Millennium II PCI graphics controller on a board fitted in a PCI accessory slot, as described in the next section of this chapter). The Cirrus Logic CL-GD5446, can be characterized as follows: 100% hardware- and BIOS-compatible with IBM VGA display standard 64-bit video memory access with 2 MB, 50 ns, EDO, video DRAM (this is not upgradeable since it is already fitted to capacity). Hardware acceleration of graphical user interface (GUI) operations through a bit-block transfer mechanism Support for up to 4 MB, 50 ns EDO video DRAM (though space is only provided on the system board for 2 MB) Integrated 24-bit, 135 MHz RAMDAC Integrated programmable, dual-clock synthesizer Green power saving features Standard and Enhanced Video Graphics Array (VGA) modes Acceleration for playback, continuous interpolation on X, continuous interpolation on Y DDC 2B compliant. Superior TV-like quality video performance: hardware video window; YUV video support; color key, chroma key; X & Y interpolated zooming.

Connectors

The Video Electronics Standards Association (VESA) defines a standard video connector, variously known as the VESA feature connector, auxiliary connector, or pass-through connector. The graphics controller supports an input/output VESA feature connector. This connector (whose pin names are listed in a table on page 51) is integrated on the system board, and is connected directly to the pixel data bus and the synchronization signals.
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The video RAM (also known as the frame buffer) is a local block of 50 ns EDO DRAM for holding both the on-screen surface (reflecting what is currently displayed on the screen), and the off-screen surface (video frame, fonts, double buffer).

Video Modes

The following table details the standard VGA modes which are currently implemented in the video BIOS. These modes are supported by standard BIOS functions; that is, the video BIOS (which is mapped contiguously in the address range C0000h to C7FFFh) contains all the routines required to configure and access the graphics subsystem.

Standard VGA Modes

Mode No. 00h, 01h 02h, 03h 04h, 05h 06h 07h 0Dh 0Eh 0Fh 10h 11h 11h+ 11h+ 12h 12h+ 12h+ 12h+ 13h Standard CGA CGA CGA CGA MDA EGA EGA EGA EGA VGA VGA VGA VGA VGA VGA VGA VGA Interface Type text text graphics graphics text graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics Resolution 360 x x x x x x x x x x x x x x x x x 200 No. of Colors 16/256K 16/256K 4/256K 2/256K monochrome 16/256K 16/256K monochrome 16/256K 2/256K 2/256K 2/256K 16/256K 16/256K 16/256K 16/256K 256/256K Vertical Refresh 70 Hz 70 Hz 70 Hz 70 Hz 70 Hz 70 Hz 70 Hz 70 Hz 70 Hz 60 Hz 72 Hz 75 Hz 60 Hz 72 Hz 75 Hz 85 Hz 70 Hz Horizontal Refresh 31.5 kHz 31.5 kHz 31.5 kHz 31.5 kHz 31.5 kHz 31.5 kHz 31.5 kHz 31.5 kHz 31.5 kHz 31.5 kHz 37.9 kHz 37.5 kHz 31.5 kHz 37.9 kHz 37.5 kHz 43.3 kHz 31.5 kHz Notes
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Extended Video Modes

Extended Mode No. 58h, 6Ah 58h, 6Ah 58h, 6Ah 58h, 6Ah 5Ch 5Ch 5Ch 5Ch 5Ch 5Dh i 5Dh 5Dh 5Dh 5Dh 5Eh 5Fh 5Fh 5Fh 5Fh 60h i 60h 60h 60h 60h 60h d 64h 64h 64h 64h 65h 65h 65h 65h 65h 66h 66h 66h 66h 67h 67h 67h 67h 67h VESA Mode No. 102h 102h 102h ergo 102h ergo 103h 103h 103h ergo 103h ergo 103h ergo 104h 104h 104h 104h 104h ergo 100h 101h 101h ergo 101h ergo 101h ergo 105h 105h 105h 105h 105h ergo 105h ergo 111h 111h ergo 111h ergo 111h ergo 114h 114h 114h ergo 114h ergo 114h ergo 110h 110h ergo 110h ergo 110h ergo 113h 113h 113h ergo 113h ergo 113h ergo Interface Type graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics Resolution 800 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 600 No. of Colors 16/256K 16/256K 16/256K 16/256K 256/256K 256/256K 256/256K 256/256K 256/256K 16/256K 16/256K 16/256K 16/256K 16/256K 256/256K 256/256K 256/256K 256/256K 256/256K 256/256K 256/256K 256/256K 256/256K 256/256K 256/256K 65,536 65,536 65,536 65,536 65,536 65,536 65,536 65,536 65,536 32,768 32,768 32,768 32,768 32,768 32,768 32,768 32,768 32,768 Vertical Refresh 56 Hz 60 Hz 72 Hz 75 Hz 56 Hz 60 Hz 72 Hz 75 Hz 85 Hz 43 Hz i 60 Hz 70 Hz 72 Hz 75 Hz 70 Hz 60 Hz 72 Hz 75 Hz 85 Hz 43 Hz i 60 Hz 70 Hz 72 Hz 75 Hz 85 Hz 60 Hz 72 Hz 75 Hz 85 Hz 56 Hz 60 Hz 72 Hz 75 Hz 85 Hz 60 Hz 72 Hz 75 Hz 85 Hz 56 Hz 60 Hz 72 Hz 75 Hz 85 Hz Horizontal Refresh 35.2 kHz 37.8 kHz 48.1 kHz 46.9 kHz 35.2 kHz 37.9 kHz 48.1 kHz 46.9 kHz 53.7 kHz 35.5 kHz 48.3 Hz 56 kHz 58 kHz 60 kHz 31.5 kHz 31.5 kHz 37.9 kHz 37.5 kHz 43.3 kHz 35.5 kHz 48.3 kHz 56 kHz 58 kHz 60 kHz 68.3 kHz 31.5 kHz 37.9 kHz 37.5 kHz 43.3 kHz 35.2 kHz 37.8 kHz 48.1 kHz 46.9 kHz 53.7 kHz 31.5 kHz 37.8 kHz 37.5 kHz 43.3 kHz 35.2 kHz 37.8 kHz 48.1 kHz 46.9 kHz 53.7 kHz interlaced interlaced Notes

clock-doubled 8 bpp

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Extended Mode No. 68h i 68h 68h 68h 68h 69h i 6Ch i 6Dh i 6Dh d 6Dh d 6Dh d 71h 71h 71h 71h 74h i 74h 74h 74h 74h 75h i 78h 78h 78h 78h 78h 79h i 79h 79h 79h 79h 7Ch d 7Ch d
VESA Mode No. 116h 116h 116h ergo 116h ergo 116h ergo 119h 106h 107h 107h 107h ergo 107h ergo 112h 112h 112h 112h 117h 117h 117h ergo 117h ergo 117h ergo 11Ah 115h 115h 115h 115h 115h 118h 118h 118h ergo 118h ergo 118h ergo -
Interface Type graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics graphics
Resolution 1024 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 864
No. of Colors 32,768 32,768 32,768 32,768 32,768 32,768 16/256K 256/256K 256/256K 256/256K 256/256K 16.7 M 16.7 M 16.7 M 16.7 M 65,536 65,536 65,536 65,536 65,536 65,536 16.7 M 16.7 M 16.7 M 16.7 M 16.7 M 16.7 M 16.7 M 16.7 M 16.7 M 16.7 M 256/256K 256/256K
Vertical Refresh 43 Hz i 60 Hz 70 Hz 75 Hz 85 Hz 43 Hz i 43 Hz i 43 Hz i 60 Hz 71.2 Hz 75 Hz 60 Hz 72 Hz 75 Hz 85 Hz 43 Hz i 60 Hz 70 Hz 75 Hz 85 Hz 43 Hz i 56 Hz 60 Hz 72 Hz 75 Hz 85 Hz 43 Hz i 60 Hz 70 Hz 75 Hz 85 Hz 70 Hz 75 Hz
Horizontal Refresh 35.5 kHz 48.3 kHz 56 kHz 60 kHz 68.3 kHz 48 kHz 48 kHz 48 kHz 65 kHz 76 kHz 80 kHz 31.5 kHz 37.8 kHz 37.5kHz 43.3 kHz 35.5 kHz 48.3 kHz 56 kHz 60 kHz 68.3 kHz 48 kHz 35.2 kHz 37.8 kHz 48.1 kHz 46.9 kHz 53.7 kHz 35.5 kHz 48.3 kHz 56 kHz 60 kHz 68.3 kHz 63.9 kHz 67.5 kHz

Notes interlaced

non Vesa timing interlaced interlaced interlaced clock-doubled clock-doubled clock-doubled

interlaced

non Vesa timing interlaced
non Vesa timing clock-doubled clock-doubled 8 bpp
The non Vesa timing, on modes 68h, 74h and 79h, arises because the VESA pixel frequency on the 5446 is 87.7 MHz, as opposed to 94.5 MHz. This should not present major problems; most of the displays that can support such video modes are high end displays that use micro-controller based electronics.
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Available Video Resolutions
The number of colors supported is limited by the graphics device and the video memory. The resolution/color/refresh-rate combination is limited by a combination of the display driver, the graphics device, and the video memory. If the resolution/refresh-rate combination is set higher than the display can support, you risk damaging the display. The following table lists the video resolutions that are available from the BIOS:

DMA Channel Controllers

Only I/O-to-memory and memory-to-I/O transfers are allowed. I/O-to-I/O and memory-to-memory transfers are disallowed by the hardware configuration. The system controller supports seven DMA channels, each with a page register used to extend the addressing range of the channel to 16 MB. The following table summarizes how the DMA channels are allocated.
First DMA controller (used for 8-bit transfers) Channel Available SoundBlaster or ECP mode for parallel port Flexible disk I/O ECP mode for parallel port or SoundBlaster Second DMA controller (used for 16-bit transfers) Channel Function Cascade from first DMA controller SoundBlaster or Available Available Available or SoundBlaster Function

Interrupt Controllers

The system has two 8259A compatible interrupt controllers. They are arranged as a master interrupt controller and a slave that is cascaded through the master. The following table shows how the master and slave controllers are connected. The Interrupt Requests (IRQ) are numbered sequentially, starting with the master controller, and followed by the slave.
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IRQ (Interrupt Vector) IRQ0(08h) IRQ1(09h) IRQ2(0Ah) Slave IRQ IRQ8(70h) IRQ9(71h) IRQ10(72h) IRQ11(73h) IRQ12(74h) IRQ13(75h) IRQ14(76h) IRQ15(77h) IRQ3(0Bh) IRQ4(0Ch) IRQ5(0Dh) IRQ6(0Eh) IRQ7(0Fh) System Timer
Interrupt Request Description
Keyboard Controller Cascade connection from INTC2 (Interrupt Controller 2) Real Time Clock Available for accessory board (ISA/PCI) SoundBlaster 3, or Available for accessory board (ISA/PCI) Available for accessory board (ISA/PCI) Mouse, or ISA accessory board Co-processor IDE, or ISA accessory board Secondary IDE or ISA/PCI accessory board Serial Port 2, Serial Port 4, or ISA accessory board Serial Port 1, Serial Port 3, or ISA accessory board SoundBlaster 1, Parallel Port 2, or ISA accessory board Flexible Disk Controller SoundBlaster 2, Parallel Port 1, or ISA accessory board
Using the Setup program: IRQ3 can be made available by disabling serial ports 2 and 4. IRQ4 can be made available by disabling serial ports 1 and 3. IRQ5 can be made available by disabling the parallel port 2. IRQ7 can be made available by disabling parallel ports 1 and 2.
PCI Interrupt Request Lines
PCI devices generate interrupt requests using up to four PCI interrupt request lines (INTA#, INTB#, INTC#, and INTD#). When a PCI device makes an interrupt request, the request is re-directed to the system interrupt controller. The interrupt request will be re-directed to one of the IRQ lines made available for PCI devices.
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The PCI interrupt lines A, B, C and D are spread across the four inputs of the interrupt router (which is part of the PCI/ISA bridge, in the PIIX3 chip). Since most PCI devices are single-function, this allows for an even distribution of the lines. The distribution is shown in the following diagram. In this, Slot 4 is present only on minitower models (and is omitted on desktop models).

Integrated graphics A

Slot 1 A B C D

Slot 2 A B C D

Slot 3 A B C D

Slot 4 (MT) A B C D

A B PCI/ISA Bridge C D
PCI interrupts are then mapped into ISA interrupts inside the PCI/ISA Bridge (in the PIIX3 chip), by configuring registers 60h through 63h.
Bit 7 6:4 3:0 Description Routing of interrupts: when enabled, this bit routes the PCI interrupt signal to the PCcompatible interrupt signal specified in bits[3:0]. At reset, this bit is disabled (set to 1) Reserved: read as 000 IRQx# Routing Bits: these bits specify which IRQ signal to generate. Possible values are: 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15.
The possible choices given by the Setup program are 9, 10, 11, 15. If some of these are unavailable due to ISA cards, some interrupts will have to be shared. The IDE controller (device 04h, function 01h) is configured in legacy mode, and uses IRQ 14 (IRQ 15 for the secondary channel).
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Power-On Self-Test and Error Messages
This chapter describes the Power-On Self-Test (POST) routines, which are contained in the computers ROM BIOS, the error messages which can result, and the suggestions for corrective action.
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5 Power-On Self-Test and Error Messages Order in Which the Tests are Performed
Order in Which the Tests are Performed
Each time the system is powered on, or a reset is performed, the POST is executed. The POST process verifies the basic functionality of the system components and initializes certain system parameters. The POST starts by displaying a graphic screen with the initial Vectra logo when the PC is restarted. If the POST detects an error, the error message is displayed inside a view system errors screen, in which the error message utility (EMU) not only displays the error diagnosis, but the suggestions for corrective action (see page 75 for a brief summary). Error codes are no longer displayed. Devices, such as memory and newly installed hard disks, are configured automatically. The user is not requested to confirm the change. Newly removed hard disks are detected, and the user is prompted to confirm the new configuration by pressing. Note, though, that the POST does not detect when a hard disk drive has been otherwise changed. During the POST, the BIOS and other ROM data is copied into high-speed shadow RAM. The shadow RAM is addressed at the same physical location as the original ROM in a manner which is completely transparent to applications. It therefore appears to behave as very fast ROM. This technique provides faster access to the system BIOS firmware. The following table lists the POST routines in the order in which they are executed (from the shadow RAM). If the POST is initiated by a soft reset and Delete , the RAM tests are not executed and shadow RAM is not cleared. In all other respects, the POST executes in the same way following power-on or a soft reset.

Initialize the Video

8042 Self-Test Timer 0/Timer 2 Test DMA Subsystem Test Interrupt Controller Test Real-Time Clock Test Audio Test
RAM Address Line Independence Test Size Extended Memory
Real-Mode Memory Test (First 640KB)

Shadow RAM Test

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Protected Mode RAM Test (Extended RAM)
Tests protected RAM in 64 KB segments above 1 MB. (This test is not done during a reset using and Delete ). Test failure causes an error code to display. Keyboard / Mouse Tests Invokes a built-in keyboard self-test of the keyboards microprocessor and tests for the presence of a keyboard and for stuck keyboard keys. Test failure causes an error code to display. If a mouse is present, invokes a built-in mouse self-test of the mouses microprocessor and for stuck mouse buttons. Test failure causes an error code to display. Tests of Flexible Disk Drive A Tests for proper operation of the flexible disk controller. Test failure causes an error code to display. Coprocessor Tests

Keyboard Test

Mouse Test
Flexible Disk Controller Subsystem Test
Internal Numeric Coprocessor Test
Checks for proper operation of the numeric coprocessor part of the processor. Test failure causes an error code to display. Communication Port Tests
Parallel Port Test Serial Port Test
Tests the integrated parallel port registers, as well as any other parallel ports. Test failure causes an error code to display. Tests the integrated serial port registers, as well as any other serial ports. Test failure causes an error code to display. Hard Disk Drive Tests Tests for proper operation of the hard disk controller. Test failure causes an error code to display. The test does not detect hard disk replacement or changes in the size of the hard disk. System Configuration Tests Initiation of the system generation (SYSGEN) process, which compares the configuration information stored in the CMOS memory with the actual system. If a discrepancy is found, an error code will be displayed. Configures any Plug and Play device detected (either PCI or ISA): All PCI devices, and any ISA device necessary for loading the operating system will be configured for use. Any ISA device that is not required for loading the operating system, will be initialized (prepared for loading of a device driver), but not fully configured for use.
Hard Disk Controller Subsystem Test

System Generation

Plug and Play Configuration
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5 Power-On Self-Test and Error Messages Error Message Summary

Error Message Summary

The POST section of the HP BIOS no longer displays numeric error codes (such as 910B) but gives a self-explanatory, descriptive diagnosis, and a list of suggestions for corrective action. The following table summarizes the most significant of the problems that can be reported.