Intel Celeron Processor up to 1.10 GHz

Datasheet

Available at 1.10 GHz, 1 GHz, 950 MHz, 900 MHz, 850 MHz, 800 MHz, 766 MHz, 733 MHz, 700 MHz, 667 MHz, 633 MHz, 600 MHz, 566 MHz, 533 MHz, 533A MHz, 500 MHz, 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, and 300A MHz core frequencies with 128 KB level-two cache (on die); 300 MHz and 266 MHz core frequencies without level-two cache. Intels latest Celeron processors in the FC-PGA/FC-PGA2 package are manufactured using the advanced 0.18 micron technology. Binary compatible with applications running on previous members of the Intel microprocessor line. Dynamic execution microarchitecture. Operates on a 100/66 MHz, transactionoriented system bus. Specifically designed for uni-processor based Value PC systems, with the capabilities of MMX technology. Power Management capabilities.
Optimized for 32-bit applications running on advanced 32-bit operating systems. Uses cost-effective packaging technology. Single Edge Processor (S.E.P.) Package to maintain compatibility with SC242 (processor core frequencies (MHz): 266, 300, 300A, 333, 366, 400, 433). Plastic Pin Grid Array (PPGA) Package (processor core frequencies (MHz): 300A, 333, 366, 400, 433, 466, 500, 533). Flip-Chip Pin Grid Array (FC-PGA / FC-PGA2) Package (processor core frequencies (MHz); 533A, 566, 600, 633, 667, 700, 733, 766, 800, 850, 900, 950); (GHz); 1, 1.10 Integrated high-performance 32 KB instruction and data, nonblocking, levelone cache: separate 16 KB instruction and 16 KB data caches. Integrated thermal diode.
The Intel Celeron processor is designed for uni-processor based Value PC desktops and is binary compatible with previous generation Intel architecture processors. The Celeron processor provides good performance for applications running on advanced operating systems such as Microsoft* Windows*98, Windows NT*, Windows* 2000, Windows XP* and Linux*. This is achieved by integrating the best attributes of Intel processorsthe dynamic execution performance of the P6 microarchitecture plus the capabilities of MMX technologybringing a balanced level of performance to the Value PC market segment. The Celeron processor offers the dependability you would expect from Intel at an exceptional value. Systems based on Celeron processors also include the latest features to simplify system management and lower the cost of ownership for small business and home environments.

FC-PGA2 Package

FC-PGA Package

PPGA Package

S.E.P. Package
Document Number: 243658-020 January 2002
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel Celeron processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intels website at http://www.intel.com. Intel, Celeron, Pentium, MMX and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 19962002, Intel Corporation

SC242242-contact slot connector. A processor in the S.E.P. Package uses this connector to
interface with a system board.
370-pin socket (PGA370)The zero insertion force (ZIF) socket in which a processor in the
PPGA package will use to interface with a system board.
Retention mechanismA mechanical assembly which holds the package in the SC242

connector.

Processor Naming Convention
A letter(s) is added to certain processors (e.g., 533A MHz) when the core frequency alone may not uniquely identify the processor. Below is a summary of what each letter means as well as a table listing all the FC-PGA/FC-PGA2 processors for the PGA370 socket.

Table 1.

Processor Identification
Processor 300 MHz 300A MHz 366 MHz 400 MHz 433 MHz 466 MHz 500 MHz 533 MHz 533A MHz 566 MHz 600 MHz 633 MHz 667 MHz 700 MHz 733 MHz 766 MHz 800 MHz 850 MHz 900 MHz 950 MHz 1 GHz 1.10 GHz Core Frequency 300 MHz 300 MHz 366 MHz 400 MHz 433 MHz 466 MHz 500 MHz 533 MHz 533 MHz 566 MHz 600 MHz 633 MHz 667 MHz 700 MHz 733 MHz 766 MHz 800 MHz 850 MHz 900 MHz 950 MHz 1 GHz 1.10 MHz System Bus Frequency (MHz) CPUID1 065xh 066xh 066xh 066xh 066xh 066xh 066xh 066xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh
NOTES: 1. Refer to the Intel Celeron Processor Specification Update for the exact CPUID for each processor.

References

The reader of this specification should also be familiar with material and concepts presented in the following documents:
AP-485, Intel Processor Identification and the CPUID Instruction (Order Number 241618)1 AP-589, Design for EMI (Order Number 243334)1 AP-900, Identifying Support for Streaming SIMD Extensions in the Processor and Operating

System1

AP-905, Pentium III Processor Thermal Design Guidelines1 AP-907, Pentium III Processor Power Distribution Guidelines1 Intel Pentium III Processor for the PGA370 Socket at 500 MHz to 933 MHz Datasheet

(Order Number 245264)

Intel Pentium III Processor Thermal Metrology for CPUID 068h Family1 Intel Pentium III Processor Software Application Development Application Notes1 Intel Celeron Processor Specification Update (Order Number 243748) 370-Pin Socket (PGA370) Design Guidelines (Order Number 244410) Intel Architecture Software Developer's Manual (Order Number 243193) Volume I: Basic Architecture (Order Number 243190) Volume II: Instruction Set Reference (Order Number 243191) Volume III: System Programming Guide (Order Number 243192)
Intel 440EX AGPset Design Guide (Order Number 290637) Intel Celeron Processor with the Intel 440LX AGPset Design Guide

(Order Number 245088)

System Bus AGTL+ Decoupling
The S.E.P. Package and FC-PGA/FC-PGA2 packages contain high frequency decoupling capacitance on the processor substrate, where the PPGA package does not. Therefore, Celeron processors in the PGA packages require high frequency decoupling on the system motherboard. Bulk decoupling must be provided on the motherboard for proper AGTL+ bus operation for all packages. See AP-585, Pentium II Processor AGTL+ Guidelines (Order Number 243330), AP587, Pentium II Processor Power Distribution Guidelines (Order Number 243332), and the Pentium II Processor Developer's Manual (Order Number 243502) for more information.

Voltage Identification

The processors voltage identification (VID) pins can be used to automatically select the VCCCORE voltage from a compatible voltage regulator. There are five VID pins (VID[4:0]) on the S.E.P. Package, while there are only four (VID[3:0]) on the PGA packages. This is because there are no Celeron processors in the PGA package that require more than 2.05 V (see Table 2). VID pins are not signals, but rather are an open or short circuit to VSS on the processor. The combination of opens and shorts defines the processor cores required voltage. The VID pins also allow for compatibility with current and future Intel Celeron processors. Note that the 11111 (all opens) ID can be used to detect the absence of a processor core in a given slot (S.E.P. Package only), as long as the power supply used does not affect the VID signals. Detection logic and pull-ups should not affect VID inputs at the power source (see Section 7.0). External logic monitoring the VID signals or the voltage regulator may require the VID pins to be pulled-up. If this is the case, the VID pins should be pulled up to a TTL-compatible level with external resistors to the power source of the regulator. The power source chosen must be guaranteed to be stable whenever the voltage regulators supply is stable. This will prevent the possibility of the processor supply going above the specified VCCCORE in the event of a failure in the supply for the VID lines. In the case of a DC-to-DC converter, this can be accomplished by using the input voltage to the converter for the VID line pull-ups. In addition, the power supply must supply the requested voltage or disable itself.

Table 2.

Voltage Identification Definition
VID4 (S.E.P.P. only) VID1 VID1 VID1 VID0 VCCCORE 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 No Core4 2.14
NOTES: 1. 0 = Processor pin connected to VSS. 2. 1 = Open on processor; may be pulled up to TTL VIH on motherboard. 3. The Celeron processor core uses a 2.0 V power source. 4. VID4 applies only to the S.E.P. Package. VID[3:0] applies to both S.E.P. and PGA packages.

System Bus Unused Pins

All RESERVED pins must remain unconnected. Connection of these pins to VCCCORE, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future Celeron processor products. See Section 5.0 for a pin listing of the processor and the location of each RESERVED pin. For Intel Celeron processors in the S.E.P. Package, the TESTHI pin must be at a logic-high level when the core power supply comes up. For more information, please refer to erratum C26 of the Intel Celeron Processor Specification Update (Order Number 243748). Also note that the TESTHI signal is not available on Intel Celeron processors in the PGA package. PICCLK must be driven with a valid clock input and the PICD[1:0] lines must be pulled-up to 2.5 V even when the APIC will not be used. A separate pull-up resistor must be provided for each PICD line. For reliable operation, always connect unused inputs or bi-directional signals to their deasserted signal level. The pull-up or pull-down resistor value is system dependent and should be chosen such that the logic-high (VIH) and logic-low (VIL) requirements are met. For the S.E.P. Package, unused AGTL+ inputs should not be connected as the package substrate has termination resistors. On the other hand, the PGA packages do not have AGTL+ termination in their package and must have any unused AGTL+ inputs terminated through a pull-up resistor. For designs that intend to only support the FC-PGA/FC-PGA2 processors, unused AGTL+ inputs will be terminated by the processors on-die termination resistors and, thus, do not need to be terminated on the motherboard. However, the reset pin should always be terminated on the motherboard. For unused CMOS inputs, active-low signals should be connected through a pull-up resistor to meet VIH requirements and active-high signals should be connected through a pull-down resistor to meet VIL requirements. Unused CMOS outputs can be left unconnected. A resistor must be used when tying bi-directional signals to power or ground. For any signal pulled to either power or ground, a resistor will allow for system testability.

Table 10. System Bus AC Specifications (Clock) at the Processor Core Pins (for Both S.E.P. and PGA Packages)
T# Parameter System Bus Frequency T1: BCLK Period T2: BCLK Period Stability T3: BCLK High Time T4: BCLK Low Time T5: BCLK Rise Time S.E.P.P. and PPGA FC-PGA/FC-PGA2 T6: BCLK Fall Time S.E.P.P. and PPGA FC-PGA/FC-PGA2 0.34 0.40 1.36 1.6 ns ns (2.0 V0.5 V) 6, 10 10, 11 0.34 0.40 1.36 1.6 ns ns (0.5 V2.0 V) 6, 10 10, 11 4.94 4.94 15.Min Nom 66.67 Max Unit MHz ns ps ns ns 4, 5, 6 6, 8, 9 @>2.0 V 6 @<0.5 V 6 Figure Notes
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies. 2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core pin. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor core pins. 3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core pin. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V at the processor core pins. 4. The internal core clock frequency is derived from the Intel Celeron processor system bus clock. The system bus clock to core clock ratio is determined during initialization. Table 12 shows the supported ratios for each processor. 5. The BCLK period allows a +0.5 ns tolerance for clock driver variation. 6. This specification applies to the Intel Celeron processor when operating at a system bus frequency of 66 MHz. 7. See Section 3.1 for Intel Celeron processor system bus clock signal quality specifications. 8. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be measured on the rising edges of adjacent BCLKs crossing 1.25 V at the processor core pin. The jitter present must be accounted for as a component of BCLK timing skew between devices. 9. The clock drivers closed loop jitter bandwidth must be set low to allow any PLL-based device to track the jitter created by the clock driver. The 20 dB attenuation point, as measured into a 10 to 20 pF load, should be less than 500 kHz. This specification may be ensured by design characterization and/or measured with a spectrum analyzer. 10.Not 100% tested. Specified by design characterization as a clock driver requirement. 11. BCLK Rise time is measure between 0.5V2.0V. BCLK fall time is measured between 2.0 V0.5 V.
Table 11. System Bus AC Specifications (SET Clock)1, 2
T# Parameter System Bus Frequency T1: BCLK Period T2: BCLK Period Stability T3: BCLK High Time T4: BCLK Low Time T5: BCLK Rise Time T6: BCLK Fall Time 2.5 2.5 2.4 2.4 0.4 0.4 1.6 1.6 10.0 10.250 Min Nom 66.67 100.00 Max Unit MHz ns ps ns ns ns ns 3 Figure Notes 4 4, 5, 10 4, 5, 11 6, 7, 10 6, 7, 11 9, 10 9, 11 9, 10 9, 11 3, 8 3, 8
NOTES: 1. Unless otherwise noted, all specifications in this table apply to Celeron processors at all frequencies. 2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor pin. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor pins. 3. Not 100% tested. Specified by design characterization as a clock driver requirement. 4. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to core clock ratio is determined during initialization. Individual processors will only operate at their specified system bus frequency, either 66 MHz or 100 MHz, not both. Table 12 shows the supported ratios for each processor. 5. The BCLK period allows a +0.5 ns tolerance for clock driver variation. See the appropriate clock synthesizer/ driver specification for details. 6. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be measured on the rising edges of adjacent BCLKs crossing 1.25 V at the processor pin. The jitter present must be accounted for as a component of BCLK timing skew between devices. 7. The clock drivers closed loop jitter bandwidth must be set low to allow any PLL-based device to track the jitter created by the clock driver. The 20 dB attenuation point, as measured into a 10 to 20 pF load, should be less than 500 kHz. This specification may be ensured by design characterization and/or measured with a spectrum analyzer. See the appropriate clock synthesizer/driver specification for details 8. BCLK Rise time is measure between 0.5 V2.0 V. BCLK fall time is measured between 2.0 V0.5 V. 9. BCLK high time is measured as the period of time above 2.0 V. BCLK low time is measured as the period of time below 0.5 V. 10.This specification applies to Pentium III processors operating at a system bus frequency of 66 MHz. 11. This specification applies to Pentium III processors operating at a system bus frequency of 100 MHz

Table 17. System Bus AC Specifications (CMOS Signal Group) at the Processor Edge Fingers (for S.E.P. Package)
T# Parameter T14: CMOS Input Pulse Width, except PWRGOOD T14B: LINT[1:0] Input Pulse Width T15: PWRGOOD Inactive Pulse Width Min 10 Max Unit BCLKs BCLKs BCLKs Figure 8 Notes Active and Inactive states 5 6, 7
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies. 2. Not 100% tested. Specified by design characterization. 3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.50 V at the processor edge fingers. All CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V. 4. These signals may be driven asynchronously. 5. This specification only applies when the APIC is enabled and the LINT1 or LINT0 pin is configured as an edge-triggered interrupt with fixed delivery; otherwise, specification T14 applies. PWRGOOD must remain below VIL,max (Table 6) until all the voltage planes meet the voltage tolerance specifications in Table 5 and BCLK has met the BCLK AC specifications in Table 10 for at least 10 clock cycles. PWRGOOD must rise glitch-free and monotonically to 2.5 V. 6. When driven inactive or after VCCCORE, and BCLK become stable. 7. If the BCLK signal meets its AC specification within 150 ns of turning on, then the PWRGOOD inactive pulse width specification (T15) is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD must still remain below VIL,max until all the voltage planes meet the voltage tolerance specifications.
Table 18. System Bus AC Specifications (CMOS Signal Group) at the Processor Core Pins (for Both S.E.P., PGA, and FC-PGA/FC-PGA2 Packages)
T# Parameter T14: CMOS Input Pulse Width, except PWRGOOD T14B: LINT[1:0] Input Pulse Width (S.E.P.P. Only) T15: PWRGOOD Inactive Pulse Width Min 10 Max Unit BCLKs BCLKs BCLKs Figure 8 Notes Active and Inactive states 5 6, 7
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies. 2. These specifications are tested during manufacturing. 3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core pins. All CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V. 4. These signals may be driven asynchronously. 5. This specification only applies when the APIC is enabled and the LINT1 or LINT0 pin is configured as an edge-triggered interrupt with fixed delivery; otherwise, specification T14 applies. 6. When driven inactive or after VCCCORE, and BCLK become stable. 7. If the BCLK signal meets its AC specification within 150 ns of turning on, then the PWRGOOD inactive pulse width specification (T15) is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD must still remain below VIL,max until all the voltage planes meet the voltage tolerance specifications. PWRGOOD must remain below VIL,max (Table 6) until all the voltage planes meet the voltage tolerance specifications in Table 5 and BCLK has met the BCLK AC specifications in Table 10 for at least 10 clock cycles. PWRGOOD must rise glitch-free and monotonically to 2.5 V.

VCC A27# VSS Rsvd

A24# VCC

VCMOS VCC V2.5 VCC

A29# A26#

A18# VSS Rsvd

VCC VSS VSS

Rsvd D0# VSS

RESET# VCC

VCC Rsvd VSS Rsvd VCC Rsvd

VSS BCLK VCC

Rsvd Rsvd
PLL1 VREF4 VCC PLL2 D6# VSS

D15# VCC D5# D1#

VCC D17# VSS D9# VCC VREF3 VCC

Rsvd VCC Rsvd

VSS Rsvd

D10# D18# D14#

Rsvd VCC VSS

LINT0 PICD1 LINT1

Rsvd VCC

VSS PREQ#

VCC D19#

PICCLK VCC

D16# D23# VCC VSS

VSS Rsvd VCC

BP2# D22# Rsvd D27# VSS VCC VCC D42# D45# VCC D44# 12 VSS D41# D63# VSS VREF1 VSS VSS D59# VSS VCC VSS Rsvd VCC VSS Rsvd VSS Rsvd VCC Rsvd 30 VSS Rsvd VCC VSS
VCC D26# VSS D33# D35# VCC

D32# VCC VCC VSS

D25# VSS

VCC D39#

VCOREDET VCC VSS D54#

D62# VSS

VREF0 VCC

D52# D40#

D31# VSS D28# 6 VCC

D55# VCC VSS

D50# VSS

BPM0# CPUPRES# Rsvd

VSS D37# 8 9

VCC D51# 13

VSS D48# 16 17

VCC D46# D53# 22 23

VCC Rsvd 33

D29# 3

D43# 7

D47# 14 15

D57# 20

D60# 26

D61# 27

PRDY# 36

Table 49. PPGA Package Signal Listing by Pin Number
A3 A5 A7 A9 A11 A13 A15 A17 A19 A21 A23 A25 A27 A29 A31 A33 A35 A37 AA1 AA3 AA5 AA33 AA35 AA37 AB2 AB4 AB6 AB32 AB34 AB36 AC1 AC3 AC5 AC33 AC35 AC37 AD2
D29# D28# D43# D37# D44# D51# D47# D48# D57# D46# D53# D60# D61# Reserved Reserved Reserved PRDY# VSS A27# A30# VCCCORE Reserved Reserved VCCCORE VCCCORE A24# A23# VSS VCCCORE VCCCMOS Reserved A20# VSS VSS FERR# Reserved VSS
AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for Future Use Reserved for Future Use Reserved for Future Use AGTL+ Output Power/Other AGTL+ I/O AGTL+ I/O Power/Other Reserved for Future Use Reserved for Future Use Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other Power/Other Reserved for Future Use AGTL+ I/O Power/Other Power/Other CMOS Output Reserved for Future Use Power/Other
AD4 AD6 AD32 AD34 AD36 AE1 AE3 AE5 AE33 AE35 AE37 AF2 AF4 AF6 AF32 AF34 AF36 AG1 AG3 AG5 AG33 AG35 AG37 AH2 AH4 AH6 AH8 AH10 AH12 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30
A31# VREF5 VCCCORE VSS VCC1.5 A17# A22# VCCCORE A20M# IERR# FLUSH# VCCCORE Reserved A25# VSS VCCCORE VSS EDGCTRL A19# VSS INIT# STPCLK# IGNNE# VSS Reserved A10# A5# A8# A4# BNR# REQ1# REQ2# Reserved RS1# VCCCORE RS0# THERMTRIP# SLP#

AM36 AN3 AN5 AN7 AN9 AN11 AN13 AN15 AN17 AN19 AN21 AN23 AN25 AN27 AN29 AN31 AN33 AN35 AN37 B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 B30 B32 B34 B36 C1
VID1 VSS A12# A16# A6# Reserved Reserved Reserved BPRI# DEFER# Reserved Reserved TRDY# DRDY# BR0# ADS# TRST# TDI TDO D35# VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE Reserved D33#
Voltage Identification Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for Future Use Reserved for Future Use Reserved for Future Use AGTL+ Input AGTL+ Input Reserved for Future Use Reserved for Future Use AGTL+ Input AGTL+ I/O AGTL+ I/O AGTL+ I/O TAP Input TAP Input TAP Output AGTL+ I/O Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Reserved for Future Use AGTL+ I/O
C3 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 D32 D34 D36 E1 E3
VCCCORE D31# D34# D36# D45# D49# D40# D59# D55# D54# D58# D50# D56# Reserved Reserved Reserved BPM0# CPUPRES# VSS VSS VCCCORE D38# D39# D42# D41# D52# VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE D26# D25#
Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Reserved for Future Use Reserved for Future Use Reserved for Future Use AGTL+ I/O Power/Other Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O
E5 E7 E9 E11 E13 E15 E17 E19 E21 E23 E25 E27 E29 E31 E33 E35 E37 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 F32 F34 F36 G1 G3 G5
VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCOREDET Reserved D62# Reserved Reserved Reserved VREF0 BPM1# BP3# VCCCORE VCCCORE D32# D22# Reserved D27# VCCCORE D63# VREF1 VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS VCCCORE VSS D21# D23# VSS
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Reserved for Future Use Power/Other Reserved for Future Use Reserved for Future Use Reserved for Future Use Power/Other AGTL+ I/O AGTL+ I/O Power/Other Power/Other AGTL+ I/O AGTL+ I/O Reserved for Future Use AGTL+ I/O Power/Other AGTL+ I/O Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ I/O AGTL+ I/O Power/Other

Table 50. PPGA Package Signal Listing in Order by Signal Name
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A20M# ADS# BCLK BNR# BP2# BP3# BPM0# BPM1# BPRI# BR0# BSEL
AK8 AH12 AH8 AN9 AL15 AH10 AL9 AH6 AK10 AN5 AL7 AK14 AL5 AN7 AE1 Z6 AG3 AC3 AJ1 AE3 AB6 AB4 AF6 Y3 AA1 AK6 Z4 AA3 AD4 AE33 AN31 W37 AH14 G33 E37 C35 E35 AN17 AN29 AJ33
AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O CMOS Input AGTL+ I/O System Bus Clock Input AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ Input AGTL+ I/O Power/Other
CPUPRES# D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38#
C37 W1 T4 N1 M6 U1 S3 T6 J1 S1 P6 Q3 M4 Q1 L1 N3 U3 H4 R4 P4 H6 L3 G1 F8 G3 K6 E3 E1 F12 A5 A3 J3 C5 F6 C1 C7 B2 C9 A9 D8
Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O
D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DRDY# EDGCTRL FERR# FLUSH# HIT# HITM# IERR# IGNNE# INIT# LINT0/INTR LINT1/NMI LOCK# PICCLK
D10 C15 D14 D12 A7 A11 C11 A21 A15 A17 C13 C25 A13 D16 A23 C21 C19 C27 A19 C23 C17 A25 A27 E25 F16 AL27 AN19 AN27 AG1 AC35 AE37 AL25 AL23 AE35 AG37 AG33 M36 L37 AK20 J33
AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ Input AGTL+ I/O Power/Other CMOS Output CMOS Input AGTL+ I/O AGTL+ I/O CMOS Output CMOS Input CMOS Input CMOS Input CMOS Input AGTL+ I/O APIC Clock Input
PICD0 PICD1 PLL1 PLL2 PRDY# PREQ# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
J35 L35 W33 U33 A35 J37 AK26 AK18 AH16 AH18 AL19 AL17 AC1 AC37 AF4 AK16 AK24 AK30 AL11 AL13 AL21 AN11 AN13 AN15 AN21 AN23 B36 C29 C31 C33 E23 E29 E31 F10 G35 G37 L33 N33 N35 N37

Table 51. Package Dimensions (FC-PGA Package)
A1 A2 B1 B2 C1 C2 D D1 G1 G2 G3 H L P Pin TP

0.787 1.000 11.183 9.225

0.889 1.200 11.285 9.327

0.031 0.039 0.440 0.363

0.035 0.047 0.445 0.368
23.495 max 21.590 max 49.428 45.466 0.000 0.000 0.000 2.540 3.048 0.431 3.302 0.483 49.632 45.947 17.780 17.780 0.Nominal
0.925 max 0.850 max 1.946 1.790 0.000 0.000 0.000 0.100 0.120 0.017 0.130 0.019 1.954 1.810 0.700 0.700 0.035 Nominal
0.508 Diametric True Position (Pin-to-Pin)
0.020 Diametric True Position (Pin-to-Pin)
NOTES: 1. Capacitors and resistors may be placed on the pin-side of the FC-PGA package in the area defined by G1, G2, and G3. This area is a keepout zone for motherboard designers.
The bare processor die has mechanical load limits that should not be exceeded during heatsink assembly, mechanical stress testing, or standard drop and shipping conditions. The heatsink attach solution must not induce permanent stress into the processor substrate with the exception of a uniform load to maintain the heatsink to the processor thermal interface. The package dynamic and static loading parameters are listed in Table 52. For Table 52, the following apply: 1. It is not recommended to use any portion of the processor substrate as a mechanical reference or load bearing surface for thermal solutions. 2. Parameters assume uniformly applied loads Table 52. Processor Die Loading Parameters (FC-PGA Package)
Parameter Dynamic (max)1 Static (max)2 Unit
Silicon Die Surface Silicon Die Edge

200 100

lbf lbf
NOTES: 1. This specification applies to a uniform and a non-uniform load. 2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and processor interface.
Mechanical Specifications (FC-PGA2 Package)
Figure 24 is provided to aid in the design of heatsink and clip solutions as well as demonstrate where pin-side capacitors will be located on the processor. Table 53 lists the measurements for these dimensions in both inches and millimeters.
Figure 24. Package Dimensions (FC-PGA2 Package)
Table 53. Package Dimensions (FC-PGA2 Package)
Millimeters Symbol Minimum Maximum Notes Minimum Maximum Notes Inches
2.266 0.980 30.800 30.800

SLEW CTRL RTT CTRL

TDO AM AL VID2 AK VSS AJ VID3 AH

VCC HITM RSV VSS VCC HIT

VSS DBSY PWRGD VCC RS0 VSS

REQ4 RSV

REQ3 LOCK VSS

THRMDN RS2 VCC

THRMDP RSV BSEL1

VREF6 VSS

REQ0 VCC

VREF7 VCC

BSEL0 VCC VSS

THERM TRIP

IGNNE AF AE

VSS FLUSH AD AC

IERR V_1.5

FERR VCC RSV

RSV AB V_CMOS AA VCC V_2.5 Y VSS VSS W BCLK V X Z

RESET RSV RSV D15 VCC

PIN SIDE VIEW

VCC PLL2 VSS

VCC U RSV T

RSV R Q RSV P RSV M

LINT1 K

RSV VREF0

Table 55 and Table 56 provide the processor pin definitions. The signal locations on the PGA370 socket are to be used for signal routing, simulation, and component placement on the baseboard. Figure 27 provides a pin-side view of the Intel Celeron FC-PGA/FC-PGA2 processor pin-out.
Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name
Pin Name Pin Signal Group
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A20M# ADS# BCLK BNR# BP2# BP3# BPM0# BPM1# BPRI# BR0#
AK8 AH12 AH8 AN9 AL15 AH10 AL9 AH6 AK10 AN5 AL7 AK14 AL5 AN7 AE1 Z6 AG3 AC3 AJ1 AE3 AB6 AB4 AF6 Y3 AA1 AK6 Z4 AA3 AD4 AE33 AN31 W37 AH14 G33 E37 C35 E35 AN17 AN29
AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O CMOS Input AGTL+ I/O System Bus Clock AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ Input AGTL+ I/O
BSEL0 BSEL15 CPUPRES# D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35#
AJ33 AJ31 C37 W1 T4 N1 M6 U1 S3 T6 J1 S1 P6 Q3 M4 Q1 L1 N3 U3 H4 R4 P4 H6 L3 G1 F8 G3 K6 E3 E1 F12 A5 A3 J3 C5 F6 C1 C7 B2
CMOS I/O Power/Other Power/Other AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O
D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DRDY# EDGCTRL 2,8 FERR# FLUSH# GND GND GND GND GND

STPCLK#

TCK TDI TDO TESTHI (S.E.P.P. only) THERMDN THERMDP

I I O I O I

THERMTRIP#
VCC1.5 (PGA packages only) VCC2.5 (PGA packages only) VCCCMOS (PGA packages only)
Table 59. Alphabetical Signal Reference (Sheet 7 of 7)
VCOREDET (PGA packages only) VID[4:0] (S.E.P.P.) VID[3:0] (PGA packages only)
The VCOREDET signal will float for 2.0 V core processors and will be grounded for the Celeron FC-PGA/FC-PGA2 processor with a 1.5V core voltage. The VID (Voltage ID) pins can be used to support automatic selection of power supply voltages. These pins are not signals, but are either an open circuit or a short circuit to VSS on the processor. The combination of opens and shorts defines the voltage required by the processor. The VID pins are needed to cleanly support voltage specification variations on Intel Celeron processors. See Table 2 for definitions of these pins. The power supply must supply the voltage that is requested by these pins, or disable itself. These input signals are used by the AGTL+ inputs as a reference voltage. AGTL+ inputs are differential receivers and will use this voltage to determine whether the signal is a logic high or logic low. For the FC-PGA/FC-PGA2 packages, VREF is typically 2/3 of VTT
VREF[7:0] (PGA packages only)

Signal Summaries

Table 60 through Table 63 list attributes of the Celeron processor output, input, and I/O signals.

Table 60. Output Signals

Name Active Level Clock Signal Group
CPUPRES# (PGA packages only) FERR# IERR# PRDY# SLOTOCC# (S.E.P.P. only) TDO THERMDN THERMTRIP# VCOREDET (PGA packages only) VID[4:0] (S.E.P.P.) VID[3:0] (PGA packages)
Low Low Low Low Low High N/A Low High
Asynch Asynch Asynch BCLK Asynch TCK Asynch Asynch Asynch
Power/Other CMOS Output CMOS Output AGTL+ Output Power/Other TAP Output Power/Other CMOS Output Power/Other

Asynch

Power/Other

Table 61. Input Signals

Name Active Level Clock Signal Group Qualified
A20M# BPRI# BCLK DEFER# FLUSH# IGNNE# INIT# INTR LINT[1:0] NMI PICCLK PREQ# PWRGOOD RESET# RS[2:0]# RTTCTRL SLEWCTRL SLP# SMI# STPCLK# TCK TDI TESTHI (S.E.P.P. only) THERMDP TMS TRST# TRDY#
Low Low High Low Low Low Low High High High High Low High Low Low N/A N/A Low Low Low High High High N/A High Low Low
Asynch BCLK BCLK Asynch Asynch Asynch Asynch Asynch Asynch Asynch Asynch BCLK BCLK Asynch Asynch Asynch Asynch Asynch TCK Asynch Asynch TCK Asynch BCLK
CMOS Input AGTL+ Input System Bus Clock AGTL+ Input CMOS Input CMOS Input CMOS Input CMOS Input CMOS Input CMOS Input APIC Clock CMOS Input CMOS Input AGTL+ Input AGTL+ Input Power/Other Power/Other CMOS Input CMOS Input CMOS Input TAP Input TAP Input Power/Other Power/Other TAP Input TAP Input AGTL+ Input

Always Always Always Always
Always 1 Always 1 Always 1 APIC disabled mode APIC enabled mode APIC disabled mode Always Always Always Always Always

During Stop-Grant state

Always
NOTE: 1. Synchronous assertion with active TRDY# ensures synchronization.
Table 62. Input/Output Signals (Single Driver)
BSEL[1:0] BP[3:2] BR0# A[31:3]# ADS# BPM[1:0]# D[63:0]# DBSY# DRDY# LOCK# REQ[4:0]#
Low Low Low Low Low Low Low Low Low Low Low
Asynch BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK
Power/Other AGTL+ I/O AGTL+I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O AGTL+ I/O
Always Always Always ADS#, ADS#+1 Always Always DRDY# Always Always Always ADS#, ADS#+1
Table 63. Input/Output Signals (Multiple Driver)
BNR# HIT# HITM# PICD[1:0]

Low Low Low High

BCLK BCLK BCLK PICCLK
AGTL+ I/O AGTL+ I/O AGTL+ I/O APIC I/O