Intended Audience

The TPS is intended to provide detailed, technical information about the D815EEA2 and D815EPEA2 boards and their components to the vendors, system integrators, and other engineers and technicians who need this level of information. It is specifically not intended for general audiences.
What This Document Contains
Chapter 5 Description A description of the hardware used on the D815EEA2 and D815EPEA2 boards A map of the resources of the board The features supported by the BIOS Setup program The contents of the BIOS Setup programs menus and submenus A description of the BIOS error messages, beep codes, and POST codes
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
Notes call attention to important information.

CAUTION

Cautions are included to help you avoid damaging hardware or losing data.

WARNING

Warnings indicate conditions, which if not observed, can cause personal injury.
Intel Desktop Board D815EEA2/D815EPEA2 Technical Product Specification

Other Common Notation

# (NxnX) Used after a signal name to identify an active-low signal (such as USBP0#) When used in the description of a component, N indicates component type, xn are the relative coordinates of its location on the D815EEA2 and D815EPEA2 boards, and X is the instance of the particular part at that general location. For example, J5J1 is a connector, located at 5J. It is the first connector in the 5J area. Gigabyte (1,073,741,824 bytes) Kilobyte (1024 bytes) Kilobit (1024 bits) 1000 bits per second Megabyte (1,048,576 bytes) Megabytes per second Megabit (1,048,576 bits) Megabits per second An address or data value ending with a lowercase h indicates a hexadecimal value. Volts. Voltages are DC unless otherwise specified. This symbol is used to indicate third-party brands and names that are the property of their respective owners.
GB KB Kbit kbits/sec MB MB/sec Mbit Mbit/sec xxh x.x V

Contents

1 Product Description
1.1 Board Differences...12 1.1.1 Feature Level Differences...12 1.1.2 Identifying Universal Boards...13 Overview....14 1.2.1 Feature Summary....14 1.2.2 Manufacturing Options...15 1.2.3 Board Layout...16 1.2.4 Block Diagrams....17 Online Support...19 Operating System Support...19 Design Specifications....20 Processor....23 System Memory....24 Chipsets....26 1.8.1 Intel 815E Chipset...26 1.8.2 Intel 815EP Chipset...31 I/O Controller....36 1.9.1 Serial Ports....36 1.9.2 Parallel Port...37 1.9.3 Diskette Drive Controller...37 1.9.4 Keyboard and Mouse Interface...37 Graphics Subsystems....38 1.10.1 Intel 815E Graphics Subsystem..38 1.10.2 Intel 815EP Graphics Subsystem...42 Audio Subsystem....43 1.11.1 AD1885 Audio Codec...43 1.11.2 Audio Connectors....43 LAN Subsystem (Optional)....45 1.12.1 Intel 82562ET Platform LAN Connect Device..45 1.12.2 RJ-45 LAN Connector LEDs...45 Hardware Management Subsystem...46 1.13.1 Hardware Monitor Component...46 1.13.2 Chassis Intrusion Detect Connector (Optional)..46 1.13.3 Fan Control and Monitoring...47 CNR Connector (Optional)...47 Power Management....48 1.15.1 Software Support...48 1.15.2 Hardware Support...52 Introduction.....57 Memory Map....57 I/O Map....58

81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93.
Hard Disk Drives Submenu....132 Removeable Devices Submenu...132 ATAPI CDROM Drives Submenu...133 Exit Menu.....133 BIOS Error Messages....135 Uncompressed INIT Code Checkpoints...137 Boot Block Recovery Code Checkpoints..137 Runtime Code Uncompressed in F000 Shadow RAM..138 Bus Initialization Checkpoints...141 Upper Nibble High Byte Functions...141 Lower Nibble High Byte Functions...142 Beep Codes....143 Diagnostic LED Codes....145
What This Chapter Contains
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 Board Differences...12 Overview....14 Online Support...19 Operating System Support...19 Design Specifications....20 Processor....23 System Memory....24 Chipsets....26 I/O Controller....36 Graphics Subsystems....38 Audio Subsystem....43 LAN Subsystem (Optional)....45 Hardware Management Subsystem...46 CNR Connector (Optional)...47 Power Management....48

1.1 Board Differences

1.1.1 Feature Level Differences
This TPS describes these Intel Desktop boards: D815EEA2 and D815EPEA2. Table 1 summarizes the differences between these boards.

Table 1.

D815EEA2
Summary of Board Differences
Includes the Intel 815E Chipset, which includes the Intel 82815 Graphics and Memory Controller Hub (GMCH) Provides these video features: AGP universal connector and an optional Digital Video Output (DVO) connector

D815EPEA2

Includes the Intel 815EP Chipset, which includes the Intel 82815EP Memory Controller Hub (MCH) Provides this video feature: AGP universal connector

Product Description

Identifying Universal Boards
The Universal versions of the D815EEA2 and D815EPEA2 can be identified by an uppercase U on the silkscreen of the board. Figure 1 shows the location of the Universal board designator.
INTEL DESKTOP BOARD D815EEA2 / D815EPEA2

BATTERY

SIDE UP XBT1061

OM12012

Figure 1. Location of Universal Board Designator
Unless otherwise stated, all information pertaining to standard boards also apply to Universal boards.

1.2 Overview

1.2.1 Feature Summary

Feature Summary

ATX (11.55 inches by 8.20 inches) Support for either an Intel Pentium III processor in a Flip Chip Pin Grid Array (FC-PGA) package or an Intel Celeron processor in an FC-PGA package Three 168-pin SDRAM Dual Inline Memory Module (DIMM) sockets Support for up to 512 MB system memory Support for single-sided or double-sided DIMMs Chipsets The D815EEA2 board includes the Intel 815E Chipset, consisting of: Intel 82815 Graphics and Memory Controller Hub (GMCH) Intel 82801BA I/O Controller Hub (ICH2) SST 49LF004A 4 Mbit Firmware Hub (FWH) The D815EPEA2 board includes the Intel 815EP Chipset, consisting of: Intel 82815EP Memory Controller Hub (MCH) Intel 82801BA I/O Controller Hub (ICH2) I/O Control Video

At boot, the BIOS displays a message indicating that any installed memory above 512 MB has not been initialized.
If more than four rows of 133 MHz SDRAM are populated, the BIOS will display a message indicating that it will initialize installed memory up to 512 MB at 100 MHz.
For information about Obtaining the PC Serial Presence Detect (SPD) Specification Refer to Table 4, page 19
Table 6 lists the supported DIMM configurations.

Table 6.

DIMM Capacity 32 MB 32 MB 48 MB 64 MB 64 MB 64 MB 96 MB 96 MB 128 MB 128 MB 128 MB 128 MB 192 MB 192 MB 256 MB 256 MB 256 MB 512 MB
Notes: 1. 2. 3. If the number of SDRAM devices is greater than nine, the DIMM will be double sided. Front side population/back side population indicated for SDRAM density and SDRAM organization. In the second column, DS refers to double-sided memory modules (containing two rows of SDRAM) and SS refers to single-sided memory modules (containing one row of SDRAM).
Supported Memory Configurations
Number of Sides DS SS DS DS SS SS DS DS DS DS SS SS DS DS DS DS SS DS SDRAM Density 16 Mbit 64 Mbit 64/16 Mbit 64 Mbit 64 Mbit 128 Mbit 64 Mbit 128/64 Mbit 64 Mbit 128 Mbit 128 Mbit 256 Mbit 128 Mbit 128/64 Mbit 128 Mbit 256 Mbit 256 Mbit 256 Mbit SDRAM Organization Front-side/Back-side 2 M x 8/2 M x M x 16/empty 4 M x 16/2 M x M x 16/4 M x M x 8/empty 8 M x 16/empty 8 M x 8/4 M x M x 16/4 M x M x 8/8 M x M x 16/8 M x M x 8/empty 16 M x 16/empty 16 M x 8/8 M x M x 8/8 M x M x 8/16 M x M x 16/16 M x M x 8/empty 32 M x 8/32 M x 8 Number of SDRAM devices 16 (Note 1) (Notes 1 and 2) (Notes 1 and 2) 8 (Notes 1 and 2) 16 (Note 1) 8 (Notes 1 and 2) 12 (Notes 1 and 2) 16 (Notes 1 and 2) 16 (Notes 1 and 2) 8 (Notes 1 and 2) (Notes 1 and 2)

1.8 Chipsets

This section describes the chipsets used by the D815EEA2 and D815EPEA2 boards: The D815EEA2 board uses the Intel 815E Chipset, described below. The D815EPEA2 board uses the Intel 815EP Chipset, described in Section 1.8.2, beginning on page 31.

Intel 815E Chipset

The Intel 815E chipset consists of the following devices: 82815 Graphics and Memory Controller Hub (GMCH) with Accelerated Hub Architecture (AHA) bus 82801BA I/O Controller Hub (ICH2) with AHA bus SST 49LF004A Firmware Hub (FWH) The GMCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the AHA bus. The ICH2 is a centralized controller for the boards I/O paths. The FWH provides the nonvolatile storage of the BIOS. The Intel 815E chipset provides the interfaces shown in Figure 5.
ATA-66/100 System Bus SDRAM Bus Network USB
82815 Graphics and Memory Controller Hub (GMCH) AHA Bus 82801BA I/O Controller Hub (ICH2) SST 49LF004A Firmware Hub (FWH)
Digital Video Display AGP Output Interface Bus
LPC Bus SMBus PCI Bus AC Link

OM11891

Figure 5. Intel 815E Chipset Block Diagram
For information about The Intel 815E chipset The resources used by the chipset The chipsets compliance with ACPI, APM, and AC 97 Refer to http://developer.intel.com/design/chipsets/815e Chapter 2 Table 4, page 19

1.8.1.1

Intel 82815 Graphics and Memory Controller Hub (GMCH)
The GMCH provides the following: An integrated Synchronous DRAM memory controller with autodetection of SDRAM An interface for a single AGP device or a Graphics Performance Accelerator (GPA) card An interface for an optional digital video output (DVO) connector for a flat panel, digital CRT, or TV-out Support for ACPI Rev. 2.0 and APM Rev. 1.2 compliant power management

1.8.1.2

Intel 82801BA I/O Controller Hub (ICH2)
The ICH2 provides the following: 33 MHz PCI bus interface Support for up to six PCI master devices Low Pin Count (LPC) interface that supports an LPC-compatible I/O controller Support for two Master/DMA devices Integrated IDE controller that supports Ultra DMA (33 MB/sec) and ATA-66/100 mode (66 MB/sec, 100 MB/sec) Integrated LAN Media Access Controller Universal Serial Bus interface with two USB controllers providing four ports in a UHCI Implementation (additional USB ports provided with the optional SMSC LPC47M142 I/O controller) Power management logic for ACPI Rev. 1.0b compliance System Management Bus (SMBus clock and data lines also routed to PCI bus connector 2) Real-time clock with 256-byte battery-backed CMOS RAM AC 97 digital link for audio codec, including: AC 97 2.1 compliance Logic for PCM in, PCM out, and mic input PCI functions for audio Communication and Network Riser (CNR) interface 1.8.1.2.1 IDE Interfaces
The ICH2s IDE controller has two independent bus-mastering IDE interfaces that can be independently enabled. The IDE interfaces support the following modes: Programmed I/O (PIO): CPU controls data transfer. 8237-style DMA: DMA offloads the CPU, supporting transfer rates of up to 16 MB/sec. Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates of up to 33 MB/sec. ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible. ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH2 ATA-100 logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to 88 MB/sec.

USB ports 0 and 1 82801BA I/O Controller Hub (ICH2) USB USB ports 2 and 3 Back panel USB connectors Back panel USB connectors

Optional Configuration

USB ports 0 and 2 82801BA I/O Controller Hub (ICH2) USB CNR connector USB USB ports 1 and 3 SMSC LPC47M142 LPC Bus I/O Controller USB USB ports 4 and 5 Front panel USB connector Back panel USB connectors USB port accesible through a USB connector on an optional CNR add-in card Back panel USB connectors

OM11892

Figure 6. USB Port Configurations
Computer systems that have an unshielded cable attached to a USB port may not meet FCC Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use shielded cable that meets the requirements for full-speed devices.
For information about The location of the USB connectors on the back panel The signal names of the back panel USB connectors The location of the optional front panel USB connector The signal names of the optional front panel USB connector The USB specification and UHCI Refer to Figure 13, page 64 Table 21, page 65 Figure 16, page 78 Table 45, page 79 Table 4, page 20

1.8.1.2.3

Real-Time Clock, CMOS SRAM, and Battery
The real-time clock provides a time-of-day clock and a multicentury calendar with alarm features. The real-time clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are reserved for BIOS use. A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the computer is not plugged into a wall socket, the battery has an estimated life of three years. When the computer is plugged in, the standby current from the power supply extends the life of the battery. The clock is accurate to 13 minutes/year at 25 C with 3.3 VSB applied. The time, date, and CMOS values can be specified in the BIOS Setup program. The CMOS values can be returned to their defaults by using the BIOS Setup program.
If the battery and AC power fail, custom defaults, if previously saved, will be loaded into CMOS SRAM at power-on.

1.8.1.3

SST 49LF004A 4 Mbit Firmware Hub (FWH)
The system BIOS is stored in the FWH.

Intel 815EP Chipset

The Intel 815EP chipset consists of the following devices: 82815EP Memory Controller Hub (MCH) with Accelerated Hub Architecture (AHA) bus 82801BA I/O Controller Hub (ICH2) with AHA bus SST 49LF004A Firmware Hub (FWH) The MCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the AHA bus. The ICH2 is a centralized controller for the boards I/O paths. The FWH provides the nonvolatile storage of the BIOS. The Intel 815EP chipset provides the interfaces shown in Figure 7.

82815EP Memory Controller Hub (MCH) AHA Bus 82801BA I/O Controller Hub (ICH2) SST 49LF004A Firmware Hub (FWH)
LPC Bus AGP Bus SMBus PCI Bus AC Link

OM11318

Figure 7. Intel 815EP Chipset Block Diagram
For information about The Intel 815EP chipset The resources used by the chipset The chipsets compliance with ACPI, APM, and AC 97 Refer to http://developer.intel.com/design/chipsets/815ep Chapter 2 Table 4, page 20

1.8.2.1

Intel 82815EP Memory Controller Hub (MCH)
The MCH provides the following: An integrated Synchronous DRAM memory controller with autodetection of SDRAM An interface for a single AGP device Support for ACPI Rev. 2.0 and APM Rev. 1.2 compliant power management

1.8.2.2

The ICH2 provides the following: 33 MHz PCI bus interface Support for up to six PCI master devices Low Pin Count (LPC) interface that supports an LPC-compatible I/O controller Support for two Master/DMA devices Integrated IDE controller that supports Ultra DMA (33 MB/sec) and ATA-66/100 mode (66 MB/sec, 100 MB/sec) Integrated LAN Media Access Controller Universal Serial Bus interface with two USB controllers providing four back panel ports in a UHCI Implementation (additional USB ports provided with the optional SMSC LPC47M142 I/O controller) Power management logic for ACPI Rev. 1.0b compliance System Management Bus (SMBus clock and data lines also routed to PCI bus connector 2) Real-time clock with 256-byte battery-backed CMOS RAM AC 97 digital link for audio codec, including: AC 97 2.1 compliance Logic for PCM in, PCM out, and mic input PCI functions for audio Communication and Network Riser (CNR) interface 1.8.2.2.1 IDE Interfaces
The ICH2s IDE controller has two independent bus-mastering IDE interfaces that can be independently enabled. The IDE interfaces support the following modes: Programmed I/O (PIO): CPU controls data transfer. 8237-style DMA: DMA offloads the CPU, supporting transfer rates of up to 16 MB/sec. Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates of up to 33 MB/sec. ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible. ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH2 ATA-100 logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to 88 MB/sec.

1.8.2.2.2

The ICH2 contains two separate USB controllers. The D815EPEA2 board has four USB ports; one USB peripheral can be connected to each port. For more than four USB devices, an external hub can be connected to any of the ports. The D815EPEA2 board fully supports the Universal Hub Controller Interface (UHCI). In the standard configuration, the D815EPEA2 boards four USB ports are implemented with stacked back panel connectors, routed through the ICH2, as shown in Figure 8. With the optional SMSC LPC47M142 I/O controller, the D815EPEA2 board supports up to seven USB ports. The SMSC LPC47M142 I/O controller provides four ports: two ports implemented with stacked back panel connectors and two ports routed to the optional front panel USB connector at location J8F1. The ICH2 provides three ports: two ports are implemented with stacked back panel connectors and the other port is accessible through a CNR add-in card, as shown in Figure 8. The D815EPEA2 board fully supports the Universal Hub Controller Interface (UHCI).
Figure 8. USB Port Configurations

1.8.2.2.3

1.8.2.3

1.9 I/O Controller

The D815EEA2 and D815EPEA2 boards support either of two I/O controllers: The standard SMSC LPC47M132 I/O controller or The optional SMSC LPC47M142 I/O controller Both I/O controllers provide the following features: Low pin count (LPC) interface 3.3 V operation Two serial ports One parallel port with Extended Capabilities Port (ECP) and Enhanced Parallel Port (EPP) support Serial IRQ interface compatible with serialized IRQ support for PCI systems PS/2-style mouse and keyboard interfaces Interface for one 1.2 MB, 1.44 MB, or 2.88 MB diskette drive Intelligent power management, including a programmable wake up event interface PCI power management support Fan control One fan control output Two fan tachometer inputs The optional SMSC LPC47M142 I/O controller provides an additional USB hub. The BIOS Setup program provides configuration options for the I/O controller.
For information about The USB hubs on the D815EEA2 board The USB hubs on the D815EPEA2 board SMSC LPC47M132 and LPC47M142 I/O controllers Refer to Section 1.8.1.2.2, page 28 Section 1.8.2.2.2, page 33 http://www.smsc.com

Serial Ports

The D815EEA2 and D815EPEA2 boards each have two serial ports. Serial port A is located on the back panel. Serial port B is accessible using the connector at location J8H1. The serial ports NS16C550-compatible UARTs support data transfers at speeds up to 115.2 kbits/sec with BIOS support. The serial ports can be assigned as COM1 (3F8h), COM2 (2F8h), COM3 (3E8h), or COM4 (2E8h).
For information about The location of the serial port A connector The signal names of the serial port A connector The location of the serial port B connector The signal names of the serial port B connector Refer to Figure 13, page 64 Table 24, page 66 Figure 16, page 78 Table 44, page 79

Targeted System Power Global States G0 working state G1 sleeping state Sleeping States S0 working S1 CPU stopped CPU States C0 working C1 stop grant Device States D0 working state D1, D2, D3 device specification specific. D3 no power except for wake up logic. D3 no power except for wake up logic. D3 no power for wake up logic, except when provided by battery or external source.

(Note 1)

Full power > 30 W 5 W < power < 30 W

G1 sleeping state G2/S5

S3 suspend to RAM. Context saved to RAM. S5 soft-off. Context not saved. Cold boot is required. No power to the system.

No power

Power < 5 W

(Note 2)

G3 mechanical off AC power is disconnected from the computer.

Notes: 1. 2.

No power to the system so that service can be performed.
Total system power is dependent on the system configuration, including add-in boards and peripherals powered by the system chassis power supply. Dependent on the standby power consumption of wake-up devices used in the system.

1.15.1.2.2

Wake Up Devices and Events
Table 11 lists the devices or specific events that can wake the computer from specific states.
Table 11. Wake Up Devices and Events
from this state S1, S3, S5 S1, S3, S5 (Note 1) S1, S3, S5 (Notes 1 and 2) S1, S3, S5 (Notes 1 and 2) S1, S3 (Note 3) S1, S3 S1, S3
These devices/events can wake up the computer Power switch RTC alarm Wake on LAN technology connector (optional) PME# Modem (back panel serial port A) USB PS/2 keyboard
Notes: 1. 2. 3. S5 events are supported only on PCI bus connector 2.
For the Wake on LAN technology connector and PME#, S5 is disabled by default in the BIOS Setup program. Setting these options to Power On will enable a wake-up event from LAN in the S5 state. Wake from CNR modem is not supported on the D815EEA2 and D815EPEA2 boards.
The use of these wake up events from an ACPI state requires an operating system that provides full ACPI support. In addition, software, drivers, and peripherals must fully support ACPI wake events.

For information about The location of the power connector The signal names of the power connector The BIOS Setup programs Power menu The ATX specification Refer to Figure 14, page 69 Table 34, page 71 Section 4.6, page 127 Table 3, page 19

1.15.2.2

Fan Connectors
The D815EEA2 and D815EPEA2 boards both have two standard fan connectors and one optional fan connector. The functions of these connectors are described in Table 12.

Table 12.

Connector Processor fan
Fan Connector Descriptions
Silkscreen Label Fan 1 Reference Designator J1B1 Function Provides +12 V DC for a processor fan or active fan heatsink. A tachometer feedback connection is also provided. Provides +12 V DC for a system or chassis fan. The fan voltage can be switched on or off, depending on the power management state of the computer. A tachometer feedback connection is also provided. Provides +12 V DC for a system or chassis. The fan voltage can be switched on or off, depending on the power management state of the computer.

System fan

Chassis fan (optional)
For information about The location of the fan connectors The signal names of the fan connectors
Refer to Figure 14, page 69 Section 2.8.2.2, page 69

1.15.2.3

Wake on LAN Technology
For Wake on LAN technology, the +5 V standby line for the power supply must be capable of providing adequate +5 V standby current. Failure to provide adequate standby current when implementing Wake on LAN technology can damage the power supply. Refer to Section 2.11.3 on page 94 for additional information.
The optional Wake on LAN technology connector is present only on boards that do not have the Intel 82562ET PLC device, which is part of the optional onboard LAN subsystem. Wake on LAN technology enables remote wakeup of the computer through a network. The LAN subsystem PCI bus network adapter monitors network traffic at the Media Independent Interface. Upon detecting a Magic Packet frame, the LAN subsystem asserts a wakeup signal that powers up the computer. Depending on the LAN implementation, the D815EEA2 and D815EPEA2 boards support Wake on LAN technology in the following ways: Through the optional Wake on LAN technology connector (APM only) Through the PCI bus PME# signal for PCI 2.2 compliant LAN designs (ACPI only) Through the onboard LAN subsystem when enabled in Setup (ACPI only)
The Wake on LAN technology connector can be used with PCI bus network adapters that have a remote wake up connector, as shown in Figure 11. Network adapters that are PCI 2.2 compliant assert the wakeup signal through the PCI bus signal PME# (pin A19 on the PCI bus connectors).

Network Interface Card

Remote Wake up connector

16 bytes

Audio (Sound Blaster Pro-compatible)
8 bytes 8 bytes 8 bytes 8 bytes 1 byte 7 bits 8 bytes 12 bytes 32 bytes 8 bytes 6 bytes 1 byte 8 bytes 2 bytes 8 bytes 4 bytes 1 byte 4 bytes
LPT3 LPT2 COM4/video (8514A) COM2 Secondary IDE channel command port Secondary IDE channel status port LPT1 Intel 82815 GMCH/AGP Intel 82815 GMCH/AGP COM3 Diskette channel 1 Primary IDE channel command port COM1 Edge/level triggered PIC ECP port, LPTn base address + 400h PCI configuration address register Turbo and reset control register PCI configuration data register continued

Technical Reference

Table 14.

I/O Map (continued)

Size Description Primary bus master IDE registers Secondary bus master IDE registers ICH2 (ACPI + TCO) D815EEA2/D815EPEA2 board resource ICH2 LAN controller ICH2 AC 97 audio master ICH2 AC 97 audio mixer ICH2 AC 97 modem mixer ICH2 USB controller #1 ICH2 USB controller #2 ICH2 (SMBus) Intel 82801BA PCI bridge

Address (hex)

FFA0 - FFAbytes FFA8 - FFAF 8 bytes 96 contiguous bytes starting on a 128-byte divisible boundary 64 contiguous bytes starting on a 64-byte divisible boundary 64 contiguous bytes starting on a 64-byte divisible boundary 64 contiguous bytes starting on a 64-byte divisible boundary 256 contiguous bytes starting on a 256-byte divisible boundary 256 contiguous bytes starting on a 256-byte divisible boundary 32 contiguous bytes starting on a 32-byte divisible boundary 32 contiguous bytes starting on a 32-byte divisible boundary 16 contiguous bytes starting on a 16-byte divisible boundary 4096 contiguous bytes starting on a 4096-byte divisible boundary

* ** ***

Default, but can be changed to another address range. Dword access only Byte access only
Some additional I/O addresses are not available due to ICH2 addresses aliassing.
For information about ICH2 addressing Refer to Section 1.3, page 19

2.4 DMA Channels

Table 15.

DMA Channels

Data Width 8 or 16 bits 8 or 16 bits 8 or 16 bits 8 or 16 bits 8 or 16 bits 16 bits 16 bits 16 bits System Resource Audio Audio/parallel port Diskette drive Parallel port (for ECP or EPP)/audio DMA controller Open Open Open

DMA Channel Number

2.5 PCI Configuration Space Map
Table 16. PCI Configuration Space Map
Device Number (hex) 02 1E 1F 1F 1F 1F 1F 1F 1F 0A 0B 0C 0D

(Note)

Bus Number (hex) 01 02
Function Number (hex) 00 00
Description Memory controller of Intel 82815 component PCI to AGP bridge Intel 82815 GMCH (graphics memory controller hub)/ Intel 82815EP MCH (memory controller hub) Hub link to PCI bridge Intel 82801BA ICH2 PCI to LPC bridge IDE controller ICH2 USB controller #1 SMBus controller ICH2 USB controller #2 AC 97 audio controller (optional) AC 97 modem controller (optional) LAN controller (optional) PCI bus connector 1 (J7B1) PCI bus connector 2 (J8B2) PCI bus connector 3 (J9B2) PCI bus connector 4 (J9B1) PCI bus connector 5 (J10B1) Add-in AGP card

Table 41.

Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33
AGP Universal Connector (J6C1)
Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 Signal Name Not connected +5 V +5 V Not connected Ground INTB# CLK REQ# Vcc3.3 ST0 ST2 RBF# Ground Not connected SBA0 Vcc3.3 SBA2 SB_STB Ground SBA4 SBA6 Reserved Ground +3.3 V (aux) Vcc3.3 AD31 AD29 Vcc3.3 AD27 AD25 Ground AD_STB1 AD23 Pin A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 Signal Name Vddq AD22 AD20 Ground AD18 AD16 Vddq FRAME# Reserved Ground Reserved Vcc3.3 TRDY# STOP# PME# Ground PAR AD15 Vddq AD13 AD11 Ground AD9 C/BE0# Vddq AD_STB0# AD6 Ground AD4 AD2 Vddq AD0 VREFG_C Pin B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 Signal Name Vddq AD21 AD19 Ground AD17 C/BE2# Vddq IRDY# +3.3 V (aux) Ground Reserved Vcc3.3 DEVSEL# Vddq PERR# Ground SERR# C/BE1# Vddq AD14 AD12 Ground AD10 AD8 Vddq AD_STB0 AD7 Ground AD5 AD3 Vddq AD1 VREFC_G
Signal Name +12 V TYPEDET# Reserved Not connected Ground INTA# RST# GNT1# Vcc3.3 ST1 Reserved PIPE# Ground WBF# SBA1 Vcc3.3 SBA3 SBSTB# Ground SBA5 SBA7 Reserved Ground Reserved Vcc3.3 AD30 AD28 Vcc3.3 AD26 AD24 Ground AD_STB1# C/BE3#

Table 42.

Pin 33
Diskette Drive Connector (J6H2)
Signal Name Ground Ground Key Ground Ground Ground Ground Ground Not connected Ground Ground Ground Ground Not connected Ground Ground Ground Pin 34 Signal Name DENSEL Reserved FDEDIN FDINDX# (Index) FDM00# (Motor Enable A) Not connected FDDS0# (Drive Select A) Not connected FDDIR# (Stepper Motor Direction) FDSTEP# (Step Pulse) FDWD# (Write Data) FDWE# (Write Enable) FDTRK0# (Track 0) FDWPD# (Write Protect) FDRDATA# (Read Data) FDHEAD# (Side 1 Select) DSKCHG# (Diskette Change)

Table 43.

IDE Connectors (J6H1, Primary and J6G2, Secondary)
Pin Signal Name Ground Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Key Ground Ground Ground Ground Ground Reserved GPIO_DMA66_Detect_Pri (GPIO_DMA66_Detect_Sec) DAG2 (Address 2) Chip Select 3P# [Chip Select 3S#] Ground
Signal Name Reset IDE Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 Ground DDRQ0 [DDRQ1] I/O Write# I/O Read# IOCHRDY DDACK0# [DDACK1#] IRQ 14 [IRQ 15] DAG1 (Address 1) DAG0 (Address 0) Chip Select 1P# [Chip Select 1S#] Activity#
Signal names in brackets ([ ]) are for the secondary IDE connector.

External I/O Connectors

Figure 16 shows the locations of the external I/O connectors on the D815EEA2 and D815EPEA2 boards.

D815EEA2 and D815EPEA2 Board Environmental Specifications

Specification

2.15 Regulatory Compliance
This section describes the D815EEA2 and D815EPEA2 boards compliance with U.S. and international safety and electromagnetic compatibility (EMC) regulations.

2.15.1

Safety Regulations
Table 58 lists the safety regulations the D815EEA2 and D815EPEA2 boards comply with when correctly installed in a compatible host system.

Table 58.

Regulation UL 1950/CSA C22.2 No. 950, rd 3 edition EN 60950, 2 Edition, 1992 (with Amendments 1, 2, 3, and 4) IEC 60950, 2 Edition, 1991 (with Amendments 1, 2, 3, and 4) EMKO-TSE (74-SEC) 207/94
Title Bi-National Standard for Safety of Information Technology Equipment including Electrical Business Equipment. (USA and Canada) The Standard for Safety of Information Technology Equipment including Electrical Business Equipment. (European Union) The Standard for Safety of Information Technology Equipment including Electrical Business Equipment. (International) Summary of Nordic deviations to EN 60950. (Norway, Sweden, Denmark, and Finland)

2.15.2

EMC Regulations
Table 59 lists the EMC regulations the D815EEA2 and D815EPEA2 boards comply with when correctly installed in a compatible host system.

Table 59.

Regulation FCC (Class B) ICES-003 (Class B) EN55022: 1994 (Class B)
Title Title 47 of the Code of Federal Regulations, Parts 2 and 15, Subpart B, Radiofrequency Devices. (USA) Interference-Causing Equipment Standard, Digital Apparatus. (Canada) Limits and methods of measurement of Radio Interference Characteristics of Information Technology Equipment. (European Union) Information Technology Equipment Immunity Characteristics Limits and methods of measurement. (European Union) Australian Communications Authority, Standard for Electromagnetic Compatibility. (Australia and New Zealand) Limits and methods of measurement of Radio Disturbance Characteristics of Information Technology Equipment. (International) Information Technology Equipment Immunity Characteristics Limits and Methods of Measurements. (International)

Table 92.

Beep 11

Beep Codes

Description Refresh failure Parity cannot be reset First 64 KB memory failure Timer not operational Not used 8042 GateA20 cannot be toggled Exception interrupt error Display memory R/W error Not used CMOS Shutdown register test error Invalid BIOS (e.g., POST module not found, etc.)
5.6 Diagnostic LEDs (Optional)
The optional enhanced diagnostics feature consists of a hardware decoder and four LEDs located between the LAN connector and the parallel port connector on the back panel. This feature requires no modifications to the chassis (other than I/O back panel shield) or cabling. Figure 26 shows the location of the diagnostic LEDs. Table 93 lists the diagnostic codes displayed by the LEDs.

OM11462A

Figure 26. Diagnostic LEDs

Table 93.

Display

Diagnostic LED Codes

BIOS Operation Power on, starting BIOS Display
Amber Amber Amber Green Green Amber Amber Green Amber Green Amber Green Green Green Amber Green Amber Amber Green Green Green Amber Green Green Amber Green Green Green Green Green Green Green

BIOS Operation Undefined

Amber Amber Amber Amber Green Amber Amber Amber Amber Green Amber Amber Green Green Amber Amber Amber Amber Green Amber Green Amber Green Amber Amber Green Green Amber Green Green Green Amber

Recovery mode

Undefined

Processor, cache, etc.

Memory, auto-size, shadow, etc. PCI bus initialization

IDE bus initialization

USB initialization

Booting operating system

Note: Undefined states are reserved for future use.
After the computer has booted, the diagnostic LEDs remain green during normal operation.

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Order Number: A52560-002

Revision History

Revision -001 Revision History First release of the Desktop Boards D815EEA2, D815EPEA2, D815EFV, and D815EPFV Product Guide Intel Date March 2001
If an FCC declaration of conformity marking is present on the board, the following statement applies: FCC Declaration of Conformity This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. For questions related to the EMC performance of this product, contact: Intel Corporation 5200 N.E. Elam Young Parkway Hillsboro, OR 97124 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate the receiving antenna. Increase the separation between the equipment and the receiver. Connect the equipment to an outlet on a circuit other than the one to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help.
Canadian Department of Communications Compliance Statement: This digital apparatus does not exceed the Class B limits for radio noise emissions from digital apparatus set out in the Radio Interference Regulations of the Canadian Department of Communications. Le prsent appareil numerique nmet pas de bruits radiolectriques dpassant les limites applicables aux appareils numriques de la classe B prescrites dans le Rglement sur le broullage radiolectrique dict par le ministre des Communications du Canada. Disclaimer Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Intel D815EEA2, D815EPEA2, D815EFV, and D815EPFV desktop boards may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from Intel Corporation by going to the World Wide Web site at: http://www.intel.com or by calling 1-800-548-4725.

Characteristic Form Factors
4 Mbit Firmware Hub (FWH)
The D815EPEA2 and D815EPFV boards include the Intel 815EP Chipset, consisting of: Intel 82815EP Memory Controller Hub (MCH) I/O Control Audio Intel 82801BA I/O Controller Hub (ICH2)
4 Mbit Firmware Hub (FWH) SMSC LPC47M132 LPC bus I/O controller
An audio subsystem that includes the: Intel 82801BA ICH2 digital controller (AC link output) Analog Devices Inc. AD1885 audio codec continued

Table 2.

Feature Summary (continued)
Specification The D815EEA2 and D815EFV boards include: Intel 82815E integrated graphics support AGP universal connector supporting 1x, 2x, or 4x AGP cards or a Graphics Performance Accelerator (GPA)

Characteristic

Rear panel VGA connector The D815EPEA2 and D815EPFV boards include an AGP universal connector supporting 1x, 2x, or 4x AGP cards Peripheral Interfaces Two serial ports: one back panel and one internal connector Four USB ports: four back panel and two optional front panel One parallel port Two IDE interfaces with Ultra DMA (33 MB/sec) and ATA-66/100 support One diskette drive interface PS/2 keyboard and mouse ports Expansion Capabilities For D815EEA2 and D815EPEA2 boards: Five PCI add-in card connector (SMBus routed to PCI bus connector 2, S5 wake from PCI bus connector 2) One AGP universal connector For D815EFV and D815EPFV boards: Three PCI add-in card connectors (SMBus routed to PCI bus connector 2, S5 wake from PCI bus connector 2)
One AGP universal connector Intel/AMI BIOS
4 Mbit Firmware Hub (FWH) Support for Advanced Power Management (APM), Advanced Configuration and Power Interface (ACPI), Plug and Play, and SMBIOS ACPI S3 Suspend to RAM (STR) sleep state Support for PCI Local Bus Specification Revision 2.2 Wake on PS/2 keyboard and USB ports Support for both ACPI Rev. 2.0 and APM Rev. 1.2 PC 99 and PC 99A Heceta 4 supporting: Remote diode temperature sense Voltage sense to detect out of range values Fan tachometer Allows add-in SCSI controllers to use the same LED as the onboard I/O controller
Instantly Available Technology Power Management PC Design Compliance Hardware Monitor

SCSI LED Connector

Desktop Board Features

Manufacturing Options

Table 3 describes the manufacturing options of the boards.
Table 3. Manufacturing Options
Specification One CNR connector: Slot shared with PCI bus connector 5 on D815EEA2 and D815EPEA2 boards. Slot shared with PCI bus connector 3 on D815EFV and D815EPFV boards. Interface for optional Digital Visual Interface (DVI) card to support Flat Panel, Digital CRT, or TV out (D815EEA2 and D815EFV boards only). Routes mic in and line out to the front panel. Provides access to two additional USB ports, routed through the optional SMSC LPC47M142 LPC bus I/O controller. Intel 82562ET that provides a basic interface to the RJ-45 connector with integrated LEDs located on the back panel. SMSC LPC47M142 LPC bus I/O controller Support for system wake up using an add-in network interface card with remote wake up capability.

The BIOS cannot determine DIMM size or type when not initialized. If more than 512 MB system memory is installed, the BIOS displays a message at boot indicating memory above 512 MB has not been initialized. The message indicates that additional information is available in Setup. The first time the BIOS detects this condition, a pause follows the message with the option to enter Setup or to <ESC> and continue to boot. The message continues to be displayed at boot time as long as the condition exists, however, the BIOS will not pause on subsequent detection. Setup displays the installed memory configuration and shows memory above 512 MB as not initialized.
Unbuffered single or double-sided DIMMs Serial Presence Detect (SPD) memory Non-ECC and ECC DIMMs (ECC DIMMs will operate in non-ECC mode only) 3.3 V memory (only) Suspend to RAM support Mixed speed DIMM configuration will default to the slowest speed DIMM installed.
The board supports the processor and memory module combinations shown in Table 5.
Table 5. Processor and Memory Module Combinations
PC100 Memory Modules will operate at 100 MHz will operate at 100 MHz will operate at 100 MHz will operate at 100 MHz PC133 Memory Modules will operate at 100 MHz will operate at 100 MHz will operate at 100 MHz will operate at 133 MHz (see note below)
Processor Type (System Bus Frequency) Intel Celeron processor (66 MHz) Intel Celeron processor (100 MHz) Intel Pentium III processor (100 MHz) Intel Pentium III processor (133 MHz)
100 MHz system bus frequency processors will support 133 MHz memory; however, the memory will operate at 100 MHz. For 133 MHz operation, only four sides of memory can be used; two double sided DIMMs, or one double sided DIMM and two single sided DIMMs. If more than four sides are used, the memory will only run at 100 MHz.

Chipsets

The D815EEA2 and D815EFV boards include the following chipset: Intel 82815E Graphics Memory Controller Hub (GMCH) with Accelerated Hub Architecture (AHA) bus Intel 82801BA I/O Controller Hub (ICH2) with AHA bus 4 Mbit Firmware Hub (FWH) Intel 82815EP Memory Controller Hub (MCH) with AHA bus Intel 82801BA I/O Controller Hub (ICH2) with AHA bus 4 Mbit Firmware Hub (FWH)

Real-Time Clock

The desktop boards have a time-of-day clock and 100-year calendar. A battery on the desktop board keeps the clock current when the computer is turned off.

USB Support

The desktop boards have four back panel USB ports. Front panel USB support is available as an option to provide an additional two USB ports. You can connect two USB peripheral devices directly to the computer without an external hub. To attach more than two devices, connect an external hub to either of the built-in ports. With the optional SMSC LPC47M142 I/O controller, the boards support up to seven USB ports. The SMSC LPC47M142 I/O controller provides four ports: two ports implemented with stacked back panel connectors and two ports routed to the optional front panel USB connector at location J8F1. The ICH2 provides three ports: two ports are implemented with stacked back panel connectors and the other port is accessible through a CNR add-in card. The desktop board supports the Universal Host Controller Interface (UHCI) and takes advantage of standard software drivers written to be compatible with UHCI.
Computer systems that have an unshielded cable attached to a USB port might not meet FCC Class B requirements even if no device or a low-speed USB device is attached to the cable. Use a shielded cable that meets the requirements for a full-speed USB device.
PCI Enhanced IDE Interface
The PCI enhanced IDE interface handles the exchange of information between the processor and peripheral devices like hard disks, CD-ROM drives, and Iomega ZIP drives inside the computer. The interface supports: Up to four IDE devices (such as hard drives) ATAPI devices (such as CD-ROM drives) PIO Mode 3 and PIO Mode 4 devices Ultra DMA (33 MB/sec) and ATA-66/100 protocols Support for laser servo (LS-120) drives

Add-in Card Connectors

The D815EEA2 and D815EPEA2 boards have the following ATX-compliant add-in card connectors: Five PCI bus connectors (PCI bus connector 5 slot shared with CNR) One AGP universal connector One optional CNR connector (slot shared with PCI bus connector 5)
The D815EFV and D815EPFV boards have the following microATX-compliant add-in card connectors: Three PCI bus connectors (PCI bus connector 3 slot shared with CNR) One AGP universal connector One optional CNR connector (slot shared with PCI bus connector 3)

AGP Universal Connector

The AGP universal connector is a high-performance interface for graphics-intensive applications such as 3D graphics. AGP is independent of the PCI bus and is intended for use with graphical display devices. The AGP universal connector supports AGP 1x, 2x, and 4x. The AGP universal connector also supports the GPA add-in card on D815EEA2 and D815EFV boards. An AGP card retention mechanism (RM) is included with the boxed desktop board. Installation instructions are presented in Chapter 2.

Audio Subsystem

The boards have an AC 97 compliant audio subsystem. The audio subsystem includes these features: Split digital/analog architecture for improved S/N (signal-to-noise) ratio: > 90 dB Power management support for APM 1.2 and ACPI 2.0 (driver dependent) 3-D stereo enhancement Intel 82801BA I/O Controller Hub (ICH2) Analog Devices Inc. AD1885 analog codec
The audio subsystem consists of the following:
The line out connector is designed to power headphones or amplified speakers only. Poor audio quality may occur if passive (non-amplified) speakers are connected to this output. Audio drivers and utilities are available from Intels World Wide Web site: http://support.intel.com/support/motherboards/desktop
The BIOS provides the Power-On Self-Test (POST), the BIOS Setup program, the PCI and IDE auto-configuration utilities, and the video BIOS. The BIOS is stored in the Firmware Hub. The BIOS can be upgraded by following the instructions in Chapter 3.

PCI Auto Configuration

If you install a PCI add-in board in your computer, the PCI auto-configuration utility in the BIOS automatically detects and configures the resources (IRQs, DMA channels, and I/O space) for that add-in board. You do not need to run the BIOS Setup program after you install a PCI add-in board.

IDE Auto Configuration

If you install an IDE device (such as a hard drive) in your computer, the IDE auto-configuration utility in the BIOS automatically detects and configures the device for your computer. You do not need to run the BIOS Setup program after installing an IDE device. You can override the autoconfiguration options by specifying manual configuration in the BIOS Setup program. To use ATA-66/100 features, the following items are required: An ATA-66/100 peripheral device An ATA-66/100 compatible cable ATA-66/100 operating system device drivers

Security Passwords

The BIOS includes security features that restrict whether the BIOS Setup program can be accessed and who can boot the computer. A supervisor password and a user password can be set for the Setup and for booting the computer, with the following restrictions: The supervisor password gives unrestricted access to view and change all Setup options. If only the supervisor password is set, pressing <Enter> at the password prompt of Setup gives the user restricted access to Setup. If both the supervisor and user passwords are set, you must enter either the supervisor password or the user password to access Setup. Setup options are then available for viewing and changing depending on whether the supervisor or user password was entered. Setting a user password restricts who can boot the computer. The password prompt is displayed before the computer is booted. If only the supervisor password is set, the computer boots without asking for a password. If both passwords are set, you can enter either password to boot the computer.

OM11310

Figure 10. Installing the I/O Shield
Installing the Desktop Board
Refer to your chassis manual for instructions on installing the desktop board. Seven screws for the D815EEA2 and D815EPEA2 boards and six screws for the D815EFV and D815EPFV boards secure the desktop board to the chassis. Figure 11 and Figure 12 respectively show the locations of the mounting screw holes.
You will need a Phillips (#2 bit) screwdriver. Refer to Appendix B for regulatory requirements and installation instructions and precautions.
Only qualified technical personnel should attempt this procedure. Disconnect the computer from its power source before performing the procedures described here. Failure to disconnect the power before you open the computer can result in personal injury or equipment damage.

OM11625

Figure 11. Location of the Mounting Screw Holes for the D815EEA2 and D815EPEA2 Boards

OM11626

Figure 12. Location of the Mounting Screw Holes for the D815EFV and D815EPFV Boards

Installing a Processor

To install a processor, follow these instructions: 1. Observe the precautions in Before You Begin (see page 25). 2. Locate the processor socket and raise the socket handle completely (see Figure 13, B). 3. Aligning the pins of the processor with the socket, insert the processor into the socket (see Figure 13, A and C). 4. Close the handle completely (see Figure 13, D).

OM11639

Figure 13. Installing the Processor in the Processor Socket
For instructions on how to install a fan heatsink for a processor 1 GHz or greater, see page 39.
5. Place the fan heatsink on top of the processor (see Figure 14).

OM11619

Figure 14. Attaching the Heatsink to the Processor
6. Attach the fan heatsink clips to the processor socket (see Figure 15).

OM11620

Fan heatsink clip Processor socket
Figure 15. Attaching the Fan Heatsink Clips to the Processor Socket
7. Connect the processor fan cable to the processor fan connector (see Figure 16).

OM11156

Figure 16. Connecting the Processor Fan Cable to the Processor Fan Connector

Removing the Processor

To remove the processor, follow these instructions: 1. Observe the precautions in Before You Begin (see page 25). 2. Disconnect the processor fan cable. 3. Detach the fan heatsink clips. 4. Remove the heatsink. 5. Raise the socket handle completely. 6. Remove the processor.
Installing a 1 GHz Processor Fan Heatsink
To install a processor, follow the instructions given on page 36, Figure 13. Follow the instructions below to install the fan heatsink on a processor 1 GHz or greater. 1. Attach the fan heatsink to the processor making sure the notch at the bottom of the heatsink is aligned on the processor socket label side (see Figure 17, A).

BIOS [drive letter:path]

Press <Enter>. Follow the instructions provided with your CD writer to copy the extracted files from the hard disk to the CD while creating a bootable CD. 9. The CD or diskette now holds the new BIOS files, the Intel Flash Update Utility, and the recovery files.
The AUTOEXEC.BAT file provided with the update files updates the boot block and BIOS core. You will be asked to reboot the system when the update process is complete. Do not interrupt the process or the system may not be capable of rebooting. 1. Boot the computer with the BIOS upgrade diskette in drive A. During system boot, the AUTOEXEC.BAT file provided with the update files will automatically run the BIOS update process. 2. The AUTOEXEC.BAT file updates the BIOS in two parts: first updating the boot block and displaying the Operation completed successfully message and then updating the BIOS core. 3. When the update process is complete, the monitor will display a message telling you to remove the diskette and to reboot the system. 4. As the computer boots, check the BIOS identifier (version number) to make sure the upgrade was successful. If a logo appears, press <Esc> to view the POST messages. 5. To enter the BIOS Setup program, press <F2> when you see the message:
Press <F2> to Run SETUP

6. 7. 8. 9. 10. 11.

For proper operation, load the BIOS Setup program defaults. To load the defaults, press <F9>. To accept the defaults, press <Enter>. In Setup, enter the settings you wrote down before beginning the BIOS upgrade. To save the settings, press <F10>. To accept the settings, press <Enter>. Turn off the computer and reboot.

Recovering the BIOS

It is unlikely that anything will interrupt the BIOS update, however, if an interruption occurs, the BIOS could be damaged. The following steps explain how to recover the BIOS if an update fails. The following procedure uses recovery mode for the Setup program. See page 48 for more information on Setup modes.
Because of the small amount of code available in the boot block area, there is no video support. You will not see anything on the screen during this procedure. Monitor the procedure by listening to the speaker and looking at the diskette drive LED. 1. Turn off the computer, disconnect the computers power cord, and disconnect all external peripherals. 2. Remove the computer cover and locate the configuration jumper block (J9G2) (see Figure 26). 3. Remove the jumper from all pins as shown below to set recovery mode for Setup.
4. Insert the bootable BIOS update diskette into diskette drive A. 5. Replace the computer cover, connect the power cord, turn on the computer, and allow it to boot. (The recovery process will take a few minutes. Listen to the speaker and watch for drive A activity.) Upon applying power, drive A will begin to show activity. In about a minute, two beeps are heard and drive A activity ceases (temporarily) indicating the successful recovery of the BIOS core. Drive A activity will begin again followed by two more beeps indicating the successful recovery of the boot block. This sequence of events indicates that successful BIOS recovery has taken place. A series of continuous beeps indicates that BIOS recovery has failed. 6. If recovery fails, return to step 1 and repeat the recovery process. 7. If recovery is successful, turn off the computer, and disconnect its power cord. 8. Remove the computer cover and continue with the following steps. 9. On the jumper block (J9G2), reinstall the jumper back on pins 1-2 as shown below to set normal mode for Setup.

10. Leave the update diskette in drive A, replace the computer cover, and connect the computers power cord. 11. Turn on the computer and continue with the BIOS update (see page 53).
You can use the BIOS Setup program to change the configuration information and boot sequence for the computer. This chapter tells you how to access the BIOS Setup program and lists Setup features, options, and default settings.
For reference purposes, you should write down the current Setup settings. When you make changes to the settings, update this record.

BIOS Setup Program Modes

The BIOS Setup program has three modes of operation: Normal mode for normal operations Configure mode for clearing passwords (see Chapter 2 for instructions) Recovery mode for BIOS recovery
The BIOS Setup Program Operating mode is controlled by the setting of the configuration jumper block. The jumper is set to normal mode at the factory.
The Setup menus described in this section apply to the desktop boards with BIOS identifier EA815.20A.86A. Desktop boards with other BIOS identifiers might have differences in some of the Setup menu screens. The BIOS Setup program can be used to view and change the BIOS settings for the computer. The BIOS Setup program is accessed by pressing the <F2> key after the Power-On Self-Test (POST) memory test begins and before the operating system boot begins. The menu bar is shown below.

Maintenance

Table 8.

Advanced

Security
BIOS Setup Program Menu Bar Main
Allocates resources for hardware components
Clears passwords and Boot Integrity Service (BIS)* credentials, and configures extended configuration memory settings
Configures advanced features available through the chipset
Sets passwords and security features
Saves or discards changes to Setup program options
Configures Selects boot power options management features
* For information about the BIS, refer to the Intel World Wide Web site at: http://developer.intel.com/design/security/index1.htm
Table 9 shows the function keys available for menu screens.
Table 9. BIOS Setup Program Function Keys
Description Selects a different menu screen Moves cursor up or down Moves cursor to the next field Executes command or selects the submenu Load the default configuration values for the current menu Save the current values and exits the BIOS Setup program Exits the menu
BIOS Setup Program Function Key <> or <> <> or <> <Tab> <Enter> <F9> <F10> <Esc>

Maintenance Menu

This menu is used to clear passwords, to access the extended configuration submenu, and to access processor information. Setup only displays this menu in the configure mode. See page 48 for information about setting the configure mode. To access this menu, select Maintenance on the menu bar at the top of the screen.

Main Menu

To access this menu, select Main on the menu bar at the top of the screen.
Table 12 describes the Main Menu. This menu reports processor and memory information and is for configuring the system date and system time.

Table 12.

Feature BIOS Version Processor Type Processor Speed System Bus Frequency Cache RAM Total Memory Memory Bank 0 Memory Bank 1 Memory Bank 2 Language Processor Serial Number System Time System Date
Options No options No options No options No options No options No options No options Description Displays the version of the BIOS. Displays processor type. Displays processor speed. Displays the system bus frequency. Displays the size of second-level cache and whether it is ECC-capable. Displays the total amount of RAM. Displays the amount and type of RAM in the memory banks. Selects the current default language used by the BIOS.
English (default) Espanol
Disabled (default) Enables and disables the processor serial number. (Present only when a Pentium III processor is installed.) Enabled Hour, minute, and second Day of week Month/day/year Specifies the current time. Specifies the current date.

Advanced Menu

To access this menu, select Advanced on the menu bar at the top of the screen.
PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration
Table 13 describes the Advanced Menu. This menu is used for setting advanced features that are available through the chipset.

Table 13.

Feature Extended Configuration PCI Configuration Boot Configuration
Options No options No options No options Description If Used is displayed, User-Defined has been selected in Extended Configuration under the Maintenance Menu. Configures individual PCI slots IRQ priority. When selected, displays the PCI Configuration submenu. Configures Plug and Play and the Numlock key, and resets configuration data. When selected, displays the Boot Configuration submenu. Configures peripheral ports and devices. When selected, displays the Peripheral Configuration submenu. Specifies type of connected IDE device. When selected, displays the Diskette Configuration submenu. Configures Event Logging. When selected, displays the Event Log Configuration submenu. Configures video features. When selected, displays the Video Configuration submenu.
Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration

Maximum Capacity LBA Mode Control Multi-Sector Transfers
Displays the capacity of the drive. Enables or disables LBA mode control. Specifies number of sectors per block for transfers from the hard disk drive to memory. Check the hard disk drives specifications for optimum setting. Specifies the PIO mode.

PIO Mode

Note: These configuration options appear only if an IDE device is installed.

Feature Ultra DMA

Primary/Secondary IDE Master/Slave Submenus (continued)
Options Disabled (default) Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 None Description Specifies the Ultra DMA mode for the drive.

Cable Detected (Note)

Displays the type of cable connected to the IDE interface: 40-conductor or 80-conductor (for ATA-66/100 devices).
Diskette Configuration Submenu
To access this menu, select Advanced on the menu bar, then Diskette Configuration.
The submenu represented by Table 19 is used for configuring the diskette drive.

Table 19.

Feature Diskette Controller Floppy A
Options Disabled Enabled (default) Not Installed 360 KB 1.2 MB 720 KB 2.88 MB 5" 5" 3" 3" Disables or enables write-protect for the diskette drive. Description Disables or enables the integrated diskette controller. Specifies the capacity and physical size of diskette drive A.
1.44/1.25 MB 3" (default) Diskette Write-Protect Disabled (default) Enabled
Event Log Configuration Submenu
To access this menu, select Advanced on the menu bar, then Event Log Configuration.
The submenu represented by Table 20 is used to configure the event logging features.

Table 20.

Feature Event Log Event Log Validity View Event Log Clear All Event Logs Event Logging Mark Events As Read
Options No options No options [Enter] No (default) Yes Disabled Enabled (default) Yes (default) No Marks all events as read. Enables logging of events. Description Indicates if there is space available in the event log. Indicates if the contents of the event log are valid. Displays the event log. Clears the event log after rebooting.
Video Configuration Submenu
To access this menu, select Advanced on the menu bar, then Video Configuration.
The submenu represented in Table 21 is for configuring the video features.

Table 21.

Feature Primary Video Adapter
Options AGP (default) PCI Description Selects primary video adapter to be used during boot. Integrated indicates that the onboard graphics subsystem is enabled on the D815EEA2 and D815EFV boards only. 1x AGP Card, 2x AGP Card, or 4x AGP Card indicates that the BIOS has detected a 1x, 2x, or 4x AGP card. Installing an add-in AGP card disables the onboard graphics subsystem on the D815EEA2 and D815EFV boards.

AGP Hardware Detected No Options

Security Menu

To access this menu, select Security from the menu bar at the top of the screen.
The menu represented by Table 22 is for setting passwords and security features.

Table 22.

Feature Supervisor Password Is User Password Is Set Supervisor Password Set User Password Clear User Password

(Note 1)

Options No options No options Description Reports if there is a supervisor password set. Reports if there is a user password set.
If no password entered previously:
Password can be up to seven Specifies the supervisor password. alphanumeric characters. Password can be up to seven Specifies the user password. alphanumeric characters. Yes (default) No Limited No Access View Only Full (default) Sets BIOS Setup Utility access rights for user level. Clears the user password.

User Access Level

(Note 2)

Unattended Start

(Notes 1, 3, and 4)
Enabled Disabled (default)
Enabled allows system to complete the boot process without a password. The keyboard remains locked until a password is entered. A password is required to boot from a diskette.
Notes: 1. 2. 3. This feature appears only if a user password has been set. This feature appears only if both a user password and a supervisor password have been set. If both Legacy USB Support (in the Peripheral Configuration submenu) and Unattended Start (in the Security menu) are enabled, USB aware operating systems can unlock a PS/2 style keyboard and mouse without requiring the user to enter a password. When Unattended Start is enabled, a USB aware operating system may override user password protection if used in conjunction with a USB keyboard and mouse without requiring the user to enter a password.

Power Menu

To access this menu, select Power from the menu bar at the top of the screen.
Maintenance Main Advanced Security Power APM ACPI Boot Exit
The menu represented in Table 23 is for setting the power management features.

Table 23.

Feature APM ACPI After Power Failure
Options No Options No Options Stays Off Last State (default) Power On Description When selected, displays the APM submenu. When selected, displays the ACPI submenu. Specifies the mode of operation if an ac power loss occurs. Stays Off keeps the power off until the power button is pressed. Last State restores the previous power state before power loss occurred. Power On restores power to the computer.
Wake on LAN (This feature is present only when there is no onboard LAN subsystem) Wake on PME Wake on Modem Ring

Default, but can be changed to another IRQ.

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The board reports POST errors in two ways: x x By sounding a beep code By displaying an error message on the monitor

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The BIOS beep codes are listed in Table 33. The BIOS also issues a beep code (one long tone followed by two short tones) during POST if the video configuration fails (a faulty video card or no card installed) or if an external ROM module does not properly checksum to zero.

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Refresh failure Parity cannot be reset First 64 K memory failure Timer not operational Processor failure (Reserved; not used) 8042 GateA20 cannot be toggled (memory failure or not present) Exception interrupt error Display memory R/W error (Reserved; not used) CMOS Shutdown register test error Invalid BIOS (such as, POST module not found)

BIOS Error Messages

When a recoverable error occurs during the POST, the BIOS displays an error message describing the problem (see Table 34).

Table 34.

GA20 Error Pri Master HDD Error Pri Slave HDD Error Sec Master HDD Error Sec Slave HDD Error Pri Master Drive - ATAPI Incompatible Pri Slave Drive - ATAPI Incompatible Sec Master Drive - ATAPI Incompatible Sec Slave Drive - ATAPI Incompatible A: Drive Error B: Drive Error CMOS Battery Low CMOS Display Type Wrong CMOS Checksum Bad CMOS Settings Wrong CMOS Date/Time Not Set DMA Error FDC Failure HDC Failure Checking NVRAM.. Update OK! Updated Failed Keyboard Error KB/Interface Error
Explanation An error occurred with Gate A20 when switching to protected mode during the memory test. Could not read sector from corresponding drive.

Error Message

Corresponding drive is not an ATAPI device. Run Setup to make sure device is selected correctly.
No response from diskette drive. The battery may be losing power. Replace the battery soon. The display type is different than what has been stored in CMOS. Check Setup to make sure type is correct. The CMOS checksum is incorrect. CMOS memory may have been corrupted. Run Setup to reset values. CMOS values are not the same as the last boot. These values have either been corrupted or the battery has failed. The time and/or date values stored in CMOS are invalid. Run Setup to set correct values. Error during read/write test of DMA controller. Error occurred trying to access diskette drive controller. Error occurred trying to access hard disk controller. NVRAM is being checked to see if it is valid. NVRAM was invalid and has been updated. NVRAM was invalid but was unable to be updated. Error in the keyboard connection. Make sure keyboard is connected properly. Keyboard interface test failed. continued

If the power supply and other modules or peripherals, as applicable, are not Class B EMC compliant before integration, then EMC testing is required on a representative sample of the newly completed computer.
Chassis and Component Certifications
Ensure that the chassis and certain components; such as the power supply, peripheral drives, wiring, and cables; are components certified for the country or market where used. Agency certification marks on the product are proof of certification. Typical product certifications include: In Europe The CE marking signifies compliance with all applicable European requirements. If the chassis and other components are not properly CE marked, a suppliers Declaration of Conformity statement to the European EMC directive and Low Voltage directive (as applicable), should be obtained. Additionally, other directives, such as the Radio and Telecommunications Terminal Equipment (R&TTE) directive may also apply depending on product features. In the United States A certification mark by a Nationally Recognized Testing Laboratory (NRTL) such as UL, CSA, or ETL signifies compliance with safety requirements. Wiring and cables must also be UL listed or recognized and suitable for the intended use. The FCC Class B logo for home or office use signifies compliance with electromagnetic interference (EMI) requirements. In Canada A nationally recognized certification mark such as CSA or cUL signifies compliance with safety requirements. The Industry Canada statement at the front of this product guide demonstrates compliance with Canadian EMC regulations. Industry Canada recognizes and accepts FCC certification as denoting compliance with national electromagnetic interference (emissions) requirements.
Prevent Power Supply Overload
Do not overload the power supply output. To avoid overloading the power supply, make sure that the calculated total current loads of all the modules within the computer is less than the output current rating of each of the power supplies output circuits.

Place Battery Marking

There is insufficient space on this desktop board to provide instructions for replacing and disposing of the Lithium ion coin cell battery. For system safety certification, the following statement or equivalent statement is required to be permanently and legibly marked on the chassis near the battery.