FWH Guidelines.... 157 9.1 9.2 9.3 FWH Decoupling... 157 In-Circuit FWH Programming.... 157 FWH VPP Design Guidelines... 157
Miscellaneous Logic.... 159 10.1 10.2 Glue Chip... 159 Discrete Logic.... 159
Platform Clock Routing Guidelines... 161 11.1 11.2 Clock Generation... 161 Clock Group Topology and Layout Routing Guidelines.. 164 11.2.1 HOST_CLK Clock Group... 164 11.2.2 CLK66 Clock Group... 168 11.2.3 AGPCLK Clock Group.. 169 11.2.MHz Clock Group... 170 11.2.5 CLK14 Clock Group... 172 11.2.6 USBCLK Clock Group... 173 Clock Driver Decoupling... 173

11.3 12

Platform Power Guidelines.... 175 12.1 12.2 Power Delivery Map.... 175 MCH Power Delivery... 177 12.2.1 MCH PLL Power Delivery... 177 12.2.2 MCH 1.5 V Power Delivery... 179 12.2.3 MCH 1.5 V Decoupling.. 180 12.2.4 MCH VTT Decoupling... 182 Intel ICH2 Power Delivery... 183 12.3.1 1.8 V / 3.3 V Power Sequencing.. 184 12.3.2 3.3 V / V5REF Sequencing... 185 12.3.3 ATX Power Supply PWRGOOD Requirements.. 185 12.3.4 Power Management Signals... 186 CK408 Power Delivery... 187 12.4.1 CK408 Power Sequencing... 189 12.4.2 CK408 Decoupling... 189 Thermal Design Power.... 191 Power_Supply PS_ON Considerations.. 191

12.5 12.6 13

Platform Mechanical Guidelines... 193 13.1 13.2 MCH Retention Mechanism and Keep-Outs.. 193 Intel Boxed Processor Mechanical Keep-Outs.. 194
Schematic Checklist.... 195 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 Host Interface.... 195 Memory Interface... 198 14.2.1 PC133 SDR SDRAM... 198 AGP Interface.... 199 Hub Interface.... 201 Intel ICH2 Interface... 202 Miscellaneous MCH Signals... 209 Clock Interface CK408... 209 Power and Ground.... 211
Intel 845 Chipset Design Layout Checklist... 213 15.1 System Bus.... 213

15.5 15.6

15.7 15.8
15.1.1 System Bus.... 213 15.1.2 Decoupling, VREF, and Filtering... 215 15.1.3 Intel Boxed Processor Mechanical Keep-Outs.. 216 System Memory (SDR).... 216 15.2.DIMM SDR-SDRAM (PC133)... 216 15.2.DIMM SDR-SDRAM (PC133)... 218 15.2.3 Decoupling, Compensation, and VREF.. 219 AGP.... 220 15.3.1 1X Signals... 220 15.3.2 2X/4X Signals... 220 15.3.3 Decoupling, Compensation, and VREF.. 221 Hub Interface.... 221 15.4.1 Interface Signals... 221 15.4.2 Decoupling, Compensation, and VREF.. 222 Clocks: CK408.... 222 15.5.1 Decoupling... 224 Intel ICH2.... 225 15.6.1 IDE.... 225 15.6.2 AC 97.... 225 15.6.3 USB 1.1.... 225 15.6.4 RTC.... 226 15.6.5 LAN.... 226 15.6.6 Intel ICH2 Decoupling... 227 15.6.7 Power/Ground Decoupling... 227 FWH.... 227 Power.... 228 15.8.1 Filtering.... 228
Appendix A: Customer Reference Board Schematics... 229

Figures

Table 8-6. LAN Design Guide Section Reference... 136 Table 8-7. Length Requirements for Figure 8-24.. 138 Table 8-8. Intel 82562ET/EM Control Signals... 152 Table 8-9. Decoupling Capacitor Recommendation.. 155 Table 11-1. Intel 845 Chipset Clock Groups... 161 Table 11-2. Platform System Clock Cross-Reference.. 162 Table 11-3. BCLK [1:0]# Routing Guidelines... 165 Table 11-4. CLK66 Routing Guidelines... 168 Table 11-5. AGPCLK Routing Guidelines... 169 Table 11-6. 33 MHz Clock Routing Guidelines... 171 Table 11-7. CLK14 Routing Guidelines... 172 Table 11-8. USBCLK Routing Guidelines... 173 Table 12-1. Power Terminology... 175 Table 12-2. PLL0 Filter Routing Guidelines... 178 Table 12-3. PLL1 Routing Guidelines.... 178 Table 12-4. Recommended Inductor Components for MCH PLL Filter. 178 Table 12-5. Recommended Capacitor Components for MCH PLL Filter. 178 Table 12-6. PLL1 Routing Guidelines.... 189 Table 12-7. Component Thermal Design Power... 191

Revision History

Rev. No. -001 -002 -003 Initial Release Title changed to include SDR memory Updated Figure 143, Intel 845 Chipset Platform Using DDR-SDRAM System Memory Power Delivery Map. Added Section 4.6.6, Electrostatic Discharge Platform Recommendations. Updated Table 3, System Bus Routing Summary for the Processor. For Intel Boxed Processor Mechanical Keep-outs, added Section 13.2 and 15.1.3. Removed the section on 45-Watt Processor Thermal Design Power (TDP) Limitation (Section 4.6.2 in Revision 002). Minor edits throughout for clarity. Description Date September 2001 January 2002 September 2002

Introduction

This design guide documents Intels design recommendations for systems based on the Intel Pentium 4 processor and the Intel 845 chipset. Design issues such as thermal considerations should be addressed using specific design guides or application notes for the processor or 845 chipset. These design guidelines have been developed to ensure maximum flexibility for board designers while reducing the risk of board related issues. The design information provided in this document falls into one of the two following categories. Design Recommendations are items based on Intels simulations and lab experience to date and are strongly recommended, if not necessary, to meet timing and signal quality specifications. Design Considerations are suggestions for platform design that provide one way to meet the design recommendations. They are based on the reference platforms designed by Intel. They should be used as examples, but may not be applicable to particular designs. Note: In this document processor and Intel Pentium 4 processor refer to the Intel Pentium 4 processor in the 478 pin package. Note: The guidelines recommended in this document are based on experience and preliminary simulation work performed at Intel while developing Pentium 4 processor and 845 chipset- based systems. This work is ongoing, and the recommendations and considerations are subject to change. Platform schematics are provided in Appendix A, Customer Reference Board Schematics. The schematics are a reference for board designers. While the schematics may cover a specific design, the core schematics will remain the same for most platforms. The schematic set provides a reference schematic for each platform component as well as common motherboard options. Additional flexibility is possible through other permutations of these options and components.

Table 4-7. Layout Recommendations for A20M#, IGNNE#, LINT[1:0], SLP#, SMI#, and STPCLK#Topology 2A
Trace Zo Trace Spacing L1 Rpu

7 mils

12 inches max
Figure 4-8. Routing Illustration for A20M#, IGNNE#, LINT[1:0], SLP#, SMI#, and STPCLK#

4.3.1.5

Topology 2B: Asynchronous GTL+ Signal Driven by the Intel ICH2 INIT#
INIT# should adhere to the routing and layout recommendations described and illustrated in Table 4-8 and Figure 4-9.
Table 4-8. Layout Recommendations for INIT#Topology 2B
Trace Zo Trace Spacing L1 L2 L4 L5 Rpu

2 inches max

17 inches max

300 5%

Figure 4-9. Routing Illustration for INIT#

VCC_FWH 300 5%

Processor Intel ICH2

Voltage Translator

Level shifting is required for the INIT# signal to the FWH to meet the input logic levels of the FWH. Figure 4-10 illustrates one method of level shifting. Figure 4-10. Voltage Translation of INIT#
INIT# to FWH 4.7 k INIT# from ICH2

INIT# Routing

4.3.1.6
Topology 2C: Asynchronous GTL+ Signal Driven by the Intel ICH2 Open DrainPWRGOOD
PWRGOOD should adhere to the routing and layout recommendations described and illustrated in Table 4-9 and Figure 4-11.
Table 4-9. Layout Recommendations for Miscellaneous SignalsTopology 2C

300 5%

Figure 4-11. Routing Illustration for PWRGOOD

4.3.1.7

Topology 3VCCIOPLL, VCCA and VSSA
VCCIOPLL and VCCA are isolated power for internal PLLs. It is critical that they have clean, noiseless power on their input pins. Further details can be found in Section 4.6.6.1.

4.3.1.8

Topology 4BR0# and RESET#
Because the processor does not have on-die termination on the BR0# and RESET# signals, it is necessary to terminate the signals using discrete components on the system board. Connect the signals between the components as shown in Figure 4-12. The 845 chipset has on-die termination; therefore it is necessary to terminate only at the processor end. The value of Rt should be 51 5% for RESET#. The value of Rt should be 150220 5% for BR0#.

6.1.2.1

Trace Lengths Less Than 6 Inches
If the AGP interface is less than 6 inches with 60 15% board impedance, at least 5-mil traces with at least 15 mils of space (1:3) between signals is required for 2X/4X lines (data and strobes). These 2X/4X signals must be matched to their associated strobe within 0.25 inch. For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) are 5.3 inches long, the data signals associated with those strobe signals (e.g., G_AD[15:0] and G_C/BE[3:0]#), can be 5.05 inches to 5.55 inches long. While another strobe set (e.g., SB_STB and SB_STB#) could be 4.2 inches long and the data signals associated to those strobe signals (e.g., SBA[7:0]) can be 3.95 inches to 4.45 inches long.
The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB and SB_STB#) act as clocks on the source synchronous AGP interface. Special care must be taken when routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed on 5-mil traces with at least 15 mils of space (1:3) between them. This pair should be separated from all other signals by at least 15 mils. The strobe pair must be length matched to less than 0.1 inch (that is, a strobe and its compliment must be the same length within 0.1 inch). Figure 6-1. AGP 2X/4X Routing Example for Interfaces Less Than 6 Inches
5 mil trace 15 mils 5 mil trace 15 mils 5 mil trace 15 mils 5 mil trace 15 mils 5 mil trace 15 mils
2X/4X Signal 2X/4X Signal 2X/4X Signal 2X/4X Signal AGP STB AGP STB AGP STB# AGP STB# 2X/4X Signal 2X/4X Signal 2X/4X Signal 2X/4X Signal
STB/STB# Length Associated AGP 2X/4X Data Signal Length

0.25" Min

0.25" Max

6.1.2.2

Trace Lengths Greater Than 6 Inches and Less Than 7.25 Inches
If the AGP interface is greater than 6 inches and less than 7.25 inches with 60 15% board impedance then at least 5-mil traces with at least 20 mils of space (1:4) between signals is required for 2X/4X lines (data and strobes). These 2X/4X signals must be matched to their associated strobe within 0.125 inch. For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) are 6.5 inches long, the data signals that are associated with those strobe signals (e.g., G_AD[15:0] and G_C/BE[2:0]#), can be 6.475 inches to 6.625 inches long. Another strobe set (e.g., SB_STB and SB_STB#) could be 6.2 inches long, and the data signals that are associated with those strobe signals (e.g., SBA[7:0]), can be 6.075 inches to 6.325 inches long. The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB and SB_STB#) act as clocks on the source synchronous AGP interface. Special care must be taken when routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed on 5-mil traces with at least 15 mils of space (1:3) between them. This pair should be separated from all other signals by at least 20 mils. The strobe pair must be length matched to less than 0.1 inches (i.e., a strobe and its compliment must be the same length within 0.1 inches).

VREF Generation

For 1.5 V add-in cards, the graphics controller and MCH generate AGP voltage reference VREF and distribute it through the connector. Two signals have been defined on the 1.5 V connector to allow VREF delivery: VREFGCVREF from the graphics controller to the chipset VREFCGVREF from the chipset to the graphics controller However, the usage of the source generated VREFCG at the MCH is not required per the AGP Interface Specification, Version 2.0. Given this and the fact that the MCH requires the presence of VREF when an AGP add-in card is present and not present, the following circuit is recommended for VREF generation. The VREF divider network should be placed near the AGP connector. The minimum trace spacing around the VREF signal must be 25 mils to reduce crosstalk and maintain signal integrity, and a 0.1 F bypass capacitor should be placed within 0.8 inches of the MCH AGPREF ball. VREF voltage must be 0.5 x VDDQ for 1.5 V operation.
Figure 6-3. AGP 2.0 VREF Generation and Distribution for 1.5 V Cards

V_1p5_core

Vrefgc Pin A66 1.5V AGP Add-in Card Vrefcg Pin B66

1 k 1? %

MCH AGPREF

0.1 F 1 k 1? %

Table 6-4. AGP VREF Routing Guidelines
AGP VREF trace width AGP VREF trace spacing to other signals AGP VREF trace breakout guidelines AGP VREF decouplingMCH max distance
12 mils 25 mils 5 mil width with 5 mil spacing for a max of 0.15 inch 0.8 inch
MCH AGP Interface Buffer Compensation
The MCH AGP interface supports resistive buffer compensation (GRCOMP). The GRCOMP signal must be tied to a 40 2% resistor to ground. This trace should be kept to 10 mils wide and less than 0.5 inch long. AGP signals have integrated pull-up resistors to AGP VDDQ, and pull-down resistors to ground. This is to ensure stable values are maintained when agents are not actively driving the bus. Table 6-5 lists signals that have integrated AGP pull-up/pull-down resistors. Their value is between 4 k and 16 k. External pull-ups and pull-downs are not needed for these signals. Note: 1X mode, trace stub to pull-up resistor should be kept to less than 0.5 inch. 2X/4X mode, trace stub to pull-up resistor should be kept to less than 0.1 inch. Short stub lengths help minimize signal reflections from the stub. The strobe signals require pullup/pull-down on the motherboard to ensure stable values when there are no agents driving the bus.

Cabling

Length of cable: Each IDE cable must be equal to or less than 18 inches. Capacitance: Less than 30 pF. Placement: A maximum of 6 inches between drive connectors on the cable. If a single drive is placed on the cable, it should be placed at the end of the cable. If a second drive is placed on the same cable, it should be placed on the next closest connector to the end of the cable (6 inches away from the end of the cable). Grounding: Provide a direct low impedance chassis path between the motherboard ground and hard disk drives. ICH2 Placement: The ICH2 must be placed equal to or less than 8 inches from the ATA connector(s).

8.1.1.1

Cable Detection for Ultra ATA/66 and Ultra ATA/100
The ICH2 IDE Controller supports PIO, Multi-word (8237 style) DMA, and Ultra DMA modes 0 through 5. The ICH2 must determine the type of cable that is present to configure itself for the fastest possible transfer mode that the hardware can support. An 80-conductor IDE cable is required for Ultra ATA/66 and Ultra ATA/100. This cable uses the same 40-pin connector as the old 40-pin IDE cable. The wires in the cable alternate: ground, signal, ground, signal, ground, signal, ground, etc. All the ground wires are tied together on the cable (and they are tied to the ground on the motherboard through the ground pins in the 40-pin connector). This cable conforms to the Small Form Factor Specification SFF-8049. This specification can be obtained from the Small Form Factor Committee.
To determine if ATA/66 or ATA/100 mode can be enabled, the ICH2 requires the system software to attempt to determine the cable type used in the system. If the system software detects an 80conductor cable, it may use any Ultra DMA mode up to the highest transfer mode supported by both the chipset and the IDE device. If a 40-conductor cable is detected, the system software must not enable modes faster than Ultra DMA Mode 2 (Ultra ATA/33). Intel recommends that cable detection be done using a combination Host-Side/Device-Side detection mechanism. Note that Host-Side detection cannot be implemented on an NLX form factor system because this configuration does not define interconnect pins for the PDIAG#/CBLID# from the riser (containing the ATA connectors) to the motherboard. These systems must rely on the Device-Side Detection mechanism only.

8.1.1.2

Combination Host-Side/Device-Side Cable Detection
Host side detection (described in the ATA/ATAPI-4 Standard, Section 5.2.11) requires the use of two GPI pins (one for each IDE channel). The proper way to connect the PDIAG#/CBLID# signal of the IDE connector to the host is shown in Figure 8-1. All IDE devices have a 10 k pull-up resistor to 5 V on this signal. Not all of the GPI and GPIO pins on the ICH2 are 5 V tolerant. If non-5 V tolerant inputs are used, a resistor divider is required to prevent 5 V on the ICH2 or Intel FWH pins. This resistor also prevents the GPI pins from floating if a device is not present on the IDE interface. The proper value of the divider resistor is 10 k (as shown in Figure 8-1).

The ICH2 contains a real time clock (RTC) with 256 bytes of battery backed SRAM. The internal RTC module provides two key functions: keeping date and time, and storing system data in its RAM when the system is powered down. This section describes the recommended hookup for the RTC circuit for the ICH2.

RTC Crystal

The ICH2 RTC module requires an external oscillating source of 32.768 kHz connected on the RTCX1 and RTCX2 pins. Figure 8-18 shows the external circuitry that comprises the oscillator of the ICH2 RTC.
Figure 8-18. External Circuitry for the Intel ICH2 RTC
VCC3_3SBY 1 k 1 F RTCX23 Vbatt_RTC 1 k 32768 Hz Xtal RM RTCX14 C1 0.047 F C31 RM VBIAS5 C21 VSS6 VCCRTC2

RTC_osc_circ

NOTES: 1. The exact capacitor value must be based on the crystal makers recommendation. (Typical values for C2 and C3 are 18 pF for a crystal with CLOAD=12.5 pF.) 2. VccRTC: Power for RTC-well. 3. RTCX2: Crystal Input 2connected to the 32.768 kHz crystal. 4. RTCX1: Crystal Input 1connected to the 32.768 kHz crystal. 5. VBIAS: RTC BIAS VoltageThis pin is used to provide a reference voltage that sets a current that is mirrored throughout the oscillator and buffer circuitry. 6. VSS: Ground.

External Capacitors

To maintain the RTC accuracy, the external capacitor C1 must be 0.047 F, and the external capacitor values (C2 and C3) should be chosen to provide the manufacturers specified load capacitance (Cload) for the crystal when combined with the parasitic capacitance of the trace, socket (if used), and package. When the external capacitor values are combined with the capacitance of the trace, socket, and package, the closer the capacitor value can be matched to the actual load capacitance of the crystal used, the more accurate the RTC will be. The following equation can be used to choose the external capacitance values (C2 and C3):
Cload = (C2 * C3)/(C2+C3) + Cparasitic
C3 can be chosen such that C3 > C2. Then C2 can be trimmed to obtain the 32.768 kHz.
RTC Layout Considerations
Keep the RTC lead lengths as short as possible (about inch is sufficient). Minimize the capacitance between Xin and Xout in the routing. Put a ground plane under the XTAL components. Do not route switching signals under the external components (unless on the other side of the board). The oscillator VCC should be clean. Use a filter, such as an RC lowpass filter or a ferrite inductor.

Intel 82562ET / 82562EM Guidelines
82562ET / 82562EM Guidelines Related Documents
Refer to Section 1.1, Related Documentation, for a list of related documents. For correct LAN performance, designers must follow the general guidelines outlined in Section 8.9.2, General LAN Routing Guidelines and Considerations. The following sections describe additional guidelines for implementing an 82562ET or 82562EM Platform LAN connect component.

8.9.4.1

Guidelines for Intel 82562ET / 82562EM Component Placement
Component placement can affect the signal quality, emissions, and temperature of a board design. This section will provide guidelines for component placement. Careful component placement can:
Decrease potential problems directly related to electromagnetic interference (EMI) than can cause failure to meet FCC and IEEE test specifications. Simplify the task of routing traces. To some extent, component orientation will affect the complexity of trace routing. The overall objective is to minimize turns and crossovers between traces.
Minimizing the amount of space needed for the Ethernet LAN interface is important because all other interfaces will compete for physical space on a motherboard near the connector edge. As with most subsystems, the Ethernet LAN circuits must be as close as possible to the connector. Therefore, it is imperative that all designs be optimized to fit in a very small space.

8.9.4.2

To minimize the effects of EMI, clock sources should not be placed near I/O ports or board edges. Radiation from these devices may be coupled onto the I/O ports or out of the system chassis. Crystals should be kept away from the Ethernet magnetics module to prevent interference of communication. The retaining straps of the crystal (if they exist) should be grounded to prevent the possibility of radiation from the crystal case, and the crystal should lay flat against the PC board to provide better coupling of the electromagnetic fields to the board. For noise free and stable operation, place the crystal and associated discretes as close as possible to the 82562ET or 82562EM keeping the trace length as short as possible, and do not route any noisy signals in this area.

8.9.4.3

Intel 82562ET / 82562EM Termination Resistors
The 100 (1%) resistor used to terminate the differential transmit pairs (TDP/TDN) and the 120 (1%) receive differential pairs (RDP/RDN) should be placed as close to the Platform LAN connect component (82562ET or 82562EM) as possible. This is because these resistors are terminating the entire impedance that is seen at the termination source (i.e., 82562ET), including the wire impedance reflected through the transformer.
Figure 8-29. Intel 82562ET/82562EM Termination

LAN Connect Interface

85262ET
Place Termination Resistors as Close to 82562ET as Possible

82562_Term

8.9.4.4

Processor Core Processor Vtt VID VREG Processor VID

1.5 V VREG

MCH Core 1.5V 1.8 V VREG MCH Vtt MCH AGP MCH Hub Interface 1.8 3.3V FET Switch MCH System Memory SDR 3.3
3.3V VREG PC-133 System Memory 3.3V
Intel Intel Intel 1.8 V VREG Intel Intel
ICH2 Core 1.8V ICH2 I/O 3.3V ICH2 Resume 1.8V ICH2 Resume I/O 3.3V ICH2 RTC 3.3V
Intel ICH2 V5REF Intel ICH2 V5REF_SUS

FWH 3.3V

LPC Super I/O 3.3V

CK -408 3.3V

Figure 12-2. Example Platform Power DeliveryIntel 845 Chipset Using PC133 SDRAM

AUD_Vcc 3VSB GND 1.5_V

ESD GND 12VFilt Phase 3 Phase 2 Phase 1 Vccp 3p3_STR

Vcc3 5VSB Vcc

MCH Power Delivery
There are no MCH power sequencing requirements. All MCH power rails should be stable before deasserting reset, but the power can be brought up in any order desired. Good design practice would have all power rails come up as close in time as practical.

12.2.1

MCH PLL Power Delivery
VCCA1 and VSSA1, and VCCA0 and VSSA0 are power sources required by the MCHs PLL clock generators.
Figure 12-3. Intel 845 Chipset PLL0 Filter
V_1P5_CORE VCCA0 (ball T13) L C PLL Intel MCH

VSSA0 (ball U13)

Length A
Table 12-2. PLL0 Filter Routing Guidelines
Trace Width Trace Spacing Trace LengthA CapacitorC InductorL
5 mils 10 mils 1.5 inches 33 F 4.7 H
Figure 12-4. Intel 845 Chipset PLL1 Filter
V_1P5_CORE VCCA1 (ball T17) L C PLL MCH

VSSA1 (ball U17)

Table 12-3. PLL1 Routing Guidelines
Table 12-4. Recommended Inductor Components for MCH PLL Filter
Value Tolerance SRF Rated I DCR

4.7 H 4.7 H 4.7 H

10% 10% 30%

35 MHz 47 MHz 35 MHz

30 mA 30 mA 30 mA
0.56 (1 max) 0.7 ( 50%) 0.3 max
Table 12-5. Recommended Capacitor Components for MCH PLL Filter

Value ESL ESR

33 F 33 F

2.5 nH 2.5 nH

0.225 0.2

12.2.2

MCH 1.5 V Power Delivery
The MCH core and AGP I/O is supplied by 1.5 V. Adequate high-frequency decoupling is needed to ensure one does not adversely impact the other.

Figure 12-5. 1.5 V Power PlaneBoard View

12.2.3

MCH 1.5 V Decoupling
The following minimum decoupling components are recommended:
Six, 0.1 F ceramic capacitor, 603 body type, X7R dielectric Two, 10 F ceramic capacitor, 1206 body type, X7R dielectric Two, 100 F electrolytic capacitor
It is recommended that low ESL ceramic capacitors, such as 0603 body types, X7R dielectric, be used. The designer should evenly distribute placement of decoupling capacitors among the AGP interface signal field, and place them as close to the MCH as possible (no further than 0.25 inch from the MCH VCC1_5 ball in the AGP ball field). Figure 12-6 shows an example placement of 1.5 V decoupling capacitors.
Figure 12-6. MCH 1.5 V Core and 1.5 V AGP I/O Decoupling Placement
Figure 12-7. VTT Power PlaneProcessor and MCH

12.2.4

MCH VTT Decoupling
Two, 10 F ceramic capacitor, 1206 body type, X5R dielectric Five, 0.1 F ceramic capacitor, 1206 type, X7R dielectric
The alternating polarity of the five, 0.1 F capacitors minimizes the area reduction caused by the vias.
Figure 12-8. VTT Power Plane at MCHVTT Decoupling at MCH
Intel ICH2 Power Delivery
Figure 12-9. Power Plane Split Example (Layer 2)
Figure 12-10. Power Plane Split Example (Layer 1)

1.8 VSB

3.3 VSB

12.3.1

1.8 V / 3.3 V Power Sequencing
The ICH2 has two pairs of associated 1.8 V and 3.3 V supplies; these are {VCC1_8, VCC3_3}, and {VccSus1_8, VccSus3_3}. These pairs are assumed to power up and power down together. The difference between the two associated supplies must never be greater than 2.0 V. The 1.8 V supply may come up before the 3.3 V supply without violating this rule (though this is generally not practical in a desktop environment because the 1.8 V supply is typically derived from the 3.3 V supply by means of a linear regulator). One serious consequence of violating this 2 V Rule is electrical overstress of oxide layers, resulting in component damage. The majority of the ICH2 I/O buffers are driven by the 3.3 V supplies, but are controlled by logic that is powered by the 1.8 V supplies. Thus, another consequence of faulty power sequencing arises if the 3.3 V supply comes up first. In this case the I/O buffers will be in an undefined state until the 1.8 V logic is powered up. Some signals that are defined as Input-only actually have output buffers that are normally disabled, and the ICH2 may unexpectedly drive these signals if the 3.3 V supply is active while the 1.8 V supply is not. Figure 12-11 is an example power-on sequencing circuit that ensures that the 2 V Rule is not violated. This circuit uses a NPN (Q2) and PNP (Q1) transistor to ensure the 1.8 V supply tracks the 3.3 V supply. The NPN transistor controls the current through PNP from the 3.3 V supply into the 1.8 V power plane by varying the voltage at the base of the PNP transistor. By connecting the emitter of the NPN transistor to the 1.8 V plane, current will not flow from the 3.3 V supply into 1.8 V plane when the 1.8 V plane reaches 1.8 V.

NMI PWRGOOD

Connect to the associated pin on the ICH2 (No extra pull-up resistors required). Connects to ICH2 CPUPWRGD pin (Weak external pull-up resistor required). Terminate to VCC_CPU through a 300 5% resistor.

SLP# SMI# STPCLK#

Connect to the associated pin on the ICH2 (No extra pull-up resistors required). Connect to the associated pin on the ICH2 (No extra pull-up resistors required). Connect to the associated pin on the ICH2 (No extra pull-up resistors required) Processor Only Signals
A[35:32]# AP[1:0]# BCLK[1:0]
No Connect. No Connect. Connect to CK408. Connect 2033 series resistors to each clock signal. Connect a 49.9 1% shunt source termination (Rt) resistor to GND for each signal on the processor side of the series resistor (50 motherboard impedance).

BPM[5:0]#

These signals should be terminated with a 51 5% resistor to VCC_CPU near the processor. If a debug port is implemented termination is required near the debug port as well. Refer to the ITP700 Debug Port Design Guide for further information. No Connect. Connect to CK408. Terminate to CK408 3.3 V supply through a 1 k resistor.

BINIT# BSEL[1:0]

COMP[1:0]
Terminate to GND through a 51.1 1% resistor. Minimize the distance from termination resistor and processor pin.

DBR# DP[3:0]# IERR#

Refer to the ITP700 Debug Port Design Guide for further information. No Connect. Terminate to VCC_CPU through a 62 5% resistor near the processor.
Description Terminate to VCC_CPU through a 49.9 1% resistor. Terminate to GND through a 100 1% resistor. Should be 2/3 VCC_CPU.

GTLREF[3:0]

ITP_CLK0 ITP_CLK1 MCERR# PROCHOT# RSP# SKTOCC# TCK TDI TDO TESTHI THERMTRIP# THERMDA THERMDC TMS TRST# VCCA VCCIOPLL VCC_SENSE VCCVID VID[4:0]
Refer to the ITP700 Debug Port Design Guide for further information. Refer to the ITP700 Debug Port Design Guide for further information. No Connect. Terminate to VCC_CPU though a 62 1% resistor near the processor. No Connect. Connect to Glue Chip / Discrete Logic (If pin is used). Refer to the ITP700 Debug Port Design Guide for further information. Refer to the ITP700 Debug Port Design Guide for further information. Refer to the ITP700 Debug Port Design Guide for further information. Refer to Section 4.3.1.11 Terminate to VCC_CPU through a 62 5% resistor near the processor. Connect to thermal monitor circuitry if used. Connect to thermal monitor circuitry if used. Refer to the ITP700 Debug Port Design Guide for further information. Refer to the ITP700 Debug Port Design Guide for further information. Connect with isolated power circuitry to VCC_CPU. Connect with isolated power circuitry to VCC_CPU. Leave as no-connect. Connect to 1.2 V linear regulator. Connect to VR or VRM. These signals must be pulled up to 3.3 V through either 1 k pull-ups on the motherboard or with internal pull-ups in the VR or VRM. Connect with isolated power circuitry to VCC_CPU. Leave as no-connect. MCH Signals Only

ST2 WBF#

VCC1_5
3.3Vaux 12V AGPCLK G_PERR# G_SERR# OVRCNT PCIRST PME# TYPEDET# USB+ USB VCC VCC5 VDDQ VREFCG VREFGC
Connect to PCI 3.3VAUX. Connect to 12 V. Connect to CK408. Terminate to VDDQ through a 4 k to 16 k resistor (6.8 k resistor value recommended). Terminate to VDDQ through a 4 k to 16 k resistor (6.8 k resistor value recommended). Connect to PCI slot PCIRST. Connect to PCI PME#. Not required. Connect to VCC3. Connect to VCC. Connect to V1.5CORE. Connect to VREF divider network at the AGP connector. Not required. MCH Signals Only

AGPREF

Connect to VREFCG pin on connector. Terminate to ground through a 0.1 F capacitor at the MCH.

GRCOMP

Pull-down to GND through a 40.2 1% resistor.
Signal Description MCH/ Intel ICH2 Signals
HI[10:0] HI_STB HI_STB# HI_REF
Connect together. Connect together. Connect together. Connect voltage divider circuit with R1=R2=150 1%. Use two 0.1 F capacitors within 150 mils of the ICH2. The MCH should be decoupled with one 0.1 F capacitor within 150 mils of the package and one 10 F capacitor nearby. Bypass to GND through a 0.1 F capacitor located near each components (MCH and ICH2) HI_REF pin. Decouple with a 0.1 F capacitor placed near the divider circuit.

VCC1_8

Connect to 1.8 V power supply. MCH Signals Only

HLRCOMP

Pull-up to VCC1_8 through a 40.2 1% resistor Intel ICH2 Signals Only

HI11 HICOMP

No extra pull-ups required. Terminate to VCC1_8 through a 40.2 1% resistor. ZCOMP is no longer supported.

Intel ICH2 Interface

Signal Description LAN Signals
If not used leave all pins as NC. For line termination, a 33 series resistors can be installed at the driver side of the interface for over/undershoot problems. Point-to-point Interconnect: Direct connect to Intel 82562EH, Intel 82562ET, or CNR. LOM/CNR implementation: Add resistor pack (033 ) to ensure that either a CNR option or a LAN on motherboard option can be implemented at one time. Stubs due to the resistor pack should not be present on the interface. Dual Footprint: Direct connect to 82562EH or 82562ET/EM. A 033 resistor can be placed as close as possible to the driving side of each signal line. To improve signal quality, use 0 resistors to connect and disconnect circuitry not shared by both configurations. Place resistor pads along the signal line to reduce stub lengths.

PLOCK#

Contains integrated pull-up resistor. Connect together.

REQ[5:0]#

Connect together. Terminate to VCC3_3 through an 8.2 k resistor or VCC5 through a 2.7 k. REQ5# can also be used as REQB# or GPI1.

REQ[A:B]#

Connect together. Terminate to VCC3_3 through an 8.2 k resistor or VCC5 through a 2.7 k. REQA# can also be used as GPI0. REQB# can also be used as REQ5# or GPI1.
Description Connect together. Terminate to VCC3_3 through an 8.2 k resistor or VCC5 through a 2.7 k.
Connect together. Terminate to VCC3_3 through an 8.2 k resistor or VCC5 through a 2.7 k. Intel ICH2/IDE Signals

Cable Detect

Host Side/Device Side Detection. Connect ICH2 GPIO pin to IDE pin PDIAG#/CBLID#. Connect to GND through a 10 k resistor. Device Side Detection. No ICH2 connection. Connect a.047 F capacitor from IDE pin PDIAG#/CBLID# to GND.

IDERST#

Formed by buffering PCIRST# signal. Terminate through a series 33 resistor.
PDA[2:0] PDCS1# PDCS3# PDD[15:0]
Contain integrated series termination resistors. Contains an integrated series termination resistor. Contains an integrated series termination resistor. Contains integrated series termination resistors. PDD7 contains an integrated pull-down resistor. Use a 0 resistor to address possible noise issues on motherboard.

PDDACK# PDDREQ

Contains an integrated series termination resistor. Contains an integrated pull-down resistor. Contains an integrated series termination resistor.

PDIOR# PDIOW# PIORDY

Contains an integrated series termination resistor. Contains an integrated series termination resistor. Contains an integrated series termination resistor. Pull-up to VCC3_3 via a 4.7 k pull-up resistor.
SDA[2:0] SDCS1# SDCS3# SDD[15:0]
Contains integrated series termination resistors. Contains an integrated series termination resistor. Contains an integrated series termination resistor. Contains integrated series termination resistors. SDD7 contains an integrated pull-down resistor. Use a 0 resistor to address possible noise issues on motherboard.

SDDACK#

Contains an integrated series termination resistor.
Description Contains an integrated pull-down resistor. Contains an integrated series termination resistor.

SDDREQ

SDIOR# SDIOW# SIORDY
Contains an integrated series termination resistor. Contains an integrated series termination resistor. Contains an integrated series termination resistor. Pull-up to VCC3_3 via a 4.7 k pull-up resistor. Intel ICH2/LPC Signals

Electrical Characteristics....119 6.1 6.2 6.3 6.4 Absolute Maximum Ratings...119 Power Characteristics....119 Signal Groups....120 DC Characteristics....122
Ballout and Package Information...125 7.1 Package Mechanical Information..134
Testability....137 8.1 8.2 XOR Test Mode Initialization...137 XOR Chains....138

Figures

Figure 1. Intel MCH Simplified Block Diagram...20 Figure 2. PAM Register Attributes...60 Figure 3. Addressable Memory Space...97 Figure 4. DOS Compatible Area Address Map...98 Figure 5. Extended Memory Range Address Map..98 Figure 6. Intel 82845 MCH Ballout Diagram (Top ViewLeft Side)..126 Figure 7. Intel 82845 MCH Ballout Diagram (Top ViewRight Side)..127 Figure 8. Intel MCH FC-BGA Package Dimensions (Top and Side View).134 Figure 9. Intel MCH FC-BGA Package Dimensions (Bottom View).135 Figure 10. XOR Tree Chain...137

Tables

Table 1. General Terminology...11 Table 2. Data Type Notation....12 Table 3. Number Format Notation...12 Table 4. Memory Capacity....16 Table 5. Intel MCH Clock Ratio Table....17 Table 6. Intel MCH Internal Device Assignments..32 Table 7. Memory-mapped Register Address Map...36 Table 8. Intel MCH Configuration Space (Device 0)...43 Table 9. PAM Register Attributes...61 Table 10. Intel MCH Configuration Space (Device 1)..80 Table 11. SMM Space Address Ranges...104 Table 12. Supported DIMM Configurations...109 Table 13. Data Bytes on DIMM Used for Programming DRAM Registers..110 Table 14. Address Translation and Decoding...111 Table 15. AGP Commands Supported by the Intel MCH When Acting as an AGP Target....113 Table 16. Data Rate Control Bits...115 Table 17. PCI Commands Supported by the Intel MCH (When Acting as a FRAME# Target)...115 Table 18. Absolute Maximum Ratings....119 Table 19. Power Characteristics...119 Table 20. Signal Groups...120 Table 21. DC Characteristics...122 Table 22. Intel 82845 MCH Ballout Listed Alphabetically by Signal Name..128 Table 23. XOR Chain 0....138 Table 24. XOR Chain 1....140 Table 25. XOR Chain 2....141 Table 26. XOR Chain 3....142 Table 27. XOR Chain 4....143 Table 28. XOR Chain 5....144 Table 29. XOR Chain 6....146 Table 30. XOR Chain 7....147

Revision History

Revision Number -001 -002 Initial Release. Changed the document name to add the term for SDR. DWTCDRAM Write Thermal Management Control Register was incorrectly placed in Device 0. It should be in Device 1. DRTCDRAM Read Thermal Management Control Register was incorrectly placed in Device 0. It should be in Device 1. Description Date September 2001 January 2002

Intel 82801BA I/O Controller Hub 2 (ICH2)
The ICH2 is a highly integrated multifunctional I/O Controller Hub that provides the interface to the PCI Bus and integrates many of the functions needed in todays PC platforms. The MCH and ICH2 communicate over a dedicated hub interface. The 82801BA ICH2 Functions and capabilities include: PCI Rev 2.2 compliant with support for 33 MHz PCI operations Supports up to 6 Request/Grant pairs (PCI slots) Power management logic support Enhanced DMA controller, interrupt controller, and timer functions Integrated IDE controller; Ultra ATA/100/66/33 USB host interface; 2 host controllers and supports 4 USB ports Integrated LAN controller System Management Bus (SMBus) compatible with most I2C devices; ICH2 has both bus master and slave capability AC 97 2.1 compliant link for audio and telephony codecs; up to 6 channels (ICH2) Low Pin Count (LPC) interface FWH Interface (FWH Flash BIOS support) Alert on LAN* (AOL and AOL2)

Intel 82845 MCH Overview

The MCH role in a system is to manage the flow of information between its four interfaces: the system bus, the memory interface, the AGP port, and the hub interface. The MCH arbitrates between the four interfaces, when each initiates an operation. While doing so, the MCH supports data coherency via snooping and performs address translation for access to AGP Aperture memory. To increase system performance, the MCH incorporates several queues and a write cache. The MCH is in a 593 pin FC-BGA package and contains the following functionality: Supports single Pentium 4 processor configuration at 400 MHz AGTL+ system bus with integrated termination supporting 32-bit system bus addressing Up to 3 GB (w/ 512 Mb technology) of PC133 SDRAM 1.5 V AGP interface with 4x SBA/data transfer and 2x/4x fast write capability 8 bit, 66 MHz 4x hub interface to the ICH2 Distributed arbitration for highly concurrent operation

System Bus Interface

The MCH is optimized for the Pentium 4 processor. The primary enhancements over the Compatible Mode P6 bus protocol are: Source synchronous double-pumped address Source synchronous quad-pumped data System bus interrupt and side-band signal delivery The MCH supports a 64-byte cache line size. Only one processor is supported at a system bus frequency of 400 MHz. The MCH supports a 3:4 host-to-memory frequency ratio (using the 100 MHz clock). The MCH integrates AGTL+ termination resistors on all of the AGTL+ signals. The MCH supports 32-bit system bus addresses, allowing the processor to access the entire 4 GB of the MCH memory address space. The MCH has a 12-deep In-Order Queue to support up to twelve outstanding pipelined address requests on the system bus. The MCH supports two outstanding defer cycles at a time; however, only one to any particular I/O interface. Processor-initiated I/O cycles are positively decoded to AGP/PCI or MCH configuration space and subtractively decoded to the hub interface. Processorinitiated memory cycles are positively decoded to AGP/PCI or system memory, and are again subtractively decoded to the hub interface, if under 4 GB. AGP semantic memory accesses initiated from AGP/PCI to system memory are not snooped on the system bus. Memory accesses initiated from AGP/PCI using PCI semantics and from the hub interface to system memory will be snooped on the system bus. Memory accesses whose addresses lie within the AGP aperture are translated using the AGP address translation table, regardless of the originating interface.

System Bus Error Checking
The MCH does not generate parity, nor check parity for data, address/request, and response signals on the processor bus.

System Memory Interface

The MCH directly supports one channel of PC133 SDRAM. The memory interface supports Single Data Rate (SDR) devices with densities of 64 Mb, 128 Mb, 256 Mb, and 512 Mb technology. The memory interface also supports variable page sizes of 2 KB, 4 KB, 8 KB, and 16 KB. Page size is individually selected for every row and a maximum of 8 pages per DIMM may be opened simultaneously. The MCH supports a maximum of 3 double-sided DIMMs (6 rows populated) with unbuffered PC133 (with or without ECC) Note that in mixed mode, populating ECC and Non-ECC memories simultaneously is not supported.

Table 4. Memory Capacity

Technology 64 Mb 128 Mb 256 Mb 512 Mb SDR (PC133) Maximum 384 MB 768 MB 1.5 GB 3 GB
The memory interface provides optional ECC error checking for system memory data integrity. During system memory writes, ECC is generated on a QWord (64 bit) basis. Because the MCH stores only entire cache lines in its internal buffers, partial QWord writes initially cause a read of the underlying data, and their write-back into memory is no different from that of a complete cache line. During system memory reads, and the read of the data that underlies partial writes, the MCH supports detection of single-bit and multiple-bit errors, and will correct single-bit errors when correction is enabled. The MCH supports a thermal management scheme to selectively manage reads and/or writes. Thermal management can be triggered by preset read/write bandwidth limits.

AGP Interface

A single AGP component or connector (not both) is supported by the MCH AGP interface. The AGP buffers operate only in 1.5 V mode. They are not 3.3 V safe. The AGP interface supports 1x/2x/4x AGP signaling and 2x/4x fast writes. AGP semantic cycles to system memory are not snooped on the system bus. PCI semantic cycles to system memory are snooped on the system bus. The MCH supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be selected during system initialization. Both upstream and downstream addressing is limited to 32 bits for AGP and AGP/PCI transactions. The MCH contains a 32 deep AGP request queue. High-priority accesses are supported. All accesses from the AGP/PCI interface that fall within the Graphics Aperture address range pass through an address translation mechanism with a fully associative 20 entry TLB. Accesses between AGP and hub interface are limited to memory writes originating from the hub interface destined for AGP. The AGP interface is clocked from a dedicated 66 MHz clock (66IN). The AGP-to-host/core interface is asynchronous.

AD_STB0#

AD_STB1

AD_STB1#

SB_STB

SB_STB#

AGP/PCI Signals
For transactions on the AGP interface carried using AGP FRAME# protocol, these signals operate similar to their semantics in the PCI 2.1 specification the exact role of all AGP FRAME# signals are defined below.
Signal Name G_FRAME# Type I/O s/t/s AGP I/O s/t/s AGP Description FRAME: During FRAME# Operations, G_FRAME# is an output when the MCH acts as an initiator on the AGP Interface. Initiator Ready#: This signal indicates the AGP compliant master is ready to provide all write data for the current transaction. Once G_IRDY# is asserted for a write operation, the master is not allowed to insert wait states. The master is never allowed to insert a wait state during the initial data transfer (32 bytes) of a write transaction. However, it may insert wait states after each 32-byte block is transferred. Target Ready: This signal indicates the AGP compliant target is ready to provide read data for the entire transaction (when the transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. The target is allowed to insert wait states after each block (32 bytes) is transferred on write transactions. STOP: G_STOP Is an input when the MCH acts as a FRAME#-based AGP initiator and an output when the MCH acts as a FRAME#-based AGP target. G_STOP# is used for disconnect, retry, and abort sequences on the AGP interface.

G_IRDY#

G_TRDY#

I/O s/t/s AGP

G_STOP#

Signal Name G_DEVSEL#

Type I/O s/t/s AGP
Description Device Select: This signal indicates that a FRAME#-based AGP target device has decoded its address as the target of the current access. The MCH asserts G_DEVSEL# based on the DRAM address range being accessed by a PCI initiator. As an input it indicates whether any device on the bus has been selected. Request: Indicates that a FRAME# or PIPE#-based AGP master is requesting use of the AGP interface. This signal is an input into the MCH. Grant: During SBA, PIPE# and FRAME# operation, G_GNT#, along with the information on the ST[2:0] signals (status bus), indicates how the AGP interface will be used next. Address/Data Bus: These signals are used to transfer both address and data on the AGP interface. Command/Byte Enable: During FRAME# Operation: During the address phase of a transaction, G_C/BE[3:0]# define the bus command. During the data phase, G_C/BE[3:0]# are used as byte enables. The byte enables determine which byte lanes carry meaningful data. During PIPE# Operation: When an address is enqueued using PIPE#, the G_C/BE# signals carry command information. The command encoding used during PIPE#-based AGP is DIFFERENT than the command encoding used during FRAME#-based AGP cycles (or standard PCI cycles on a PCI bus).

G_REQ#

I AGP O AGP I/O AGP I/O AGP

G_GNT#

G_AD[31:0] G_C/BE[3:0]#

I/O AGP

Parity: During FRAME# Operations: This signal is driven by the MCH when it acts as a FRAME#-based AGP initiator during address and data phases for a write cycle, and during the address phase for a read cycle. PAR is driven by the MCH when it acts as a FRAME#-based AGP target during each data phase of a FRAME#-based AGP memory read cycle. Even parity is generated across AD[31:0] and G_C/BE[3:0]#. During SBA and PIPE# Operation: This signal is not used during SBA and PIPE# operation.
NOTE: PCIRST# from the ICH2 is connected to RSTIN# and is used to reset AGP interface logic within the MCH. The AGP agent will also use PCIRST# provided by the ICH2 as an input to reset its internal logic.
Clocks, Reset, and Miscellaneous Signals
Signal Name BCLK BCLK# 66IN Type I CMOS I CMOS Description Differential Host Clock In: These pins receive a differential host clock from the external clock synthesizer. This clock is used by all of the MCH logic that is in the host clock domain. 66 MHz Clock In: This pin receives a 66 MHz clock from the clock synthesizer. This clock is used by AGP/PCI and hub interface clock domains. Note: That this clock input is 3.3 V tolerant. SCK[11:0] RSTIN# O CMOS I CMOS System Memory Clocks (SDR): These signals deliver a synchronized clock to the DIMMs. There are two per row. Reset In: When asserted, this signal asynchronously resets the MCH logic. RSTIN# is connected to the PCIRST# output of the ICH2. All AGP/PCI output and bi-directional signals will also three-state compliant to PCI Rev 2.0 and 2.1 specifications. Note: This input needs to be 3.3 V tolerant. TESTIN# I CMOS Test Input: This pin is used for manufacturing and board level test purposes. Note: This signal has an internal pull-up resistor.
Voltage Reference and Power Signals
Signal Name HVREF SDREF HI_REF AGPREF HLRCOMP Type Ref Ref Ref Ref I/O CMOS I/O CMOS I/O CMOS I CMOS I/O CMOS Description Host Reference Voltage: Reference voltage input for the data, address, and common clock signals of the host AGTL+ interface. SDRAM Reference Voltage: Reference voltage input for DQ, DQS, RDCLKIN (SDR). Hub Interface Reference: Reference voltage input for the hub interface. AGP Reference: Reference voltage input for the AGP interface. Compensation for Hub Interface: This signal is used to calibrate the hub interface I/O buffers. It is connected to a 40.2 pull-up resistor with 1% tolerance and is pulled up to VCC1_8. Compensation for AGP: This signal is used to calibrate buffers. It is connected to a 40.2 pull-down resistor with a 1% tolerance. Compensation for Host: These signals are used to calibrate the host AGTL+ I/O buffers. Each signal is connected to a 24.9 pull-down resistor with a 1% tolerance. Host Reference Voltage: Reference voltage input for the compensation logic. System Memory RCOMP: 1.5 V Power Input: These pins are connected to a 1.5 V power source. 1.8 V Power Input Pins: These pins are connected to a 1.8 V power source. SDRAM Power Input Pins: These pins are connected to a 3.3 V power source for SDR. PLL Power Input Pins: These pins provide power for the PLL. AGTL+ Bus Termination Voltage Inputs: These pins provide the AGTL+ bus termination. Ground: The VSS pins are the ground pins for the MCH. PLL Ground: The VSSA[1:0] pins are the ground pins for the PLL on the MCH.

Term Reserved Registers

Description In addition to reserved bits within a register, the MCH contains address locations in the configuration space that are marked Reserved. When a Reserved register location is read, a random value is returned. (Reserved registers can be 8-, 16-, or 32-bit in size). Registers that are marked as Reserved must not be modified by system software. Writes to Reserved registers may cause system failure. Upon a Full Reset, the MCH sets all of its internal configuration registers to predetermined default states. Some register values at reset are determined by external strapping options. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software (usually BIOS) to properly determine the DRAM configurations, operating parameters and optional system features that are applicable, and to program the MCH registers accordingly.
Default Value upon a Reset
PCI Bus Configuration Space Access
The MCH and ICH2 are physically connected by the hub interface. From a configuration standpoint, the hub interface is PCI bus 0. As a result, all devices internal to the MCH and ICH2 appear to be on PCI bus 0. The systems primary PCI expansion bus is physically attached to the ICH2 and, from a configuration perspective appears to be a hierarchical PCI bus behind a PCI-toPCI bridge and, therefore, has a programmable PCI Bus number. Note that the primary PCI bus is referred to as PCI_A in this document and is not PCI bus #0 from a configuration standpoint. The AGP appears to system software to be a real PCI bus behind PCI-to-PCI bridges resident as devices on PCI bus 0. The MCH contains two PCI devices within a single physical component. The configuration registers for the four devices are mapped as devices residing on PCI bus 0.
Device 0: Host-Hub Interface Bridge/DRAM Controller. Logically this appears as a PCI device residing on PCI bus 0. Physically Device 0 contains the standard PCI registers, DRAM registers, the Graphics Aperture controller, and other MCH specific registers.
Device 1: Host-AGP Bridge. Logically this appears as a virtual PCI-to-PCI bridge residing on PCI bus 0. Physically Device 1 contains the standard PCI-to-PCI bridge registers and the standard AGP/PCI configuration registers (including the AGP I/O and memory address mapping). Table 6 shows the Device # assignment for the various internal MCH devices. Table 6. Intel MCH Internal Device Assignments
MCH Function DRAM Controller/8 bit HI_A Controller Host-to-AGP Bridge (virtual P2P) Bus 0, Device # Device 0 Device 1
NOTE: A physical PCI bus 0 does not exist. The hub interface and the internal devices in the MCH and ICH2, logically constitute PCI Bus 0 to configuration software.
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8 functions with each function containing up to 256 8-bit configuration registers. The PCI specification defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported by a mapping mechanism implemented within the MCH. The PCI specification defines two mechanisms to access configuration space, Mechanism #1 and Mechanism #2. The MCH supports only Mechanism #1. The configuration access mechanism makes use of the CONF_ADDR Register (at I/O address 0CF8h though 0CFBh) and CONF_DATA register (at I/O address 0CFCh though 0CFFh). To reference a configuration register a DWord I/O write cycle is used to place a value into CONF_ADDR that specifies the PCI bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. CONF_ADDR[31] must be 1 to enable a configuration cycle. CONF_DATA then becomes a window into the four bytes of configuration space specified by the contents of CONF_ADDR. Any read or write to CONF_DATA results in the MCH translating the CONF_ADDR into the appropriate configuration cycle. The MCH is responsible for translating and routing the processors I/O accesses to the CONF_ADDR and CONF_DATA registers to internal MCH configuration registers, hub interface or AGP.

The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only. Each PAM Register controls two regions, typically 16 KB in size. Each of these regions has a 4-bit field. The four bits that control each region have the same encoding and defined in the following table.
Bits [7, 3] Reserved X Bits [6, 2] Reserved X Bits [5, 1] WE 0 Bits [4, 0] RE 0 Description Disabled. System memory is disabled and all accesses are directed to the hub interface. The MCH does not respond as a PCI target for any read or write access to this area. Read Only. Reads are forwarded to system memory and writes are forwarded to the hub interface for termination. This write protects the corresponding memory segment. The MCH responds as an AGP or hub interface target for read accesses but not for any write accesses. Write Only. Writes are forwarded to system memory and reads are forwarded to the hub interface for termination. The MCH responds as an AGP or hub interface target for write accesses but not for any read accesses. Read/Write. This is the normal operating mode of system memory. Both read and write cycles from the host are claimed by the MCH and forwarded to system memory. The MCH responds as an AGP or hub interface target for both read and write accesses.
At the time that a hub interface or AGP accesses to the PAM region may occur, the targeted PAM segment must be programmed to be both readable and writeable. As an example, consider BIOS that is implemented on the expansion bus. During the initialization process, the BIOS can be shadowed in system memory to increase the system performance. When BIOS is shadowed in system memory, it should be copied to the same address location. To shadow the BIOS, the attributes for that address range should be set to write only. BIOS is shadowed by first performing a read of that address. This read is forwarded to the expansion bus. The host then does a write of the same address, which is directed to system memory. After the BIOS is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus. Table 9 and Figure 2 show the PAM registers and the associated attribute bits: Figure 2. PAM Register Attributes
Offset PAM6 PAM5 PAM4 PAM3 PAM2 PAM1 PAMR Reserved Reserved Write Enable (R/W) 1=Enable 0=Disable Read Enable (R/W) 1=Enable 0=Disable 6 R 5 WE 4 RE 3 R 2 R 1 WE 0 RE Read Enable (R/W) 1=Enable 0=Disable Write Enable (R/W) 1=Enable 0=Disable Reserved Reserved
96h 95h 94h 93h 92h 91h 90h
Table 9. PAM Register Attributes

3.5.26

AGPSTATAGP Status Register (Device 0)
Address Offset: Default Value: Access: Size: A4A7h 1F00_0217h RO 32 bits
This register reports AGP device capability/status.
Bit 31:24 Description Request Queue (RQ). This field contains the maximum number of AGP command requests the MCH is configured to manage. 1Fh = Allows a maximum of 32 outstanding AGP command requests. 23:8:2:0 Reserved. Side Band Addressing Support (SBA). Hardwired to 1 to indicate that the MCH supports side band addressing. Reserved. Greater that 4 GB Support (4G). Hardwired to 0 to indicate that the MCH does not support addresses greater than 4. Fast Write Support (FW). Hardwired to 1 to indicate that the MCH supports Fast Writes from the host to the AGP master. Reserved. Data Rate Support (RATE). Hardwired to 111. After reset, the MCH reports its data transfer rate capability. Bit 0 identifies if AGP device supports 1x data transfer mode, bit 1 identifies if AGP device supports 2x data transfer mode, bit 2 identifies if AGP device supports 4x data transfer mode. 111 = 1x, 2x, and 4x data transfer modes are supported by the MCH Note: The selected data transfer mode applies to both AD bus and SBA bus. It also applies to Fast Writes if they are enabled.

3.5.27

AGPCMDAGP Command Register (Device 0)
Address Offset: Default Value: Access: Size: A8ABh 0000_0000h R/W 32 bits
This register provides control of the AGP operational parameters.
Bit 31:Reserved. SideBand Address Enable (SBAEN). 0 = Disable. 1 = Enable. 8 AGP Enable (AGPEN). 0 = The MCH ignores all AGP operations, including the sync cycle. Any AGP operation received while this bit is 1 will be serviced, even if this bit is set to 0. If this bit transitions from a 1 to a 0 on a clock edge in the middle of an SBA command being delivered in 1X mode, the command will be issued. 1 = The MCH will respond to AGP operations delivered via PIPE# or to operations delivered via SBA if the AGP Side Band Enable bit is also set to 1. 7:Reserved. Fast Write Enable (FWEN). 0 = When this bit is set to 0, or when the data rate bits are set to 1x mode, the memory write transactions from the MCH to the AGP master use standard PCI protocol. 1 = MCH uses the Fast Write protocol for memory write transactions from the MCH to the AGP master. Fast Writes occur at the data transfer rate selected by the DRATE bits (2:0) in this register. 3 2:0 Reserved. Data Rate (DRATE). The settings of these bits determine the AGP data transfer rate. One (and only one) bit in this field must be set to indicate the desired data transfer rate. 001 = 1x transfer mode 010 = 2x transfer mode 100 = 4x transfer mode Configuration software updates this field by setting only one bit that corresponds to the capability of AGP master (after that capability has been verified by accessing the same functional register in the AGP masters configuration space.) Note: This field applies to AD and SBA buses. It also applies to Fast Writes if they are enabled. Description

Bit 31:12

Description Aperture Translation Table Base (TTABLE). This field contains a pointer to the base of the translation table used to map memory space addresses in the aperture range to addresses in system memory. Note: It should be modified only when the GTLB has been disabled.

3.5.31

AMTTAGP Interface Multi-Transaction Timer Register (Device 0)
Address Offset: Default Value: Access: Size: BCh 00h R/W 8 bits
AMTT is an 8-bit register that controls the amount of time that the MCH arbiter allows AGP master to perform multiple back-to-back transactions. The MCH AMTT mechanism is used to optimize the performance of the AGP master (using PCI protocol) that performs multiple back-toback transactions to fragmented memory ranges (and as a consequence it can not use long burst transfers). The AMTT mechanism applies to the host-AGP transactions as well and it guarantees to the processor a fair share of the AGP interface bandwidth. The number of clocks programmed in the AMTT represents the guaranteed time slice (measured in 66 MHz clocks) allotted to the current agent (either AGP master or host bridge) after which the AGP arbiter will grant the bus to another agent. The default value of AMTT is 00h and disables this function. The AMTT value can be programmed with 8-clock granularity. For example, if the AMTT is programmed to 18h, then the selected value corresponds to the time period of 24 AGP (66 MHz) clocks.
Bit 7:3 Description Multi-Transaction Timer Count Value (MTTC). The number programmed in these bits represents the guaranteed time slice (measured in eight 66 MHz clock granularity) allotted to the current agent (either AGP master or MCH) after which the AGP arbiter will grant the bus to another agent. Reserved.

3.5.32

LPTTAGP Low Priority Transaction Timer Register (Device 0)
Address Offset: Default Value: Access: Size: BDh 00h R/W 8 bits
LPTT is an 8-bit register similar in function to AMTT. This register is used to control the minimum tenure on the AGP for low-priority data transactions (both reads and writes) issued using PIPE# or SB mechanisms. The number of clocks programmed in the LPTT represents the guaranteed time slice (measured in 66 MHz clocks) allotted to the current low priority AGP transaction data transfer state. This does not necessarily apply to a single transaction but it can span over multiple low-priority transactions of the same type. After this time expires, the AGP arbiter may grant the bus to another agent if there is a pending request. The LPTT does not apply in the case of high-priority request where ownership is transferred directly to high-priority requesting queue. The default value of LPTT is 00h and disables this function. The LPTT value can be programmed with 8-clock granularity. For example, if the LPTT is programmed to 10h, the selected value corresponds to the time period of 16 AGP (66 MHz) clocks.

3.5.36

ERRCMDError Command Register (Device 0)
Address Offset: Default Value: Access: Size: CACBh 0000h R/W 16 bits
This register enables various errors to generate a SERR message via the hub interface. Since the MCH does not have an SERR# signal, SERR messages are passed from the MCH to the ICH2 over the hub interface. When a bit in this register is set, a SERR message will be generated on the hub interface when the corresponding flag is set in the ERRSTS register. The actual generation of the SERR message is globally enabled for Device 0 via the PCICMD register. Note: An error can generate one and only one error message via the hub interface. It is softwares responsibility to make sure that when an SERR error message is enabled for an error condition, SMI and SCI error messages are disabled for that same error condition.
Bit 15:Reserved. SERR on Non-DRAM Lock (LCKERR). 0 = Disable.
1 = Enable. The MCH will generate a hub interface SERR special cycle when a processor lock cycle is detected that does not hit system memory. 8:Reserved. SERR on Target Abort on Hub Interface Exception (TAHLA_SERR). 0 = Disable. 1 = Enable. Generation of the hub interface SERR message is enabled when a MCH-originated hub interface cycle is completed with Target Abort completion packet or special cycle status. 5 SERR on Detecting Hub Interface Unimplemented Special Cycle (HIAUSCERR). SERR messaging for Device 0 is globally enabled in the PCICMD register. 0 = Disable. MCH does not generate an SERR message for this event. 1 = Enable. MCH generates a SERR message over the hub interface when an unimplemented Special Cycle is received on the hub interface.
Description SERR on AGP Access Outside of Graphics Aperture (OOGF_SERR). 0 = Disable. 1 = Enable. Generation of the hub interface SERR message is enabled when an AGP access occurs to an address outside of the graphics aperture.
SERR on Invalid AGP Access (IAAF_SERR). 0 = Disable. 1 = Generation of the hub interface SERR message is enabled when an AGP access occurs to an address outside of the graphics aperture and either to the 640 KB 1 MB range or above the top of memory.
SERR on Invalid Translation Table Entry (ITTEF_SERR). 0 = Disable. 1 = Enable. Generation of the hub interface SERR message is enabled when an invalid translation table entry was returned in response to an AGP access to the graphics aperture.
SERR Multiple-Bit DRAM ECC Error (DMERR_SERR). 0 = Disable. For systems not supporting ECC, this bit must be disabled. 1 = Enable. Generation of the hub interface SERR message is enabled when the MCH system memory controller detects a multiple-bit error.
SERR on Single-bit ECC Error (DSERR). 0 = Disable. For systems that do not support ECC, this bit must be disabled. 1 = Enable. Generation of the hub interface SERR message is enabled when the MCH system memory controller detects a single bit error.

3.5.37

SMICMDSMI Command Register (Device 0)

START Read Thermal Management (SRTM). Software writes to this bit to start and stop read thermal management. 0 = Read thermal management stops and the counters associated with RTMW and RTHM are reset. 1 = Read thermal management begins based on the settings in RTMW and RTHM, and remains to be in effect until this bit is reset to 0.
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System Address Map

A system based on the 845 chipset supports 4 GB of addressable memory space and 64 KB+3 of addressable I/O space. The I/O and memory spaces are divided by system configuration software into regions. The memory ranges are useful either as system memory or as specialized memory, while the I/O regions are used solely to control the operation of devices in the system. When the MCH receives a write request whose address targets an invalid space, the data is ignored. For reads, the MCH responds by returning all zeros on the requesting interface.

Memory Address Ranges

The system memory map is broken into two categories: Extended Memory Range (1 MB to 4 GB). The second is extended memory, existing between 1MB and 4GB. It contains a 32-bit memory space, which is used for mapping PCI, AGP, APIC, SMRAM, and BIOS memory spaces. DOS Compatible Area (below 1 MB). The final range is a DOS legacy space, which is used for BIOS and legacy devices on the LPC interface.
Figure 3. Addressable Memory Space
16 GB Additional System M em ory Address Range 4 GB PCI Mem ory Address Range Top of Low Mem ory System M em ory Address Range 1 MB DOS Legacy Address Range Independently Program m able Non-overlapping W indows Hub Interface AG P Graphics Aperture I/O Aperture APICs

sys_addr_map_1

These address ranges are always mapped to system memory, regardless of the system configuration. Memory may be taken out of the system memory segment for use by System Management Mode (SMM) hardware and software. The Top of Low Memory (TOM) register defines the top of system memory. Note that the address of the highest 16 MB quantity of valid memory in the system is placed into the GBA15 register. For memory populations <3 GB, this value will be the same as the one programmed into the TOM register. For other memory configurations, the two are unlikely to be the same, since the PCI configuration portion of the BIOS software will program the TOM register to the maximum value that is less than the amount of memory in the system and that allows enough room for all populated PCI devices.

AGP Interface Overview

The MCH supports 1.5 V AGP 1x/2x/4x devices. The AGP signal buffers are 1.5 V drive/receive (buffers are not 3.3 volt tolerant). The MCH supports 2x/4x source synchronous clocking transfers for read and write data, and sideband addressing. The MCH also support 2x and 4x clocking for Fast Writes initiated from the MCH (on behalf of the processor). AGP PIPE# or SBA[7:0] transactions to system memory do not get snooped and are, therefore, not coherent with the processor caches. AGP FRAME# transactions to system memory are snooped. AGP PIPE# and SBA[7:0] accesses to and from the hub interface are not supported. AGP FRAME# access from an AGP master to the hub interface are also not supported. Only the AGP FRAME memory writes from the hub interface are supported.

AGP Target Operations

As an initiator, the MCH does not initiate cycles using AGP enhanced protocols. The MCH supports AGP cycles targeting the interface to system memory only. The MCH supports interleaved AGP PIPE# and AGP FRAME#, or AGP SBA[7:0] and AGP FRAME# transactions.
Table 15. AGP Commands Supported by the Intel MCH When Acting as an AGP Target
AGP Command C/BE[3:0]# Encoding Cycle Destination Read Hi-Priority Read Reserved Reserved Write Hi-Priority Write System memory Hub interface System memory The Hub interface N/A N/A System memory Hub interface System memory Hub interface MCH Host Bridge Response as PCIx Target Low-priority read Complete with random data High-priority read Complete with random data No response No response Low-priority write Cycle goes to DRAM with byte enables inactive High-priority write Cycle goes to DRAM with byte enables inactive; does not go to the hub interface No response No response Low-priority read Complete locally with random data; does not go to the hub interface High-priority read Complete with random data Complete with QW of random data No response No response; Flag inserted in MCH request queue No response No response No response
Reserved Reserved Long Read
N/A N/A System memory Hub interface

Hi-Priority Long Read

System memory Hub interface
Flush Reserved Fence Reserved Reserved Reserved

The 845 chipset is supported by the CK_408 compliant clock synthesizer. For details on clocking, refer to the Intel Pentium 4 Processor in a 478 Pin Package and Intel 845 Chipset Platform Design Guide.
Intel MCH System Reset and Power Sequencing
For details on MCH system reset and power sequencing, refer to the Intel Pentium 4 Processor in a 478 Pin Package and Intel 845 Chipset Platform Design Guide.
Electrical Characteristics
This chapter contains the absolute maximum operating ratings, power characteristics, and DC characteristics for the 82845 MCH.

Absolute Maximum Ratings

Table 18 lists the MCHs maximum environmental stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. Functional operating parameters are listed in the DC tables.
Warning: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operating beyond the operating conditions is not recommended and extended exposure beyond operating conditions may affect reliability. Table 18. Absolute Maximum Ratings
Symbol Tstorage VCC1_5 VCC1_8 VCCSM VTT Parameter Storage Temperature 1.5 V Supply Voltage with respect to VSS 1.8 V Supply Voltage with respect to VSS 3.3 V Supply Voltage with respect to VSS AGTL+ buffer DC input voltage with respect to VSS Min -55 -0.72 -0.88 -2.83 -0.55 Max 150 2.3 2.69 6.3 2.3 Unit C V V V V Notes

Power Characteristics

Symbol IVTT IVCC1_5_CORE IVCC1_5_AGP IVCC1_8 IVCCSM ISUS_3.3 Parameter MCH VTT supply current 1.5 V core supply current 1.5 V AGP supply current 1.8 V hub interface supply current 3.3 V system memory supply current 3.3 V standby supply current HVREF, AGPREF, HI_REF, SDREF supply current Min Typ Max 2.4 1.5 0.37 0.20 2.10 Unit A A A A A mA mA Notes
Table 19. Power Characteristics
NOTES: 1. These current levels can happen simultaneously, and can be summed into one supply.

Signal Groups

The signal description includes the type of buffer used for the particular signal: AGTL+ AGP Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete details. The MCH integrates most AGTL+ termination resistors. AGP interface signals. These signals are compatible with AGP 2.0 1.5 V Signaling Environment DC and AC Specifications. The buffers are not 3.3 V tolerant. Hub Interface 1.8 V CMOS buffers. System memory 3.3 V CMOS buffers.
HI CMOS SM CMOS Table 20. Signal Groups

Signal Group (a)

Signal Type AGTL+ I/O
Signals ADS#, BNR#, BR0#,DBSY#, DBI[3:0]#, DRDY#, HA[31:3]#, HADSTB[1:0] #, HD[63:0]#, HDSTBP[3:0]#, HDSTBN[3:0]#, HIT#, HITM#, HREQ[4:0]# BPRI#, CPURST#, DEFER#, HTRDY#, RS[2:0]# HLOCK# HVREF, HSWING[1:0] AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, G_FRAME#, G_IRDY#, G_TRDY#, G_STOP#, G_DEVSEL#, G_AD[31:0], G_C/BE[3:0]#, G_PAR PIPE#, SBA[7:0], RBF#, WBF#, SB_STB, SB_STB#, G_REQ# ST[2:0], G_GNT# AGPREF HI_[10:0], HI_STB, HI_STB# HI_REF SDQ[63:0], SCB[7:0] SCS[11:0]#, SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE#, SCKE[5:0], SCK[11:0], RDCLKO RDCLKI SDREF TESTIN# RSTIN# (3.3V) VTT