Intel Pentium P6000 and U5000 Mobile Processor Series

Specification Update

February 2011 Revision 008
Document Number: 323874-008
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Contents

Preface..... 5 Summary Tables of Changes... 7 Identification Information.... 14 Errata..... 17 Specification Changes.... 49 Specification Clarifications... 50 Documentation Changes... 51

Revision History

Revision Initial release

Description

Revision Date May 2010 June 2010 July 2010 September 2010 October 2010 December 2010 January 2011 February 2011
Added P6000 sku information Added BG81 and BG82 Removed erratum description for BG61 Added BG83. Changed wording on BG31. and BG66. Added BG84 and BG85 Added BG86.
Added BG87. and BG88. Added U5600 processor information in Table 1-1
Added errata BG89. BG90. BG91. BG92. BG93. Added P6300 processor information in Table 1-1

Preface

This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published.

Summary Tables of Changes
The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations:
Codes Used in Summary Tables

Stepping

X: (No mark) or (Blank box): This erratum is fixed in listed stepping or specification change does not apply to listed stepping. Errata exists in the stepping indicated. Specification Change or Clarification that applies to this stepping.
(Page): Page location of item in this document.

Status

Doc: Plan Fix: Fixed: No Fix: Document change or update will be implemented. This erratum may be fixed in a future stepping of the product. This erratum has been previously fixed. There are no plans to fix this erratum.
Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document. Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intels microprocessor Specification Updates:

Errata (Sheet 1 of 5)

Number BG1 Steppings C-2 X K-0 X Status No Fix ERRATA The Processor May Report a #TS Instead of a #GP Fault REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher Priority Interrupts/Exceptions and May Push the Wrong Address onto the Stack Performance Monitor SSE Retired Instructions May Return Incorrect Values Premature Execution of a Load Operation Prior to Exception Handler Invocation MOV To/From Debug Registers Causes Debug Exception Incorrect Address Computed For Last Byte of FXSAVE/ FXRSTOR Image Leads to Partial Memory Update Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM Single Step Interrupts with Floating Point Exception Pending May Be Mishandled Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception General Protection Fault (#GP) for Instructions Greater than 15 Bytes May Be Preempted General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit LBR, BTS, BTM May Report a Wrong Address When an Exception/Interrupt Occurs in 64-bit Mode MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang Corruption of CS Segment Register during RSM While Transitioning from Real Mode to Protected Mode Performance Monitoring Events for Read Miss to Level 3 Cache Fill Occupancy Counter May Be Incorrect Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately #GP on Segment Selector Descriptor That Straddles Canonical Boundary May Not Provide Correct Exception Error Code Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint Is Set on a #GP Instruction

BG54 BG55 BG56 BG57 BG58 BG59 BG60 BG61 BG62
No Fix No Fix No Fix No Fix No Fix No Fix No Fix NA

Errata (Sheet 4 of 5)

Number Steppings C-2 X K-0 X Status ERRATA MSR_TURBO_RATIO_LIMIT MSR May Return Intel Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations PCI Express* x16 Port Logs Bad TLP Correctable Error When Receiving a Duplicate TLP PCI Express x16 Root Port Incorrectly NAK's a Nullified TLP PCI Express Graphics Receiver Error Reported When Receiver with L0s Enabled and Link Retrain Performed Internal Parity Error May Be Incorrectly Signaled during Deep Power Down Technology (code name C6 state) Exit PMIs during Core Deep Power Down Technology (code name C6 state) Transitions May Cause the System to Hang 2-MB Page Split Lock Accesses Combined with Complex Internal Events May Cause Unpredictable System Behavior Extra APIC Timer Interrupt May Occur during a Write to the Divide Configuration Register 8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides With Interrupt Acknowledge Cycle From the Preceding Interrupt CPUID Incorrectly Reports a C-State as Available When this State is Unsupported The Combination of a Page-Split Lock Access and Data Accesses That Are Split across Cacheline Boundaries May Lead to Processor Livelock Processor Hangs on Package Deep Power Down technology (code named Deep Power Down Technology (code name C6) State Exit A Synchronous SMI May Be Delayed FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit ModeFP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode PCI Express Cards May Not Train to x16 Link Width The APIC Timer Current Count Register May Prematurely Read 0x0 While the Timer Is Still Running CKE May go Low Within tRFC(min) After a PD Exit Under Certain Low Temperature Conditions, Some Uncore Performance Monitoring Events May Report Incorrect Results Performance Monitor Events for Hardware Prefetches Which Miss The L1 Data Cache May be Over Counted Correctable and Uncorrectable Cache Errors May be Reported Until the First Core C6 Transition

When EAX is initialized to a value of 1, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID value in the EAX register. Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register. Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.
Intel Pentium P6000 and U5000 Mobile Processor Series can be identified by the following register contents:
Processor Stepping C-2 K-0 NOTES:
1. 2. 3. 4. The Vendor ID corresponds to Bits 15:0 of the Vendor ID Register located at offset 0001h in the PCI function 0 configuration space. The Device ID corresponds to Bits 15:0 of the Device ID Register located at Device 0 offset 0203h in the PCI function 0 configuration space. The Revision Number corresponds to Bits 7:0 of the Revision ID Register located at offset 08h in the PCI function 0 configuration space. Correct Host Device ID requires firmware support.

Vendor ID1 8086h 8086h

Device ID2 0044h 0044h

Revision ID3 12h 18h

Component Marking Information
The processor stepping can be identified by the following component markings: Figure 1-1. Intel Pentium Mobile processor PGA Component Markings
For P G A G RP 1 LIN E1 (lim ited to cha r, pt font): G RP 2 LIN E1 (lim ited to cha r, pt font): IN TEL{M }{C }Y Y P RO C #
G RP 3 LIN E1 : (lim ited to 1 (ex) cha r, pt font): {e4 } G RP 4 LIN E1 (lim ited to 9 cha r, pt font): SSP EC G RP 4 LIN E2 (lim ited to 9 cha r, pt font): {FP O }
Figure 1-2. Intel Pentium Mobile processor BGA Component Markings
For BG A G RP 1 LIN E1 (limited to cha r, pt font): i{M}{C}Y Y SSP EC P RO C# G RP 2 LIN E1 : (lim ited to 1 (ex) cha r, pt font): {e1 } G RP 3 LIN E1 (limited to cha r, pt font): {FP O }
Table 1-1. Processor Identification
Processor Number Stepping/ Processor Signature/Host Device ID/ Host Revision ID L3 Cache (MB) Frequency LFM Frequency Max Intel Turbo Boost Technology Frequency Single Core Turbo Dual Core Turbo Graphics Turbo
Core Base (GHz) Graphics Base (MHz) DDR3 (MT/s)
C-2/ SLBWB P6000 20652h/ 0044h/12h K-0/ SLBUH U5400 20655h/ 0044h/18h K-0/ SLBSM U5600 20655h/ 0044h/18h K-0/ Q4CT P6300 20655h/ 0044h/18h K-0/ SLBU8 P6300 20655h/ 0044h/18h 3MB 3MB 3MB
Core: 1.86 GHz Gfx: 500 MHz DDR3: 1066/800 MT/s Core: 1.2 GHz Gfx: 166 MHz DDR3: 800 MT/s Core: 1.33 GHz Gfx: 166 MHz DDR3: 800 MT/s Core: 2.26 GHz 3 MB Gfx: 500 MHz DDR3: 1066/ 800 MT/s Core: 2.26 GHz 3 MB Gfx: 500 MHz DDR3: 1066/ 800 MT/s
Core1: NA Core2: NA Gfx: 667 MHz Core1: NA Core2: NA Gfx: 500 MHz Core1: NA Core2: NA Gfx: 500 MHz Core1: NA Core2: NA Gfx: 667 MHz Core1: NA Core2: NA Gfx: 667 MHz 933 MHz PGA 933 MHz PGA 667 MHz BGA 667 MHz BGA 933 MHz PGA

2,3,5, 6,8

1,4,5, 6,7 1,4,5, 6,7

NOTES:

1. 2. 3. 4. 5. 6. 7. 8. Core Tjmax = 105C, Graphics Tjmax = 100C Core Tjmax = 90C, Graphics Tjmax = 85C Standard voltage with 35W TDP Ultra low voltage with 18W TDP The core frequency reported in the processor brand string is rounded to 2 decimal digits. (For example, core frequency of 2.6666, repeating 6, is reported as @2.67 in brand string. Core frequency of 2.5333, is reported as @2.53 in brand string.) Intel GPMT is supported. GPMT frequency runs at 366 MHz. This part supports C1, C1E, C3 and Deep Power Down Technology (code name C6 state) This part supports C1, C1E and C3

QDF / S-Spec Number

Package

Errata

BG1. Problem: The Processor May Report a #TS Instead of a #GP Fault A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception) instead of a #GP fault (general protection exception).
Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially-available software. Workaround:None identified. Status: BG2. For the steppings affected, see the Summary Tables of Changes. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations Under certain conditions as described in the Software Developers Manual section Outof-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors the processor performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data size or may observe memory ordering violations.

Problem:

Implication: Upon crossing the page boundary the following may occur, dependent on the new page memory type:
UC the data size of each write will now always be 8 bytes, as opposed to the

original data size.

WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.

Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if alignment checks are disabled at the start of the IRET. This erratum can only be observed with a software generated stack frame. Workaround:Software should not generate misaligned stack frames for use with IRET. Status: BG12. Problem: For the steppings affected, see the Summary Tables of Changes. General Protection Fault (#GP) for Instructions Greater Than 15 Bytes May Be Preempted When the processor encounters an instruction that is greater than 15 bytes in length, a #GP is signaled when the instruction is decoded. Under some circumstances, the #GP fault may be preempted by another lower priority fault (e.g., Page Fault (#PF)). However, if the preempting lower priority faults are resolved by the operating system and the instruction retried, a #GP fault will occur.
Implication: Software may observe a lower-priority fault occurring before or in lieu of a #GP fault. Instructions of greater than 15 bytes in length can only occur if redundant prefixes are placed before the instruction. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG13. Problem:

General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit In 32-bit mode, memory accesses to flat data segments (base = 00000000h) that occur above the 4-G limit (0ffffffffh) may not signal a #GP fault.
Implication: When such memory accesses occur in 32-bit mode, the system may not issue a #GP fault. Workaround:Software should ensure that memory accesses in 32-bit mode do not occur above the 4-G limit (0ffffffffh). Status: BG14. Problem: For the steppings affected, see the Summary Tables of Changes. LBR, BTS, BTM May Report a Wrong Address When an Exception/Interrupt Occurs in 64-bit Mode An exception/interrupt event should be transparent to the LBR (Last Branch Record), BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However, during a specific boundary condition where the exception/interrupt occurs right after the execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF) in 64-bit mode, the LBR return registers will save a wrong return address with Bits 63 to 48 incorrectly sign extended to all 1's. Subsequent BTS and BTM operations which report the LBR will also be incorrect.
Implication: LBR, BTS and BTM may report incorrect information in the event of an exception/ interrupt. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Implication: An incorrect error code may be pushed onto the stack. Intel has not observed this erratum with any commercially-available software. Workaround:None identified. Status: BG20. Problem: For the steppings affected, see the Summary Tables of Changes. Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint Is Set on a #GP Instruction While coming out of cold reset or exiting from Deep Power Down Technology (code name C6 state), if the processor encounters an instruction longer than 15 bytes (which causes a #GP) and a code breakpoint is enabled on that instruction, an IQ (Instruction Queue) parity error may be incorrectly logged resulting in an MCE (Machine Check Exception).
Implication: When this erratum occurs, an MCE may be incorrectly signaled. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/ POP SS Instruction If It Is Followed by an Instruction That Signals a Floating Point Exception A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints until after execution of the following instruction. This is intended to allow the sequential execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having an invalid stack during interrupt handling. However, an enabled debug breakpoint or single step trap may be taken after MOV SS/POP SS if this instruction is followed by an instruction that signals a floating point exception rather than a MOV [r/e]SP, [r/e]BP instruction. This results in a debug exception being signaled on an unexpected instruction boundary since the MOV SS/POP SS and the following instruction should be executed atomically.
Implication: This can result in incorrect signaling of a debug exception and possibly a mismatched Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any exception. Intel has not observed this erratum with any commercially-available software or system. Workaround:As recommended in the IA32 Intel Architecture Software Developers Manual, the use of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure since the MOV [r/e]SP, [r/e]BP will not generate a floating point exception. Developers of debug tools should be aware of the potential incorrect debug event signaling created by this erratum. Status: BG22. Problem: For the steppings affected, see the Summary Tables of Changes. IA32_MPERF Counter Stops Counting during On-Demand TM1 According to the Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A: System Programming Guide, the ratio of IA32_MPERF (MSR E7H) to IA32_APERF (MSR E8H) should reflect actual performance while Intel TM1 or ondemand throttling is activated. Due to this erratum, IA32_MPERF MSR stops counting while Intel TM1 or on-demand throttling is activated, and the ratio of the two will indicate higher processor performance than actual.

Implication: The incorrect ratio of IA32_APERF/IA32_MPERF can mislead software P-state (performance state) management algorithms under the conditions described above. It is possible for the Operating System to observe higher processor utilization than actual, which could lead the OS into raising the P-state. During Intel TM1 activation, the OS Pstate request is irrelevant and while on-demand throttling is enabled, it is expected that the OS will not be changing the P-state. This erratum should result in no practical implication to software. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG23. Problem:

The Memory Controller tTHROT_OPREF Timings May Be Violated during SelfRefresh Entry During self-refresh entry, the memory controller may issue more refreshes than permitted by tTHROT_OPREF (bits 29:19 in MC_CHANNEL_{0,1}_REFRESH_TIMING CSR).
Implication: The intention of tTHROT_OPREF is to limit current. Since current supply conditions near self refresh entry are not critical, there is no measurable impact due to this erratum. Workaround:None identified. Status: BG24. Problem: For the steppings affected, see the Summary Tables of Changes. Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does Not Work When either the IA32_MPERF or IA32_APERF MSR (E7H, E8H) increments to its maximum value of 0xFFFF_FFFF_FFFF_FFFF, both MSRs are supposed to synchronously reset to 0x0 on the next clock. This synchronous reset does not work. Instead, both MSRs increment and overflow independently.
Implication: Software can not rely on synchronous reset of the IA32_APERF/IA32_MPERF registers. Workaround:None identified. Status: BG25. Problem: For the steppings affected, see the Summary Tables of Changes. Disabling Thermal Monitor While Processor Is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio If a processor is at its TCC (Thermal Control Circuit) activation temperature and then Thermal Monitor is disabled by a write to IA32_MISC_ENABLES MSR (1A0H) bit [3], a subsequent re-enable of Intel Thermal Monitor will result in an artificial ceiling on the maximum core P-state. The ceiling is based on the core frequency at the time of Intel Thermal Monitor disable. This condition will only correct itself once the processor reaches its TCC activation temperature again.
Implication: Since Intel requires that Intel Thermal Monitor be enabled in order to be operating within specification, this erratum should never be seen during normal operation. Workaround:Software should not disable Intel Thermal Monitor during processor operation. Status: For the steppings affected, see the Summary Tables of Changes.

BG26. Problem:

Infinite Stream of Interrupts May Occur If an ExtINT Delivery Mode Interrupt Is Received While All Cores Are in Deep Power Down Technology (code name C6 state) If all logical processors in a core are in Deep Power Down Technology (code name C6 state), an ExtINT delivery mode interrupt is pending in the xAPIC and interrupts are blocked with EFLAGS.IF=0, the interrupt will be processed after Deep Power Down Technology (code name C6 state) wakeup and after interrupts are re-enabled (EFLAGS.IF=1). However, the pending interrupt event will not be cleared.
Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the external interrupt. Intel has not observed this erratum with any commercially-available software/system. Workaround:None identified. Status: BG30. Problem: For the steppings affected, see the Summary Tables of Changes. Two xAPIC Timer Event Interrupts May Unexpectedly Occur If an xAPIC timer event is enabled and while counting down the current count reaches 1 at the same time that the processor thread begins a transition to a low power Cstate, the xAPIC may generate two interrupts instead of the expected one when the processor returns to C0.
Implication: Due to this erratum, two interrupts may unexpectedly be generated by an xAPIC timer event. Workaround:None identified. Status: BG31. Problem: For the steppings affected, see the Summary Tables of Changes. EOI Transaction May Not Be Sent If Software Enters Core Deep Power Down Technology (code name C6 state) during an Interrupt Service Routine If core Deep Power Down Technology (code name C6 state) is entered after the start of an interrupt service routine but before a write to the APIC EOI register, the core may not send an EOI transaction (if needed) and further interrupts from the same priority level or lower may be blocked.
Implication: EOI transactions and interrupts may be blocked when core Deep Power Down Technology (code name C6 state) is used during interrupt service routines. Intel has not observed this erratum with any commercially-available software. Workaround:Software should check the ISR register and if any interrupts are in service only enter C1. Status: For the steppings affected, see the Summary Tables of Changes.

BG42. Problem:

Performance Monitor Counters May Count Incorrectly Under certain circumstances, a general purpose performance counter, IA32_PMC0-4 (C1H - C4H), may count at core frequency or not count at all instead of counting the programmed event.
Implication: The Performance Monitor Counter IA32_PMCx may not properly count the programmed event. Due to the requirements of the workaround there may be an interruption in the counting of a previously programmed event during the programming of a new event. Workaround:Before programming the performance event select registers, IA32_PERFEVTSELx MSR (186H - 189H), the internal monitoring hardware must be cleared. This is accomplished by first disabling, saving valid events and clearing from the select registers, then programming three event values 0x4300D2, 0x4300B1 and 0x4300B5 into the IA32_PERFEVTSELx MSRs, and finally continuing with new event programming and restoring previous programming if necessary. Each performance counter, IA32_PMCx, must have its corresponding IA32_PREFEVTSELx MSR programmed with at least one of the event values and must be enabled in IA32_PERF_GLOBAL_CTRL MSR (38FH) bits [3:0]. All three values must be written to either the same or different IA32_PERFEVTSELx MSRs before programming the performance counters. Note that the performance counter will not increment when its IA32_PERFEVTSELx MSR has a value of 0x4300D2, 0x4300B1 or 0x4300B5 because those values have a zero UMASK field (bits [15:8]). Status: BG43. Problem: For the steppings affected, see the Summary Tables of Changes. Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT Stores to Local DRAM Correctly When a IA32_PERFEVTSELx MSR is programmed to count the Offcore_response_0 event (Event:B7H), selections in the OFFCORE_RSP_0 MSR (1A6H) determine what is counted. The following two selections do not provide accurate counts when counting NT (Non-Temporal) Stores:
OFFCORE_RSP_0 MSR bit [14] is set to 1 (LOCAL_DRAM) and bit [7] is set to 1
(OTHER): NT Stores to Local DRAM are not counted when they should have been.
OFFCORE_RSP_0 MSR bit [9] is set to (OTHER_CORE_HIT_SNOOP) and bit [7] is
set to 1 (OTHER): NT Stores to Local DRAM are counted when they should not have been. Implication: The counter for the Offcore_response_0 event may be incorrect for NT stores. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG44. Problem:

Back to Back Uncorrected Machine Check Errors May Overwrite IA32_MC3_STATUS.MSCOD When back-to-back uncorrected machine check errors occur that would both be logged in the IA32_MC3_STATUS MSR (40CH), the IA32_MC3_STATUS.MSCOD (bits [31:16]) field may reflect the status of the most recent error and not the first error. The rest of the IA32_MC3_STATUS MSR contains the information from the first error. of IA32_MC3_STATUS.MSCOD if

BG57. Problem:

Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts transitions from x87 Floating Point (FP) to MMX instructions. Due to this erratum, if only a small number of MMX instructions (including EMMS) are executed immediately after the last FP instruction, a FP to MMX transition may not be counted.
Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially-available software. Workaround:None Identified. Status: BG58. Problem: For the steppings affected, see the Summary Tables of Changes. LER MSRs May Be Unreliable Due to certain internal processor events, updates to the LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_LER_TO_LIP (1DEH), may happen when no update was expected.
Implication: The values of the LER MSRs may be unreliable. Workaround:None Identified. Status: BG59. Problem: For the steppings affected, see the Summary Tables of Changes. MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error A single Data Translation Look Aside Buffer (DTLB) error can incorrectly set the Overflow (bit [62]) in the MCi_Status register. A DTLB error is indicated by MCA error code (bits [15:0]) appearing as binary value, 000x 0100, in the MCi_Status register.
Implication: Due to this erratum, the Overflow bit in the MCi_Status register may not be an accurate indication of multiple occurrences of DTLB errors. There is no other impact to normal processor functionality. Workaround:None identified. Status: BG60. Problem: For the steppings affected, see the Summary Tables of Changes. Debug Exception Flags DR6.B0-B3 Flags May Be Incorrect for Disabled Breakpoints When a debug exception is signaled on a load that crosses cache lines with data forwarded from a store and whose corresponding breakpoint enable flags are disabled (DR7.G0-G3 and DR7.L0-L3), the DR6.B0-B3 flags may be incorrect.

Implication: Due to this erratum, the count value for some uncore Performance Monitoring Events may be inaccurate. The degree of under or over counting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software. Workaround:None identified. Status: BG81. Problem: For the steppings affected, see the Summary Tables of Changes. Performance Monitor Events for Hardware Prefetches Which Miss the L1 Data Cache May be Over Counted Hardware prefetches that miss the L1 data cache but cannot be processed immediately due to resource conflicts will count and then retry. This may lead to incorrectly incrementing the L1D_PREFETCH.MISS (event 4EH, umask 02H) event multiple times for a single miss.
Implication: The count reported by the L1D_PREFETCH.MISS event may be higher than expected. Workaround:None identified Status: BG82. Problem: For the steppings affected, see the Summary Tables of Changes Correctable and Uncorrectable Cache Errors May be Reported Until the First Core C6 Transition On a subset of processors it is possible that correctable/uncorrectable cache errors may be logged and/or a machine check exception may occur prior to the first core C6 transition. The errors will be logged in IA32_MC5_STATUS MSR (415H) with the MCACOD (Machine Check Architecture Error Code) bits [15:0] indicating a Cache Hierarchy Error of the form 000F 0001 RRRR TTLL.
Implication: Due to this erratum, correctable/uncorrectable cache error may be logged or signaled. Workaround:It is possible for the BIOS to contain a workaround for this erratum. Status: BG83. Problem: For the steppings affected, see the Summary Tables of Changes DTS Temperature Data May Be Incorrect On a Return From the Package C6 Low Power State The DTS (Digital Thermal Sensor) temperature value may be incorrect for a small period of time (less than 2ms) after a return from the package Deep Power Down Technology (code named C6) low power state.
Implication: The DTS temperature data (including temperatures read by Platform Environment Control Interface) may be reported lower than the actual temperature. Fan speed control or other system functions which are reliant on correct DTS temperature data may behave unpredictably Workaround:It is possible for the BIOS to contain a workaround for this erratum Status: For the steppings affected, see the Summary Tables of Changes

USB Devices May Not Function Properly With Integrated Graphics While Running Targeted Stress Graphics Workloads With Non-Matching Memory Configurations When the integrated graphics engine continuously generates a large stream of writes to system memory, and Intel Flex Memory Technology is enabled, with a different amount of memory in each channel, the memory arbiter may temporarily stop servicing other device-initiated traffic. In some cases this can cause certain USB devices, such as keyboard and mouse, to become unresponsive. Intel has only observed this erratum with targeted stress content. This erratum is not seen when the platform is configured with single channel or dual channel symmetric memory and is not dependent on the memory frequency.
Implication: Due to this erratum, certain USB devices may become unresponsive. Workaround:None identified. Status: BG85. Problem: For the steppings affected, see the Summary Tables of Changes. Intel Turbo Boost Technology Ratio Changes May Cause Unpredictable System Behavior When Intel Turbo Boost Technology is enabled as determined by the TURBO_MODE_DISABLE bit being 0 in the IA32_MISC_ENABLES MSR (1A0H), the process of locking to new ratio may cause the processor to run with incorrect ratio settings. The result of this erratum may be unpredictable system behavior.
Implication: Due to this erratum, unpredictable system behavior may be observed Workaround:It is possible for the BIOS to contain a workaround for this erratum. Status: BG86. For the steppings affected, see the Summary Tables of Changes. PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred Under very specific timing conditions, if software tries to disable a PerfMon counter through MSR IA32_PERF_GLOBAL_CTRL (0x38F) or through the per-counter eventselect (e.g. MSR 0x186) and the counter reached its overflow state very close to that time, then due to this erratum the overflow status indication in MSR IA32_PERF_GLOBAL_STAT (0x38E) may be left set with no way for software to clear it.
Implication: To this erratum, software may be unable to clear the PerfMon counter overflow status indication Workaround:Software may avoid this erratum by clearing the PerfMon counter value prior to disabling it and then clearing the overflow status indication bit. Status: For the steppings affected, see the Summary Tables of Changes.

BG87. Problem:

An Unexpected Page Fault or EPT Violation May Occur After Another Logical Processor Creates a Valid Translation for a Page An unexpected page fault (#PF) or EPT violation may occur for a page under the following conditions: The paging structures initially specify no valid translation for the page.

2.4.1.2.4

Clip Stage The Clip stage performs general processing on incoming 3D objects. However, it also includes specialized logic to perform a Clip Test function on incoming objects. The Clip Test optimizes generalized 3D Clipping. The Clip unit examines the position of incoming vertices, and accepts/rejects 3D objects based on its Clip algorithm.

2.4.1.2.5

Strips and Fans (SF) Stage The SF stage performs setup operations required to rasterize 3D objects. The outputs from the SF stage to the Windower stage contain implementation-specific information required for the rasterization of objects and also supports clipping of primitives to some extent.

2.4.1.2.6

Windower/IZ (WIZ) Stage The WIZ unit performs an early depth test, which removes failing pixels and eliminates unnecessary processing overhead. The Windower uses the parameters provided by the SF unit in the object-specific rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of pixels. The Windower is also capable of performing dithering, whereby the illusion of a higher resolution when using low-bpp channels in color buffers is possible. Color dithering diffuses the sharp color bands seen on smooth-shaded objects.

2.4.1.3

The Video Engine handles the non-3D (media/video) applications. It includes support for VLD and MPEG2 decode in hardware.

2.4.1.4

2D Engine
The 2D Engine contains BLT (Block Level Transfer) functionality and an extensive set of 2D instructions. To take advantage of the 3D during engines functionality, some BLT functions make use of the 3D renderer.

2.4.1.4.1

Integrated Graphics VGA Registers The 2D registers consists of original VGA registers and others to support graphics modes that have color depths, resolutions, and hardware acceleration features that go beyond the original VGA standard.

2.4.1.4.2

Logical 128-Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The 128-bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations. The BLT engine can be used for the following:

Utilizes internal graphics controller dynamic frequency performance states to
achieve their highest performance within the rated thermal power envelope. Intel Dynamic Frequency enabled processors will offer a range of upside performance capability beyond their rated or guaranteed frequency.
Controls the processor core and internal graphics controller Intel Turbo Boost
performance states to ensure that overall MCP thermal power consumption does not exceed the specified MCP thermal power limit.
Limits MCP component usage to ensure that each of the components' Tj,max value is
not exceeded. It is possible that the thermal influence between the MCP components could potentially cause a component to reach its Tj,max, invoking undesirable component hardware autothrottling. It is expected that when running the TDP workload, power sharing control may limit the entire range of component Intel Turbo Boost capabilities (effectively, disabling them). The principal component of the power sharing control architecture is the policy manager within the Intel Turbo Boost Technology driver which:
Communicates with the graphics software driver to limit, or increase, internal

graphics thermal power.

Communicates with the processor core via the PCH to processor core PECI interface
to limit, or increase, processor core thermal power. The Intel Turbo Boost Technology policy manager will set a thermal power limit to which the graphics driver and processor core will adjust their Intel Turbo Boost Technology performance dynamically, to stay within the limit. Note: The processor PECI pin must be connected to the PCH PECI pin in order for Intel Turbo Boost Technology to properly function.
Component Power Measurement/Estimation Error
The processor input pin (ISENSE) informs the processor core of how much amperage the processor core is consuming. This information is provided by the processor core VR. The process will calculate its current power based upon the ISENSE input information and current voltage state. The internal graphics and memory controller power is estimated by the GFX driver using PMON. Any error in power estimation or measurement may limit or completely eliminate the performance benefit of Intel Turbo Boost Technology. When a power limit is reached, Power sharing control will adaptively remove Intel Turbo Boost Technology states to remain with the MCP thermal power limit. Power sharing control assumes the power error is always accurate so if the ISENSE input reports power greater than the actual power, control mechanisms will lower performance before the actual TDP power limit is reached. Intelligent Power sharing will provide better overall Intel Turbo Boost Technology performance with increasing VR current sense accuracy. Designers and system manufacturers should study trade-offs on VR component accuracy characteristics, such as inductors, to find the best balance of cost vs. performance for their system price and performance targets.

The voltage will be optimized according to the temperature, the core bus ratio, and
number of cores in deep C-states.
The core power and temperature are reduced while minimizing performance
degradation. A small amount of hysteresis has been included to prevent an excessive amount of operating point transitions when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point. This is illustrated in Figure 5-12.
Figure 5-12.Frequency and Voltage Ordering
Once a target frequency/bus ratio is resolved, the processor core will transition to the new target automatically.
On an upward operating point transition, the voltage transition precedes the

frequency transition.

On a downward transition, the frequency transition precedes the voltage transition.
When transitioning to a target core operating voltage, a new VID code to the voltage regulator is issued. The voltage regulator must support dynamic VID steps to support this method. During the voltage change:
It will be necessary to transition through multiple VID steps to reach the target

operating voltage.

Each step is 12.5 mV for Intel MVP-6.5 compliant VRs. The processor continues to execute instructions. However, the processor will halt
instruction execution for frequency transitions.
If a processor load-based Enhanced Intel SpeedStep Technology/P-state transition (through MSR write) is initiated while the Adaptive Thermal Monitor is active, there are two possible outcomes:
If the P-state target frequency is higher than the processor core optimized target
frequency, the p-state transition will be deferred until the thermal event has been completed.
If the P-state target frequency is lower than the processor core optimized target
frequency, the processor will transition to the P-state operating point. 5.2.1.1.2 Clock Modulation If the frequency/voltage changes are unable to end an Adaptive Thermal Monitor event, the Adaptive Thermal Monitor will utilize clock modulation. Clock modulation is done by alternately turning the clocks off and on at a duty cycle (ratio between clock on time and total time) specific to the processor. The duty cycle is factory configured to 37.5% on and 62.5% off and cannot be modified. The period of the duty cycle is configured to 32 microseconds when the TCC is active. Cycle times are independent of processor frequency. A small amount of hysteresis has been included to prevent excessive clock modulation when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases. Clock modulation is automatically engaged as part of the TCC activation when the frequency/VID targets are at their minimum settings. Processor performance will be decreased by the same amount as the duty cycle when clock modulation is active. Snooping and interrupt processing are performed in the normal manner while the TCC is active.

5.2.3.2

Processor Thermal Data Sample Rate and Filtering
The processor digital thermal sensor (DTS) provides an improved capability to monitor device hot spots, which inherently leads to more varying temperature readings over short time intervals. To reduce the sample rate requirements on PECI and improve thermal data stability vs. time the processor DTS implements an averaging algorithm that filters the incoming data. This filter is expressed mathematically as: PECI(t) = PECI(t-1)+1/(2^^X)*[Temp - PECI(t-1)] where:
PECI(t) is the new averaged temperature PECI(t-1) is the previous averaged temperature Temp is the raw temperature data from the DTS X is the Thermal Averaging Constant (TAC)
The Thermal Averaging Constant is a BIOS configurable value that determines the time in milliseconds over which the DTS temperature values are averaged (the default time is 256 ms). Short averaging times will make the averaged temperature values respond more quickly to DTS changes. Long averaging times will result in better overall thermal smoothing but also incur a larger time lag between fast DTS temperature changes and the value read via PECI. Within the processor, the DTS converts an analog signal into a digital value representing the temperature relative to PROCHOT# circuit activation. The conversions are in integers with each single number change corresponding to approximately 1C. DTS values reported via the internal processor MSR will be in whole integers. As a result of the PECI averaging function described above, DTS values reported over PECI will include a 6-bit fractional value. Under typical operating conditions, where the temperature is close to PROCHOT#, the fractional values may not be of interest. But when the temperature approaches zero, the fractional values can be used to detect the activation of the PROCHOT# circuit. An averaged temperature value between 0 and 1 can only occur if the PROCHOT# circuit has been activated during the averaging window. As PROCHOT# circuit activation time increases, the fractional value will approach zero. Fan control circuits can detect this situation and take appropriate action as determined by the system designers. Of course, fan control chips can also monitor the PROCHOT# pin to detect PROCHOT# circuit activation via a dedicated input pin on the package.

Table 6-33.Processor Power Signals (Sheet 2 of 3)
Signal Name VID[6] VID[5:3]/CSC[2:0] VID[2:0]/MSID[2:0] Description VID[6:0] (Voltage ID) Pins: Used to support automatic selection of power supply voltages (VCC). These are CMOS signals that are driven by the processor. CSC[2:0]/VID[5:3] - Current Sense Configuration bits, for ISENSE gain setting. This value is latched on the rising edge of VTTPWRGOOD. MSID[2:0]/VID[2:0]- Market Segment Identification is used to indicate the maximum platform capability to the processor. A processor will only boot if the MSID[2:0] pins are strapped to the appropriate setting (or higher) on the platform (see Table 7-37 for MSID encodings). MSID is used to help protect the platform by preventing a higher power processor from booting in a platform designed for lower power processors. MSID[2:0] are latched on the rising edge of VTTPWRGOOD. NOTE: VID[5:3] and VID[2:0] are bidirectional. As an input, they are CSC[2:0] and MSID[2:0] respectively. VTT_SELECT VCC_SENSE VSS_SENSE The VTT_SELECT signal is used to select the correct VTT voltage level for the processor. Voltage Feedback Signals to an Intel MVP-6.5 Compliant VR: Use VCC_SENSE to sense voltage and VSS_SENSE to sense ground near the silicon with little noise. Isolated low impedance connection to the processor VTT voltage and ground. They can be used to sense or measure voltage near the silicon. Graphics core power rail. VAXG_SENSE and VSSAXG_SENSE provide an isolated, low impedance connection to the VAXG voltage and ground. They can be used to sense or measure voltage near the silicon. GFX_VID[6:0] (Voltage ID) pins are used to support automatic selection of nominal voltages (VAXG). These are CMOS signals that are driven by the processor. GPU output signal to Intel MVP6.5 compliant VR. This signal is used as an on/off control to enable/disable the GPU VR. O CMOS O A Direction/Buffer Type O CMOS

VTT_SENSE VSS_SENSE_VTT

VAXG VAXG_SENSE VSSAXG_SENSE

Ref O A

GFX_VID[6:0]

O CMOS

GFX_VR_EN
Table 6-33.Processor Power Signals (Sheet 3 of 3)
Signal Name GFX_DPRSLPVR Description GPU output signal to Intel MVP6.5 compliant VR. When asserted this signal indicates that the GPU is in render suspend mode. This signal is also used to control render suspend state exit slew rate. Current Sense from an Intel MVP6.5 Compliant Regulator to the GPU. Filtered power for VDDQ (BGA Only) Filtered power for VTT0 (BGA Only) Processor Connection to On-board decoupling capacitors (BGA only) Direction/Buffer Type O CMOS
GFX_IMON VDDQ_CK VTT0_DDR VCAP0 VCAP1 VCAP2

I A Ref Ref PWR

Ground and NCTF
Signal Name VSS VSS_NCTF DC_TEST_xx# Description Processor ground node Non-Critical to Function: The pins are for package mechanical reliability. Daisy Chain Test - These pins are for solder joint reliability and are non-critical to function (BGA only). NC Direction/Buffer Type GND

Table 6-34.Ground and NCTF
Processor Internal Pull Up/Pull Down
Table 6-35.Processor Internal Pull Up/Pull Down
Signal Name SM_DRAMPWROK VCCPWRGOOD_0 VCCPWRGOOD_1 VTTPWRGOOD BPM#[7:0] TCK TDI TMS TRST# Pull Down Pull Up Pull Up Pull Up Pull Up Pull Up VSS VTT VTT VTT VTT VTT 10 - 20 k 44 - 55 k 44 - 55 k 44 - 55 k 44 - 55 k 1 - 5 k Pull Up/Pull Down Pull Down Pull Down VSS VSS Rail Value 10 - 20 k 10 - 20 k
Signal Name TDI_M PREQ# CFG[17:0] Pull Up/Pull Down Pull Up Pull Up Pull Up VTT VTT VTT Rail Value 44 - 55 k 44 - 55 k 5 - 14 k
Electrical Specifications

Power and Ground Pins

The processor has VCC, VTT, VDDQ, VCCPLL, VAXG and VSS (ground) inputs for on-chip power distribution. All power pins must be connected to their respective processor power planes, while all VSS pins must be connected to the system ground plane. Use of multiple power and ground planes is recommended to reduce I*R drop. The VCC pins must be supplied with the voltage determined by the processor Voltage IDentification (VID) signals. Likewise, the VAXG pins must also be supplied with the voltage determined by the GFX_VID signals. Table 7-36 specifies the voltage level for the various VIDs. The voltage levels are the same for both the processor VIDs and GFX_VIDs.

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low- and full-power states. To keep voltages within specification, output decoupling must be properly designed.
Design the board to ensure that the voltage provided to the processor remains within the specifications listed in Table 7-36. Failure to do so can result in timing violations or reduced lifetime of the processor.

Voltage Rail Decoupling

The voltage regulator solution must:
provide sufficient decoupling to compensate for large current swings generated
during different power mode transitions.
provide low parasitic resistance from the regulator to the socket. meet voltage and current specifications as defined in Table 7-36.
Processor Clocking (BCLK, BCLK#)
The processor utilizes a differential clock to generate the processor core(s) operating frequency, memory controller frequency, and other internal clocks. The processor core frequency is determined by multiplying the processor core ratio by 133 MHz. Clock multiplying within the processor is provided by an internal phase locked loop (PLL), which requires a constant frequency input, with exceptions for Spread Spectrum Clocking (SSC). The processors maximum core frequency is configured during power-on reset by using its manufacturing default value. This value is the highest core multiplier at which the processor can operate.

VID1 VID1 VID0 VID0 VID0 VID1 VID0 VCC (V) 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750
Table 7-36.Voltage Identification Definition (Sheet 4 of 4)
VIDVIDVIDVIDVIDVIDVIDVCC (V) 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000
Table 7-37.Market Segment Selection Truth Table for MSID[2:0]
MSID[2] MSID[1] MSID[0] Reserved Reserved Reserved Reserved Standard Voltage (SV) 35-W Supported Reserved Reserved Reserved 3 Description1,2 Notes
NOTES: MSID[2:0] signals are provided to indicate the maximum platform capability to the processor. MSID is used on rPGA988A platforms only. 3. Processors specified for use with a -1.9 m
Reserved or Unused Signals
The following are the general types of reserved (RSVD) signals and connection guidelines:
RSVD - these signals should not be connected RSVD_TP - these signals should be routed to a test point RSVD_NCTF - these signals are non-critical to function and may be left unconnected Arbitrary connection of these signals to VCC, VTT, VDDQ, VCCPLL, VAXG, VSS, or to any other signal (including each other) may result in component malfunction or incompatibility with future processors. See Chapter 8 for a pin listing of the processor and the location of all reserved signals. For reliable operation, always connect unused inputs or bi-directional signals to an appropriate signal level. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs maybe left unconnected; however, this may interfere with some Test Access Port (TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bi-directional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within 20% of the impedance of the baseboard trace, unless otherwise noted in the appropriate platform design guidelines. For details see Table 7-45.

Signal Groups

Table 7-46.PCI Express DC Specifications
Symbol VTX-DIFF-p-p VTX_CM-AC-p ZTX-DIFF-DC ZRX-DC ZRX-DIFF-DC VRX-DIFFp-p VRX_CM-AC-p PEG_ICOMPO PEG_ICOMPI PEG_RCOMPO PEG_RBIAS Alpha Group (ad) (ad) (ad) (ac) (ac) (ac) (ac) (ae) (ae) (ae) (ae) Parameter Differential Peak-to-Peak Tx Voltage Swing Tx AC Peak Common Mode Output Voltage (Gen 1 Only) DC Differential Tx Impedance (Gen 1 Only) DC Common Mode Rx Impedance DC Differential Rx Impedance (Gen1 Only) Differential Rx Input Peak-to-Peak Voltage (Gen 1 only) Rx AC Peak Common Mode Input Voltage Comp Resistance Comp Resistance Comp Resistance Comp Resistance 49.5 49.5 49.5 742.0.175 Min 0.8 Typ Max 1.120 1.50.5 50.5 50.5 757.5 Units V mV V mV Notes1,2,6 1,10 1,8,1,11 1,7 4,5 4,5 4,5 4,5
NOTES: 1. Refer to the PCI Express Base Specification for more details. 2. VTX-AC-CM-PP and VTX-AC-CM-P are defined in the PCI Express Base Specification. Measurement is made over at least 10^6 UI. 3. As measured with compliance test load. Defined as 2*|VTXD+ - VTXD- |. 4. COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to VSS. 5. PEG_ICOMPO, PEG_ICOMPI, PEG_RCOMPO are the same resistor 6. RMS value. 7. Measured at Rx pins into a pair of 50- terminations into ground. Common mode peak voltage is defined by the expression: max{|(Vd+ - Vd-) - V-CMDC|}. 8. DC impedance limits are needed to guarantee Receiver detect. 9. The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to ensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediately and the 15 Rx Common Mode Impedance (constrained by RLRX-CM to 50 20%) must be within the specified range by the time Detect is entered. 10. Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.
Table 7-47.eDP DC Specifications
Symbol Parameter Min Typ Max Units Notes4
eDP_HPD# VIL VIH eDP_AUX, eDP_AUX# VAUX-DIFFp-p (Tx) VAUX-DIFFp-p (Rx) eDP COMPs eDP_ICOMPO eDP_ICOMPI eDP_RCOMPO eDP_RBIAS Comp Resistance Comp Resistance Comp Resistance Comp Resistance 49.5 49.5 49.5 742.750 50.5 50.5 50.5 757.5 2,3 2,3 2,3 2,3 AUX Peak-to-Peak Voltage at the transmitting device AUX Peak-to-Peak Voltage at the receiving device 0.39 0.32 1.38 1.36 V Input Low Voltage Input High Voltage -0.3 0.6 0.3 1.155 V V

VS S VS S P I EC T ER T H M R IP# P _S M YN C VS S D I_ X[ MT 1] VT_S T E NE S FD X# F I_T [ I_T D X [4] 4] F I_T D X# [1] F I_ X[ DT 1 ] F I_ X# DT [2]
F I_T D X# [3] F I_T [ D X 2 ] V SS
PG L PG X E _C E _T [ K 15 ] V SS PG L PG X E _C E _T K# # [15] D I_T M X# [0] P _T EG X VS S #[14] P _ X[ EGT VS S 14] V SS VS S P _R EG X #[1 3] V SS PE _R G X [15 ] VS S VS S P _R EG C O PO M VS S R D SV V SS RVDN S _ CF T D _T S CE TC _3 D I_T [ M X 0] VT W TP R GO OD VS S D I_T [ M X 2] D I_T # D I_R M X M X[ [3] 0] D I_R M X #[0 ] VS S VS S R D SV _N CF T RT # S IN R V _N SD CF T D _ ES CT T 1 _E D I_T # M X [1] D I_T # M X [2] VS S V SS D I_T [ M X 3 ] D I_R D I_ X M X[ M R 2] # [2] D I_ X MR V SS # [1] V SS D I_R M X[ 1] VS S D I_R M X #[3] D I_R [ M X 3] V SS FD X# I_T [0] F I_T [ D X 0]

L K J H G F E D C

PE _T GX #[7]
PE _T P _ X G X EGT #[6] #[10] P _T [ EG X VS S 6] P _T EG X #[9 ]

PE _T [ G X 9] VS S

PE _R G X [7]
PE _R PE _ X G X GR #[8] [9] P _R EG X VS S [8 ] P _R EG X [10]

PE _R G X #[10] V SS

PG X E _R [11]
P _R PE _R EG X G X [12] [13] PE _R G X V SS # [12] PE _ X GR #[14 ]

P _R EG X [14] VS S

P _X EGR #[1 5]
EG B P _IC P _R EG OP MI IAS PE _IC G VS S OP MO RVD S
R VD S R D D _T S SV _N C E CF T T _A5
Table 8-51.BGA1288 Processor Ball List by Ball Name (Sheet 1 of 37)
Pin Name BCLKAC71 BCLK # BCLK_ITP BCLK_ITP # BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] CATERR# CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] COMP0 Pin # AK7 AK8 K71 J70 J69 J67 J62 K65 K62 J64 K69 M69 N61 AL4 AM2 AK1 AK2 AK4 AJ2 AT2 AG7 AF4 AG2 AH1 AC2 AC4 AE2 AD1 AF8 AF6 AB7 AE66 Buffer Type DIFF CLK DIFF CLK DIFF CLK DIFF CLK GTL GTL GTL GTL GTL GTL GTL GTL GTL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Analog Dir I I O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I I I I I I I I
Table 8-51.BGA1288 Processor Ball List by Ball Name (Sheet 2 of 37)
Pin Name COMP1 COMP2 COMP3 DBR# DC_TEST_A5 DC_TEST_A68 DC_TEST_A69 DC_TEST_A71 DC_TEST_BR1 DC_TEST_BR71 DC_TEST_BT1 DC_TEST_BT3 DC_TEST_BT69 DC_TEST_BT71 DC_TEST_BV1 DC_TEST_BV3 DC_TEST_BV5 DC_TEST_BV68 DC_TEST_BV69 DC_TEST_BV71 DC_TEST_C3 DC_TEST_C69 DC_TEST_C71 DC_TEST_E1 DC_TEST_E71 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] Pin # AD69 AC70 AD71 W71 A5 A68 A69 A71 BR1 BR71 BT1 BT3 BT69 BT71 BV1 BV3 BV5 BV68 BV69 BV71 C3 C69 C71 E1 E71 F9 J6 K9 J2 F7 J8 K8 J4 G17 M15 G13 DMI DMI DMI DMI DMI DMI DMI DMI DMI DMI DMI I I I I I I I I O O O Buffer Type Analog Analog Analog Dir I I I O
Table 8-51.BGA1288 Processor Ball List by Ball Name (Sheet 3 of 37)

Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 1 of 37)
Pin # A5 A6 A8 A10 A12 A13 A15 A17 A19 A20 A22 A24 A26 A27 A29 A31 A33 A34 A36 A38 A40 A41 Pin Name DC_TEST_A5 RSVD_NCTF VSS RSVD VSS PEG_ICOMPO VSS PEG_RX#[14] VSS PEG_RX#[12] VSS PEG_RX[10] VSS PEG_RX[8] VSS PEG_TX#[9] VSS PEG_TX[6] VSS PEG_TX#[4] VSS ISENSE GND Analog GND PCIe GND PCIe GND PCIe GND PCIe GND PCIe GND PCIe GND PCIe GND Analog I O O O I I I I I GND Buffer Type Dir
A59 A61 A62 A64 A66 A68 A69 A71 AA1 AA4 AA12 AA14 AA15 AA17 AA19 AA21 AA23 AA24 AA26 AA28 AA30 AA32 AA33 AA35 AA37 AA39 AA41
Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 3 of 37)
Pin # AA42 AA44 AA46 AA48 AA50 AA51 AA53 AA55 AA57 AA59 AA60 AA62 AA64 AA66 AA69 AA71 AB2 AB5 AB7 AB9 AB12 AB14 AB15 AB17 AB19 AB21 AB23 AB24 AB26 AB28 AB30 AB32 AB33 AB35 AB37 AB39 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCAP2 VCAP2 VSS VSS VSS RSVD RSVD_TP FDI_LSYNC[1] FDI_INT CFG[17] VSS VTT1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CMOS CMOS CMOS GND REF GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND I I I Pin Name Buffer Type GND REF GND REF GND REF GND REF GND PWR PWR GND GND GND Dir
Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 4 of 37)
Pin # AB41 AB42 AB44 AB46 AB48 AB50 AB51 AB53 AB55 AB57 AB59 AB60 AB62 AB70 AC1 AC2 AC4 AC5 AC7 AC9 AC10 AC64 AC67 AC69 AC70 AC71 AD1 AD4 AD12 AD14 AD15 AD17 AD19 AD21 AD23 AD24 VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCAP2 VCAP2 VSS VSS VSS CFG[11] CFG[12] VSS FDI_FSYNC[0] FDI_FSYNC[1] VSS VSS VSS RSVD COMP2 RSVD_TP CFG[14] VSS VTT1 VTT1 VTT1 VAXG VAXG VAXG VAXG VAXG CMOS GND REF REF REF REF REF REF REF REF I Analog I Pin Name Buffer Type REF GND REF GND REF GND REF GND REF GND PWR PWR GND GND GND CMOS CMOS GND CMOS CMOS GND GND GND I I I I Dir
Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 5 of 37)
Pin # AD26 AD28 AD30 AD32 AD33 AD35 AD37 AD39 AD41 AD42 AD44 AD46 AD48 AD50 AD51 AD53 AD55 AD57 AD59 AD60 AD62 AD69 AD71 AE2 AE64 AE66 AE70 AF1 AF4 AF10 AF12 AF14 AF15 AF17 AF19 AF21 Pin Name VAXG VAXG VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCAP2 VCAP2 VSS COMP1 COMP3 CFG[13] VSS COMP0 VSS VSS CFG[8] VSSAXG_SENSE VAXG_SENSE VAXG VAXG VAXG VAXG VAXG Buffer Type REF REF REF REF REF REF REF REF REF GND REF GND REF GND REF GND REF GND PWR PWR GND Analog Analog CMOS GND Analog GND GND CMOS Analog Analog REF REF REF REF REF I O O I I I I Dir
Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 6 of 37)
Pin # AF23 AF24 AF26 AF28 AF30 AF32 AF33 AF35 AF37 AF39 AF41 AF42 AF44 AF46 AF48 AF50 AF51 AF53 AF55 AF57 AF59 AF6 AF60 AF62 AF69 AF71 AF8 AG2 AG6 AG7 AG9 AG64 AG67 AG70 AH1 AH4 Pin Name VAXG VAXG VAXG VAXG VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCAP2 CFG[16] VCAP2 VSS VSS GFX_VID[0] CFG[15] CFG[9] VSS CFG[7] VSS VSS GFX_VID[1] GFX_VID[2] CFG[10] VSS Buffer Type REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF PWR CMOS PWR GND GND CMOS CMOS CMOS GND CMOS GND GND CMOS CMOS CMOS GND O O I I O I I I Dir

Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 24 of 37)
Pin # BP35 BP39 BP42 BP46 BP49 BP53 BP56 BP58 BP60 BR1 BR3 BR5 BR6 BR8 BR10 BR62 BR64 BR66 BR68 BR69 BR71 BT1 BT3 BT5 BT12 BT13 BT15 BT17 BT19 BT20 BT22 BT24 BT26 BT27 BT29 BT31 Pin Name SA_CK#[0] SM_RCOMP[1] VSS SB_CS#[0] SB_DQ[35] SB_DQ[40] SB_DQ[44] SA_DQS#[6] SB_DQ[49] DC_TEST_BR1 VSS RSVD_TP SB_DQ[10] SB_DQ[11] SB_DQ[16] SB_DQ[52] SB_DQ[51] SB_DQ[50] VSS VSS DC_TEST_BR71 DC_TEST_BT1 DC_TEST_BT3 RSVD_NCTF SB_DQ[17] SB_DM[2] SB_DQ[18] SB_DQS[3] SB_DQS#[3] SB_DQ[31] SB_DQ[27] SB_CKE[1] SB_CKE[0] SB_MA[9] SB_MA[12] SB_MA[6] DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 I/O O I/O I/O I/O I/O I/O O O O O O DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 GND GND I/O I/O I/O I/O I/O I/O GND Buffer Type DDR3 Analog GND DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 O I/O I/O I/O I/O I/O Dir O
Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 25 of 37)
Pin # BT33 BT34 BT36 BT38 BT40 BT41 BT43 BT45 BT47 BT48 BT50 BT52 BT54 BT55 BT57 BT59 BT61 BT68 BT69 BT71 BU7 BU9 BU11 BU12 BU14 BU16 BU18 BU19 BU21 BU23 BU25 BU26 BU28 BU30 BU32 BU33 Pin Name SB_MA[5] SB_MA[0] SA_MA[0] SA_BS[0] SB_RAS# SB_WE# SB_CS#[1] SB_MA[13] SB_DQ[36] SB_DQ[32] SB_DQS[4] SB_DQS#[4] SB_DQ[39] SB_DQ[45] SB_DQ[43] SB_DQ[42] SB_DQ[53] VSS DC_TEST_BT69 DC_TEST_BT71 VSS SB_DQ[14] VSS SB_DQS#[2] VSS SB_DQ[23] VSS SB_DQ[25] VSS SB_MA[15] VSS SB_MA[11] VDDQ SB_MA[3] VSS SB_CK[0] GND DDR3 GND DDR3 GND DDR3 GND DDR3 GND DDR3 GND DDR3 REF DDR3 GND DDR3 O O O O I/O I/O I/O I/O Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 GND Dir O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 26 of 37)
Pin # BU35 BU37 BU39 BU40 BU42 BU44 BU46 BU48 BU49 BU51 BU53 BU55 BU56 BU58 BU60 BU62 BU63 BU65 BV1 BV3 BV5 BV6 BV8 BV10 BV12 BV13 BV15 BV17 BV19 BV20 BV22 BV24 BV26 BV27 BV29 BV31 Pin Name VDDQ VSS SB_CK#[1] VDDQ SB_MA[10] VSS SB_CAS# VSS SB_ODT[1] VSS SB_DQ[41] VSS SB_DQS[5] VSS SB_DQ[46] VSS SB_DQS#[6] SB_DM[6] DC_TEST_BV1 DC_TEST_BV3 DC_TEST_BV5 RSVD_NCTF RSVD_NCTF SB_DQ[15] SB_DQ[20] SB_DQS[2] SB_DQ[19] SB_DQ[22] SB_DQ[29] SB_DQ[30] SB_DQ[26] SB_BS[2] SB_MA[14] SB_MA[8] SB_MA[2] SB_MA[4] DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 I/O I/O I/O I/O I/O I/O I/O I/O O O O O O Buffer Type REF GND DDR3 REF DDR3 GND DDR3 GND DDR3 GND DDR3 GND DDR3 GND DDR3 GND DDR3 DDR3 I/O O I/O I/O I/O O O O O Dir

Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 27 of 37)
Pin # BV33 BV34 BV36 BV38 BV40 BV41 BV43 BV45 BV47 BV48 BV50 BV52 BV54 BV55 BV57 BV59 BV61 BV62 BV64 BV66 BV68 BV69 BV71 C3 C5 C68 C69 C71 D6 D8 D10 D12 D13 D15 D17 D19 Pin Name SM_RCOMP[0] SB_CK#[0] SA_MA[2] SB_CK[1] SM_RCOMP[2] SB_BS[1] SB_BS[0] SB_ODT[0] SB_DM[4] SB_DQ[33] SB_DQ[34] SB_DQ[37] SB_DQ[38] SB_DQS#[5] SB_DM[5] SB_DQ[47] SB_DQ[48] SB_DQS[6] VSS VSS DC_TEST_BV68 DC_TEST_BV69 DC_TEST_BV71 DC_TEST_C3 RSVD_NCTF VSS DC_TEST_C69 DC_TEST_C71 VSS RSVD VSS PEG_RCOMPO VSS PEG_RX[15] VSS PEG_RX#[13] GND Analog GND PCIe GND PCIe I I I GND GND Buffer Type Analog DDR3 DDR3 DDR3 Analog DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 GND GND Dir I O O O I O O O O I/O I/O I/O I/O I/O O I/O I/O I/O
Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 28 of 37)
Pin # D20 D22 D24 D26 D27 D29 D31 D33 D34 D36 D38 D40 D41 D43 D45 D47 D48 D50 D52 D54 D55 D57 D59 D61 D62 D64 D66 E1 E3 E5 E12 E16 E30 E33 E37 E42 VSS PEG_RX#[11] VSS PEG_RX#[9] VSS PEG_RX#[7] VSS PEG_TX[10] VSS PEG_TX[7] VSS PEG_TX#[3] VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VID[1] VID[2] CSC[2]/VID[5] VID[6] DC_TEST_E1 RSVD_NCTF VSS VSS VSS VSS VSS VSS VCC GND GND GND GND GND GND REF Pin Name Buffer Type GND PCIe GND PCIe GND PCIe GND PCIe GND PCIe GND PCIe GND REF REF REF REF REF REF REF REF REF REF CMOS CMOS CMOS CMOS O O I/O O O O O I I I Dir
Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 29 of 37)
Pin # E46 E50 E53 E57 E60 E68 E69 E71 F1 F4 F7 F9 F10 F20 F21 F28 F40 F47 F48 F55 F61 F63 F64 F66 F68 F71 G3 G13 G15 G17 G20 G21 G24 G25 G28 VCC VCC VCC VCC VCC VSS VSS DC_TEST_E71 RSVD_NCTF VSS DMI_RX#[0] DMI_RX[0] DMI_TX#[3] VSS PEG_TX[14] VSS PEG_RX[0] VSS VSS VCC VSS VSS_SENSE VCC_SENSE PROC_DPRSLPVR PSI# VSS RSTIN# DMI_TX[2] VSS DMI_TX[0] VSS PEG_TX#[14] VSS PEG_RX[5] PEG_RX#[4] GND DMI DMI DMI GND PCIe GND PCIe GND GND REF GND Analog Analog CMOS Async CMOS GND CMOS DMI GND DMI GND PCIe GND PCIe PCIe I I O O I O O O O O I O I I O Pin Name Buffer Type REF REF REF REF REF GND GND Dir

Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 30 of 37)
Pin # G30 G32 G34 G38 G40 G43 G44 G47 G48 G51 G53 G55 G57 G60 G70 H1 H15 H17 H24 H25 H32 H34 H36 H43 H44 H51 H53 H60 H71 J11 J13 J2 J4 J6 J8 VSS PEG_TX#[5] PEG_RX[2] PEG_RX#[1] PEG_RX#[0] VSS VCC VSS VSS VCC VSS VCC VSS VCC VSS VSS VTTPWRGOOD DMI_TX#[0] PEG_RX#[6] PEG_RX#[5] PEG_TX[5] PEG_RX#[2] VSS VSS VCC VCC VSS VCC VSS DMI_TX[3] DMI_TX#[2] DMI_RX[3] DMI_RX#[3] DMI_RX[1] DMI_RX#[1] Pin Name Buffer Type GND PCIe PCIe PCIe PCIe GND REF GND GND REF GND REF GND REF GND GND Async CMOS DMI PCIe PCIe PCIe PCIe GND GND REF REF GND REF GND DMI DMI DMI DMI DMI DMI O O I I I I I O I I O I O I I I Dir
Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 31 of 37)
Pin # J9 J20 J21 J28 J30 J38 J40 J47 J48 J55 J57 J62 J64 J65 J67 J69 J70 K1 K4 K6 K8 K9 K11 K15 K17 K24 K25 K32 K34 K36 K43 K44 K51 K53 VSS PEG_TX#[15] PEG_CLK# PEG_RX[4] PEG_TX[8] PEG_RX[1] VSS VSS VSS VCC VSS BPM#[2] BPM#[5] VSS BPM#[1] BPM#[0] BCLK_ITP # FDI_TX[0] VSS VSS DMI_RX#[2] DMI_RX[2] VSS DMI_TX#[1] VSS PEG_RX[6] VSS VSS VSS VSS VSS VCC VCC VSS Pin Name Buffer Type GND PCIe DIFF CLK PCIe PCIe PCIe GND GND GND REF GND GTL GTL GND GTL GTL DIFF CLK FDI GND GND DMI DMI GND DMI GND PCIe GND GND GND GND GND REF REF GND I O I I I/O I/O O O I/O I/O O I I O I Dir
Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 32 of 37)
Pin # K60 K62 K64 K65 K69 K71 L2 L13 L20 L21 L28 L30 L38 L40 L47 L48 L55 L57 L70 M1 M4 M15 M17 M24 M25 M32 M34 M36 M42 M44 M51 M53 M60 M69 VCC BPM#[4] VSS BPM#[3] BPM#[6] BCLK_ITP FDI_TX#[0] VSS PEG_TX[15] PEG_CLK PEG_TX#[11] PEG_TX#[8] PEG_TX#[1] PEG_TX[0] VSS VSS VCC VSS VSS VSS FDI_TX#[2] DMI_TX[1] PM_SYNC PEG_TX#[13] PEG_TX[12] PEG_TX#[2] PEG_RX[3] VSS VSS VCC VCC VSS VCC BPM#[7] Pin Name Buffer Type REF GTL GND GTL GTL DIFF CLK FDI GND PCIe Diff CLK PCIe PCIe PCIe PCIe GND GND REF GND GND GND FDI DMI CMOS PCIe PCIe PCIe PCIe GND GND REF REF GND REF GTL I/O O O I O O O I O I O O O O I/O I/O O O I/O Dir
Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 33 of 37)
Pin # M71 N2 N5 N7 N9 N10 N13 N15 N17 N19 N21 N24 N26 N28 N30 N32 N38 N40 N42 N44 N46 N48 N50 N51 N53 N55 N57 N61 N63 N65 N67 N70 P1 Pin Name PROC_DETECT FDI_TX[2] FDI_TX[1] FDI_TX#[1] FDI_TX[4] FDI_TX#[4] VTT_SENSE VSS THERMTRIP# PECI VSS PEG_TX[13] PEG_TX#[12] PEG_TX[11] VSS PEG_TX[2] PEG_TX[1] PEG_TX#[0] VCC VCC VSS VCC VSS VCC VSS VCC VSS CATERR# VSS TMS PROCHOT# RESET_OBS# FDI_TX#[3] FDI FDI FDI FDI FDI Analog GND Async GTL Async GND PCIe PCIe PCIe GND PCIe PCIe PCIe REF REF GND REF GND REF GND REF GND GTL GND CMOS Async GTL Async CMOS FDI I I/O O O I/O O O O O O O O I/O O O O O O O Buffer Type Dir