1.5 1.6 1.7 1.2.1

Interfaces.... 20

2.5 2.6

Technologies...36 3.1 4.1 Intel Graphics Dynamic Frequency...36 ACPI States Supported....37 4.1.1 System States...37 4.1.2 Processor Core/Package Idle States...37 4.1.3 Integrated Memory Controller States..38 4.1.4 PCIe Link States...38 4.1.5 DMI States....38 4.1.6 Integrated Graphics Controller States...38 4.1.7 Interface State Combinations..39 Processor Core Power Management...39 4.2.1 Enhanced Intel SpeedStep Technology..40 4.2.2 Low-Power Idle States....40 4.2.3 Requesting Low-Power Idle States..42 4.2.4 Core C-states....43 4.2.5 Package C-States...44 IMC Power Management...47 4.3.1 Disabling Unused System Memory Outputs..48 4.3.2 DRAM Power Management and Initialization..48 PCIe Power Management...49 DMI Power Management...50 Integrated Graphics Power Management...50 4.6.1 Intel Display Power Saving Technology 5.0 (Intel DPST 5.0).50 4.6.2 Graphics Render C-State...50 4.6.3 Graphics Performance Modulation Technology..50 4.6.4 Intel Smart 2D Display Technology (Intel S2DDT)..50 Thermal Power Management...51 Thermal Design Power and Junction Temperature...52 5.1.1 Intel Graphics Dynamic Frequency..52 5.1.2 Intel Graphics Dynamic Frequency Thermal Design Considerations and Specifications....53 5.1.3 Idle Power Specifications...55 5.1.4 Intelligent Power Sharing Control Overview..56 5.1.5 Component Power Measurement/Estimation Error..57 Thermal Management Features...57 5.2.1 Processor Core Thermal Features..57 5.2.2 Integrated Graphics and Memory Controller Thermal Features..64 5.2.3 Platform Environment Control Interface (PECI)..67 System Memory Interface...70 Memory Reference and Compensation...72 Reset and Miscellaneous Signals...73 PCI Express Graphics Interface Signals...74 Embedded DisplayPort (eDP)...75 Intel Flexible Display Interface Signals...75 DMI.....76 PLL Signals...76 TAP Signals...77 Power Management....37

4.3 4.4 4.5 4.6

Thermal Management....52
Signal Description....69 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9
6.10 6.11 6.12 6.13 6.7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11
Error and Thermal Protection... 78 Power Sequencing... 79 Processor Power Signals... 80 Ground and NCTF.... 82 Processor Internal Pull Up/Pull Down... 82 Power and Ground Pins... 84 Decoupling Guidelines... 84 7.2.1 Voltage Rail Decoupling... 84 Processor Clocking (BCLK, BCLK#)... 84 7.3.1 PLL Power Supply... 85 Voltage Identification (VID)... 85 Reserved or Unused Signals... 89 Signal Groups.... 90 Test Access Port (TAP) Connection... 92 Absolute Maximum and Minimum Ratings... 93 Storage Conditions Specifications.. 93 DC Specifications.... 94 7.10.1 Voltage and Current Specifications.. 95 Platform Environmental Control Interface (PECI) DC Specifications.. 102 7.11.1 DC Characteristics... 102 7.11.2 Input Device Hysteresis... 103 Processor Pin Assignments... 104 Package Mechanical Information.. 178

Figure 1-1. Intel Pentium P6000 and U5000 Mobile Processor Series on the Calpella Platform
Dual Core Processor Discrete Graphics (PEG)

PCI Express* x16

Processor

GPU, Memory Controller

800/1066 MT/s 2 Channels 1 SO-DIMM / Channel
Embedded DisplayPort* (eDP)
DDR3 SO-DIMMs PCI Express x 1
Intel Flexible Display Interface

DMI2 (x4)

Digital Display x 3
LVDS Flat Panel Analog CRT

Intel Management Engine

Serial ATA USB 2.0

6 Ports 3 Gb/s 14 Ports

Mobile Intel 5 Series Chipset PCH
Dual Channel NAND Interface

Intel HD Audio

SMBUS 2.0

SPI Flash PCI FWH

Controller Link 1 SPI

PCI Express*

WiFi Gigabit Network Connection

Super I/O

8 PCI Express* x1 Ports (2.5 GT/s)
Processor Feature Details
Two execution cores A 32-KB instruction and 32-KB data first-level cache (L1) for each core A 512-KB shared instruction/data second-level cache (L2), 256-KB for each core Up to 3-MB shared instruction/data third-level cache (L3), shared among all cores

Supported Technologies

Intel 64 architecture Execute Disable Bit Processor Context Identifier (PCID) (U5000 processor series only)
Please refer to the Intel Pentium P6000 and U5000 Mobile Processor Series Specification Update for feature support details

Interfaces

System Memory Support
One or two channels of DDR3 memory with a maximum of one SO-DIMM per

channel

Single- and dual-channel memory organization modes Data burst length of eight for all memory organization modes Memory DDR3 data transfer rates of 800 MT/s (SV/ULV) and 1066 MT/s (SV) 64-bit wide channels DDR3 I/O Voltage of 1.5 V Non-ECC, unbuffered DDR3 SO-DIMMs only Theoretical maximum memory bandwidth of:
12.8 GB/s in dual-channel mode assuming DDRMT/s
1-Gb, and 2-Gb DDR3 DRAM technologies are supported for x8 and x16 devices. Using 2-Gb device technologies, the largest memory capacity possible is 8 GB,
assuming dual-channel mode with two x8, double-sided, un-buffered, non-ECC, SO-DIMM memory configuration.
Up to 32 simultaneous open pages, 16 per channel (assuming 4 Ranks of 8 Bank

Devices)

Memory organizations:
Single-channel modes Dual-channel modes - Intel Flex Memory Technology:
Dual-channel symmetric (Interleaved) Dual-channel asymmetric
Command launch modes of 1n/2n Partial Writes to memory using Data Mask (DM) signals On-Die Termination (ODT) Intel Fast Memory Access (Intel FMA):
Just-in-Time Command Scheduling Command Overlap Out-of-Order Scheduling
The Processor PCI Express ports are fully compliant to the PCI Express Base
Specification Revision 2.0. One 16-lane PCI Express* port intended for graphics attach.

250 MB/s given the 8b/10b encoding used to transmit data across this interface. Does not account for packet overhead and link maintenance.
Maximum theoretical bandwidth on interface of 1 GB/s in each direction
simultaneously, for an aggregate of 2 GB/s when DMI x4.
Shares 100-MHz PCI Express reference clock. 64-bit downstream address format, but the processor never generates an address
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped.
Supports the following traffic types to or from the PCH:
DMI -> PCI Express Port 0 write traffic DMI -> DRAM DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)

Processor core -> DMI

APIC and MSI interrupt messaging support:
Message Signaled Interrupt (MSI and MSI-X) messages
Downstream SMI, SCI and SERR error indication. Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters.
DC coupling no capacitors between the processor and the PCH. Polarity inversion. PCH end-to-end lane reversal across the link. Supports Half Swing low-power/low-voltage.
Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a PECI client (the processor) and a PECI master (the PCH).
Intel HD Graphics Controller
The integrated graphics controller contains a refresh of the fifth generation graphics
Intel Dynamic Video Memory Technology (Intel DVMT) support Intel Graphics Performance Modulation Technology (Intel GPMT) Intel Smart 2D Display Technology (Intel S2DDT) Intel Clear Video Technology
MPEG2 Hardware Acceleration WMV9/VC1 Hardware Acceleration AVC Hardware Acceleration ProcAmp Advanced Pixel Adaptive De-interlacing Sharpness Enhancement De-noise Filter High Quality Scaling Film Mode Detection (3:2 pull-down) and Correction Intel TV Wizard
12 EUs Dedicated analog and digital display ports are supported through the Intel 5 Series

Chipset PCH

Embedded DisplayPort* (eDP*)
Shared with PCI Express Graphics port Shared on upper four logical lanes, after any lane reversal eDP[3:0] map to PEG[12:15] (non-reversed) eDP[3:0] map to PEG[3:0] (reversed) Concurrent eDP and PEG x1 supported
Intel Flexible Display Interface (Intel FDI)
Carries display traffic from the integrated graphics controller in the processor to the
legacy display connectors in the PCH.
Based on DisplayPort standard. Two independent links - one for each display pipe. Four unidirectional downstream differential transmitter pairs:

Scalable down to 3X, 2X, or 1X based on actual display bandwidth requirements Fixed frequency 2.7 GT/s data rate
Two sideband signals for Display synchronization:
FDI_FSYNC and FDI_LSYNC (Frame and Line Synchronization)
One Interrupt signal used for various interrupts from the PCH:
FDI_INT signal shared by both Intel FDI Links
PCH supports end-to-end lane reversal across both links.

Power Management Support

Processor Core
Full support of ACPI C-states as implemented by the following processor C-states:
Ultra low voltage supports C0, C1, C1E, C3, C6 Standard voltage supports C0, C1, C1E, C3
Enhanced Intel SpeedStep Technology

System

S0, S3, S4, S5

Memory Controller

Conditional self-refresh (Intel Rapid Memory Power Management (Intel RMPM)) Dynamic power-down
L0s and L1 ASPM power management capability
Integrated Graphics Controller
Intel Smart 2D Display Technology (Intel S2DDT) Intel Display Power Saving Technology (Intel DPST) Graphics Render C-State (RC6)
Thermal Management Support
Digital Thermal Sensor Adaptive Thermal Monitor THERMTRIP# and PROCHOT# support On-Demand Mode Open and Closed Loop Throttling Memory Thermal Throttling External Thermal Sensor (TS-on-DIMM and TS-on-Board) Render Thermal Throttling Fan speed control with DTS

Package

The Intel Pentium P6000 and U5000 Mobile Processor Series is available is
available on: A 37.5 x 37.5 mm rPGA package (rPGA988A) (Standard Voltage only) A 34 x 28 mm BGA package (BGA1288) (Ultra Low voltage only)

Terminology

Term BLT Deep Power Down Technology CRT DDR3 DP DMA DMI DTS ECC eDP* Intel DPST Enhanced Intel SpeedStep Technology Execute Disable Bit Block Level Transfer Code named as C6 state throughout the document Cathode Ray Tube Third-generation Double Data Rate SDRAM memory technology DisplayPort* Direct Memory Access Direct Media Interface Digital Thermal Sensor Error Correction Code Embedded DisplayPort* Intel Display Power Saving Technology Technology that provides power management capabilities to laptops. Description

2.4.1.2.5

Strips and Fans (SF) Stage The SF stage performs setup operations required to rasterize 3D objects. The outputs from the SF stage to the Windower stage contain implementation-specific information required for the rasterization of objects and also supports clipping of primitives to some extent.

2.4.1.2.6

Windower/IZ (WIZ) Stage The WIZ unit performs an early depth test, which removes failing pixels and eliminates unnecessary processing overhead. The Windower uses the parameters provided by the SF unit in the object-specific rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of pixels. The Windower is also capable of performing dithering, whereby the illusion of a higher resolution when using low-bpp channels in color buffers is possible. Color dithering diffuses the sharp color bands seen on smooth-shaded objects.

2.4.1.3

The Video Engine handles the non-3D (media/video) applications. It includes support for VLD and MPEG2 decode in hardware.

2.4.1.4

2D Engine
The 2D Engine contains BLT (Block Level Transfer) functionality and an extensive set of 2D instructions. To take advantage of the 3D during engines functionality, some BLT functions make use of the 3D renderer.

2.4.1.4.1

Integrated Graphics VGA Registers The 2D registers consists of original VGA registers and others to support graphics modes that have color depths, resolutions, and hardware acceleration features that go beyond the original VGA standard.

2.4.1.4.2

Logical 128-Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The 128-bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations. The BLT engine can be used for the following:
Move rectangular blocks of data between memory locations Data alignment To perform logical operations (raster ops)

The rectangular block of data does not change, as it is transferred between memory locations. The allowable memory transfers are between: cacheable system memory and frame buffer memory, frame buffer memory and frame buffer memory, and within system memory. Data to be transferred can consist of regions of memory, patterns, or solid color fills. A pattern is always 8 x 8 pixels wide and may be 8, 16, or 32 bits per pixel. The BLT engine expands monochrome data into a color depth of 8, 16, or 32 bits. BLTs can be either opaque or transparent. Opaque transfers move the data specified to the destination. Transparent transfers compare destination color to source color and write according to the mode of transparency selected. Data is horizontally and vertically aligned at the destination. If the destination for the BLT overlaps with the source memory location, the BLT engine specifies which area in memory to begin the BLT transfer. Hardware is included for all 256 raster operations (source, pattern, and destination) defined by Microsoft, including transparent BLT. The BLT engine has instructions to invoke BLT and stretch BLT operations, permitting software to set up instruction buffers and use batch processing. The BLT engine can perform hardware clipping during BLTs.
Integrated Graphics Display Pipes
The integrated graphics controller display pipe can be broken down into three components:
Display Planes Display Pipes Embedded DisplayPort and Intel FDI
Figure 2-8. Processor Display Block Diagram
Sprite A Cursor A VGA Plane B Sprite B Cursor B Alpha Blend/ Gamma/ Panel Fitter

2.4.2.1

Display Planes
A display plane is a single displayed surface in memory and contains one image (desktop, cursor, overlay). It is the portion of the display HW logic that defines the format and location of a rectangular region of memory that can be displayed on display output device and delivers that data to a display pipe. This is clocked by the Core Display Clock.

2.4.2.1.1

Planes A and B Planes A and B are the main display planes and are associated with Pipes A and B respectively. The two display pipes are independent, allowing for support of two independent display streams. They are both double-buffered, which minimizes latency and improves visual quality.

2.4.2.1.2

Sprite A and B Sprite A and Sprite B are planes optimized for video decode, and are associated with Planes A and B respectively. Sprite A and B are also double-buffered.

2.4.2.1.3

Cursors A and B Cursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration, and are associated with Planes A and B respectively. These planes support resolutions up to 256 x 256 each.

eDP Signal eDP_TX[0] eDP_TX#[0] eDP_TX[1] eDP_TX#[1] eDP_TX[2] eDP_TX#[2] eDP_TX[3] eDP_TX#[3] PEG Signal PEG_TX[15] PEG_TX#[15] PEG_TX[14] PEG_TX#[14] PEG_TX[13] PEG_TX#[13] PEG_TX[12] PEG_TX#[12] Lane Reversal PEG_TX[0] PEG_TX#[0] PEG_TX[1] PEG_TX#[1] PEG_TX[2] PEG_TX#[2] PEG_TX[3] PEG_TX#[3]
When eDP is enabled, the lower logical lanes are still available for standard PCIe devices, using the PEG 0 controller. PEG 0 is limited to x1. The board manufacture chooses whether to use eDP and whether to use lane numbering reversal. The eDP interface supports link-speeds of 1.62 Gbps and 2.7 Gbps on 1, 2 or 4 data lanes. The eDP and PCI Express x1 may be supported concurrently. eDP interface may support -0.5% SSC and non-SSC clock settings.
The Intel Flexible Display Interface (Intel FDI) is a proprietary link for carrying display traffic from the integrated graphics controller to the PCH display I/Os. Intel FDI supports two independent channels; one for pipe A and one for pipe B.
Each channel has four transmit (Tx) differential pairs used for transporting pixel
and framing data from the display engine.
Each channel has one single-ended LineSync and one FrameSync input (1-V CMOS

signaling).

One display interrupt line input (1-V CMOS signaling). Intel FDI may dynamically scalable down to 2X or 1X based on actual display

bandwidth requirements.

Common 100-MHz reference clock is sent to both processor and PCH. Each channel transports at a rate of 2.7 Gbps. PCH supports end-to-end lane reversal across both channels (no reversal support

required)

The PECI is a one-wire interface that provides a communication channel between a PECI client (processor) and a PECI master, usually the PCH. The processor implements a PECI interface to:
Allow communication of processor thermal and other information to the PECI

master.

Read averaged Digital Thermal Sensor (DTS) values for fan speed control.

Interface Clocking

Internal Clocking Requirements
Table 2-4. Processor Reference Clocks
Reference Input Clocks BCLK/BCLK# PEG_CLK/PEG_CLK# DPLL_REF_SSCLK/DPLL_REF_SSCLK# Input Frequency 133 MHz 100 MHz 120 MHz Associated PLL Processor/Memory/Graphics PCI Express*/DMI/Intel FDI Embedded DisplayPort* (eDP)

Technologies

Intel Graphics Dynamic Frequency
Graphics render frequency are selected by the Intel graphics driver dynamically based on graphics workload demand as permitted by Intel Turbo Boost Technology Driver. The processor core die and the integrated graphics and memory controller core die have an individual TDP limit. If one component is not consuming enough thermal power to reach its TDP, the other component can increase its TDP limit and take advantage of the unused thermal power headroom. For the integrated graphics, this could mean an increase in the render core frequency (above its rated frequency) and increased graphics performance.

4.2.4.3

Core C3 State
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while maintaining its architectural state. All core clocks are stopped at this point. Because the cores caches are flushed, the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory.

4.2.4.4

Core C6 State
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an MWAIT(C6) instruction. Before entering core C6, the core will save its architectural state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts. During exit, the core is powered on and its architectural state is restored.

4.2.4.5

C-State Auto-Demotion
In general, deeper C-states such as Deep Power Down Technology (code named C6 state) have long latencies and have higher energy entry/exit costs. The resulting performance and energy penalties become significant when the entry/exit frequency of a deeper C-state is high. Therefore incorrect or inefficient usage of deeper C-states have a negative impact on battery life. In order to increase residency and improve battery life in deeper C-states, the processor supports C-state auto-demotion. There are two C-State auto-demotion options:
Deep Power Down Technology (code named C6 state) to C3 Deep Power Down Technology (code named C6 state)/C3 To C1
The decision to demote a core from Deep Power Down Technology (code named C6 state) to C3 or C3/Deep Power Down Technology (code named C6 state) to C1 is based on each cores immediate residency history. Upon each core Deep Power Down Technology (code named C6 state) request, the core C-state is demoted to C3 or C1 until a sufficient amount of residency has been established. At that point, a core is allowed to go into C3/Deep Power Down Technology (code named C6 state). Each option can be run concurrently or individually. This feature is disabled by default.

Package C-States

The processor supports C0, C1/C1E, C3, and Deep Power Down Technology (code named C6 state) package idle power states. The following is a summary of the general rules for package C-state entry. These apply to all package C-states unless specified otherwise:

5.2.2.1.5

5.2.2.1.6
Hysteresis Operation Hysteresis provides a small amount of positive feedback to the thermal sensor circuit to prevent a trip point from flipping back and forth rapidly when the temperature is right at the trip point. The digital hysteresis offset is programmable via processor registers.

5.2.2.2

Memory Thermal Throttling Options
The integrated graphics and memory controller has two, independent mechanisms that cause system memory throttling: TDP Controller: The TDP Controller is the main mechanism for limiting MCH power by limiting memory bandwidth. Utilized as a thermal throttling mechanism, this feature is triggered by the Hot temperature trip point of the Graphics and Memory Controller
digital thermal sensor (DTS) and initiates duty cycle throttling to delay memory transactions and thereby reducing MCH power. Power reduction is memory configuration and application dependant but duty cycle throttling intervals can be customized for maximum throttling efficiency. The TDP Controller can also be used as a bandwidth limiter using programmable memory read/write bandwidth thresholds. Intel sets the default thresholds that will not restrict bandwidth and performance for most applications but these thresholds can be modified to reduce MCH power regardless of DTS temperature. Note: The TDP controller can be used as a closed loop thermal throttling (CLTT) mechanism or an open loop thermal throttling (OLTT) mechanism, although CLTT is recommended.
DRAM Thermal Management: Ensures that the DRAM chips are operating within
thermal limits. The integrated graphics and memory controller can control the amount of integrated graphics and memory controller-initiated bandwidth per rank to a programmable limit via a weighted input averaging filter.

5.2.2.3

External Thermal Sensor Interface Overview
The integrated graphics and memory controller supports two inputs for external thermal sensor notifications, based on which it can regulate memory accesses.
The thermal sensors should be capable of measuring the ambient temperature only and should be able to assert PM_EXT_TS#[0] and/or PM_EXT_TS#[1] if the preprogrammed thermal limits/conditions are met or exceeded. An external thermal sensor with a serial interface may be placed next to a SO-DIMM (or any other appropriate platform location), or a remote Thermal Diode may be placed next to the SO-DIMM (or any other appropriate platform location) and connected to the external Thermal Sensor. Additional external thermal sensor's outputs, for multiple sensors, can be wire-OR'd together allow signaling from multiple sensors that are physically located separately. Software can, if necessary, distinguish which SO-DIMM(s) is the source of the overtemp through the serial interface. However, since the SO-DIMM's is located on the same Memory Bus Data lines, any integrated graphics and memory controller-based read throttle will apply equally. Thermal sensors can either be directly routed to the integrated graphics and memory controller PM_EXT_TS#[0] and PM_EXT_TS#[1] pins or indirectly routed to integrated graphics and memory controller by invoking an Embedded Controller (EC) connected in between the thermal sensor and integrated graphics and memory controller pins. Both routing methods are applicable for both thermal sensors placed on the motherboard (TS-on-Board) and/or thermal sensors located on the memory modules (TS-on-DIMM).

PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external Adaptive Thermal Monitor devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature. Temperature sensors located throughout the die are implemented as analog-to-digital converters calibrated at the factory. PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control. More detailed information may be found in the Platform Environment Control Interface (PECI) Specification.

7.11.1

DC Characteristics
The PECI interface operates at a nominal voltage set by VTT. The set of DC electrical specifications shown in Table 7-48 is used with devices normally operating from a VTT interface supply. VTT nominal levels will vary between processor families. All PECI devices will operate at the VTT level determined by the processor installed in the system. For specific nominal VTT levels, refer to Table 7-44.
Table 7-48.PECI DC Electrical Limits
Symbol Definition and Conditions Min Max Units Notes1
Vin Vhysteresis Vn Vp Isource Isink Ileak+ IleakCbus Vnoise
Input Voltage Range Hysteresis Negative-edge Threshold Voltage Positive-edge Threshold Voltage High-Level Output Source (VOH = 0.75 * VTT) Low-Level Output Sink (VOL = 0.25 * VTT) High-Impedance State Leakage to VTT (Vleak = VOL) High-Impedance Leakage to GND (Vleak = VOH) Bus Capacitance Per Node Signal Noise Immunity above 300 MHz
-0.150 0.1 * VTT 0.275 * VTT 0.550 * VTT -6.0 0.5 N/A N/A N/A 0.1 * VTT
VTT N/A 0.500 * VTT 0.725 * VTT N/A 1.N/A
V V V V mA mA A A pF Vp-p 2 2
NOTES: 1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. 2. The leakage specification applies to powered devices on the PECI bus.

7.11.2

Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 7-16 as a guide for input buffer design.
Figure 7-16.Input Device Hysteresis
VTTD Maximum VP Minimum VP Minimum Hysteresis Maximum VN Minimum VN PECI Ground PECI Low Range Valid Input Signal Range PECI High Range

Pin Name PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] PEG_TX#[0] Pin Number A28 B29 A30 K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 L33 Buffer Type PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe Dir. I I I I I I I I I I I I I I I I I I I O O O O O O O O O O O O O O O O O
Pin Name PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PM_EXT_TS#[0] PM_EXT_TS#[1] PM_SYNC PRDY# PREQ# PROC_DPRSLPV R PROCHOT# PSI# RESET_OBS# RSTIN# RSVD RSVD RSVD RSVD RSVD RSVD RSVD Pin Number M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 AN15 AP15 AL15 AT28 AP27 AM34 AN26 AN33 AP26 AL14 A19 A20 AB9 AC9 AG9 AH15 AH25 Buffer Type PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe CMOS CMOS CMOS Async GTL Async GTL CMOS Async GTL Async CMOS Async CMOS CMOS Dir. O O O O O O O O O O O O O O O I I I O I O I/O O O I
Pin Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD_NCTF RSVD_NCTF Pin Number AJ15 AJ26 AJ27 AJ33 AL22 AL24 AL25 AL27 AL28 AL29 AP25 AP30 AP32 AP33 AR32 AR33 AT31 AT32 B19 B20 C15 D15 E30 E31 G17 G25 H17 J17 J28 J29 L28 M27 T9 U9 A3 A33 Buffer Type Dir.
Pin Name RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP Pin Number A34 AP1 AP35 AR1 AR2 AR35 AT3 AT33 AT34 B35 C1 C35 AA1 AA2 AA4 AA5 AD2 AD3 AD5 AD7 AD9 AE3 AE5 AG7 AJ12 AJ13 AK26 AL26 AT2 E15 F15 H16 N2 N3 R8 R9 Buffer Type Dir.
Pin Name RSVD_TP RSVD_TP RSVD_TP RSVD_TP SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_CK[0] SA_CK[1] SA_CK#[0] SA_CK#[1] SA_CKE[0] SA_CKE[1] SA_CS#[0] SA_CS#[1] SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] Pin Number V4 V5 W2 W3 AC3 AB2 U7 AE1 AA6 Y6 AA7 Y5 P7 P6 AE2 AE8 B9 D7 H7 M7 AG6 AM7 AN10 AN13 A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type Dir.

Table 8-51.BGA1288 Processor Ball List by Ball Name (Sheet 7 of 37)
Pin Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VCAP0_VSS_SENSE VCAP0_SENSE RSVD_NCTF RSVD_TP RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_TP RSVD_TP RSVD_TP SA_BS[0] SA_BS[1] SA_BS[2] Pin # AP66 AR69 AR71 AT67 AT70 AU2 AU69 AU71 AV4 AV69 AV71 B7 B9 D8 R64 R66 T2 T4 U1 V2 W64 W66 A6 BR5 BT5 BV6 BV8 C5 E3 F1 AN7 AP2 AU1 BT38 BH38 BF21 DDR3 DDR3 DDR3 O O O Buffer Type Dir
Table 8-51.BGA1288 Processor Ball List by Ball Name (Sheet 8 of 37)
Pin Name SA_CAS# SA_CK[0] SA_CK[1] SA_CK#[0] SA_CK#[1] SA_CKE[0] SA_CKE[1] SA_CS#[0] SA_CS#[1] SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] Pin # BK43 BM34 BK36 BP35 BH36 BF20 BK24 BH40 BJ47 BB10 BJ10 BM15 BN24 BG44 BG53 BN62 BH59 AT8 AT6 BB5 BB9 AV7 AV6 BE6 BE8 BF11 BE11 BK5 BH13 BF9 BF6 BK7 BN8 BN11 BN9 BG17 Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 Dir O O O O O O O O I/O O I/O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Table 8-51.BGA1288 Processor Ball List by Ball Name (Sheet 9 of 37)
Pin Name SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] Pin # BK15 BK9 BG15 BH17 BK17 BN20 BN17 BK25 BH25 BJ20 BH21 BG24 BG25 BJ40 BM43 BF47 BF48 BN40 BH43 BN44 BN47 BN48 BN51 BH53 BJ55 BH48 BJ48 BM53 BN55 BF55 BN57 BN65 BJ61 BF57 BJ57 BK64 Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 Dir I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Table 8-51.BGA1288 Processor Ball List by Ball Name (Sheet 10 of 37)
Pin Name SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] Pin # BK61 BJ63 BF64 BB64 BB66 BJ66 BF65 AY64 BC70 AY7 BJ5 BL13 BN21 BK44 BH51 BM60 BE64 AY5 BJ7 BN13 BL21 BH44 BK51 BP58 BE62 BT36 BP33 BV36 BG34 BG32 BN32 BK32 BJ30 BN30 BF28 BH34 Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 Dir I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O

Table 8-51.BGA1288 Processor Ball List by Ball Name (Sheet 11 of 37)
Pin Name SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] SA_ODT[0] SA_ODT[1] SA_RAS# SA_WE# SB_BS[0] SB_BS[1] SB_BS[2] SB_CAS# SB_CK[0] SB_CK[1] SB_CK#[0] SB_CK#[1] SB_CKE[0] SB_CKE[1] SB_CS#[0] SB_CS#[1] SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] Pin # BH30 BJ28 BF40 BN28 BN25 BF43 BL47 BL38 BF38 BV43 BV41 BV24 BU46 BU33 BV38 BV34 BU39 BT26 BT24 BP46 BT43 BB4 BL4 BT13 BP22 BV47 BV57 BU65 BF67 BA2 AW2 BD1 BE4 AY1 BC2 BF2 Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 Dir O O O O O O O O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O
Table 8-51.BGA1288 Processor Ball List by Ball Name (Sheet 12 of 37)
Pin Name SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] Pin # BH2 BG4 BG1 BR6 BR8 BJ4 BK2 BU9 BV10 BR10 BT12 BT15 BV15 BV12 BP12 BV17 BU16 BP15 BU19 BV22 BT22 BP19 BV19 BV20 BT20 BT48 BV48 BV50 BP49 BT47 BV52 BV54 BT54 BP53 BU53 BT59 Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 Dir I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Table 8-51.BGA1288 Processor Ball List by Ball Name (Sheet 13 of 37)
Pin Name SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] Pin # BT57 BP56 BT55 BU60 BV59 BV61 BP60 BR66 BR64 BR62 BT61 BN68 BL69 BJ71 BF70 BG71 BC67 BK70 BK67 BD71 BD69 BD4 BN4 BV13 BT17 BT50 BU56 BV62 BJ69 BE2 BM3 BU12 BT19 BT52 BV55 BU63 Buffer Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 Dir I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Intel Pentium P6000 and U5000 Mobile Processor Series

Specification Update

February 2011 Revision 008
Document Number: 323874-008
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Legal Lines and Disclaimers
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. The processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Intel Core, Centrino, Celeron, Pentium, Intel Xeon, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 2010, Intel Corporation. All Rights Reserved.

Contents

Preface..... 5 Summary Tables of Changes... 7 Identification Information.... 14 Errata..... 17 Specification Changes.... 49 Specification Clarifications... 50 Documentation Changes... 51

Revision History

Revision Initial release

Description

Revision Date May 2010 June 2010 July 2010 September 2010 October 2010 December 2010 January 2011 February 2011
Added P6000 sku information Added BG81 and BG82 Removed erratum description for BG61 Added BG83. Changed wording on BG31. and BG66. Added BG84 and BG85 Added BG86.
Added BG87. and BG88. Added U5600 processor information in Table 1-1
Added errata BG89. BG90. BG91. BG92. BG93. Added P6300 processor information in Table 1-1

Preface

This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published.

Affected Documents

Document Title Intel Pentium P6000 and U5000 Mobile Processor Series Datasheet Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series Datasheet - Volume 1 and Volume 2 Document Number Location 323873 322812, 322813

Related Documents

Document Title AP-485, Intel Processor Identification and the CPUID Instruction Intel 64 and IA-32 Architectures Software Developers Manual, Volume 1: Basic Architecture Intel 64 and IA-32 Architectures Software Developers Manual, Volume 2A: Instruction Set Reference Manual A-M Intel 64 and IA-32 Architectures Software Developers Manual, Volume 2B: Instruction Set Reference Manual N-Z Intel 64 and IA-32 Architectures Software Developers Manual, Volume 3A: System Programming Guide Intel 64 and IA-32 Architectures Software Developers Manual, Volume 3B: System Programming Guide Intel 64 and IA-32 Intel Architecture Optimization Reference Manual Intel 64 and IA-32 Architectures Software Developers Manual Documentation Changes (see note 1) ACPI Specifications NOTES:

1. Documentation changes for the Intel 64 and IA-32 Architecture Software Developer's Manual Volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document, the Intel 64 and IA-32 Architecture Software Developer's Manual Documentation Changes. Follow the link http://developer.intel.com/ products/processor/manuals/index.htm to access this documentation.
Document Number/ Location http://www.intel.com/ design/processor/applnots/ 241618.htm http://www.intel.com/ products/processor/manuals/ index.htm

www.acpi.info

Nomenclature
Errata are design defects or errors. These may cause the Arrandale Processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics,e.g., core speed, L3 cache size, package type, etc. as described in the processor identification information table. Read all notes associated with each S-Spec number. Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification. Specification Clarifications describe a specification in greater detail or further highlight a specifications impact to a complex design situation. These clarifications will be incorporated in any new release of the specification. Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification. Note: Errata remain in the specification update throughout the products lifecycle, or until a particular stepping is no longer commercially-available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.).

Summary Tables of Changes
The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations:
Codes Used in Summary Tables

Stepping

X: (No mark) or (Blank box): This erratum is fixed in listed stepping or specification change does not apply to listed stepping. Errata exists in the stepping indicated. Specification Change or Clarification that applies to this stepping.
(Page): Page location of item in this document.

Status

Doc: Plan Fix: Fixed: No Fix: Document change or update will be implemented. This erratum may be fixed in a future stepping of the product. This erratum has been previously fixed. There are no plans to fix this erratum.
Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document. Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intels microprocessor Specification Updates:

Errata (Sheet 1 of 5)

Number BG1 Steppings C-2 X K-0 X Status No Fix ERRATA The Processor May Report a #TS Instead of a #GP Fault REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher Priority Interrupts/Exceptions and May Push the Wrong Address onto the Stack Performance Monitor SSE Retired Instructions May Return Incorrect Values Premature Execution of a Load Operation Prior to Exception Handler Invocation MOV To/From Debug Registers Causes Debug Exception Incorrect Address Computed For Last Byte of FXSAVE/ FXRSTOR Image Leads to Partial Memory Update Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM Single Step Interrupts with Floating Point Exception Pending May Be Mishandled Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception General Protection Fault (#GP) for Instructions Greater than 15 Bytes May Be Preempted General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit LBR, BTS, BTM May Report a Wrong Address When an Exception/Interrupt Occurs in 64-bit Mode MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang Corruption of CS Segment Register during RSM While Transitioning from Real Mode to Protected Mode Performance Monitoring Events for Read Miss to Level 3 Cache Fill Occupancy Counter May Be Incorrect Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately #GP on Segment Selector Descriptor That Straddles Canonical Boundary May Not Provide Correct Exception Error Code Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint Is Set on a #GP Instruction

BG85 BG86 X

No Fix No Fix
BG88 BG89 BG90 BG91 BG92 BG93 BG94

Specification Changes

Number Specification Changes None for this revision of this specification update.
Specification Clarifications
Number Specification Clarifications None for this revision of this specification update.

Documentation Changes

Number Documentation Changes None for this revision of this specification update.
Identification Information
Component Identification via Programming Interface
The Intel Pentium P6000 and U5000 Mobile Processor Series stepping can be identified by the following processor signatures:
Reserved 31:28 Extended Family1 27:20 00000000b Extended Model2 19:16 0010b Reserved 15:14 Processor Type3 13:12 00b Family Code4 11:Model Number5 7:4 0101b Stepping ID6 3:0 xxxxb
NOTES: 1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8], to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4, or Intel Core processor family. 2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are used to identify the model of the processor within the processors family. 3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM processor, an OverDrive processor, or a dual processor (capable of being used in a dual processor system). 4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan. 6. The Stepping ID in bits [3:0] indicates the revision number of that model. See above table for the processor stepping ID number in the CPUID information.
When EAX is initialized to a value of 1, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID value in the EAX register. Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register. Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.
Intel Pentium P6000 and U5000 Mobile Processor Series can be identified by the following register contents:
Processor Stepping C-2 K-0 NOTES:
1. 2. 3. 4. The Vendor ID corresponds to Bits 15:0 of the Vendor ID Register located at offset 0001h in the PCI function 0 configuration space. The Device ID corresponds to Bits 15:0 of the Device ID Register located at Device 0 offset 0203h in the PCI function 0 configuration space. The Revision Number corresponds to Bits 7:0 of the Revision ID Register located at offset 08h in the PCI function 0 configuration space. Correct Host Device ID requires firmware support.

QDF / S-Spec Number

Package

Errata

BG1. Problem: The Processor May Report a #TS Instead of a #GP Fault A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception) instead of a #GP fault (general protection exception).
Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially-available software. Workaround:None identified. Status: BG2. For the steppings affected, see the Summary Tables of Changes. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations Under certain conditions as described in the Software Developers Manual section Outof-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors the processor performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data size or may observe memory ordering violations.

Problem:

Implication: Upon crossing the page boundary the following may occur, dependent on the new page memory type:
UC the data size of each write will now always be 8 bytes, as opposed to the

original data size.

WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.
WT there may be a memory ordering violation.
Workaround:Software should avoid crossing page boundaries from WB or WC memory type to UC, WP or WT memory type within a single REP MOVS or REP STOS instruction that will execute with fast strings enabled. Status: For the steppings affected, see the Summary Tables of Changes.
Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher Priority Interrupts/Exceptions and May Push the Wrong Address onto the Stack Normally, when the processor encounters a Segment Limit or Canonical Fault due to code execution, a #GP (General Protection Exception) fault is generated after all higher priority Interrupts and exceptions are serviced. Due to this erratum, if RSM (Resume from System Management Mode) returns to execution flow that results in a Code Segment Limit or Canonical Fault, the #GP fault may be serviced before a higher priority Interrupt or Exception (e.g., NMI (Non-Maskable Interrupt), Debug break(#DB), Machine Check (#MC), etc.). If the RSM attempts to return to a noncanonical address, the address pushed onto the stack for this #GP fault may not match the non-canonical address that caused the fault.

Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commerciallyavailable software. Workaround:None identified. Status: BG4. Problem: For the steppings affected, see the Summary Tables of Changes. Performance Monitor SSE Retired Instructions May Return Incorrect Values Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used to track retired SSE instructions. Due to this erratum, the processor may also count other types of instructions resulting in higher than expected values.
Implication: Performance Monitoring counter SIMD_INST_RETIRED may report count higher than expected. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG5. Problem:

Premature Execution of a Load Operation Prior to Exception Handler Invocation If any of the below circumstances occur, it is possible that the load portion of the instruction will have executed before the exception handler is entered.
If an instruction that performs a memory load causes a code segment limit

violation.

If a waiting X87 floating-point (FP) instruction or MMX technology (MMX)
instruction that performs a memory load has a floating-point exception pending.
If an MMX or SSE/SSE2/SSE3/SSSE3 extensions (SSE) instruction that performs a
memory load and has either CR0.EM=1 (Emulation bit set), or a floating-point Topof-Stack (FP TOS) not equal to 0, or a DNA exception pending. Implication: In normal code execution where the target of the load operation is to write back memory there is no impact from the load being prematurely executed, or from the restart and subsequent re-execution of that instruction by the exception handler. If the target of the load is to uncached memory that has a system side-effect, restarting the instruction may cause unexpected system behavior due to the repetition of the sideeffect. Particularly, while CR0.TS [bit 3] is set, a MOVD/MOVQ with MMX/XMM register operands may issue a memory load before getting the DNA exception. Workaround:Code which performs loads from memory that has side-effects can effectively workaround this behavior by using simple integer-based load instructions when accessing side-effect memory and by ensuring that all code is written such that a code segment limit violation cannot occur as a part of reading from side-effect memory. Status: BG6. Problem: For the steppings affected, see the Summary Tables of Changes. MOV To/From Debug Registers Causes Debug Exception When in V86 mode, if a MOV instruction is executed to/from a debug registers, a general-protection exception (#GP) should be generated. However, in the case when the general detect enable flag (GD) bit is set, the observed behavior is that a debug exception (#DB) is generated instead.

Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to execute a MOV on debug registers in V86 mode, a debug exception will be generated instead of the expected general-protection fault. Workaround:In general, operating systems do not set the GD bit when they are in V86 mode. The GD bit is generally set and used by debuggers. The debug exception handler should check that the exception did not occur in V86 mode before continuing. If the exception did occur in V86 mode, the exception may be directed to the general-protection exception handler. Status: For the steppings affected, see the Summary Tables of Changes.

BG7. Problem:

Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update A partial memory state save of the 512-byte FXSAVE image or a partial memory state restore of the FXRSTOR image may occur if a memory address exceeds the 64-KB limit while the processor is operating in 16-bit mode or if a memory address exceeds the 4-GB limit while the processor is operating in 32-bit mode.
Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as expected but the memory state may be only partially saved or restored. Workaround:Software should avoid memory accesses that wrap around the respective 16-bit and 32-bit mode memory limits. Status: BG8. Problem: For the steppings affected, see the Summary Tables of Changes. Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM After a return from SMM (System Management Mode), the CPU will incorrectly update the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their data invalid. The corresponding data if sent out as a BTM on the system bus will also be incorrect. This issue would only occur when one of the 3 above-mentioned debug support facilities are used.
Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be used. Workaround:None identified. Status: BG9. Problem: For the steppings affected, see the Summary Tables of Changes. Single Step Interrupts with Floating Point Exception Pending May Be Mishandled In certain circumstances, when a floating point exception (#MF) is pending during single-step execution, processing of the single-step debug exception (#DB) may be mishandled.

Implication: When this erratum occurs, #DB will be incorrectly handled as follows:
#DB is signaled before the pending higher priority #MF (Interrupt 16) #DB is generated twice on the same instruction
Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG10. Problem:

Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame The ENTER instruction is used to create a procedure stack frame. Due to this erratum, if execution of the ENTER instruction results in a fault, the dynamic storage area of the resultant stack frame may contain unexpected values (i.e., residual stack data as a result of processing the fault).
Implication: Data in the created stack frame may be altered following a fault on the ENTER instruction. Refer to Procedure Calls for Block-Structured Languages in IA-32 Intel Architecture Software Developer's Manual, Vol. 1, Basic Architecture, for information on the usage of the ENTER instructions. This erratum is not expected to occur in Ring 3. Faults are usually processed in Ring 0 and stack switch occurs when transferring to Ring 0. Intel has not observed this erratum on any commercially-available software. Workaround:None identified. Status: BG11. Problem: For the steppings affected, see the Summary Tables of Changes. IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET instruction even though alignment checks were disabled at the start of the IRET. This can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e mode, RSP is aligned to a 16-byte boundary before pushing the stack frame.
Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if alignment checks are disabled at the start of the IRET. This erratum can only be observed with a software generated stack frame. Workaround:Software should not generate misaligned stack frames for use with IRET. Status: BG12. Problem: For the steppings affected, see the Summary Tables of Changes. General Protection Fault (#GP) for Instructions Greater Than 15 Bytes May Be Preempted When the processor encounters an instruction that is greater than 15 bytes in length, a #GP is signaled when the instruction is decoded. Under some circumstances, the #GP fault may be preempted by another lower priority fault (e.g., Page Fault (#PF)). However, if the preempting lower priority faults are resolved by the operating system and the instruction retried, a #GP fault will occur.

Implication: When this erratum occurs, an MCE may be incorrectly signaled. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/ POP SS Instruction If It Is Followed by an Instruction That Signals a Floating Point Exception A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints until after execution of the following instruction. This is intended to allow the sequential execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having an invalid stack during interrupt handling. However, an enabled debug breakpoint or single step trap may be taken after MOV SS/POP SS if this instruction is followed by an instruction that signals a floating point exception rather than a MOV [r/e]SP, [r/e]BP instruction. This results in a debug exception being signaled on an unexpected instruction boundary since the MOV SS/POP SS and the following instruction should be executed atomically.
Implication: This can result in incorrect signaling of a debug exception and possibly a mismatched Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any exception. Intel has not observed this erratum with any commercially-available software or system. Workaround:As recommended in the IA32 Intel Architecture Software Developers Manual, the use of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure since the MOV [r/e]SP, [r/e]BP will not generate a floating point exception. Developers of debug tools should be aware of the potential incorrect debug event signaling created by this erratum. Status: BG22. Problem: For the steppings affected, see the Summary Tables of Changes. IA32_MPERF Counter Stops Counting during On-Demand TM1 According to the Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A: System Programming Guide, the ratio of IA32_MPERF (MSR E7H) to IA32_APERF (MSR E8H) should reflect actual performance while Intel TM1 or ondemand throttling is activated. Due to this erratum, IA32_MPERF MSR stops counting while Intel TM1 or on-demand throttling is activated, and the ratio of the two will indicate higher processor performance than actual.
Implication: The incorrect ratio of IA32_APERF/IA32_MPERF can mislead software P-state (performance state) management algorithms under the conditions described above. It is possible for the Operating System to observe higher processor utilization than actual, which could lead the OS into raising the P-state. During Intel TM1 activation, the OS Pstate request is irrelevant and while on-demand throttling is enabled, it is expected that the OS will not be changing the P-state. This erratum should result in no practical implication to software. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG42. Problem:

Performance Monitor Counters May Count Incorrectly Under certain circumstances, a general purpose performance counter, IA32_PMC0-4 (C1H - C4H), may count at core frequency or not count at all instead of counting the programmed event.
Implication: The Performance Monitor Counter IA32_PMCx may not properly count the programmed event. Due to the requirements of the workaround there may be an interruption in the counting of a previously programmed event during the programming of a new event. Workaround:Before programming the performance event select registers, IA32_PERFEVTSELx MSR (186H - 189H), the internal monitoring hardware must be cleared. This is accomplished by first disabling, saving valid events and clearing from the select registers, then programming three event values 0x4300D2, 0x4300B1 and 0x4300B5 into the IA32_PERFEVTSELx MSRs, and finally continuing with new event programming and restoring previous programming if necessary. Each performance counter, IA32_PMCx, must have its corresponding IA32_PREFEVTSELx MSR programmed with at least one of the event values and must be enabled in IA32_PERF_GLOBAL_CTRL MSR (38FH) bits [3:0]. All three values must be written to either the same or different IA32_PERFEVTSELx MSRs before programming the performance counters. Note that the performance counter will not increment when its IA32_PERFEVTSELx MSR has a value of 0x4300D2, 0x4300B1 or 0x4300B5 because those values have a zero UMASK field (bits [15:8]). Status: BG43. Problem: For the steppings affected, see the Summary Tables of Changes. Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT Stores to Local DRAM Correctly When a IA32_PERFEVTSELx MSR is programmed to count the Offcore_response_0 event (Event:B7H), selections in the OFFCORE_RSP_0 MSR (1A6H) determine what is counted. The following two selections do not provide accurate counts when counting NT (Non-Temporal) Stores:
OFFCORE_RSP_0 MSR bit [14] is set to 1 (LOCAL_DRAM) and bit [7] is set to 1
(OTHER): NT Stores to Local DRAM are not counted when they should have been.
OFFCORE_RSP_0 MSR bit [9] is set to (OTHER_CORE_HIT_SNOOP) and bit [7] is
set to 1 (OTHER): NT Stores to Local DRAM are counted when they should not have been. Implication: The counter for the Offcore_response_0 event may be incorrect for NT stores. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Implication: Software may not operate properly if it relies on the processor to deliver page faults when reserved bits are set in paging-structure entries. Workaround:Software should not set Bit 7 in any PML4E or PDPTE that has Present Bit (Bit 0) set to 1. Status: BG49. Problem: For the steppings affected, see the Summary Tables of Changes. BIST Results May Be Additionally Reported after a GETSEC[WAKEUP] or INITSIPI Sequence BIST results should only be reported in EAX the first time a logical processor wakes up from the Wait-For-SIPI state. Due to this erratum, BIST results may be additionally reported after INIT-SIPI sequences and when waking up RLP's from the SENTER sleep state using the GETSEC[WAKEUP] command.
Implication: An INIT-SIPI sequence may show a non-zero value in EAX upon wakeup when a zero value is expected. RLP's waking up for the SENTER sleep state using the GETSEC[WAKEUP] command may show a different value in EAX upon wakeup than before going into the SENTER sleep state. Workaround:If necessary software may save the value in EAX prior to launching into the secure environment and restore upon wakeup and/or clear EAX after the INIT-SIPI sequence. Status: For the steppings affected, see the Summary Tables of Changes.

BG50. Problem:

Pending x87 FPU Exceptions (#MF) May Be Signaled Earlier Than Expected x87 instructions that trigger #MF normally service interrupts before the #MF. Due to this erratum, if an instruction that triggers #MF is executed while Enhanced Intel SpeedStep Technology transitions, Intel Turbo Boost Technology transitions, or Thermal Monitor events occur, the pending #MF may be signaled before pending interrupts are serviced.
Implication: Software may observe #MF being signaled before pending interrupts are serviced. Workaround:None identified. Status: BG51. Problem: For the steppings affected, see the Summary Tables of Changes. Multiple Performance Monitor Interrupts Are Possible on Overflow of IA32_FIXED_CTR2 When multiple performance counters are set to generate interrupts on an overflow and more than one counter overflows at the same time, only one interrupt should be generated. However, if one of the counters set to generate an interrupt on overflow is the IA32_FIXED_CTR2 (MSR 30BH) counter, multiple interrupts may be generated when the IA32_FIXED_CTR2 overflows at the same time as any of the other performance counters.
Implication: Multiple counter overflow interrupts may be unexpectedly generated. Workaround:None identified. Status: BG52. Problem: For the steppings affected, see the Summary Tables of Changes. LBRs May Not Be Initialized during Power-On Reset of the Processor If a second reset is initiated during the power-on processor reset cycle, the LBRs (Last Branch Records) may not be properly initialized.

Implication: Due to this erratum, debug software may not be able to rely on the LBRs out of poweron reset. Workaround:Ensure that the processor has completed its power-on reset cycle prior to initiating a second reset. Status: BG53. For the steppings affected, see the Summary Tables of Changes. LBR, BTM or BTS Records May Have Incorrect Branch from Information after an Enhanced Intel SpeedStep Technology Transition, T-states, C1E, or Adaptive Thermal Throttling The From address associated with the LBR (Last Branch Record), BTM (Branch Trace Message) or BTS (Branch Trace Store) may be incorrect for the first branch after an Enhanced Intel SpeedStep Technology transition, T-states, C1E (C1 Enhanced), or Adaptive Thermal Throttling.
Implication: When the LBRs, BTM or BTS are enabled, some records may have incorrect branch From addresses for the first branch after an Enhanced Intel SpeedStep Technology transition, T-states, C1E, or Adaptive Thermal Throttling. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG54. Problem:

DPRSLPVR Signal May Be Incorrectly Asserted on Transition between Low Power C-states On entry to or exit from package Deep Power Down Technology (code name C6 state) states, DPRSLPVR (Deeper Sleep Voltage Regulator) signal may be incorrectly asserted.
Implication: Due to this erratum, platform voltage regulator may shutdown Workaround:It is possible for the BIOS to contain a workaround for this erratum. Status: BG55. Problem: For the steppings affected, see the Summary Tables of Changes. Performance Monitoring Events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA May Not Count Events Correctly Performance Monitor Events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA should only increment the count when a load is blocked by a store. Due to this erratum, the count will be incremented whenever a load hits a store, whether it is blocked or can forward. In addition this event does not count for specific threads correctly.
Implication: If Intel Hyper-Threading Technology is disabled, the Performance Monitor events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA may indicate a higher occurrence of loads blocked by stores than have actually occurred. If Intel Hyper-Threading Technology is enabled, the counts of loads blocked by stores may be unpredictable and they could be higher or lower than the correct count. Workaround:None identified. Status: BG56. Problem: For the steppings affected, see the Summary Tables of Changes. Storage of PEBS Record Delayed Following Execution of MOV SS or STI When a performance monitoring counter is configured for PEBS (Precise Event Based Sampling), overflow of the counter results in storage of a PEBS record in the PEBS buffer. The information in the PEBS record represents the state of the next instruction to be executed following the counter overflow. Due to this erratum, if the counter overflow occurs after execution of either MOV SS or STI, storage of the PEBS record is delayed by one instruction.

Implication: The DTS temperature data (including temperatures read by Platform Environment Control Interface) may be reported lower than the actual temperature. Fan speed control or other system functions which are reliant on correct DTS temperature data may behave unpredictably Workaround:It is possible for the BIOS to contain a workaround for this erratum Status: For the steppings affected, see the Summary Tables of Changes
USB Devices May Not Function Properly With Integrated Graphics While Running Targeted Stress Graphics Workloads With Non-Matching Memory Configurations When the integrated graphics engine continuously generates a large stream of writes to system memory, and Intel Flex Memory Technology is enabled, with a different amount of memory in each channel, the memory arbiter may temporarily stop servicing other device-initiated traffic. In some cases this can cause certain USB devices, such as keyboard and mouse, to become unresponsive. Intel has only observed this erratum with targeted stress content. This erratum is not seen when the platform is configured with single channel or dual channel symmetric memory and is not dependent on the memory frequency.
Implication: Due to this erratum, certain USB devices may become unresponsive. Workaround:None identified. Status: BG85. Problem: For the steppings affected, see the Summary Tables of Changes. Intel Turbo Boost Technology Ratio Changes May Cause Unpredictable System Behavior When Intel Turbo Boost Technology is enabled as determined by the TURBO_MODE_DISABLE bit being 0 in the IA32_MISC_ENABLES MSR (1A0H), the process of locking to new ratio may cause the processor to run with incorrect ratio settings. The result of this erratum may be unpredictable system behavior.
Implication: Due to this erratum, unpredictable system behavior may be observed Workaround:It is possible for the BIOS to contain a workaround for this erratum. Status: BG86. For the steppings affected, see the Summary Tables of Changes. PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred Under very specific timing conditions, if software tries to disable a PerfMon counter through MSR IA32_PERF_GLOBAL_CTRL (0x38F) or through the per-counter eventselect (e.g. MSR 0x186) and the counter reached its overflow state very close to that time, then due to this erratum the overflow status indication in MSR IA32_PERF_GLOBAL_STAT (0x38E) may be left set with no way for software to clear it.