INTELLIVISION MASTER COMPONENT OWNER'S MANUAL
Intellivision Master Component Owner's Manual

CONTENTS

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How to Connect the Antenna Switchbox Set Up Your Master Component How to Insert the Cartridge How to Use the Master Component The Intermission Code and the Automatic Blank Screen How to Return Your Television Set to Regular Programming The Hand Controllers How to Take Care of Your Master Component Troubleshooting Checklist Important Safety Instructions
FOR COLOR TV VIEWING ONLY OPEN THE CARTON AND YOU WILL FIND THESE PARTS:
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The INTELLIVISION II also includes an external 16.2 VAC power supply that plugs into an electrical outlet. A cable from the power supply plugs into a jack on the back of the console. The Intellivision II also has a single ON/OFF/RESET button and features detachable hand controllers. The SEARS TELE-GAMES SUPER VIDEO ARCADE version of the Intellivision features detachable hand controllers. Warning: This equipment has been certified to comply with the limits for a Class B computing device pursuant to Subpart J of Part 15 of FCC rules. Only peripherals (computer input/output devices, terminals, printers, etc.) certified to comply with the Class B limits
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may be attached to this computer. Operation with non-certified peripherals is likely to result in interference to radio and TV reception.
How to Connect the Antenna Switchbox
The Antenna Switch Box enables you to use your television set for either regular television programming or with Intellivision. Once the Antenna Switch Box is installed, a flick of the switch allows you to make your choice. CONNECTING THE SWITCH BOX IS EASY. JUST FOLLOW THESE SIMPLE STEPS: THE ONLY TOOL YOU WILL NEED IS A FLATHEAD SCREWDRIVER. Disconnect the VHF twin lead antenna wire (if there is one) from your television set and connect it to the Antenna Switch Box. Connect the twin lead wire from the Switch Box to the VHF screw terminals of your television set. IMPORTANT! If you disregard any of the following rules you may cause interference to nearby television sets.
Never attach loose wires to your antenna terminals when you are using the Master Component. The Antenna Switch Box comes with its own twin lead wire. Never substitute a longer twin lead wire from the Switch Box to your television set. Do not attach the twin lead wire from the Switch Box to any television antenna or cable-TV outlet.
WHERE FLAT "TWIN LEAD" TYPE OF ANTENNA WIRE IS USED
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FOR TV INSTALLATIONS WHERE ROUND "COAX" TYPE OF ANTENNA WIRE IS USED
NOTE: FOLLOW THE DIRECTIONS IN YOUR TV OWNERS MANUAL OR ON THE BACK OF YOUR SET FOR CHOOSING BETWEEN THE ALTERNATE "COAX" VHF TERMINAL AND THE FLAT "TWIN LEAD" VHF SCREW TERMINALS. YOU MUST SELECT THE FLAT "TWIN LEAD" VHF SCREW TERMINALS WHEN USING THE SWITCH BOX. IF YOUR TV DOES NOT HAVE
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FLAT "TWIN LEAD" VHF SCREW TERMINALS, USE "CABLE READY" HOOK-UP BELOW. CONNECTION TO A "CABLE-READY" TELEVISION
NOTE FOR THE NEW MILLENNIUM: RADIO SHACK SELLS A CABLE-READY SWITCHBOX (Cat. #15-1268) IN THEIR STORES AND ON-LINE HERE.
Set Up Your Master Component
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1. Connect the Switch Box cable to the Switch Box by plugging it into socket marked GAME CORD. Plug other end of cable into the Master Component socket in the rear of the Master Component on the right hand side. It makes no difference which end goes where; cable is symmetrical. Your Switch Box is equipped with an adhesive backing for installation on the back of your TV set. Simply peel off thin paper layer to expose adhesive surface and place firmly on desired mounting location. 2. Turn the Master Component over, face down, and see switch labeled "CH 3-CH 4." (On an INTELLIVISION II, this switch is on the back of the console.) If Channel 3 is a normal television station channel or cable channel in your area and Channel 4 is not, then move the switch to Channel 4. If Channel 4 is a normal television station channel or cable channel in your area and Channel 3 is not, move the switch to Channel 3. If both Channels 3 and 4 are normal television station channels or cable channels in your area, move the switch to the channel with the weaker reception. (If you receive Channel 3 better than Channel 4, move switch to Channel 4 and vice versa.) 3. Plug the power cord of the Master Component into a wall outlet. (For the INTELLIVISION II, plug the power supply into a wall outlet and connect the cord from the power supply to input jack on back of console.) 4. Set the Antenna Switch Box at GAME. 5. Turn on your television set. 6. Turn your television set to either Channel 3 or 4, depending on where you set the Master Component switch in Step 2. If Master Component switch is set on CH 3, turn TV set to Channel 3. If Master Component switch is set on CH 4, turn TV set to Channel 4.

How to Insert the Cartridge
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INSERTING THE CARTRIDGE IS SIMPLE. JUST FOLLOW THESE DIRECTIONS: 1. Hold the cartridge so that the name of the game can be read right side up. 2. Insert the cartridge into the slot on the right side of the Master Component. Insert the cartridge firmly until it is engaged, but do not force it. To remove the cartridge, simply pull it straight out of the slot. The Master Component should be turned to OFF when the System is not in use.
How to Use the Master Component
1. Turn on your television set and slide the Master Component ON-OFF switch to ON. (On INTELLIVISION II, press ON/OFF/RESET button.) 2. Cartridge may be inserted prior to turning on TV set and Master Component. If not, insert the cartridge. The first thing you will see is a copyright notice and game title (e.g., Baseball cartridge will show game, title and date of copyright). NOTE: If no playfield appears on your television screen, or if a non-rational sequence of information appears on the screen, check to be sure that the cartridge is inserted properly, that the power is on and that all connections are properly made. If everything is correct, merely push the RESET button on top of Master Component. This will remedy the situation. What has happened is that the game program has been picked up at the wrong point. Pushing the RESET button gets the computer started at the beginning. 3. Adjust fine tuning control on Channel 3 or Channel 4 of television. If it is not normally used, it is likely to be badly out of adjustment. 4. Adjust the television VHF fine tuning control to best picture and sound. If your set has automatic fine tuning you should operate your TV with automatic fine tune on. If difficulty in fine tuning is encountered, try tuning in the game channel with the automatic tuning feature turned off. Adjust volume, picture and color controls to a pleasing level. A gradual discoloring of white areas in the game playfield indicates that the brightness or contrast controls have been set too high. 5. Follow the instruction book for individual cartridge you are using. 6. If at any point in the game you wish to start over, simply press the RESET button.
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The Intermission Code and the Automatic Blank Screen

If for any reason you wish to interrupt your game, use the Intermission Code on your Hand Controller. Merely depress keys 1 and 9 simultaneously on either one of the Hand Controllers. This will cause the television screen to go blank and will freeze the game at the point you left it. To resume the game, just push any key on either Hand Controller and the game will begin again where you left off. If you leave the game without using the Intermission Code, the Master Component will automatically turn the screen blank after five minutes. To turn the screen on again, you simply press any key on either Hand Controller. The purpose of this unique feature is to eliminate the possibility of a permanent playfield image being imprinted on your television screen.
How to Return Your Television Set to Regular Programming
1. Slide the POWER switch on the Master Component to OFF. (On INTELLIVISION II, press down and hold ON/OFF/RESET button for 2 seconds.) 2. Slide the switch on the Antenna Switch Box from GAME to TV.

The Hand Controllers

The Master Component contains two Hand Controllers which are permanently attached with coil cables. (On INTELLIVISION II and SEARS TELE-GAMES SUPER VIDEO ARCADE consoles, hand controllers are detachable. Make sure controllers are securely plugged in before playing.) Since the Hand Controllers are crucial to any game you play, hold the Hand Controller in your hand before you begin play, just to get the feel of it.
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You will notice that there are 12 keys on the keypad. These are used for feeding data into the computer. With each cartridge, there are two overlays which fit over the keypads of the two Hand Controllers. These overlays are keyed to the particular game being played and determine how the keys on the keypad relate to the cartridge. Slip the overlay under the keypad frame as shown. The lip at the top of the controller will prevent overlay from being pushed back out during normal game play. There are two action buttons on each side of the Hand Controller. The top buttons, one on each side, perform the same function for the convenience of either rightor left-handed players. The bottom buttons perform varying functions. The functions of all the buttons depend on the cartridge being used and are different for each cartridge overlay. The disc at the base of the Hand Controller is a directional control for those cartridges in which direction is a factor. There are 16 directions on the disc. Direction of disc corresponds to direction on television screen. UP on the disc (toward the keypad) is UP on the screen, etc. For further instructions, refer to

your cartridge instructions.
To operate the directional disc, press your finger on the outer edge and slide your finger around the edge to change direction of object you are moving. You have the ability to move the object in any direction you wish. To stop motion, simply stop pressing disc. You must be pressing on the disc in some direction for motion to take place. The keypad buttons and directional disc cannot be operated simultaneously. However, the action buttons and directional disc can be. See cartridge instructions. When returning the Hand Controller to the Master Component, coil the cable beneath it in the cradle. To avoid permanently overstretching the coiled cables, they should not be pulled out to their extreme length. IMPORTANT: When playing your INTELLIVISION game, make sure BOTH hand-held controllers are lifted out of their slots in the Master Component. Remove BOTH hand controllers even though you are using only one for the game.
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How to Take Care of Your Master Component
The Intellivision Master Component will bring you many years of fun and excitement if you follow a few simple rules to keep it in good condition. Read the following points carefully. They will help you get the maximum use from your Master Component. Do not force the cartridge into the component slot. Intellivision game cartridges are designed to inhibit hand contact with their electronic circuitry. However, care should be taken not to get the fingers into the open end of the cartridge. Static electricity, such as the kind you get from a rug, could damage the sensitive electronic components in the cartridge. Turn the Master Component OFF when not in use. If the Master Component is not to be used for a length of time the Switch Box Cable may be unplugged and stored behind TV. Handle the Master Component carefully. Do not drop the cartridges, component or Hand Controllers. Do not lift the Master Component or the Hand Controllers by the wires, as serious damage can result. Avoid exposing the cartridges, Master Component or Hand Controllers to excessive heat. Do not set large objects which would block ventilation openings on top of Master Component housing. Do not spill liquids onto the cartridges, Master Component or Hand Controllers. Clean the exterior of your Master Component with a soft, slightly dampened cloth, BUT ONLY AFTER YOU HAVE TURNED THE POWER SWITCH TO "OFF" AND DISCONNECTED THE POWER CORD FROM THE 120 VOLT WALL OUTLET. NOTE: It is normal for the top of Master Component to become warm during operation. The lower left corner of the Master Component will be slightly warm even when the Master Component On-Off switch is in the OFF position.

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Troubleshooting Checklist

SCREEN IS BLANK

See "The Intermission Code and the Automatic Blank Screen," above. Press any key on either Hand Controller keypad.

NO TELEVISION PROGRAMS

Twin lead wire from Switch Box not properly attached to VHF terminals on television set. Switch Box set at GAME. Change to TV. Antenna wire not properly attached to Switch Box.
BUZZING SOUND OR SOUND DISTORTION
Television set not properly tuned. Adjust controls to make sound and picture clear. Broadcast interference on Channel 3, 4 or cable TV from an especially strong television station in your area. Disconnect the TV-VHF antenna wires from the Switch Box and continue playing, but you will have to reconnect again for TV viewing.

NO GAME SOUND EFFECTS

Volume control on television set turned down. Turn it up. TV not fine tuned properly.
NO PLAYFIELD IMAGE OR WHITE-GREY SCREEN
Cartridge not properly inserted in slot. Check all connections, make sure power plug is plugged into outlet and that outlet has not been turned off by wall switch. Make sure you are tuned to correct channel, either Channel 3 or 4. Antenna Switch Box set at TV. Change to GAME. Cable not properly plugged into Switch Box.
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INTELLIVISION MASTER COMPONENT OWNER'S MANUAL r r
Master Component power switch not turned on. Twin lead wire from Switch Box not properly attached to VHF terminals on television set.
EITHER SIDE OF PLAYFIELD NOT VISIBLE ON SCREEN
Adjust the horizontal hold control on your television set.
PLAYFIELD INDISTINCT, RESEMBLING A WEAK SIGNAL
Television set not properly adjusted. Adjust fine tuning, brightness and contrast controls. Loose connections at antenna terminals of television set or Switch Box. Switch Box Cable not plugged in fully.

PLAYFIELD BLURRED OR WOBBLY OR NO COLOR
Television set not properly fine tuned. Adjust television fine tuning, color or tint controls. Broadcasting on Channel 3, 4 or cable TV by an especially strong television station in your area. Disconnect TV-VHF antenna wires from the Switch Box. Reconnect to watch regular TV.
NOTE: If Master Component malfunctions after all troubleshooting steps have been taken, disconnect and determine if television set is functioning properly. If it is, Master Component may require repair.
Important Safety Instructions
READ INSTRUCTIONS All safety and operating instructions should be read before operating this appliance. HEED THE WARNINGS All warnings on this appliance and in the operating instructions should be adhered to.
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1. FOLLOW INSTRUCTIONS

All operating and use instructions should be followed.

2. CLEANING

Unplug the unit from the wall outlet before cleaning. Do not use liquid cleaners or aerosol cleaners. Use a damp cloth for cleaning.

3. ATTACHMENTS

Do not use attachments not recommended by Mattel Electronics or INTV Corporation as they may cause hazards.

4. VENTILATION

Slots and openings in the cabinet are provided for ventilation to protect it from overheating, and to ensure reliable operation of this product. These openings must not be blocked by placing the product on a bed, sofa, rug or other similar surface. Never place the product near or over a radiator or a heat register. Do not power on the unit in a built-in installation unless proper ventilation is provided.

5. WATER AND MOISTURE

Do not use near water.

6. POWER SOURCES

Operate only from the type of power source indicated on the marking label. If you are not sure of the type of power in your home consult your appliance dealer or power company.

7. POWER CORD PROTECTION

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INTELLIVISION MASTER COMPONENT OWNER'S MANUAL q
Power supply cords should be routed so that they are not likely to be walked on or pinched, paying particular attention to the cords at plugs, convenience receptacles, and the point where they exit from the appliance.
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Intellivision Master Component Hardware

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Figures
Slightly Simplified Block Diagram
Intellivision I Schematic (from Sylvania Service Manual)
Note: This image is courtesy of Frank Palazzolo's 2bits website

Component Overview

Chips present in the Master Component (aside from misc discrete logic). These are taken in left-toright, top-to-bottom order from the Intellivision schematics. Part Description Number CP-1610 CPU RA-39600 RO-39504 Notes
This is the main CPU. Contains 352 words of 16-bit memory. Also contains a second bus for interfacing to the STIC and its memory bus. The System RAM 16-bit System RAM includes a special 20-word FIFO for shifting characters out to the STIC, and logic for interfacing the STIC and CPU to each other. One-half of EXEC The EXEC ROM is stored in two 2Kx10-bit ROMs. This is one of ROM (Intellivision them. On the Intellivision 2, these two ROMs are combined into a 1 only) single ROM. This chip generates the display signals from the card information Standard Television stored in System RAM, and the graphics patterns stored in the
http://spatula-city.org/~im14u2c/intv/tech/master.html

11/21/2009

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Graphics ROM and Graphics RAM. It does not generate NTSC directly; rather it drives the "Color Processor" chip to generate the NTSC line levels. This 2048 x 8-bit ROM stores the built-in graphics for the RO-3Intellivision. The ROM provides special control signals for controlling Graphics ROM 9503 the graphics RAM. This includes address decode, read strobe and write strobe signals. These two RAMs combine together to provide 512 bytes of two GTE programmable graphics patterns for games. They are controlled by Graphics RAM 3539 special hardware in the Graphics ROM which performs a decode of the STIC's memory bus. This ROM provides the other half of the EXEC. It also provides One-half of EXEC RO-3address and bus signal decoding for the 8-bit scratchpad RAM and the ROM (Intellivision 9502 Programmable Sound Generator. On the Intellivision 2, this ROM is 1 only). combined with the RO-3-9504 (above) into a single 4.25K ROM. This provides 240 usable words of scratchpad RAM. In order to GTE8-bit Scratchpad simplify the address decoding logic, the upper 16 bytes of this RAM's 3539 RAM address space have been replaced with the Programmable Sound Generator's address space instead. This device takes the pixel-rate 5-bit input from the STIC and converts it into an NTSC rate signal. It outputs four I/Q phases for AY-3Color Processor every STIC pixel (eg. +I, +Q, -I, -Q). The lower 4 bits specify one of 8915 Chip the Inty's familiar 16 colors. The 5th bit is used to specify other NTSC signal states such as blanking, colorburst, etc. This is the sound chip. It provides 3 tone voices and one noise channel AY-3Programmable that can be mixed into the tone channels. It also provides two 8-bit 8914 Sound Generator bidirectional ports which are used for the Intellivision's controller pads.

Interface Circuit

System Architecture
The Intellivision Master Component is built around two main data busses, the CPU Address/Data bus and the STIC Address/Data bus. Both busses are time-multiplexed between address and data, and both have a number of specialized control signals associated with them.
System Architecture :: The CPU Bus
The CPU Address/Data bus has 16 Address/Data Lines named DB0 through DB15, and three control lines named BDIR, BC2, and BC1. (Additionally, the active low signals ~BUSRQ and ~BUSAK are available for Direct Memory Access requests. These are discussed later.) The CPU Bus originates at the CP-1600 CPU, and is directly connected to the 16-bit System RAM, 8-bit Scratchpad RAM, the PSG, the STIC, and the various program ROMs in the system. It does not connect directly to the GRAM or GROM, as these are controlled via the STIC. (Communication between the STIC bus and the CPU bus is described later.)

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Because the CPU Bus is time-multiplexed between Address and Data values, it relies on external devices to latch addresses during one bus phase before performing the access in a later bus phase. The value on the BDIR/BC2/BC1 control lines designates the current phase for the CPU bus. As there are 3 control lines, there are 8 bus phases defined. These are described in the following table: General Instruments Bus Protocol

BDIR BC2 BC1 Mnemonic

Description During this stage, no device is active on the bus. DB0 through DB15 are allowed to float, with their previous No ACTion driven value fading away during this phase. This bus phase is issued by the CPU during a Direct Addressing Mode instruction. Prior to this phase, an address will have been latched in a device by a prior BAR or ADAR bus phase. Then, during this phase, the currently Address Data selected device responds with its data on the bus, and at to Address the end of this phase, all devices should latch this address Register as the address for the next memory access (DTB, DW, or DWS phases). The CPU asserts nothing during this phase -rather, it expects the currently addressed device to inform the rest of the machine of the address for the next access. This bus phase is entered during interrupt processing, after the current program counter has been written to the stack. It's also entered into on the first cycle after coming out of Interrupt RESET. During this phase, an external device should Address to Bus assert the address of the Interrupt or RESET vector as appropriate. The CPU then moves this address into the program counter and resumes execution. This phase is entered during a read cycle. During this phase, the currently addressed device should assert its data Data To Bus on the bus. The CPU then reads this data. During this phase, the CPU asserts the address for the Bus to Address current memory access. All devices on the bus are expected to latch this address and perform address Register decoding at this time. Data Write The DW and DWS bus phases initiate a write cycle. They always occur together on adjacent cycles, with data remaining stable on the bus across the transition from DW to DWS. During these phases, the data being written is available for external memories to latch. The CP-1600 allows two full CPU cycles for external RAM to latch the data. The CPU enters this bus phase on the first cycle of interrupt processing. During the phase, the CPU places the current stack pointer value on the bus as it prepares to "push" the current program counter on the stack. Devices are expected to treat INTAK similarly to a BAR bus phase. Indeed, on the Intellivision Master Component, only the

Data Write Strobe

INTerrupt

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AcKnowledge 16-bit System RAM sees the INTAK bus phase. It uses this bus phase to trigger a special bus-copy mode as well as for latching the current address. For all other devices in the system, INTAK is remapped to BAR by some discrete logic, and so is processed as a normal addressing cycle elsewhere. While the table is well and good as a reference, it would be useful to illustrate how these phases are used. Also, the CPU state-flow diagram is very useful for understanding how these bus phases work. The CP-1600's bus transactions typically last between 4 and 7 CPU cycles. Half of these cycles are NACT cycles, inserted as spacing cycles between the activity cycles. As a general rule, there is a NACT cycle inserted after every cycle EXCEPT in two specific cases. The first is between DW and DWS, which always occur back-to-back. The second is during an indirect access after an SDBD instruction, where the CPU omits NACT states after both DTBs. The tables below illustrate the various bus transations, complete with a cycle-by-cycle description of the transaction. Instruction Fetch or Indirect/Immediate-Mode Data Read Cycle Phase Description CPU asserts address of the Instruction or Data to read. Devices should latch BAR 1 the address at this time and perform address decoding. The CPU deasserts the bus, and no other bus NACT 2 activity occurs during this cycle. The addressed device asserts its data on the bus. DTB The CPU then reads this data. The device deasserts the bus, and no other bus NACT activity occurs during this cycle. Indirect/Immediate-Mode Data Write Cycle Phase Description CPU asserts address of the Data to write. Devices should latch the address at this time and perform address decoding.
The CPU deasserts the bus, and no other bus activity occurs during this cycle.
The CPU asserts the data to be written. The addressed device can latch the data at this DW time, although it is not necessary yet, as the data is stable through the next phase. The CPU continues to assert the data to be DWS written. The addressed device can latch the data at this time if it hasn't already.
[Aside: Yes, the CP-1600 does have an "Immediate Mode Write", where it writes the contents of a register to an immediate operand. The reason for this is that "Immediate Mode" is really "Indirect Mode", using the program counter as the pointer register. Cute.]

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Direct Addressing Mode Read Cycle Phase Description CPU asserts address of the Instruction or Data to read. Devices should latch BAR 1 the address at this time and perform address decoding. The CPU deasserts the bus, and no other bus NACT 2 activity occurs during this cycle. The addressed device asserts the data that is at the location addressed during BAR. This data is ADAR then latched as an address 3 by all devices for a subsequent DTB bus phase. The CPU remains off the bus during this cycle. The device deasserts the bus, and no other bus NACT 4 activity occurs during this cycle. The newly-addressed device (the one whose address was given during DTB ADAR) asserts its data on the bus. The CPU then reads this data. The device deasserts the bus, and no other bus NACT activity occurs during this cycle.
Direct Addressing Mode Write Cycle Phase Description CPU asserts address of the Data to write. Devices should latch the address at this time and perform address decoding.
The addressed device asserts the data that is at the location addressed during BAR. This data is then latched as an address by all ADAR devices for subsequent DW and DWS bus phase. The CPU remains off the bus during this cycle.
The device deasserts the bus, and no other bus activity occurs during this cycle.
The CPU asserts the data to be written. The newly-addressed device (the one whose address was given during ADAR) can latch DW the data at this time, although it is not necessary yet, as the data is stable through the next phase. The CPU continues to assert the data to be DWS written. The addressed device can latch the data at this time if it hasn't already.
Indirect/Immediate Addressing Mode Read with SDBD Cycle Phase Description Cycle Phase
Interrupt Processing Description The CPU asserts the current Stack Pointer address (the value in R6), and increments the stack pointer internally. Devices are

CPU asserts address of

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the lower byte of Data to read. Devices should latch the address at this time BAR and perform address decoding.
expected to latch this address and decode it internally. Also, devices are expected to take any special interrupt-acknowledgement INTAK steps at this time. (On the Intellivision, this bus phase is remapped to BAR for most devices. The only device that sees INTAK is the 16-bit System RAM.)

The CPU deasserts the bus, and no other bus NACT activity occurs during this cycle. The addressed device asserts its data on the bus. DTB The CPU then reads this data. The device deasserts the bus during the first quarter of this cycle, and the CPU asserts a new address for the upper byte BAR of Data during the latter half of this cycle. Notice that there is no NACT spacing cycle before this BAR! The CPU deasserts the bus, and no other bus NACT activity occurs during this cycle. The addressed device asserts its data on the bus. The CPU then reads this DTB data. As with cycle 3, there is no NACT spacing cycle after this cycle!
The CPU deasserts the bus, and no other bus activity occurs during this cycle. The CPU outputs the current program counter address. The device addressed during INTAK should latch the data either now or during the next cycle (DWS).
The CPU continues to assert the current program counter address. If the addressed DWS device hasn't done so already, it should latch the data now.
An external device asserts the new program counter address (the address of the interrupt service routine) on the bus. The CPU IAB latches this address and transfers it to the program counter. On the Intellivision, one of the EXEC ROMs handles the program counter address assertion. The device deasserts the bus, and no other NACT bus activity occurs during this cycle.
System Architecture :: The STIC Bus
The STIC bus is somewhat simpler than the CPU bus. The STIC bus originates at the STIC and extends to the 16-bit System RAM, the 8-bit Graphics ROM, and the 8-bit Graphics RAM. The bus itself is a 14bit bus which multiplexes address and data in a manner similar to the CP-1600. What's interesting about the STIC bus is that it's used directly by the STIC during active display and indirectly by the CPU during vertical retrace. This will be covered in greater detail in the next section. The STIC's bus protocol is an extreme subset of the CP-1600's. Rather than provide a 3-wire set of

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encoded bus controls, the STIC provides 3 decoded bus phase lines, BAR', DTB', and DWS'. Only one of these three lines is asserted at a time, to designate which bus phase the STIC is executing. (The NACT bus state exists when all three lines are de-asserted.) In addition to the bus control lines, the STIC provides three timing lines, SR1, SR2 and SR3 which are used to synchronize various events with respect to display time. Transactions by the STIC are initiated by cycling the BAR', DTB' and DWS' lines in approximately the same way that the CPU would do so. This is largely due to the fact that the STIC actually can act as intermediary for the CPU in some cases (as covered in the next section.) Nonetheless, there are some important differences:
There aren't as many NACT cycles introduced by the STIC as there are by the CPU. Rather, DTB' is asserted as soon as BAR' is deasserted. During a write cycle, DTB' is momentarily asserted after BAR' until the STIC figures out that it's performing a write cycle. DTB' is deasserted and the STIC goes back to the NACT state before finally asserting DWS for a write.

The STIC bus itself is largely boring. During active display, the STIC is grabbing bits of display data from the System RAM, GRAM and GROM. During vertical retrace, the STIC bus serves as an extension of the CPU bus. This leads us to the next section.
System Architecture :: Bridging the CPU and STIC busses
The System RAM is the key component which glues the STIC and CPU worlds together. Both the STIC and the CPU are bandwidth hogs, requiring unfettered access to large amounts of data. Yet they also need to communicate a great deal. The System RAM makes this possible by acting both as a bridge and as an isolator for the two busses. The System RAM itself has two busses -- a 16-bit data/address bus on the CPU side and a 14-bit data/address bus on the STIC side. The CPU side bus speaks normal GI bus protocol, using BC1, BC2 and BDIR control signals. The STIC side is much less flexible, serving alternately as a passthrough for the CPU bus in CPU-controlled mode, and as a state-machine-driven character output in STIC-controlled mode. Outside of active display time, the STIC and System RAM work together to open the STIC bus up to CPU accesses. Upon seeing an INTAK bus cycle, the System RAM enters the so-called CPU controlled mode. In this mode, the System RAM acts as a bidirectional buffer, copying the lower 14 bits of the CPU bus over to the STIC bus in most cases, or from the STIC bus back to the CPU bus during a read. This bridges the two data/address buses. It does not handle the control signals, however. During the CPU-controlled mode, the STIC performs bus decoding on behalf of the CPU bus, converting the 3-wire GI bus protocol into the decoded signals BAR', DTB' and DWS' mentioned previously. These signals are fed on behalf of the CPU to the GRAM and GROM, thereby allowing the CPU access during this time to all of the peripherals that are on the STIC bus, namely the GRAMs, the GROM, and the STIC itself. At the start of active display, the STIC issues a ~BUSRQ to the CPU, requesting access to the bus. (~BUSRQ is tied to the SR2 timing signal on the STIC.) The CPU responds after the first interruptible instruction by bringing ~BUSAK low. The System RAM switches to STIC-controlled mode upon seeing

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the first ~BUSAK high-to-low transition, thereby ending the bus-copying behavior of CPU-controlled mode. [Note that it is certainly possible that the CPU will not see this ~BUSRQ phase if it is executing too many non-interruptible instructions in a row. In that scenario, the System RAM will remain in bus-copy mode, although the STIC has stopped decoding the bus-control signals for the CPU. The result is that the CPU still cannot access the STIC bus. If the CPU continues to ignore ~BUSRQ during active display, the System RAM will remain in bus-copy mode and CPU will fight with the STIC over the bus. This is bad, as the System RAM and the STIC will both attempt to drive the STIC bus, leading to hardware fights and potential physical hardware failure. Not to mention that the display will be totally garbaged up.] In STIC controlled mode, the STIC bus side of the System RAM becomes a timing driven entity that is controlled through the SR2 and SR3 timing signals. While in STIC-controlled mode, the System RAM nearly completely isolates the CPU bus from the STIC bus, except when the STIC needs to access the System RAM. This is where ~BUSRQ and ~BUSAK come in to play. It only makes sense, then that the ~BUSAK high-to-low transition (which is essentially a slightly time-delayed SR2 transition) is what causes the System RAM to exit CPU-controlled mode and enter "buffer fill mode" for the STIC. While ~BUSRQ is active, the SR3 signal is pulsed 20 times to trigger 20 reads to the display memory to read the next row of cards. (The STIC asserts ~BUSRQ for this, because the System RAM is single-ported and can only be read by one device at a time.) This row's worth of values are read onto the STIC bus and into a separate 20 word buffer. Once the row is read into these buffer registers, ~BUSRQ is released and the CPU is allowed to resume calculation. The row buffer is then subsequently read up to 15 more times (again, by pulsing SR3) for each of the scan-lines of the display in order to generate the row of cards on the screen, without disrupting the CPU's progress at all. It's important to note: ~BUSRQ does steal cycles from the CPU during active display. Some measurements place this penalty at almost 10% during active display. Altogether, there are between 13 and 14 ~BUSRQ's per frame (depending on the setting of the vertical delay register), with each lasting for approximately 110 CPU cycles. A minimum of 60 CPU cycles are required to read the 20 cards from System RAM, based on experimental evidence, which means that a correct program should have no more than about 40 cycles of non-interruptible instructions in a row. The figure below illustrates what a typical frame time looks like. Timing Diagram Showing SR1 (~INTRM) and ~BUSRQ Timing

Using some simple timing that consist mostly of non-interruptible code, I've measured the following cycle counts for an NTSC Intellivision:

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NTSC Intellivision Timing Parameters Parameter NTSC Clock Rate STIC Scanlines per Frame Active Scanlines per Frame Actual Effective Frame Rate CP-1600 Clock Rate (NTSC/4) Display disabled: CPU Cycles per Frame CPU Cycles per Scanline CPU Cycles available in Bus Copy mode Measurement
3579545 Hz 262 scanlines 192 scanlines 59.92 Hz 894886.25 Hz Hz 14934 cycles
Display enabled, vertical delay == 0: ~13518 cycles Display enabled, vertical delay > 0: ~13572 cycles
57 cycles 3780 - 3790 cycles
Additionally, I've worked out (with Kyle Davis' help) the following formulas for describing when various events (eg. ~BUSRQ asserted) occur relative to the start of frame. All of these quantities are expressed in raw CPU cycles. NTSC Intellivision Timing Equations Event Switch from CPU-controlled to STIC-controlled Assert ~BUSRQ to fetch display row 0 through 11. Equation
3790 (approx) 3933 + 114*vertical_delay + 912*row_number 4043 + 114*vertical_delay +
De-assert ~BUSRQ after fetching display row 0 through 11. 912*row_number Assert ~BUSRQ to "fetch" extra row (occurs only if vertical_delay == 0). De-assert ~BUSRQ after extra "fetch" (occurs only if vertical_delay == 0). Assert ~INTRM (aka. SR1)

Interfacing

The Master Component interfaces to a variety of external devices, primarily through two sets of external links: the cartridge port and the hand controller ports. Game cartridges and most peripherals connect via the cartridge port, whereas the two hand controllers connect via the hand controller ports.
Interfacing :: The Cartridge Port
The Master Component's cartridge port consists of a single 44-pin 0.1" spacing edge-card connector. A number of essential bus signals are brought out on this connector. The following figures illustrate which of these signals corresponds to each of the various cartridge pins. The table afterwards lists what each signal does.

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Pin Mapping On Intellivision Cartridges
Pin Assignments Component Side (Top) Solder Side (Bottom) Description Name Pin Pin Name Description Ground. GND GND Ground. Character BLaNK CBLNK ~MSYNC Master SYNC. External Audio Input. AUDIO 6 External Video Input. VIDEO 8 Master CLocK. MCLK 10 Reset input. RESET 12 Timing signal from the STIC. SR??? 16 Intellivoice special purpose. ??? 18 GND 20 GND 22 Ground GND 24 GND 26 GND 28 BUS AcKnowledge. ~BUSAK 30 This is an input. This BC1 drives the 32 EXEC ROMs, the PSG, and the 8-bit BC1 RAMs. This is an input. This BC2 drives the 34 EXEC ROMs, the PSG, and the 8-bit BC2 RAMs. This is an input. This BDIR drives the EXEC ROMs, the PSG, and the 8-bit BDIR 36 RAMs. This is an output. This BDIR is usually looped back by the cartridge BDIR 38 on pin 36. This is an output. This BC2 is usually

Ext. Ext.

DB7 DB8 DB6 DB9 DB5 DB10 DB4 DB11 DB3 DB12 DB13 DB2 DB14
Bit 7 of the Address / Data Bus. Bit 8 of the Address / Data Bus. Bit 6 of the Address / Data Bus. Bit 9 of the Address / Data Bus. Bit 5 of the Address / Data Bus. Bit 10 of the Address / Data Bus. Bit 4 of the Address / Data Bus. Bit 11 of the Address / Data Bus. Bit 3 of the Address / Data Bus. Bit 12 of the Address / Data Bus. Bit 13 of the Address / Data Bus. Bit 2 of the Address / Data Bus. Bit 14 of the Address / Data Bus. Bit 1 of the Address / Data Bus.

31 DB1

33 DB0
Bit 0 of the Address / Data Bus.

35 DB15

Bit 15 of the Address / Data Bus. This is an output. This BDIR usually provides the current bus phase to the cartridge ROMs. This is an output. This BC2 usually

37 BDIR

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looped back by the cartridge on pin BC2 34. This is an output. This BC1 is usually looped back by the cartridge on pin BC1 32. Ground GND

39 BCBCVcc

provides the current bus phase to the cartridge ROMs. This is an output. This BC1 usually provides the current bus phase to the cartridge ROMs. +5v power.
The following meanings are assigned to the cartridge port signals:
Vcc -- +5v Power GND -- Ground RESET -- System Reset
Pulling this line low will send a short reset pulse to the STIC. This will result in ~MSYNC being brought low by the STIC, thereby resetting the machine.

~MSYNC -- Master Sync

This signal goes low for at least 10ms during Reset. It is generated by the STIC as soon as the STIC recognizes a low pulse on its RESET line.

MCLK -- Master Clock

This pin provides the 3.579545MHz master clock signal that drives the Master Component.
BC1, BC2, BDIR -- Bus Control
These are the bus control signals as described in the CPU sections above. The outputs on pins 38, 40, and 42 come directly from the INTAK remapping circuitry. Cartridges generally loop these signals back on pins 36, 34, and 32. The outputs on pins 37, 39, and 41 are also directly connected to the INTAK remapping circuitry, and are the signals that most Mattel cartridges use for determining the bus phaase.

DB0 thru DB15 -- Address/Data Bus
This is the 16-bit multiplexed address/data bus.
~BUSAK -- BUS AcKnowledge
This signal goes low when the CPU has relinquished the bus during a DMA access by the STIC. It appears possible that external devices can access the PSG, EXEC, and 8-bit RAM during the time ~BUSAK is low, but it's unclear whether this is the case. In all likelihood, it is not the case.
SR1 -- STIC Timing Signal
This signal is tied to the CPU's ~INTRM input, triggering an interrupt when the STIC goes into the

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vertical refresh phase.
CBLNK -- "Character BLaNK" / Horizontal Retrace
Used for genlocking the Keyboard Component's TMS9927 to the Master Component's AY8900 STIC.
EXT AUDIO -- External Audio Input
The Intellivoice and ECS's second Programmable Sound Generator provide audio input via this pin. I'd imagine if the Keyboard Component can generate Audio, it also provides it on this pin.
EXT VIDEO -- External Video Input
This was originally designed to accept the genlocked video from the Keyboard Component. The Intellivision II changed the circuit external video output slightly to accept the non-genlocked video from the System Changer. It also moved this to a different pin.
??? -- Intellivision special purpose
These pins are tied to ground on non-Intellivoice cartridges, and left open on Intellivoice-aware cartridges.