KD-SH99R

SERVICE MANUAL

CD RECEIVER

Detachable

ATT ANGLE EQ CD FM AM RD

SEL VOLUME

RM-RK100

Area Suffix E ------- Continental Europe EX ----- Central Europe

Contents

Safety precaution Preventing static electricity Disassembly method Adjustment method Flow unit reading TOC of CD/CD-R/CD-RW Maintenance of laser pickup Replacement of laser pickup Description of major ICs
COPYRIGHT 2001 VICTOR COMPANY OF JAPAN, LTD.
1- 2 1- 3 1- 4 1-15 1-18 1-20 1-20 1-21~45

No.49645 Jun. 2001

< Service mode >
The menu in the service mode can be switched with UP/DOWN. The menu selected by the SEL button input is executed. The ordinary mode
"UP" + "DOWN" + VR counterclockwise rotation.

DEL EEPROM CH CH ERR

EEPROM data all clear (changer is connected). CD changer error career call (changer is connected).

DELL CH ERR

CD changer EEPROM clear (EEPROM career)

RUNNING CD

CD running mode (Do not use in service).

RUNNING SH

Running mode of front panel (Do not use in service).

DEL DATA

CD ERROR MECHA ERR error career deletion.

CD ADJ R

Self adjustment value call (It is a display switch with VR).

MEKACON WR

Sub-microcomputer writing (Do not use in service).

TEMP DATA

Temperature data call.

VERSION

Microcomputer version confirmation. The display changes in the up/down key. The main microcomputer : SH99 J203 The Sub-microcomputer : SH99S 122 CD relation error career reading

< Error display >

Item DISC_ERROR_0 DISC_ERROR_1 DISC_ERROR_2 DISC_ERROR_3 DISC_ERROR_4 DISC_ERROR_5 EJECT_ERR Content Others FOCUS NG Self adjustment NG CLV NG TOC reading NG or MP3 FILE CHECK NG BLANK DISC

CD ERROR

MECHA ERR
Panel relation error career reading
<ERROR CODE of Panel mechanism>
Memory to EEPROM of 6 digits, 1st and 2nd digit are indicate the operation mode when occur the error, 3rd to 6th digit are indicate details of error. LCD indication time is use lower 2digits of details of error. This series is indicate ERR XX (XX is error code). <ex.> When details of error is 0A0001 , it is indicate ERR 01, details of error is 0E0031 , it is ERR 31. Switch is from this side sequentially PSW1, PSW2,..PSW6.
Details of error 1. Error of door open (fault of PSW1) (1) Time out by PSW1 not changed (2) PSW1 change during waiting 300ms after open position detected 2. Error of door close (fault of PSW6) (1) Time out by PSW6 not changed (2) PSW6 change during waiting 300ms after close position detected 3. Error of shift to DETACH position (fault of PSW5) (1) Time out by PSW5 not changed to open side (2) Shift to open side, pass the DETACH position then detect ANGLE1 (3) Time out by PSW5 not changed to close side (4) Shift to close side, pass the DETACH position then detect close position 4. Error of angle adjustment 4-1 Shift to ANGLE1 (fault of PSW4) (1) Time out by PSW4 not changed to shift for open side (2) Shift to open side, pass the ANGLE1 then detect ANGLE2 (3) Time out by PSW4 not changed to shift for close side (4) Shift to close side, pass the ANGLE1 then detect DETACH position 4-2 Shift to ANGLE2 (fault PSW3) (1) Time out by PSW3 not change to shift for open side (2) Shift to open side, pass the ANGLE2 then detect ANGLE3 (3) Time out by PSW3 not changed to shift for close side (4) Shift to close side, pass the ANGLE2 then detect ANGLE1 4-3 Shift to ANGLE3 (fault PSW2) (1) Time out by PSW2 not changed to shift for open side (2) Shift to open side, pass the ANGLE3 then detect OPEN position (3) Time out by PSW2 not changed for shift for close side (4) Shift to close side, pass the ANGLE3 then detect ANGLE2 5. PSW fault condition at initialize When all PSW is checked immediately after RESET, and the state of SWITCH which cannot be originally is detected, it is displayed as ERR 00.
Error code 0A0001 0A0002 0B0006 0B0007 0C0011 0C0012 0C0013 0C0014
0D0021 0D0022 0D0023 0D0024 0E0031 0E0032 0E0033 0E0034 0F0041 0F0042 0F0043 0F0044 000000

Description of major ICs

UPD784215AGC146(IC701):MAIN CPU

1.Pin layout

2.Block diagram
INTP2/NMI INTP0,INTP1 INTP3-INTP6 TI00 TI01 TO0 TI1 TO1 TI2 TO2
PROGRAMMABEL INTERRUPT CONTROLLER TIMER/COUNTER (16 BITS)
UART/IOE1 BAUD-RATE GENERATOR UART/IOE2 BAUD-RATE GENERATOR CLOCKED SERIAL INTERFACE
RxD1/SI1 TxD1/SO1 ASCK1/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SI0 SO0 SCK0 AD0-AD7 A0-A7 A8-A15

TIMER/COUNTER1 (8 BITS)

TIMER/COUNTER2 (8 BITS)

TI5/TO5

TIMER/COUNTER5 (8 BITS)

BUS I/F

A16-A19 RD WR WAIT ASTB

TI6/TO6

TIMER/COUNTER6 (8 BITS) TIMER/COUNTER7 (8 BITS)

78K/IV CPU CORE

ROM PORT 0 PORT 1 PORT 2 PORT 3

TI7/TO7

P00-P06 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P70-P72 P80-P87 P90-P95 P100-P103 P120-P127 P130,P131 RESET

TI8/TO8

TIMER/COUNTER8 (8 BITS)

WATCH TIMER

PORT 4 PORT 5

WATCHDOG TIMER

PORT 6 PORT 7
RTP0-RTP7 ANO0 ANO1 AV REF1 AV SS ANI0-ANI7 AV REF0 AV DD AV SS PCL

REAL-TIME OUTPUT PORT

PORT 8 PORT 9

D/A CONVERTER

PORT 10 PORT 12 PORT 13

A/D CONVERTER

CLOCK OUTPUT CONTROL BUZZER OUTPUT

SYSTEM CONTROL

X1 X2 XT1

XT2 VDD VSS TEST

UPD784215AGC146(1/2)

Pin No. 49 50

Symbol PREQ AMUTE
DIMMER-OUT ANT PEM VDD X2 X1 VSS XT2 XT1 RESET BUS-INT PS2 RDS-SCK RDS-DA REMOCON AVDD AVREF0 SD-ST MRC DATA KEY0 KEY1 TEMP LEVEL SQ S.METER AVSS INLOCK NC AVREF BUS-SI BUS-SO BUS-SCK (STAGE) LCD-DA LCD-CL LCD-CE BUZZER EPDAI EPDAD EPCLK BUS-I/O PM0 PM1
I/O O O O O O O O O I I I O I I I I I I I I I I I I I O O I O I/O I O O O O I O O O O O
Function Mechanism power supply ON/OFFdemand output("L":On demand) Audio output MUTE control signal output ("L" :MUTE ON) Non connected Non connected Non connected Non connected Unused output port Antenna remote output 5V connection Sub-clock 32.738MHz Sub-clock 32.738MHz GND connection Sub-clock 12.5MHz Sub-clock 12.5MHz Reset detection terminal Non connected J-BUS signal interrupt input POWER SAVE2 BACK UP synchronization. It is H input and stop mode. Unused input port RDS clock input RDS data input Remote control signal input 5V connction 5V connection Station detector, stereo signal input. It is H and broadcasting station havingBroadcasting station,L:stereo MRC DATA input Key input 0 Key input1 Temperature data input for contrast correction Level meter input S.QUALITY level input S.METER level input GND connection The LOCK detection output. At LOCK:H Unused output port 5V connection J-BUS data input J-BUS data output J-BUS clock I/O H:L:Initialization port Data output to LCD driver Clock output to LCD driver Chipenable output to LCD driver Buzzer output Communication data input of 12C Communication data input of 12C Communication data input of 12C The J-BUS I/O switch output. When outputting :H,When inputting :L Panel close side motor control signal output Panel opening side motor control signal output

UPD784215AGC146(2/2)

Pin No. 99 100

Symbol

DETACH VCR CONT PNL SW1 PNL SW2 PNL SW3 PNL SW4 PNL SW5 PNL SW6 AFCK SEEK/STOP S MUTE FM/AM PLL-CE PLL-DO PLL-CLK PLL-DI TEL-MUTE AMP KILL VSS DIMMER-IN PS1 POWER CD-ON MUTE W-LPF1 W-LPF2 W-MUTE VDD VOL-DA VOL-CLK CF-SEL PMKICK EMPH VOL-1 VOL-2 (J/R) BUCK CCE LSI RST TEST
I/O O O O I O I I I I I I O O O O O O O I I O I I O O O O O O O O O O O O O I I I O O O O O O O O I
Function Non connected Non connected Non connected The detach signal input. It is L of 200ms or more and operation mode. It is H and POWER SAVE. Signal output for VCR control Panel position detection switch one signal input. Panel position detection switch two signal input. Panel position detection switch three signal input. Panel position detection switch four signal input. Panel position detection switch five signal input. Panel position detection switch six signal input The Af check output. When you check AF:L. The auto seek stop switch output. At SEEK:H, STOP:L. Software mute output for CF switch noise. FM and the AM switch output. At FM:H,At AM:L CE output for IC control for PLL. Data output for IC control for PLL. Clock output for IC control for PLL. Data input for IC control for PLL. Telephone ,ute detection input. POWER-AMP, ON/OFF switch output. H:OFF GND connection Dimmer detection input. L:Dimmer ON At POWER SAVE of POWER SAVE1.ACC and synchronization:L. When operating :H. The POWER ON/OFF switch output. At the time of the POWER ON:H. The CD power supply control signal output. At CD:H. The mute output. At the time of the MUTE ON:L. Sub woofer cutoff frequency control output 1 Sub woofer cutoff frequency control output 2 The mute output for the sub woofer. At the time of the MUTE ON:H. 5V connection. Data output for IC control for electronic volume. Clock output for IC control electronic volume. Signal output for FM belt region filter switch. Signal output for panel motor kick The CD emphasis output. When turning.At On:H. Non connected Pulse which rotation volume pulse signal inputs, and becomes judgment of change actually. rotation volume pulse signal input H:J version and L:R version Non connected Non connected CDLSI reset signal output GND connection Non connected Non connected Non connected Non connected Non connected Panel SW1

(DISC SEL) SW1

UPD63711AGC(IC603):RF Servo amp

108 73

2.Pin function Pin No. 9 Symbol VSSO ZRASO ZCASO ZCAS1 VSSO ZOE ZUWE ZLWE VSSO I/O O I I I I O I I

UPD63711AGC(1/3)

RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 VDD0 VSS0 RA8 IO0 IO1 IO2 IO3 IO4 IO5 VSSO

O O O O O I O

Function It is GND of the logic circuit. It is RFOK signal output terminal. Reset signal input terminal. (Active row) Command/parameter identification signal input terminal A0=L:STB active=Address register set. A0=H:STB active= Parameter set. The data strove signal input terminal. It is signal to de the latch in LSI as for the cereal data. The clock signal input terminal to input and output the cereal data. Input data from terminal SI is taken by standing up about this signal, and the cereal data from the terminal SO is output with go down. The cereal data and the status signal are output. Cereal data input terminal. The crystal oscillation control terminal. Please input the reset signal before stopping the crystal oscillation. Moreover, the crystal oscillation is steady and input the reset signal, please when moves from the state of the crystal oscillation stop to the ordinary mode. XTALEN=L:ordinary mode XTALEN=H:Crystal oscillation stop. Positive power supply supply terminal to logic circuit. Positive power supply supply terminal to D/A converter. R-ch audio signal output terminal. It is D/A converter GND. The outside credit capacitor connection terminal for SCF regulator. It is D/A converter GND. L-ch audio signal output terminal. Positive power supply supply terminal to D/A converter. Output terminal of right channel voice data. PWM output. Left channel voice data audio output terminal. PWM output. Positive power supply supply terminal to crystal oscillation circuit. Crystal departure pendulum connection terminal (Output) Crystal departure pendulum connection terminal (Input) It is GND of the crystal oscillation circuit. Positive power supply supply terminal to logic circuit. The output terminal of priemphasis information in sub code Q. When the emphasis is added, high level is output. Polarity can be switched by the command. F6H LSB EP=0:Normal output EP=1:Reversing output. Flag output terminal which shows that data under output is composed by data which cannot be corrected.(active high) The cereal data input terminal to building DAC into. When DSP etc. are not connected with latter part, it should be short with the terminal DOUT. It is an output terminal of the cereal voice data. Cereal clock input terminal to building DAC into. The output voice data changes from DOUT by standing up about this clock. The system connected with latter part must take data by standing up about this signal. The output voice data changes from DOUT by standing up about this clock.The system connected with latter part must take data by standing up about this signal.

IO6 IO7 IO8 IO9

O I O I

UPD63711AGC(2/3)

Pin No. 43
Symbol IO11 IO12 IO13 VSSO VDD1 IO14 IO15 DREQ DRESP IOP7 IOP6

I/O I O O O O I O O O

IOP5 IOP4 IOP3 IOP2 IOP1 IOP0 HDBDIR DVDD PACK TSO TSI TSCK_B TSTB_B DGND TEST0 TEST1 ATEST AGND FD TD SD MD DACO FBAL TBAL TEVCA AVDD EFM ASY C3T RFI AGCO AGCI RFO
O O O O O I I I I O O O O O O O O O O I I O I O
Function LRCK signal input terminal to building DAC into. Signal which distinguishes left channel/right channel of voice data output from DOUT. Terminal (88.2kHz)(WDCK)of the output of the frequency signal twice defect detection output terminal(HOLD) LRCK HOLD/WDCK can be switched with the microcomputer. Terminal of output of data of Digital audio interface. It is GND of the logic circuit. Buffer ring output terminal of oscillation. The state of this terminal is output to Bit5 of the status output. Positive power supply supply terminal to logic circuit. It is EFM-synchronous detection signal.becomes high-level when the output of the synchronous pattern detection signal and the frame counter is corresponding by the EFM recovery part, and becomes a row level at the disagreement. Mirror output terminal. (MIRR).It is a frame synchronous signal of PLL system. The one that a basic frequency (44.1kHz)of the reading signal obtained in PLL system was divided makes almost equally to the synchronization(7.35kHz) of one frame. (WFCK)MIRR/WFCK can be switched with the microcomputer. the terminal for the monitor of the bit clock. When PLL is locked, the go down edge of the EFM signal and this signal locks. it is GND of the logic circuit. The output terminal which shows the C1 error correction result. Even go down of RFCK is fixed. It is an output terminal which shows the C2 error correction result. Even of RFCK is fixed. Positive power supply supply terminal to logic circuit. It is PACK synchronous signal shows the head of packing. It is a cereal output terminal of the CD-TEXT data. It is a serial input terminal of the CD-TEXT control parameter. Cereal clock input terminal of CD-TEXT. Terminal of input of parameter strove signal of CD-TEXT. It is GND of the logic circuit. It is a test terminal. Please connect with GND usually. It is a test terminal. Please make to the opening usually. It is GND of an analog circuit. Focus drive output terminal. Tracking drive output terminal. Thread drive output terminal. Spindle drive output terminal. It is DAC output terminal for the adjustment. A set value of CRAM7FH is output. It is DAC output terminal for the adjustment. A set value of CRAM7CH is output (built-in RF FE amplifier offeset). It is DAC output terminal for the adjustment. A set value of CRAM7DH is output. It is DAC output terminal for the adjustment. A set value of CRAM7EH is output (built-in RF TE amplifier offset). It is a positive power supply supply terminal to an analog circuit. EFM signal output terminal. It is a standard voltage input terminal of the EFM comparator. Capacitor connection terminal for 3T detection. RF signal input terminal for EFM data generation. RF signal output terminal after gain is adjusted. Input terminal of RF-AGC amplifier. Output terminal of RF saming amplifier.

UPD63711AGC(2/2)

Pin No. 100
Symbol EQ2 EQ1 RF AGND A C B D F E AVDD REFOUT FE FEO TE TEO TE2 TEC AGND PD LD PN AVDD
I/O I I I I I I I O I O I O O I I O I -
Function Equalizer part connection terminal of RF amplifier. Reversing input terminal of RF saming amplifier. It is GND of an analog circuit. Photo detector A input terminal. Photo detector B input terminal. Photo detector C input terminal. Photo detector D input terminal. Photo detector F input terminal. Photo detector E input terminal. Positive power supply supply terminal to analog circuit. reference potential output terminal. Focus make an error amplifier reversing input terminal. Focus Allah amplifier output terminal. Tracking make an error amplifier reversing input terminal. Tracking error amplifier output terminal. Terminal to which tracking error after amplifies is output. The tracking comparator input terminal. The tracking error signal which cuts the DC element is input. The tracking 0 crossing is detected by using this signal in LSI. it is GND of an analog circuit. It is a terminal of the input of the detection signal of PD for the LD output monitor. LD control current output terminal. It is a control polarity set value of the APC circuit. Positive power supply supply terminal to analog circuit.
TC74VHC157FT-X(IC803):DAC SW

1.Pin lauout

SELECT 1 1A 2 1B 3 1Y 4 2A 5 2B 6 2Y 7 GND 8 ASG B Y A B A B Y A

2.Pin function 10 9

Vcc ST 4A 4B 4Y 3A 3B 3Y ST H L L L L
INPUTS SELECT X L L H H A X L H X X B X X X L H OUTPUT L L H L H

X:Don't Care

UPD70F3033AC015(IC606):SUB CPU
2.Pin function Pin No. Symbol TSI TSCK JBSO JBSI JBCK EVDD EVSS TSTB XRESET MIRR AO SO SI SCK WSEN DSPRST SWAIT VPP SA4 SA5 SA6 STB DRVMUTE LOAD1 LOAD2 SA0 SA1 SA2 SA3 RESET XT1 XT2 I/O O O O I I/O O O I O I O O O O I O O O O O O O O O O O I I I O O O O O O O I I/O I/O I/O I/O

UPD70F3033AC015(1/2)

Function CD TEXT control parameter cereal output. CD TEXT control cereal clock output. JBUS cereal data output. JBUS cereal data input. Cereal clock I/O. 5V(power supply for port for I/O). GND(GND for port for I/O). CD TEXT parameter strobe signal output. LSI reset output. MIRR signal input(H:Speculer). Command:/parameter:H switch signal output. DSP cereal data input. DSP cereal data input. DSP cereal data clock output. Internal CD/DC operation of MP3 operation & beginning. DSP RESET:L. WAIT signal input from DECODER. FLASH writing power supply. DECODER address passing output. DECODER address passing output. DECODER address passing output. (Non connected) DSP cereal data latch output. Servo deriver MUTE control signal output(L:MUTE:ON) Loading drive. Loading drive. DECODER address passing output. DECODER address passing output. DECODER address passing output. DECODER address passing output. Microcomputer reset terminal(L:Reset) Sub-clock Sub-clock The main clock crystal oscillation machine. The main clock crystal oscillation machine(20MHz). 5V GND Internal system clock output(Non connecte) DECODER data writing. (Non connected) (Non connected) DECODER data reading. Address bus enable. JBUS I/O switch. Mechanism power supply ON:L. DECODER I/O data bus DECODER I/O data bus DECODER I/O data bus DECODER I/O data bus

IN/OUT

SOD SOI SOC PI18 XVDD XVSS SID SII SIC PI4 PI3 PI2
O O O IN/OUT Supply Supply I I I IN/OUT IN/OUT IN/OUT

MAS3507D-QG-G10(2/2)

Pin no. 44
Symbol PI1 P0 CLKO PUP WSEN ERDY AVDD CLKI AVSS
I/O IN/OUT IN/OUT O O I O Supply I Supply
Function Start-up 1) : SDO Select 32 bit mode / 16 bit I 2 S mode Operation : MPEG header bit 30(Emphasis) Start-up 1) : Select Multimedia mode / Broadcast mode Operation MPEG header bit 31 (Emphasis) Clock Output (normal 24.576 MHz) Power Up, i.e.Status of Voltage Supervision WS Enable : Enable DSP WSEN=0 : Valid clock input at CLKI WSEN=1 : Clock synthesizer PLL locked Supply for Analog Circuits Clock Input Ground Supply for Analog Circuits
Start-up configuration see Table 2.7.3. in (1)
BU4066BCFV-X (IC322) : Quad analog switch
1. Pin layout & Block diagram VDD 14 CCI/OO/IO/II/O3 8

1 I/O1

2 O/I1

3 O/I2

4 I/O2
KD-SH99R LC895199K-ND2(IC601):CD-ROM decoder
2.Pin function Pin No. Symbol VSSO ZRASO ZCASO ZCAS1 VSSO ZOE ZUWE ZLWE VSSO RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 VDD0 VSS0 RA8 IO0 IO1 IO2 IO3 IO4 IO5 VSSO IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 VSSO VDD1 IO14 IO15 DREQ DRESP IOP7 IOP6 IOP5 IOP4 IOP3 IOP2 IOP1 IOP0 HDBDIR Function

LC895199K-ND2(1/3)

RAS signal output terminal to buffer DRAM CAS signal output 0 terminal to buffer DRAM(0 is used usually) CAS signal output terminal 1 to buffer DRAM Buffer DRAM output enable Buffer DRAM upper write enable Buffer DRAM lower write enable Address signal output terminal to data buffer DRAM
5.0V Address signal output terminal to data buffer DRAM Data I/O terminal to data buffer DRAM. With built-in pull-up resistor
Data I/O terminal to data buffer DRAM. With built-in pull-up resistor
3.3V Data I/O terminal to data buffer DRAM.With buolt-in pull-up resistor

General-purpose I/O port

LC895199K-ND2(2/3)

Pin No. 109

Symbol TEST0 XTALCK XTAL VDD0 VSS0 MCK TEST1 DSDATA DLRCK DBCK C2PO SDATA BCK LRCK EXCK WFCK SBSO SCOR PLL1 PLL2 PLL3 VSS0 VDD1 ZRESET MCK3 CSCTRL ZRO ZWR ZCS SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 D0 D1 D2 VDD0 VSS0 D3 D4 D5 D6 D7 ZINTO ZINT1 ZSMAIT ZRSTCPU CSEL ZHRST ATPINSEL ZDASP ZCS3FX ZCS1FX DA2 VSS1 VDD1

Function The terminal TEST.Please connect with VSS X'tal oscillation circuit input terminal X'tal oscillation circuit output terminal 5.0V 1/1,2/2,STOP output terminal of XTALCK The terminal TEST. Please connet with VSS DAC output terminal Terminal for CD-DSP I/F

SUB-CODE I/O terminal

Relation connection of PLL terminal (It is analog VSS in version LC895199 with built-in PLL) 3.3V (It is analog VDD in version LC895199 with buikt-in PLL) LSI reset terminal 1/1, 1 /5, 2/5, 1/512, and STOP output terminal of XTALCK Active Lo and Hi selection terminal on MC(microcontroller) side CS Reading data of MC(microcontroller) signal input terminal Writing data of MC(microcontroller) signal input terminal Register chip selection signal input terminal from MC(microcontroller) MC(microcontroller) register selection signal terminal
MC(microcontroller) data signal terminal.With buit-in puul-up resistor. 5.0V MC(microcontroller) data signal terminal. With buit-in pull-up resistor.
Interrupt request signal output terminal to MC(microcontroller) WAIT signal to MC(microcontroller) Reset signal to CPU ATAPI control signal ATAPi data bus Terminal ATAPI arrangement select terminal. Connects with VDD0 ATAPI data bus

LC895199K-ND2(3/3)

Pin No. 144
Symbol DAO ZPDIAG DA1 ZIOCS16 HITRQ ZDMACK VSS1 IORDY ZDIOR ZDIOR DMARQ VSS1 DD15 DDO DD14 DD1 VDDO VSS1 DD13 DD2 DD12 DD3 VSS1 DD11 DD4 DD10 VSS1 VDD0 DD5 DD9 DD6 VSS1 DD8 DD7 VDD1

Function ATAPI data bus

ATAPI data bus
ATAPi data bus ATAPi control signal ATAPI control signal 5.0V ATAPI control signal

ATAPI control signal

5.0V ATAPI control signal
HA13164 (IC961) : Regulator
+B C1 100u VCC C2 0.1u ACC

MEMORY

ACC BATT.DET OUT
ANT OUT C3 0.1u EXT OUT C4 0.1u ANT CTRL

Surge Protector

COMPOUT

VDD OUT C7 0.1u

CD OUT C5 0.1u AUDIO OUT C6 10u

SW5VOUT

ILMOUT

C8 0.1u

ILM AJ UNIT R: C:F note1) TAB (header of IC) connected to GND
3.Pin function Pin No. 15 Symbol EXT ANT ACC VDD SW5V ACC5V ANT CTRL MEMORY BATT DET 9V CTRL CD8V AJ ILMI GND Function Output voltage is VCC-1 V when M or H level applied to CTRL pin. Output voltage is VCC-1 V when M or H level to CTRL pin and H level to ANT-CTRL. Connected to ACC. Regular 5.7V. Output voltage is 5V when M or H level applies to CTRL pin. Output for ACC detector. L:ANT output OFF , H:ANT output ON Connected to VCC. Low battery detect. Output voltage is 9V when M or H level applied to CTRL pin. L:BIAS OFF, M:BIAS ON, H:CD ON Output voltage is 8V when H level applied to CTRL pin. Adjustment pin for ILM output voltage. Output voltage is 10V when M or H level applies to CTRL pin. Connected to GND.

LC75878W (IC501) : LCD driver

1. Pin layout

100 ~ ~ ~ 50

COM1 COM8

75 ~ 51

S75/COM9 S74/COM10 S73

2. Block diagram

GENERAL PORT

COMMON DRIVER
SEGMENT DRIVER & LATCH

OSC VLCD

CLOCK GENERATOR

CONTROL REGISTER

CONTRAST ADJUSTER VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VDD VSS

SHIFT REGISTER

CCB INTERFACE

3. Pin function

No. 1~75 76~83 84~Symbol SEG1~SEG73 SEG74 SEG75 COM8~COM1 P1~P4 VDD VLCD VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VSS OSC LCD RESET CE CL DI I/O O O O O O O I I I I I/O I I I I Function Segment driver output pin. Segment driver output pin. Segment driver output pin. Common driver output pin. General-purpose output pin. Logic block power supply pin. LCD driver power supply pin. LCD driver bias 4/4 voltage (H-level) power pin. LCD driver bias 3/4 voltage (intermediate level) power pin. LCD driver bias 2/4 voltage (intermediate level) power pin. LCD driver bias 1/4 voltage (intermediate level) power pin. LCD driver bias 0/4 voltage (L-level) power pin. Power supply pin to connect to ground. Oscillator pin. Display off, general-purpose output port L fixed input pin. Chip enable Synchronization clock Transfer data
M61508FP-X (IC911) : E. volume
1. Pin layout & Block diagram

LOUDNESS

3BAND TONE CONTROL (BASS/MID/TREBLE)

VDO (Digital)

VCC (Anarog)

Soft select

Z E R O C RO S S D E T E C TO R

A B B A

Zero detect Select SW

TIMER DETECTOR

3BAND TONE CONTROL (BASS/MID/TREBLE) GND
2. Pin function Pin No. Symbol REF 1 DEFP INDEFN ININAINBINCINDDEFN OUTSEL OUTVOL INTONE OUTFADER INREAR OUTFRONT OUT15 NonFader OUT1 GND 16 DATA 17 VDDOUTVDDOUTCLOCK 20 VDD NonFader OUT2 FRONT OUTREAR OUTFADER INTONE OUTVOL INSEL OUTDEFN OUTINDINCINBINADEFN INDEFP INVCC 36
Function Grand for IC signal Differential motion amp. Positive terminal Differential motion amp. Negative terminal Input terminal of input selector switch channel 1 Input terminal of input selector switch channel 1 Input terminal of input selector switch channel 1 Input terminal of input selector switch channel 1 Differential output terminal (-) Input selector output terminal Volume 1 input terminal Tone output terminal Volume 2 input terminal Fader volume control (Rear) output terminal Fader volume control (Front) output terminal Non fader volume output terminal GND terminal Control data input terminal Test terminal Test terminal Clock input terminal for serial data transport Power supply terminal for digital Non fader volume control output terminal Fader volume (Front) output terminal Fader volume (Rear) output terminal Volume 2 input terminal Tone output terminal Volume 1 input terminal Input selector output terminal Differential output terminal (-) Input terminal of input selector switch channel 2 Input terminal of input selector switch channel 2 Input terminal of input selector switch channel 2 Input terminal of input selector switch channel 2 Differential motion amp negative input terminal Differential motion amp positive input terminal Power supply terminal

M63008FP-X (IC604) : 5ch Actuator driver

CH3IN OUT3 GND

VM3+ VBS2 VM3IN3+ Vm2 IN3N.C

SS,GND

39 VBS2
IN1+ IN1OUT1 VM1(+) VM1(-) VM2(+) VM2(-) OUT2 IN2-I IN2+ VREFO VREF REGB REG+

R R Vm1 Vm2

IN3IN3+ OUT3 CH3 IN VM3(+) VM3(-)

CH1 X5

Vrefm1

Vrefm2

CH3 X8

CH2 X5

VBS1 VBS1

HI :Sleep

CH4 X8
VM4(+) VM4(-) IN4IN4+ OUT4 VM5(+) vm5(-) IN5IN5+ OUT5
Low,Open VBS1 MUTE ON 1~4 CH 5CH

20 VBS2 2

VREF 1.25V

CH5 X8

E5 MUTE1 SS,GND MUTE2 GND (4PIN)
PCM1716E-X (IC802) : D/A converter

1. Pin layout 28 15

1 2. Block diagram
BCK LBCK DATA Serial Input I/F 8X Oversampling Digital Filter with ML/llS MC/DM1 MD/DM0 CS/WO MODE MUTE RST Function Controller Mode Control I/F SCK BPZ-Cont Crystal OSC

Vcc2R AGND2R

Vcc2L AGND2L
DAC Mult-level Delta-Sigma Modulator DAC

Low-pass Filter

VoutL EXTL

VoutR EXTR ZERO

Open drain Power Supply

Pin No.

Vcc1 AGND1

Vcc DGND

Symbol LRCK DATA BCK CLKO XTI XTO DGND VDD VDD2R AGND2R EXTR NC VOUTR AGND1 Vcc1 VOUTL NC EXTL AGND2L Vcc2L ZERO RST CS/IWO MODE MUTE MD/DM0 MC/DM1 ML/IIS
I/O I I I O I O O O O O O I I I I I I I
Function LRCK clock input Serial audio data input Bit clock input for serial audio data Buffered output of system clock Oscillator input / External clock input Oscillator output Digital ground Digital power +5V Analog power +5V Analog ground Rch common pin of analog output amp Non connection Rch analog voltage output of audio signal Analog ground Analog power +5V Lch analog voltage output of audio signal Non connection Lch common pin of analog output amp Analog ground Analog power +5V Zero data flag Reset Chip select / Input format selection Mode control select Mute control Mode control, Data / De-emphasis selection 1 Mode control, BCK / De-emphasis selection 2 Mode control, WDCK / Input format selection

SAA6579T-X(IC51):RDS

QUAL RDDA Vref MUX VODA VSSA CIN SCOUT 16 RDCL 15 TOSCO 13 OSCI 12 V0DD 11 VSSD 10 TEST 9 MODE

ANTIALIASING FILTER

57 kHz BANDPASS (8th ORDER)

RECONSTRUCTION FILTER

OSCILATOR AND DIVIDER

QUALITY BIT GENERATOR

S-81332HG-KC-X (IC804) : Regulator
1. Pin layout Vout GND Vin 2. Block diagram

VIN 3 VREF 1 VOUT

LB1830M-X(IC608):Regulator
1.Pin layout 2.Block diagram

OUT1 Vs OUT2

IN2 IN1 Vm Vm1 Vcont 6

5 Vcc OUT2 GND OUT1 Vs

Logic Predriver

IN1 IN2 Vm

Vcont Vref
TC74VHC126FT-X(IC605):Buffer

1.Pin layout 2.Function

1G 1 1A 2 1Y 3 2G 4 2A 5 2Y 6 GND 7
14 Vcc 13 4G 12 4A 11 4Y 10 3G 3A 3Y

INPUTS G A L H H X L H

OUTPUT Y Z L H X:Don't Care Z: High impedance
Electrical parts list (Main board)
Block No. 01 Remarks Area
BZ791 C 1 C 2 C 3 C 4 C 5 C 7 C 8 C 9 C 10 C 21 C 22 C 23 C 24 C 25 C 32 C 34 C 47 C 51 C 52 C 53 C 54 C 55 C 56 C 57 C 81 C 82 C 84 C 91 C 92 C 94 C 103 C 110 C 112 C 118 C 120 C 141 C 142 C 143 C 144 C 161 C 162 C 163 C 164 C 172 C 173 C 174 C 175 C 203 C 210 C 212 C 220 C 241 C 242 C 243 C 244 C 272 C 273 C 301 C 302 C 303 C 304 C 305

Parts number

QAN0009-001Z NCB31EK-473X QERF1CM-476Z NCB31HK-103X QERF1CM-476Z QERF1AM-107Z QERF1AM-227Z NCB31HK-103X QERF1AM-107Z NCB31EK-473X NCS31HJ-331X NCB31HK-103X NCB31HK-472X NCB31CK-104X QERF1HM-474Z QERF1HM-104Z NCB31CK-104X NCS31HJ-101X NDC31HJ-820X NDC31HJ-470X QERF0JM-476Z NCB31HK-103X NCS31HJ-561X NCB31EK-223X QERF1HM-225Z QERF1EM-475Z NCS31HJ-821X NCB31HK-153X QERF1EM-475Z NCS31HJ-821X NCB31HK-153X QERF1EM-475Z NBE21CM-105X NBE21CM-105X QCBB1HK-101Y NCB31CK-104X QERF1HM-105Z QERF1HM-105Z NCS31HJ-101X NCS31HJ-101X QERF1HM-105Z QERF1CM-226Z NCB21EK-473X QERF1HM-224Z QERF1CM-106Z QERF0JM-226Z NCB21EK-223X QERF0JM-476Z QERF1EM-475Z NBE21CM-105X NBE21CM-105X NCB31CK-104X QERF1HM-105Z QERF1HM-105Z NCS31HJ-101X NCS31HJ-101X QERF1CM-106Z QERF0JM-226Z QERF1EM-475Z QERF1EM-475Z QERF1CM-476Z NCB31HK-103X QERF1EM-475Z

Parts name

BUZZER C CAPACITOR E CAPACITOR C CAPACITOR E CAPACITOR E CAPACITOR E CAPACITOR C CAPACITOR E CAPACITOR C CAPACITOR C CAPACITOR C CAPACITOR C CAPACITOR C CAPACITOR E CAPACITOR E CAPACITOR C CAPACITOR C CAPACITOR C CAPACITOR C CAPACITOR E CAPACITOR C CAPACITOR C CAPACITOR C CAPACITOR E CAPACITOR E CAPACITOR C CAPACITOR C CAPACITOR E CAPACITOR C CAPACITOR C CAPACITOR E CAPACITOR C CAPACITOR C CAPACITOR C CAPACITOR C CAPACITOR E CAPACITOR E CAPACITOR C CAPACITOR C CAPACITOR E CAPACITOR E CAPACITOR C CAPACITOR E CAPACITOR E CAPACITOR E CAPACITOR C CAPACITOR E CAPACITOR E CAPACITOR C CAPACITOR C CAPACITOR C CAPACITOR E CAPACITOR E CAPACITOR C CAPACITOR C CAPACITOR E CAPACITOR E CAPACITOR E CAPACITOR E CAPACITOR E CAPACITOR C CAPACITOR E CAPACITOR

C 306 C 307

QERF1EM-475Z QERF1AM-107Z QERF1EM-475Z QERF1EM-475Z QERF1AM-107Z QERF1CM-106Z QERF1CM-476Z QERF1HM-225Z NCB31CK-823X NCB31HK-682X QERF1HM-225Z NCB31HK-123X NCB31HK-562X NCB31EK-273X NCB31EK-273X NCB31EK-333X NCB31EK-473X NCB31EK-473X QERF1HM-225Z QERF1HM-225Z QERF1EM-475Z QERF1EM-475Z QERF1CM-476Z NCB31HK-103X QERF1EM-475Z QERF1EM-475Z QERF1AM-107Z QERF1EM-475Z QERF1EM-475Z QERF1AM-107Z QERF1HM-225Z QERF1HM-225Z NCS31HJ-7R0X NCS31HJ-7R0X NCF31CZ-104X NCB31CK-104X NCF31CZ-104X NCB31HK-103X NBE21AM-106X NCF31CZ-104X NCF31CZ-104X NCF31CZ-104X NCF31CZ-104X NCF31CZ-104X NCF31CZ-104X NCF31CZ-104X NCF31CZ-104X NCF31CZ-104X NCF31CZ-104X NCB31HK-103X NCB31CK-104X NCF31CZ-104X NCB31CK-104X NCB31HK-102X NBE41AM-226X NCB31HK-103X NCB31CK-104X NCS31HJ-4R0X NCS31HJ-120X NCS31HJ-220X NCS31HJ-560X NCS31HJ-270X NCB31CK-104X

AU.R AU.G R740 AU.L R741 10V TP1 R737

RR339 100

EX.R Q983 D964 CRS03-W

22/16 R975

R926 R927

270 270

C987 NI
TEMP LCDCL R711 ACC5V R743 R928 R929 RKEY1 R742 KEY0 REMOCON R707 4.7k NI R709 10k R708 4.7k MRC NI R710 10k KEY0 10k KEY1

C971 22/16

Q986 UN2211

C982 10/16

CN771 QNZ0095-001

C336 0.047

C337 0.047

D986 MA152WA

CN302 QGA2501C1-06

C722 0.1

R775 R776 100k R777 22k R10k R782 JBUSCK

REMOCON

L784 NQL013K-1R8X

NI R755

R747 R748

C755 0.047

JBUSSISO CH.R C774 NI

CN705 QGA2006C1-02

RDSSCK

BUSINT

NQL013K-1R8X
Parts are safety assurance parts. When replacing those parts make sure to use the specified one. AUX IN SIGNAL TUNER SIGNAL CD SIGNAL CD CHANGER SIGNAL FRONT SIGNAL

GND J1 TU1 CN771

BUSSCK

JBUSSISO

JBUSCK

C725 0.047

QAX0617-001Z

1k D754

IC-PST9333U

FLCDDA

QAX0401-001

R797 1k

R798 1k

1SS355-X 0.022 C707

C792 NI

BZ791 QAN0009-001Z

C791 0.1/50

C705 470p C713 220/10

C715 NI

C704 8p

C703 27p

C702 27p

C701 22p

Q791 UN2211

D795 SML-310FT/JKL/X

C771 0.047 C772 NI

TC74VHC126FT

SML-310FT/JKL/X

CN701 QGF0503F3-07X

C998 100p

C754 0.1

BUZZER

C773 NI
REAR SIGNAL LINE IN SIGNAL
Note:1016801A1_LVS10168-001A_1/2

CN704 NI

qqr1198-001

C961 2200/16

KD-SH99R CD servo control section
RA8 RA7 RA6 IO15 IO14 IO13 IO12 IO11 IO10 R607 R608 RRA5 IO9 IO8 RA4 LC UC OE

R813 C811 120p 2.7k

R811 R812

33k 12k

C809 47/6.3

C803 47/6.3

C610 0.1

C611 0.1

C612 0.1

RA R611

RA0 R612

RA1 R613

WE R610

R822 12k R821 33k

NJM4580V-X

CN601 QGB2027M2-26X

IS41C16256-35T

15K R827

R823 2.7k

C620 0.01

Tuner pack section

A B C D E F G 2-5