Great Company Great People
Hurricane3 High chassis guide

Table of contents

1. Specification 2. Block Diagram 3. Trouble Shooting 4. Debugging Method 5. Adjustment UI Specification 6. Document

2006.05.03

Great Company Great People -1/53-
DDC PA Gr Blue Ocean P Innovation

Model Concept

Design

42PC1R 37LC2R

H&C

2 Tone

Feature
New XD Engine 10 Bit HDMI 3D Surround (Royalty Free) 1Tuner(EU), 2Tuner(Non-EU) AV Input Navigation Stand-by Power consumption 1W On Screen Equalizer

Module

Clear Filter Brightness : 1,200 / Contrast : 10,000 : 1 ASIC : 4025
Brightness : 500 / Contrast : 1600 : 1 View Angle : 178

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Blue Ocean P Innovation

Tool line up

Type H&C

PC1/PC3

PB2 Tool(Better High) All H&C

H&C

LB2 Tool(Better High) All H&C

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Model Specification
Model Aspect Ratio Cell Pitch(mm) Screen size(mm) Resoultion Luminance (cd/) Contrast Ratio View Angle Color(R,G,B) Input Signal OSD Language Market place Remark 37LC2R-ZH 16:9 0.2 0.6 940.3 1366X768 (WXGA) 500 1200:1 178Min 16.7 Mil PAL E/F/G/S/I/ SW/N/D EU 1-Tuner 37LC2R-TH 16:9 0.2 0.6 940.3 1366X768 (WXGA) 500 1200:1 178Min 16.7 Mil Multi E/C/F/G/S /Arab/Parsi N-EU 2-Tuner 42LC2R-ZH 16:9 0.227 0.681 1067.3 1366X768 (WXGA) 500 1200:1 178Min 16.7 Mil PAL E/F/G/S/I/SW/ N/D EU 1-Tuner 42LC2R-TH 16:9 0.227 0.681 1067.3 1366X768 (WXGA) 500 1200:1 178Min 16.7 Mil Multi E/C/F/G/S /Arab/Parsi N-EU 2-Tuner 32LB1R-TH 16:9 0.17 0.51 800.4 1366X768 (WXGA) 500 1200:1 178Min 16.7 Mil Multi E/C/F/G/S /Arab/Parsi N-EU 2-Tuner 37LB1R-TH 16:9 0.2 0.6 940.3 1366X768 (WXGA) 500 1200:1 178Min 16.7 Mil Multi E/C/F/G/S /Arab/Parsi N-EU 2-Tuner 42LB1R-TH 16:9 0.227 0.681 1067.3 1366X768 (WXGA) 500 1200:1 178Min 16.7 Mil Multi E/C/F/G/S /Arab/Parsi N-EU 2-Tuner

V I D E O

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Model RF In AV in Monitor out S-Video in J A C K Component Input(Y,Pb,Pr) Variable Audio out PC Audio In RGB Input RS-232C Remote control AC Input Power Consumption SIZE (W x H x D) (mm) :with stand Weight with Packing(kg) 37LC2R-ZH 110-240V 50/60Hz 286 35.5 37LC2R-TH 110-240V 50/60Hz 286 35.5 42LC2R-ZH 110-240V 50/60Hz 86 42.3 42LC2R-TH 110-240V 50/60Hz 286 42.3 32LB1R-TH 110-240V 50/60Hz 140 911.22.6 37LB1R-TH 110-240V 50/60Hz 190 1045.8693.8 260.4 31.6 42LB1R-TH 110-240V 50/60Hz 00 41.4

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Model Aspect Ratio Cell Pitch Resolution Peak White /special (cd/) Contrast Ratio 42PC1R-ZH 16:9 300(um) 676(um) 1024X768 (XGA) 340 /540 10000:1 (1% full white window in dark room) EU 1-Tuner 42PC1R-TH 16:9 300(um) 676(um) 1024X768 (XGA) 340 / 540 10000:1 (1% full white window in darkroom) N-EU 1-Tuner 42PC1R-CH 16:9 300(um) 676(um) 1024X768 (XGA) 340/ 540) 10000:1 (1% full white window in dark room) China 1-Tuner 42PC3R-ZH 16:9 270(um) 810(um) 1024X768 (XGA) 340(540) 10000:1 (1% full white window in dark room) EU 1-Tuner 50PC1R-ZH 16:9 270(um) 810(um) 1366X768 (WXGA) 280(400) 10000:1 (1% full white window in dark room) EU 2-Tuner 50PC1R-TH 16:9 270(um) 810(um) 1366X768 (WXGA) 280(400) 10000:1 (1% full white window in dark room) N-EU 2-Tuner 50PC1R-CH 16:9 270(um) 810(um) 1366X768 (WXGA) 280(400) 10000:1 (1% full white window in dark room) China 1-Tuner

Market place Remark

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Model RF In AV in Monitor out S-Video in J A C K Component Input(Y,Pb,Pr) Variable Audio out PC Audio In RGB Input RS-232C Remote control AC Input Power Consumption SIZE (W x H x D) (mm) :with stand Weight with Packing(kg) 42PC1R-ZH 110-240V 50/60Hz 330 1129748.29.3 42PC1R-TH 110-240V 50/60Hz 330 1129748.29.3 42PC1R-CH 110-240V 50/60Hz 330 1129748.29.3 42PC3R-ZH 110-240V 50/60Hz 330 1129748.5 336.6 31.3 50PC1R-ZH 110-240V 50/60Hz 430 1302.6872 355.8 51.5 50PC1R-TH 110-240V 50/60Hz 430 1302.6872 355.8 51.5 50PC1R-CH 110-240V 50/60Hz 430 1302.6872 355.8 51.5

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Main Feature Compare with H2
Platform Version Up (H2H3)
LCD Board & PDP Board is different Same PCB Board (With option) Main/Sub IC is separate Main/Sub Picture IC were merging (Only One Main IC : XD8662)
Added features in circuit
New XD Engine -. Adaptive NR -. No noise boosting Sharpness -. Sub Picture Y/C Separate Sharpness Control Blue-tone stretch (Only White region)

New Feature of PDP Module
Decrease the reflection of eternal light -> increase the clarity and contrast (XGA Grade extended) 10 Bit Input and Processing Adopt Low Contour noise Algorithm
Improved Function from H2
Sub Picture 3D Comb Filter 8Bit 10 Bit Signal Processing (Decoder, ADC, de-interlacer, Output)

Productivity

Support DMS Full process (Productivity will be very higher then previous model)

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H3 High Whole Block Diagram
IR RS232 RGB_PC RGB_DTV PC_Audio COMP Tx/Rx : 15Vpp DSUB_SCL / DSBU_SDA DS_VS / DS_HS PC_Audio_L/R : 700mVrms Comp_L/R : 500mVrms Comp_SW TX ST3232C 24C02 74HC14 SCART1_FB HDMI_DATA HDMI_CLK/DE HDMI_VS/HS IR K4D261638F-LC50X2 DDRRAM(128MB X2) AT49BV160C F-ROM(2MB)
TXD /RXD : 5V Digital VGA_RGB : 0.7Vpp AIP_RAW_VS / AIP_RAW_HS_CS : 5V High/Low COMP_Y/Pb/Pr : 1/0.7Vpp COMP2_Y/Pb/Pr : 1/0.7Vpp SCART1_RGB : 0.7Vpp

Comp_SW Comp2_SW I2C

MAIN SCALER XD8662

CN_IIS MC_IIS

Tx0/1/2/3/4/C DISP_EN SCL/SDA_Part OUTPUT 31P_LVDS
Comp2_L/R : 500mVrms Comp2_SW SCART1_LIN/RIN : 500mVrms SCART1_ID
MAIN_V or Y/C OUT : 2Vpp SUB_V : 2Vpp SCART1_VIN : 1Vpp

Variable_audio_out L/R

Scart1 (TV_out)

Scart2 (MNT_OUT)

RF Rear AV (AV3)
SCART1_ID SCART2_ID SCART2_LIN/RIN : 500mVrms SCART2_VIN/YIN/CIN : 1/0.285Vpp SCART2_ID MNT_LOUT/ROUT MNT_OUT TU_MAIN : 1Vpp I2C AV SWITCH TUNER SIF (MAIN) CXA2069Q AM_Audio SCART1,2_LIN/RIN TUNER TU_SUB : 1Vpp (SUB) LIN3/RIN3 : 500mVrms VIN3/YIN3/CIN3 : 1/0.285Vpp AV3_SW/S3_SW
PC_Audio_L/R AM_Audio / S I F COMP1,2_RIN/LIN AV_LOUT/ROUT HDMI_IIS TV_L/R OUT : 500mVrms
Audio S/W & CONTROL MSP4450K

I2S (SCK/WCK/DATA)

MNT_OUT
MNT_OUT : 1Vpp MNT_LOUT/ROUT : 500mVrms I2C HDMI Rx ANX9021 24C02 HDMI_DATA : 3.3V HDMI_CLK/DE : 3.3V HDMI_IIS : 3.3V HDMI_VS/HS : 3.3V

PWM NTP2000H

L_CH R_CH

AMP TAS5122

L_SPK_OUT R_SPK_OUT

HDMI1/2

AV4_SW/S4_SW VIN4/YIN4/CIN4 : 1/0.285Vpp LIN4/RIN4 : 500mVrms Video Signal Audio Signal

Variable Audio_out

SCL/SDA Variable_audio_out L/R : 500mVrms

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Main Scaler(XD8668) Features

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Main Scaler(XD8668) Block Diagram
The FLI8668 chip has a flexible Analog Front End (AFE) with 13 configurable inputs through an analog multiplexer before the Analog to Digital Converters (ADCs). It also contains an embedded Multi-Standard Video Decoder. This decoder contains a digital comb filter for optimum Y/C separation. A 3D comb filter is a vailable for optimum Y/C separation, that reduces or eliminates any artifacts due to poor Y/C separation seen on standard 2D video decoders on composite inputs, most commonly found on TV tuners. The FLI8668 microprocessor can process a wide range of Vertical Blanking Interval (VBI) data and display this data with the bitmap OSD processor. The microprocessor can support VBI data processing in the Main or PIP channels as well as in the background when the corresponding video stream is not pre sent on the output stream. The VBI dataslicer can extract data encoded into the VBI of the input video stream. Decoded data bytes from the VBI dataslicer are stored in a memory buffer for subsequent processing by the microprocessor. The microprocessor decodes the different formats of the VBI data and pas ses the information to the OSD controller for output to the display controller. The VBI decoding process can run continuously in the background for inputs th at contain VBI data.

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Main Scaler(FLI8668) Block Diagram Explanation
The Digital Input Port is a 48-bit data input with flexible configuration to support a wide range of digital sources. It consists of two 24-bit ports (PORT A and PORTB),two sets of control signals (VS,HS,ODD,etc.), and 4 input clocks. Up to 4 different inputs are supported as long as at least 2 of these in puts are 8-bit CCIR656. The digital input port can also be configured to support one 30-bit input with a second 16-bit input port. Bit 7 to 0 of PORTA ca n be configured as a bidirectional interface for media card applications. DCDi (Directional Correlation De-Interlacing) is an algorithm from Genesis Microchips Faroudja division, that is used to deinterlace video content (co nvert from interlaced to progressive scan). DCDi is known for its smooth interpolation of video content as it fills in the missing lines. Its purpose is to eli minate jagged edges (jaggies) along diagonal lines caused by interpolation, resulting in the projection of cinema-like images with exceptional picture q uality. The FLI8668 allows a very flexible PIP display configuration whereby either the graphics or video channel may act as the PIP source to overlay over the other channel. Any one of the inputs (analog RBG, 24-bit digital, 8-bit digital, YPbPr, composite video, etc) may be multiplexed to either channel. T he PIP can be from any of the AIP (Analog Input Port) 1 or 2 or DIP (Digital Input Port) 1 or 2. Single PIP allows the PIP display to be placed arbitrarily in the display window. It can be placed within the Main display, partially overlapped with Main display, or fully detached from Main display. Multiple PIP s display allows a number of PIP windows to be displayed at the same time depending on display pixel resolution. The Main and one PIP window will be running in real time. There are up to 16 PIP windows available at the same time, however only one might be active. All of them should be aligned to the 4x4 grid. Default S/W application uses multiple PIP windows to display different RF channels. Two LVDS channels (A and B) are available on the output of the FLI8668 to transmit data and timing information to the display device. FLI8668 direct ly drives the standard LVDS interface panels, supporting all standard data formatssingle and dual bus, 18- or 24-bit data output. The 24-bit data may be mapped as either standard receiver formats. The FLI8668 has a fully programmable, true color bitmapped OSD controller capable of displaying up to 16 tiles or bitmap windows on the display. The individual tiles are programmable for location, size and bits per pixel, and have a precedence determining which tiles appear when overlapping oc curs on the display. Tile data is stored in the external frame store memory by the OCM in either : 1, 2, 4, or 8-bit per pixel format. On-chip table registe rs point to the start of tiles in external memory. A programmable on-chip 256x24-bit color lookup table is provided to map the OSD pixels onto a true 2 4-bit color space. The FLI8668 on-chip microcontroller (OCM) serves as the system microcontroller. It programs the FLI8668 and manages other devices in the system such as the keypad and non-volatile RAM (NVRAM) using general-purpose input/output (GPIO) pins. The OCM can address a 22-bit address space to utilize 4 MB external ROM.

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H3 High Power

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H3 High Power - A

Power Sequence :

1. Power Cord connect to set. Power b/d supplies 5VST CON from wafer P1000 pin 3 and 8. This is also distri buted as +5VST_CORTEZ, that connect to Regulator IC1001, IC1004, and IC1005, which regulate 1.8, 2.5, and 3.3V for Cortez (turns ON). Also distributed as + 5VST, that connect to Transistors Q1000,1001,1004, and 1005. AC_DET signal are sent by Power b/d from pin 1 waf er P1000 to pin N23 of IC800(Cortez). Then Cortez s end 3.3V_ON from pin M2 to Power b/d via pin 13 P1 000. IC800 send RL_ON from pin U24, this switches the tr ansistor Q1004 ON so +5VST grounded, this makes t he transistor Q1000 OFF, so other +5VST supplies R L_ON on pin 2 wafer P1000. So Relay on Power b/d t urns on to supplies 3.4, 6, 12, and 19V.(section 2) 5VDet is sent by Power b/d to Cortez. Then Cortez s end command to turn on VaVs from pin U25 that swit ches ON transistor Q1005, so +5VST grounded, this makes transistor Q1001 OFF, and this make another +5VST supplies to pin 5 wafer P1000. The Power b/ d supplies X b/d and Y b/d.

AC_DET RL_ON +5VST

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H3 High Power - B

3V1.8V 5V3.3V
1. The +5VST_Cortez as an input on pin 1 of IC1001(B A033T), a LOW SATURATION VOLTAGE REGULATO R, is being step-down to 3.3V. Then this output act as input and enable for IC1003 pin 2 and pin 1 (SC15 65-1.8TR), a VERY LOW DROP OUT 1.5 Amp REGU LATOR WITH ENABLE, the output 1.8V is in pin 4, that is regulated to +1.8V_ADC_CTZ,+1.8V_CORE _CTZ, +1.8V_DLL_CTZ, and +1.8V_PLL_CTZ. The P_12 (from section 2), as an input on pin 1 of IC(KA7809R), a 3-TERMINAL 1A POSITIVE VOL TAGE REGULATOR, regulated to be 9V output on pin 3, distributed as +9V_CXA2069, +9V_MSP4450, +9 V, and +9V_TK1184. The VAVS_ON from Cortez switches ON transistor Q 1006, and makes +12V_panel grounded and supply pi n1-4 IC1006(SI925DY), a DUAL P-CHANNEL LOGIC LEVEL POWER TRENCH MOSFET, minimized ON s tate resistance, and the output is on pin 5-8 a 12V_L CD. The VAVS_ON also enable IC1007 pin 7, to s tep-down an input +12V_PANEL on pin 2 into 5V_LC D on pin 1 and 3.

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H3 High Power - C

5V3.3V

Power Sequence : 1. The+5V_CORTEZ acts as input on pin 1 of IC1005( BA033T) a LOW SATURATION VOLTAGE REGUL ATOR, which step-down into 3.3V output on pin 3. This outputs then is distributed as +3.3V_PLL_C TZ, +3.3V_LBADC_CTZ, +3.3V_LVDS_CTZ, + 3.3V_LVDS_PLL_CTZ, and +3.3V_IO_CTZ. The 3.3V output from IC1005 also acts as input on p in 1 of IC1000 (MIC39100-2.5WS), a 2.5V/1A REGU LATOR, step down the 3.3V into 2.5V output on pi n 3 as a +2.5V_DDR_CTZ.

3.3V2.5V

The+5V_CORTEZ also acts as input on pin 1 of IC1 004(BA033T, a LOW SATURATION VOLTAGE REG ULATOR, which step-down into 3.3V output on pin 3. This outputs then is distributed as +3.3V_ADDC1 _CTZ, and +3.3V_ADDC2_CTZ

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Trouble Shooting Guide

1. No power

Symptom 1) Minute discharge doesnt occur at module. 2) Front LED doesnt come into action.

Start check

Is inserted a plug in power cord? YES Is connected the Line Filter and PSU? YES Is normal the fuse of PSU? Plasma(F101), LCD(F111) YES Is it connected that PSU and 13pin cable in VSC board?

Plug in a power cord

Connect a cable. Plasma (EL11), LCD(SC100)

Replace the fuse

Connect the 13pin cable.
YES After remove all cables connected to PSU(except the CN101), authorizes the AC voltage marking on manual. When ST-by 5V doesnt operate, replace PSU

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2. Protection mode
Symptom 1) After once shining, it doesnt discharge minutely from module. 2) The relay falls.( The sound is audible Click) 3) It is converted with the color where the front LED is red from white.
Is output the normality Low/High Voltage except Stand-by 5V?
Is the PSU normal? YES Is the each connector normal? YES Is the Y- Board normal ? YES Is the Z- Board normal ? YES Is the X- Board normal ?

Replace the power board

After connecting well each connector the normality it operates?
Is normal the fuse (FS2,FS3) on Y-B/D? YES
Is normal the output voltage after remove P1connector of Y-B/D?

Replace Y-B/D

Replace the fuse NO Is normal the output voltage after remove P1 connector of Z-B/D? Replace Z-B/D
Is normal the fuse (FS1,FS2) on Z-B/D? YES
Replace the fuse After remove P100,110 output voltage normality: Replace Right X-B/D After remove P200,210 output voltage normality: Replace Left X-B/D
Is normal the output voltage after remove P100,110,200, 210 connector of X-B/D?

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3. No Raster
Symptom 1) No OSD and image occur at screen. 2) It maintains the condition where the front LED is white
Does minute discharge at Module? YES
Is the inverter/VaVs on? YES Check the PDP/LCD Module
Is the link cable normal? YES Is the IC800s output normal?
Reconnect the link cable in P803(Plasma)/P804(LCD)

Replace the VSC

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4. In case of becomes unusual display from RF mode(Main)
Is normal video output of the Tuner? (Check TU201_Pin14)
Is the Tuner Cable connected well?
Is normal the Input voltage ? (Check Pin8, Pin6)
Is normal the I2C communication ? (Check Pin5, Pin4)

NO YES

Cable inserts well.

Check the power ( L1103)

Change the Tuner
Is normal video output NO of CXA2069Q? (Check R324, In case of S-Video check R324, R328)
Is normal the Input voltage ? (Check L308)
YES Is normal the I2C communication ?

(Check R309, R310)

Check the power ( Check L1004)

Change the IC(IC300)

Is the LVDS Cable connected well?

Cable inserts well

Change the IC(IC800)

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5. In the case of becomes unusual display from rear AV mode(main)
Is normal video input of the A/V jack? (Check R2101)

Check the input source)

Same as Block A
6. In the case of becomes unusual display from rear S-Video mode(main)
Is normal video input of the A/V jack? (Check R198, R199, R2100)
7. In the case of becomes unusual display from side AV mode(main)
Is normal video input of the A/V jack? (Check R343)

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8. In the case of becomes unusual display from side S-Video mode(main)
Is normal video input of the A/V jack? (Check R339, R341, L310)

Check the input source

9. In the case of becomes unusual display from SCART 1 mode(main)
Is normal video input of the A/V jack? (Check R102)
10. In the case of becomes unusual display from SCART 1_RGB mode(main)
Is normal video input of the A/V jack? (Check L111, L112, L106)

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11. In the case of becomes unusual display from SCART 2 mode(main)
Is normal video input of the A/V jack? (Check R115)
12. In the case of becomes unusual display from SCART 2_YC mode(main)

Is normal video input of the A/V jack? (Check R115, R149)

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13. In case of becomes unusual display from RF mode(Sub)
Is normal video output of the Tuner? (Check TU200_Pin14)

(Check Pin5, Pin4)

Is normal video output of CXA2069Q? YES (Check R312, In case of S-Video check R312, R314)
Is normal the I2C communication ? (Check R309, R310)
14. In case PIP doesnt display from other modes(Sub)
Same as the case of main except block A should be change to B

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15. In case of becomes unusual display from component1 mode(main/sub)
Is normal video input of the JK102? (Check L126, L127, L128)

Change IC(IC800)

16. In case of becomes unusual display from component 2 mode(main/sub)
Is normal video input of the JK103? (Check L129, L130, L131)
17. In case of becomes unusual display from RGB mode(main/sub)
Is normal R, G, B input and H,V sync of the JK500? (Check R509, R511, R512 R513, R515)

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18. No Sound

Symptom

LED is White Screen is existent, but sound isnt

Check follow

All input (mode) is no sound? YES Only HDMI is no Sound? YES Only AV input is no Sound? Is the output of IC300(pin52,53) normal? YES YES Check the signal after IC300 refer to circuit diagram Is the speaker on in menu? YES Is the speaker cable normal? YES IC400 operate normally? YES IC401 operate normally? YES Only RF is no Sound? IC402 operate normally? YES Check the Speaker cable Set on speaker in menu
Download the EDID data NO

Replace IC300 NO

Replace IC400 NO

Replace IC401 NO

Check the Tuner In/Out NO

Replace IC402 NO

Replace VSC B/D

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19. HDMI mode

Is normal only video ?

Download EDID data each port. 1. Check TV input mode. (HDMI1 port support HDMI and DVI. So if you input DVI signal and PC audio from phone jack, You can hear PC audio. ) 2. Unplug and plug HDMI cable. (sometimes ESD surge occurred at HDMI port.) 3. Check HDMI Mute register. (0x68, offset 0x37) 4. Check Audio-out channel mute register (0x68, offset 0x32) is appropriately enabled.

No Is normal only audio? No Check TMDS line wave. (R1215 ~ R1222/ R1226 ~ R1233) Yes

Is wave continuous?

Check HDMI source. Change another source or cable.
Yes 1. Check HDMI receivers status register. (0x60, offset 0x06) If the value is 0xf or 0x8, it is normal. 2. Check HDCP register. (0x60, offset 0x32) Enable bit 6: HDCP key loaded Enable bit 5: HDCP decryption active Enable bit 4: HDCP authen. attempted
Reset TMDS power down/on register. - 0x60, offset 0x3f : 0xf7 => 0xff
Normal video, Normal audio?

Replace IC1200

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Gprobe5 Install & Download Guide

GProbe 5.2.0.2.exe

Install the GProbe Software from the Desktop using the GProbe 5.2.0.2.exe file.

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CGProbe Redistributable 5.2.0.4
After installing GProbe 5.2.0.2 install the CGProbe from CGProbe Redistributable 5.2.0.4.exe as shown in the figure.

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GProbe 5
Select the Icon named GProbe 5 Tool for downloading the software in T.V. from the desktop.

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Help Menu
Verify the GProbe UI Version: 5.2.02 and CGProbe Version: 5.2.0.4 from the Help menu under About GProbe.

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Connection Settings

Select Chip:

Choose the appropriate chip from Select Chip: FLI8638 Check Connection settings.

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Set the Connections as shown in figure: Device: Serial Protocols: SERIAL1 Scheme: Serial connection for all Genesis Chips
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Set the Connections as shown in figure: Port: COM1 Data Bits: 8 Baud Rate: 115200 Parity: None Stop Bits: 1
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Set the Connections as shown in figure: Port: 0x378 Clock Frequency: 60000 Hz Scheme: Standard Speed LPT1(0x378)
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Set the Connections as shown in figure: I/p Pin: 15(active high) SDA Signal I/p Pin: 11(active high) Scheme: Default Pin Assignments
O/p Pin: 17(active high) SDA Signal O/p Pin: 9 (active high)

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Set the Connections as shown in figure: Scheme: Default USB Setting
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Set the Connections as shown in figure: Short Timeout: 1000 ms Address: 4096 Scheme: Default Setting
Long Timeout: 15000 ms Size: 4096

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Select the Commands Option and then select the Batch option to locate the Path from where the.text file has to be downloaded which contains the information regarding the location of final.hex file.

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browse
Browse the.txt file from its specified location in the directory such as: C:\clearcase_rohit\rohit_view2\CC_HURRICANE3_H\10_Source\FLI8668\Isp\b atch\CORTEZ_A.txt
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After selecting the Appropriate Batch file Check that the T.V is in GProbe Mode for downloading the software other wise it generate an Error. RS232 Host: Gprobe. Baud Rate: 115200bps(T.V in Power on state)/9600bps (T.V in stand by Power off).

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After selecting the Appropriate Batch file Check that the T.V is in GProbe Mode for downloading the software other wise it generate an Error. Error: Timeout while waiting for Response.

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If the connections between T.V Board and C.P.U are not proper or T.V is not in the GProbe mode it will give Error Message as shown in figure. Error Message: Timeout while waiting for Response. So Check the connection properly and GProbe condition & again Start Downloading.

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After Downloading complete its shows : Execution time: XXX.XX second (~~Approx) Batch: Command Successful.

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Gprobe5 Debugging

GPIO port debugging
appstest 0 input appstest funtion help

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Register Bit Types
After value change, Input 0xe000 = 0xff in command window Execute (Real value change)
After value change, Directly Real value change
PAA,CRW,CRO,RO,WO type We could not change the register value using the Gprobe5

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IC control Example
EEPROM initialization (Except adjustment Data) EEPROM initialization (Include adjustment Data) EEPROM Specific address value : Byte read EEPROM EEPROM Specific address : Byte write appstest 21 Addr Data appstest 24 Addr appstest 23 Addr Data appstest 4 appstest 75 SubAddr Addr appstest 76 SubAddr Addr Data appstest 33 appstest 32 Addr1 Addr2 appstest 31 Addr1 Addr2 Data appstest 60 Main Pip MonitorOut appstest 61 EEPROM Specific address value : Word read EEPROM Specific address HDMI initialization HDMI HDMI Specific register : value read HDMI Specific register : value write MSP initialization MSP MSP Specific register : value read MSP Specific register : value write CXA2069 register : write CXA2069 CXA2069 Status : read : Word write appstest appstest appstest 22 Addr

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EDID data Download Guide.
1. Required Test Equipment
1) Adjusting PC with S/W for writing EDID Data.(S/W : EDID TESTER Ver.2.5) 2) A Jig for EDID Download 3) Cable : Serial(9Pin or USB) to D-sub 15Pin cable, D-sub 15Pin cable, DVI to HDMI cable. 2. Setting of the device

Connection Diagram of DDC download

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3. Preparation for Adjustment 1) As above Fig. 5, Connect the Set, EDID Download Jig,, PC & Cable 2) Turn on the PC & EDID Download Jig. And Execute the S/W : EDID TESTER Ver.2.5 3) Set up the S/W option.
Repeat Number : 5 Device Address : A0 PageByte : 8

4) Power on the Set

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4. Example Data of EDID(42PC1R-ZH) 1) 42PC1R-ZH DDC data of Analog-RGB (Check Sum : CE )

[BLOCK0]

2) 42PC1R-ZH DDC data of Digital_HDMI (Check Sum : 0B2B)

[BLOCK1]

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5. Sequence of Adjustment 1) Init the data 2) Load the EDID data.( Open File : Analog ,Digital) 3) Push the Write Data & Verify button. And confirm Yes. 4) If the writing is finished, you will see the OK message 5) It is important that PP62A/C has two HDMI so digital DDC downloading must be performed two times(HDMI 1 , HDMI 2)

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Document
Owners Manual Module CAS Circuit Diagram Adjustment UI Specification Area Option Table

Owner's manual _ EU

Owner's manual _ Non EU

42X3_PDP

50X3_PDP

32LCD_LPL

37LCD_LPL

42LCD_LPL

37LCD_AUO

Circuit Diagram_VSC

Circuit Diagram _ Local key

Circuit Diagram _ PreAMP

Circuit Diagram _ Side AV

Adj_UI Specification

LCD H3 High Option Table

PDP H3 High Option Table

Gprobe5

GProbe5.2.0.2

CGProbe5.2.0.4

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