Logic Characteristics of 40 nm thinthin-channel InAs HEMTs
Tae-Woo Kim, Dae-Hyun Kim* and Jess A. del Alamo
Microsystems Technology Laboratories MIT *Presently with Teledyne Scientific Sponsors: Intel & FCRP-MSD Fabrication: MTL, NSL, SEBL at MIT IPRM

June 4th, 2009

Scaling issues in III-V HEMT III Motivation
III-V HEMT: Model system for future III-V logic FETs

Key dimensions:

- Gate Length (Lg) - Barrier Thickness (tins) - Side-recess Length (Lside) - Channel Thickness (tch)

Gate Source

Lg Lside

Drain Drain

Barrier Channel Buffer

Scaling trajectory:

- Lg tins , tch , Lside
< Schematic of III-V HEMT >
Goal : Explore trade-offs involved in channel thickness p scaling

Thin channel InAs HEMT

Oxide O id InGaAs/InAlAs
The image cannot be display ed. Your computer may not hav e enough memory to open the image, or the image may hav e been corrupted. Restart y our computer, and then open the file again. If the red x still appears, y ou may hav e to delete the image and then insert it again. The image cannot be display ed. Your computer may not hav e enough memory to open the image, or the image may hav e been corrupted. Restart y our computer, and then open the file again. If the red x still appears, y ou may hav e to delete the image and then insert it again.

Lside tins tch Lg

In0.7Ga0.3As:1nm InAs:2nm In0.7Ga0.3As:2nm

Lg ~ 40 nm

tins = 5 nm

tch = 5 nm

6nmInP
11nmIn0.52Al0.48A 11 I As
The image cannot be display ed. Your computer may not hav e enough memory to open the image, or the image may hav e been corrupted. Restart y our computer, and then open the file again. If the red x still appears, y ou may hav e to delete the image and then insert it again.

Buffer:In0.52Al0.48As

n,Hall = 9,950 cm2/V-sec
Reference : InAs HEMT with tch = 10 nm n,Hall = 13,500 cm2/V-sec <D.-H. KIM IEDM 08>
Triple-step t T i l t gate recess process - Gate metal stack: Ti/Pt/Au - Lside = 80 nm, tins = 5 nm
Output & gm Char.: Lg = 40 nm
1.0 0.8 0.6 0.4 0.2 0.0 0.0 VGS = 0 V 0.2 0.4 VDS [V] 0.6 0.8 tch = 5 nm InAs HEMT tch = 10 nm InAs HEMT Lg = 40 nm

VGS = 0.5 V

tch = 5 nm InAs HEMT tch = 10 nm InAs HEMT Lg = 40 nm

1.6 gm [mS m] S/

VGS = 0.3 V

ID [ mA/m ]

1.2 0.8 0.4 VDS = 0.5 V 0.0 -0.6 -0.4 -0.2 0.0 VGS [V] 0.2 0.4 0.6

VGS = 0.1 V

- Good ID saturation, pinch-off behavior - gm = mS/m @ VDS=0.5 V 1.65 S/ 05
Subthreshold Char.: Lg = 40 nm
1E-3 1E-4 1E-5 ID [ A/m ] / 1E-6 1E-7 1E-8 1E-9 tch = 5 nm InAs HEMT s h tch = 10 nm InAs HEMT

VDS = 0.5 V VDS = 0.05 V

ThinchannelHEMTs
SharperSS LowerDIBL L LargerION/IOFF I
Lg = 40 nm -0.6 -0.4 -0.2 0.0 VGS [V] 0.2 0.4 0.6
For tch = 5 nm device at VDS = 0.5 V, SS = 72 mV/dec, DIBL = 72 mV/V and ION/IOFF = 2.5 x 104

Subthreshold Char. vs Lg

10 ID [A/m] 10 10
LG = 40 nm LG = 50 nm LG = 70 nm LG = 80 nm LG = 100 nm LG = 150 nm LG = 200 nm

Lg Lg

VDS = 0.5 V

0.0 VGS [V]

Harmonious scaling Very small VT roll off with Lg (34 mV)

SS & DIBL vs. Lg

90 Subtreshold swing [mV/dec]
In0.7Ga0.3As HEMT: tch = 13 nm
In0.7Ga0.3As HEMTs: tch = 13 nm InAs HEMTs: tch = 10 nm

InAs HEMTs: tch = 10 nm

DIBL [mV V/V]

InAs HEMTs: tch = 5 nm

Lside = 80 nm, tins = 5 nm

Lg [nm] 200

160 200

Lg [nm]

Excellent electrostatic integrity and scalability with thin channel
<D.-H. KIM IPRM 09>
Key trade-off: Source resistance trade< Gate current injection technique>
0.34 0.32 R s [Ohm.m mm] 0.30 0.28 0.26 0.24 0.22
Rs = 0.25 Ohm mm Rs = 0.24 Ohm mm Rs = 0.255 Ohm mm 280
tch = 13 nm In0.7Ga0.3As HEMTs tch = 10 nm InAs HEMTs tch = 5 nm InAs HEMTs Rsheet = 320 Ohm/sq

120 Lg [nm]

Thin-channel InAs HEMTs: - Higher Rsh higher Rs

Scalability of gmi

<gmi from S-parameters>
In0.7Ga0.3As HEMT: tch = 13 nm InAs HEMT: tch = 10 nm InAs HEMT: tch = 5 nm

gmi [mS/m] m

VDS = 0.5 V 40 Lg [nm] 160 200
Thin-channel InAs HEMTs: - Lower values of gmi due to lower n - But velocity less affected better gmi scalability down to 40 nm

fT & fmax char. : Lg = 40 nm
fT fmax tch = 5 nm devices 445 GH GHz 395 GHz tch = 10 nm devices 520 GHz GH 337 GHz

H21 & UG [dB]

VDS = 0.6 V UG VGS = V 0.2 Lg = 40 nm

0.0 1k

Frequency [GHz]
For thin-channel InAs HEMT: Low fT but high fmax
Why high fmax ? Evaluation of go
1.0 Lg = 40 nm 0.8 0.6 0.4 0.2 0.0.2
Output co onductanc [mS/mm ce m]

InAs HEMT tch = 10 nm

InAs HEMT
InGaAs HEMT tch = 13 nm 0.3 0.4 ID [mA/mm] 0.5 0.6 0.7
Lower DIBL, lower Impact ionization: DIBL improved output conductance with thin channel

Unified FOM for Logic

ION at given IOFF and VDD

VDD = 0.5 V

IOFF = 100 nA/m

ION [mA/m] m

InAs HEMTs: tch = 10 nm In0 7Ga0 3As HEMTs: 0.7 0.3 tch = 13 nm

32 nm CMOS

100 Lg [nm]
For thin-channel InAs HEMT: thin channel Better scalability in sub 100nm regime

Conclusion

Thin-channel (tch = 5 nm) InAs HEMTs
At Lg = 40 nm, thin-channel HEMTs are excellent
DIBL = 72 mV/V, S = 72 mV/dec and ION/IOFF > 104
Main advantage: improved electrostatics and scalability Trade-offs: T d ff n = cm2/V 9,950 /V-sec, Rs = 0.255 mm

Future work:

Increase gate foot stem height ~ 200 nm to improve fT Extract injection velocity and gate capacitance. Optimize barrier to lower Rs and RC.

2010 International Conference on Indium Phosphide and Related Materials Conference Proceedings 22nd IPRM 31 May - 4 June 2010, Kagawa, Japan

11:00 - 11:15 FrB2-2

Logic Characteristics of 40 nm thin-channel InAs HEMTs
Tae-Woo Kim, Dae-Hyun Kim* and Jess A. del Alamo Microsystems Technology Laboratories (MTL), Massachusetts Institute of Technology (MIT), Cambridge, MA 02139, USA, E-mail: twkim78@mit.edu *Teledyne Scientific Company, CA, USA. Abstract We have experimentally investigated the trade-offs involved in thinning down the channel of III-V FETs with the ultimate goal of enhancing the electrostatic integrity and scalability of these devices. To do so, we have fabricated InAs HEMTs with a channel thickness of tch = 5 nm and we have compared them against, InAs HEMTs with tch = 10 nm. The fabricated thin-channel devices exhibit outstanding logic performance and scalability down to 40 nm in gate length. Lg = 40 nm devices exhibit S = 72 mV/dec, DIBL = 72 mV/V, and ION/IOFF = 2.5 x 104, all at VDS = 0.5 V. However, there are trade-offs of using a thin channel which manifest themselves in a higher source resistance, lower transconductance, and lower fT when compared with InAs HEMTs with tch = 10 nm.

INTRODUCTION

As conventional Si CMOS scaling approaches the end of the roadmap, III-V based MOSFETs are being considered as an alternative technology to continue transistor size scaling [12]. In the quest to map the potential of III-Vs for future CMOS applications, the High Electron Mobility Transistor (HEMT) has emerged as a valuable model system to understand fundamental physical and technological issues. In fact, recently, excellent logic characteristics have been demonstrated in InAs HEMTs with gate length as small as 30 nm [3-4]. This is mainly a result of the outstanding electron transport properties of InAs and the use of a thin quantum well channel. Further scalability to Lg = 10 nm dimension characteristic of a future III-V CMOS technology will require harmonious scaling of all relevant device dimensions including the channel thickness. A consequence of very thin channel is that carrier transport deteriorates, mainly as a result of increased carrier scattering [5]. This can detract from performance. In order to understand the trade-offs involved in thinning the channel in sub-100 nm III-V FETs, we have experimentally investigated the characteristics of InAs HEMTs with a 5 nm thick channel. This is half the value of earlier device demonstrations from our group [4]. We show that a very thin channel design substantially improves short channel effects (SCEs) and output conductance (go) characteristics but deteriorates its transport properties and access resistance. Future self-aligned gate (SAG) device architectures should be able to mitigate these problems. giving the details of the epitaxial layer structure. This heterostructure is essentially identical to that of our previous InAs HEMT designs [4] except that the channel consists of a multilayer structure with a 2 nm thick pure InAs core surrounded by a 1 nm In0.7Ga0.3As top cladding and a 2 nm nm In0.7Ga0.3As bottom cladding layer. In an epi wafer with an identical heterostructure except for a simpler 10 nm InGaAs capping layer with 1 x 1018 /cm3 Si doping, the Hall mobility (n,Hall) and carrier density (ns) were 9,950 cm2/V-s and 2.5 x 1012 /cm3. This is about 30 % lower than the value obtained in a 10 nm thick channel InAs HEMT heterostructure with a 5 nm InAs core [6] and reveals the increased carrier scattering that comes with channel thickness scaling.

PROCESS TECHNOLOGY

Fig. 1 shows a schematic cross sectional view of the device
Fig. 1 Schematic of thin-channel InAs HEMT. The heterostructure features a 5 nm total channel thickness that includes a 2 nm InAs core channel layer.
978-1-4244-5920-9/10/$26.IEEE
Device fabrication closely follows our previous device demonstrations [6]. We used a three-step gate recess process that yielded an InAlAs barrier thickness in the intrinsic region, tins, of about 4 nm and a Ti/Pt/Au (20/20/300 nm) T-gate with gate-cap edge distance Lside = 80 nm. We have fabricated devices with Lg values in the range of 40 to 200 nm. For reference, we simultaneously fabricated devices on an InAs HEMT heterostructure with tch = 10 nm that it is very similar to an epi wafer structure that we have processed earlier [6]. These devices have gone through an identical process and should therefore have closely matched dimensions.
tch = 5 nm InAs HEMT tch = 10 nm InAs HEMT VGS = 0.5 V

LG = 40 nm VGS = 0.3 V

ID [ mA/mm ]
0.4 VGS = 0.1 V 0.2 VGS = 0 V 0.0 0.0 0.2
DC AND LOGIC CHARACTERISTICS
Fig. 2 shows the output characteristics of 40 nm gate length InAs HEMTs on both heterostructures. Both devices exhibit excellent pinch-off and saturation characteristics up to VDS = 0.7 V. The threshold voltages of both devices are -0.22 V at 1 mA/mm of ID and VDS = 0.5 V. Interestingly, the thin channel device show much better output conductance. This is expected as a result of reduced impact ionization and VT dependence on VDS (DIBL, discussed below). These are both a product of a thin highly quantized channel. However, the thin-channel HEMTs exhibit slightly higher RON. Fig. 3 shows subthreshold and gate current characteristics of both 40 nm InAs HEMTs at VDS = 50 mV and 0.5 V. The thin-channel (tch = 5 nm) device shows much shaper subthreshold swing and much less threshold voltage shift with VDS (DIBL) than the thick-channel (tch = 10 nm) device. For the tch = 5nm device, the subthreshold swing (S) is 72 mV/dec, the drain-induced-barrier-lowering (DIBL) is 72 mV/V, and the ION/IOFF ratio is 2.5 x 104. These results compare favorably with those obtained on the tch = 10 nm device which are 79 mV/dec, 84 mV/V, and 9 x 103, respectively. Fig. 4 shows typical transconductance characteristics of both InAs HEMTs at VDS = 0.5 V. The 5 nm thick channel device exhibits a maximum transconductance of 1.65 S/mm, while the 10 nm channel HEMT shows 1.75 S/mm. Fig. 5 shows the subthreshold and gate leakage current characteristics of thin channel InAs HEMTs from Lg = 200 nm to 40 nm at VDS = 0.5 V. There is a very small VT shift of less than 34 mV as the gate length scales down from 200 to 40 nm. In contrast, the VT shift of the 10 nm thick devices over the same gate length rage is 55 mV. The superior scalability of the 5 nm devices is also manifested in the evolution of S and DIBL with Lg (Fig. 6 and Fig. 7). These figures also include result from an earlier set of devices with a 13 nm InGaAs channel, and similar value of Lside and tins [3]. It is clear that thinning down the channel brings significant benefits in terms of improved electrostatic integrity and scalability.

0.4 VDS [V]

Fig. 2 Output characteristics for both 40 nm gate length InAs HEMTs.
1E-3 1E-4 1E-5 ID [ A/m ] 1E-6 1E-7 1E-8 LG = 40 nm 1E-9 -0.6 -0.4 -0.2 0.0 VGS [V] 0.2 0.4 0.6 tch = 5 nm InAs HEMT tch = 10 nm InAs HEMT

VDS = 0.5 V VDS = 0.05 V

Fig. 3 Subthreshold and gate leakage characteristics for both 40 nm gate length InAs HEMTs.
2.0 tch = 5 nm InAs HEMT tch = 10 nm InAs HEMT 1.6 LG = 40 nm

GM [S/mm]

0.4 VDS = 0.5 V 0.0 -0.6 -0.4 -0.2 0.0 VGS [V] 0.2 0.4 0.6
Fig. 4 Transconductance characteristics for both 40 nm gate length InAs HEMTs.

10 ID [A/m] 10

LG = 40 nm LG = 50 nm LG = 70 nm LG = 80 nm LG = 100 nm LG = 150 nm LG = 200 nm
90 Subtreshold swing [mV/dec]
In0.7Ga0.3As HEMTs : tch = 13 nm

InAs HEMTs : tch = 10 nm

InAs HEMTs : tch = 5 nm

VDS = 0.5 V

0.0 VGS [V]

80 Lg [nm]

160 200
Fig. 5 Subthreshold and IG characteristics for 5 nm thick channel InAs HEMTs with different values of Lg at VDS = 0.5 V. The increased RON observed in Fig. 2 and the decreased transconductance observed in Fig. 4 for the thin channel device also points out the trade-offs of the present approach. They essentially arise from enhanced scattering which translates into lower channel electron mobility. Fig. 8 shows the evolution of the transconductance as a function of gate length at VDD = 0.5 V for the three types of devices. At all gate lengths, the present devices exhibit a lower extrinsic transconductance than the 10 nm thick channel InAs HEMTs but better than the 13 nm thick channel InGaAs HEMTs which show poor scalability. To understand this result better, we have carried out measurements of the effective source resistance, RS*, using the gate current injection method [7]. As shown in Fig. 9, RS can be extracted by linear extrapolation to zero Lg. The extracted RS* for thin channel devices is 0.255 Ohmmm, in contrast with 0.24 Ohmmm for the 10 nm thick channel devices and 0.25 Ohmmm for the 13 nm thick channel devices. In addition, we found that devices with the 5 nm thick channel exhibit a higher sheet resistance (320 Ohm/sq) in the channel region when compared with 240 Ohm/sq for the 10 nm InAs HEMTs and 280 Ohm/sq of the 13 nm InGaAs HEMTs. Selfaligned gate (SAG) device architectures should be able to partially mitigate this problem. Using these measurements, we have extracted the intrinsic transconductance of our transistors. Our extraction accounts for the effects of output conductance (go), RS, and RD. Fig. 8 shows a reduced value of gmi for the thin channel when compared with the 10 nm thick channel devices but better scalability. In fact, at Lg = 40 nm, the intrinsic transconductance is about the same in both transistors. It seems reasonable to expect that for shorter gate lengths, the thin channel device will surpass the thicker designs in terms of intrinsic transconductance as it should continue to scale much better.

Fig. 6 Subthreshold swing of InAs HEMTs with tch = 5 nm and 10 nm as well as In0.7Ga0.3As HEMTs with tch = 13 nm as a function of Lg.
In0.7Ga0.3As HEMTs : tch = 13 nm InAs HEMTs : tch = 10 nm

DIBL [mV/V]

Lg [nm]
Fig. 7 DIBL of InAs HEMTs with tch = 5 nm and 10 nm as well as In0.7Ga0.3As HEMTs with tch = 13 nm as a function of Lg.
3 In0.7Ga0.3As HEMT : tch = 13 nm InAs HEMT : tch = 10 nm InAs HEMT : tch = 5 nm 4.0 3.5 3.0 gm [mS/m] 2.2.0 1.5 1.0 VDS = 0.5 V 80 Lg [nm] 200 0.5 gmi [mS/m]
Fig. 8 Intrinsic transconductance (gmi) and extrinsic transconductance (gm) as a function of gate length.
MICROWAVE CHARACTERISTICS
tch = 13 nm In0.7Ga0.3As HEMTs
tch = 10 nm InAs HEMTs Small-signal microwave performance was characterized tch = 5 nm InAs HEMTs 0.32 from 0.5 to 40 GHz. On-wafer open and short patterns were used to subtract pad capacitances and inductances from the 0.30 measured device S-parameters. Fig. 10 plots current gain (H21) and unilateral gain (Ug) as a function of frequency for the best 0.28 bias conditions at VGS = 0.2 V and VDS = 0.6 V for Lg = 40 nm thin and thick channel InAs HEMTs. Values of fT = 445 GHz 0.26 and fmax = 395 GHz have been obtained for the tch = 5 nm device while values of fT = 520 GHz and fmax = 337 GHz have 0.24 been obtained for the tch = 10 nm device. For the 5 nm channel device, fT is lower but fmax is higher. Low fT mainly comes 0.22 from a high source resistance and a higher gate capacitance without any higher intrinsic transconductance which reflects a Lg [nm] lower velocity. The higher fmax is due to the improved output * conductance (go) characteristics which arise from the reduced Fig. 9 Effective source resistance Rs as a function of Lg impact ionization and strong electron confinement. This is obtained through the gate current injection technique. shown in Fig. 11 which graphs the output conductance (go) as 40 1.0 a function of ID for three difference devices with Lg = 40 nm. tch = 5 nm tch = 10 nm H21 devices devices As ID increases, 5 nm thick channel InAs HEMTs exhibit 445 GHz 520 GHz fT much better output conductance (go) than the 10 nm thick fmax 395 GHz 337 GHz InAs HEMTs.

R s [Ohm.mm]

CONCLUSION
We have demonstrated 40 nm InAs HEMTs with a 5 nm thick channel. The devices show excellent short-channel effects and scalability although their performance suffers from an increased source resistance. In particular, 40 nm devices exhibits S = 72 mV/dec, DIBL = 72 mV/V, and ION/IOFF = 2.5 x 104. These encouraging results stem from the combination of the outstanding transport properties of InAs and the tight electron confinement afforded by the thin channel. But there are trade-offs in the thin channel approaches which are related to degraded transport properties and access resistance. However, future self-aligned gate (SAG) device architectures should be able to mitigate these problems. This work suggests that future thin InAs channel MOSFETs have the potential for scaling to very small dimensions.

H21 & UG [dB]

VDS = 0.6 V UG VGS = 0.2 V Lg = 40 nm

Frequency [GHz]

0.0 1k
Fig. 10 Microwave characteristics of both types of 40 nm InAs HEMTs with tch = 5 nm and tch = 10 nm.

REFERENCE

[1] R. Chau et al., IEEE Tran. Nanotechnol., pp. 153, 2005. [2] D.-H. Kim et al., IEEE TED, pp. 2546, 2008. [3] D.-H. Kim et al., IPRM, PP. 132, 2009. [4] D.-H. Kim et al., IEDM, pp. 146, 2008. [5] K. Uchida et al., IEDM, pp. 633, 2001. [6] D.-H. Kim et al., IEDM, pp. 629, 2007. [7] D. R. Greenberg et al., IEEE TED, pp. 1304, 1996.
Output conductance [mS/mm]

0.8 tch = 10 nm 0.6

tch = 5 nm

ACKNOWLEDGEMENTS

This work was sponsored by Intel Corporation and FCRPMSD at MIT. Device fabrication took place at the facilities of the Microsystems Technology Laboratories (MTL), the Scanning Electron Beam Lithography (SEBL) and the NanoStructures Laboratory (NSL) at MIT.

tch = 13 nm

0.0 0.2

0.4 ID [mA/mm]

Fig. 11 Output conductance (go) characteristics as a function of ID for three different Lg = 40 nm devices at VDS = 0.5 V.