33-228

Electronics

Spring 2011
Version of April 27, 2011
Lab 11: Digital Circuits and Logic Gates
Reference Reading: Chapter 7, Sections 7.4, 7.5, 7.6, 7.7 and 7.8. Time: Two lab periods will be devoted to this lab. Goals 1. Become familiar with the operation of simple logic gates. 2. Be able to set up and use a ip-op. 3. Understand what a switch de-bouncer does. 4. Be able to set up and use a 555 clock chip. 5. Be able to design and construct a digital counter. 6. Be able to construct a shift register circuit.

Introduction

In this lab, we will become familiar with logic gates and the use of more complicated logic circuits. We will also set up a clock circuit and use it to drive a counting circuit. The logic gates that we will be using come in rectangular packages called DIPs (dual in-line packages) as shown in Figure 1. The pin numbering scheme is standard over all such chips and is indicated in the gure. Not only will the IC have inputs and outputs related to the logic gates inside, it will also have an external power (VCC ) and ground connections. As with op-amps, these power connections are not typically shown in circuit diagrams, but are crucial to the operation of the chip.
Figure 1: The pin numbering scheme on rectangular IC packaging. The tab as indicated by the dark oval in the diagram tags the end of the chip with the lowest and highest pin numbers.
Preliminary Lab Questions
There is no preliminary work in this lab.

Equipment and Parts

In this lab we will utilize the following equipment. This equipment is located at your lab station. 1. The Tektronix TDS 2012B digital oscilloscope. 2. Two P2220 probes for the oscilloscope. 3. One USB memory stick which is no larger than 2GB. 4. The Interplex Electronics 1200CA-1 power brick and bus connector. 5. The Stanford Research Systems DS335 signal generator. 6. One BNC to alligator cable. 7. The Metex 4650 digital meter. 8. The Global Specialities PB10 proto-board (see Appendix ?? for a description). You will also need the following components in order to carry out this lab. It makes more sense to get them as you need them, rather than all at once before the start of the lab. 1. Eight 220 resistors. 2. Two 1 k resistors. 3. Five 1% 20 k resistors. 4. One 7400 Nand Chip. 5. One 7402 Nor Chip. 6. One 555 Clock chip. 7. Eight LEDs. 8. Two single-pull, double-throw switches. 9. Additional resistors and capacitors you choose to match your circuit designs. 2

Procedure

Logic Gates
In this section we will verify the functioning of simple logic gates. The operation of logic gates are specied by truth tables as shown in the text. In order to verify the operation of a gate it is necessary to measure the output for all possible combinations of inputs. In this section we will verify the truth table for the 7400 NAND gate and the 7402 NOR gates ( pin-outs shown in Figure 3). The specications sheets for these two gates can be found on the course web site. Note that the pin conguration for the two integrated circuits is dierent. You will nd that each of the ICs that we use are so-called quad packs, meaning that they each contain four independent gates. We will only need to measure one of the gates in each IC. While we could simply test this with a 5 V power supply and a DVM, we will build a somewhat more sophisticated circuit for this. We will us a 5 V DC power supply and a single ground connection to power the IC. We will also use the 5 V supply to provide the logic signals to the IC. To do this, we will us a pair of single pole double throw switches (SPDT) to switch the gate inputs between the supply level and ground. It is important to note that for logic inputs we must use either 5 V or 0 V. We cannot simply let an input oat if we want 0 V. The correct wiring is indicated in Figure 2.

Figure 2: Two single pole double throw switches which are used to control the input to a NAND logic gate. The output is then measured to the right of the gate.

! !

Output

1A 1B 1Y 2A 2B 2Y GND

VCC 4B 4A 4Y 3B 3A 3Y

1Y 1A 1B 2Y 2A 2B GND

VCC 4Y 4B 4A 3Y 3B 3A
Figure 3: The pin out of the 7400 (left)and 7402 (right) chips. These each have four gates, with inputs A and B and output Y. Note that they are not pin compatible. 3
You could use either the scope or an LED to observe the output. In this lab, we will measure the output of the logic gate using an LED. When using LEDs to observe the output of TTL logic, be sure to put them in series with current-limiting resistors. This limits the maximum current to around 10 mA and will protect the output ports of the gates. Such a circuit is shown in Figure 4, we can have the LED on either when the output is high or when it is low, depending on which conguration we use. In fact, we could also connect LEDs to the two inputs to the gate as well. In such a case, we could easily read o the truth table for our logic gates.
Figure 4: Current limiting resistors should be used in series with LEDs. (left) LED lights when output high. (right) LED lights when output low. Use the circuits to measure the truth tables for both the NAND and NOR gate as indicated above. Demonstrate that it agrees with what is listed in your text book. In order to see how fast these ICs are and how clean the signals are at high frequency, replace one of the switches with the DS335 (5V peak-to-peak, 2.5V oset square wave) and drive the circuit at high speed. Tie the second input either to ground or to 5V so that the DS335 switches the output, then look at the output on your scope. Can you deduce a rough estimate for the maximum clock rate at which such circuits can be used?

5V 220

RS Flip Flops
A ip-op circuit is a memory circuit. It can be set into two possible output states. A common holding input will then keep both of these output states until some input changes. In this sense, 4
the ip-op can hold one bit of informationeither a 0 or a 1. The simplest of the ip-op circuits is an RS ip-op. In an RS ip-op, the R stands for RESET and the S stands for SET. They can be thought of as either SETting the output to 1 or RESETting the output to 0. Procedure An RS ip-op can be built using two NAND gates as shown on the left-hand side of Figure 5. While the circuit diagrams in this section look deceptively simpleno resistors, no capacitors, no inductorsthey are not. You will nd it necessary to be very careful in wiring the circuits as there are lots of wires and interconnections. At this point, we will note that a NAND and an inverted OR are the same thing. This amounts to an application of DeMorgans theorem. If you switch where the inverting circles are (between inputs and outputs ) and switch between OR and AND, you have the same thing you started with. Show that the truth table for both a NAND gate and an inverted OR gate are the same.

Figure 5: The left-hand circuit shows an Reset-Set (RS) ip-op built from two NAND gates. By DeMorgans Theorem, this can be shown to be logically equivalent to the circuit on the right which has the negated R and S going into two OR gates. We will now build an RS ip-op using the 74xx00 NAND gate that we used earlier. Dont forget to wire up the +5 V and ground to your gate. SETing this circuit makes the Q output high (and the Q output low). RESETting reverses this. Keeping the SET and RESET signal o (which means at the supply voltage) leaves the circuit in its previous state. So the normal state of the circuit is to have both inputs high. In this state, the output remembers which input was last toggled from high to low and back to high again. Any number ( 1) of such toggles yields the same output. As soon as the opposite input is toggled to low, the output switches and stays the same when this input is returned to the high state. You can use the switch set-up you used above to toggle the inputs to low and back to high. Verify the memory feature of this circuit and the ability to set outputs to a desired state. Write out the values of the four inputs to the two gates, for each of the four possible SET/RESET input combinations. What happens when both the SET and RESET signals are present at the same time? (Demonstrate the memory eect of this circuit.) A Switch De-bouncer When we use a switch in a circuit, we nominally assume that its output will be a perfect step function. Either going from low to high or from high to low, and then remaining. Unfortunately, the mechanical nature of many switches leads to a situation where the process of mechanically opening or closing a switch actually causes the switch to 5
bounce, and the output oscillates many times before settling in to the desired state. In many situations, this is not desirable. An RS ip op can be used to de-bounce a switch. Once a RS ip-op has changed states, it will not change back unless the other input is toggled. Because a switch does not actually bounce back and forth between the two inputs, we can use an RS ip-op to ignore the bounce. Such a circuit is shown in Figure 6.

Figure 6: An RS ip-op used to de-bounce the output from a switch. Once the ip-op changes state, it will remain in the new state, independent of whether the switch bounces. Build the de-bounce circuit shown in Figure 6 and demonstrate that it does function as a switch. To see the de-bouncing eect, you can look at the input to the Set on one scope trace and the Q output on the other. Note what you observe in your lab book.

2H e

+5 V 1 k

Clocks

Digital electronics does not normally sit in some xed state, but rather performs logic operations on input to produce output. The rate at which these operations are performed is dened by an external clock. A typical processor chip for a computer has a rating that is in GigaHertz that indicates the clock speed. While we will not be doing such high-speed electronics, we will set up a clock in this lab and then use its output to drive a circuit. We will us a so-called 555 chip for this. This is a very common chip whose pin-out has been standardized over all vendors. This is shown in Figure 7. The circuit inside the 555 is shown in Figure 8. A detailed discussion of how this works can be found in section 7.6 in your textbook. The basic idea is to use an RC circuit to dene a characteristic time, RC , at which the clock ticks. However, we have somewhat more control in that we can also control what fraction of the clock period which is high and that which is low, fhigh and flow. This functionality can be achieved using two resistors and a capacitor which are hooked up externally to the 555. The appropriate circuit is shown in Figure 9. In terms of R1 , R2 and C, it can be shown that the period of the clock is T555 = ln(2) (R1 + 2R2 ) C. 6
Ground 1 Trigger 2 Output 3 Reset 4
8 VCC 7 Discharge 6 Threshold 5 Control Voltage
Figure 7: The pin-out of the 555 clock chip.

VCC

xyy z Threshold 1 VCC 3
Discharge xyy z Trigger

2H e

Figure 8: The circuit inside the 555, showing the two comparators and RS ip-op. The ln(2) comes from the exponential decay of an RC circuit and what fraction of the characteristic time it takes to fall below some threshold. In addition to the period, we have the high and low fractions. These are given as flow = fhigh = which are an apparent voltage divider. Procedure Before proceeding, we note that you will be using the clock circuit in this part of the lab to drive the circuits in the next two sections. DO NOT DISASSEMBLE YOUR CLOCK CIRCUIT. It is also advisable that you try to build your clock circuit as close to one end of your proto-board as possible. Otherwise, you will run out of board real estate later in the lab. In this lab, we would like to set up our 555 chip to have a period of about 1 second and to have the high fraction be about twice the low fraction. Before starting, use the high and low 7 R2 R1 + 2R2 R1 + R2 R1 + 2R2

Figure 9: A 555 clock IC in a circuit to produce a clock output signal with period T = 0.693 (R1 + 2R2 ) C. The output is on the Clock line. fractions to nd the relative size of the two resistors. Using the relation that you derived, it is possible to calculate the needed capacitance for a specied resistance to yield the correct period. Work out several possible values that use dierent orders of magnitudes of the capacitance, (e.g F , 10s of F , 100s of F and 1000s of F. Based on the values you get, justify your decision for your nal choice. At this point, inventory the capacitors that are available in lab. Choosing one that we have, determine the values of the needed resistances and see how close you can get to them. Once you have all your components (measured), build the circuit shown in Figure 9 and measure its output. Does it have the expected period. Finally, add an LED to the output of your clock chip (Figure 4) and let the lights ash.
} H || 2H 2 xyyyz| 3I |{ f

The Binary Counter

In addition to the RS ip-op, there are other types of ip-op circuits. In this section, we will use a so-called JK ip-op (see section 7.5.2 in your textbook) to build a counting circuit. The JK ip-op has three main inputs, J, K and a clock. It also has a clear which allows it to be put in some default state. Depending on the levels at the J and K inputs, the rising edge of the clock ( or the falling edge, in some chips) causes the output Q to change. The truth-table for the JK ip-op is shown in Table 1. We rst note that CLR is high (or in the table, the NOT CLR is low), the ip-op is put into a default state. In normal operation, the CLR is low (the NOT CLR is high). In normal operation, if both J and K are low, then clocking the circuit leaves the Q and Q outputs unchanged. If one of J or K is high, and the other is low, then Q is set to the value of J and Q is set to the value of K. If both J and K are high, then clocking the circuit causes Q to be set to what Q was before the clock pulse, while Q will be set to the former value of Q. In this mode, we say that it toggles the value of Q. In this lab, we will be using the 7473 chip 8
which has a NOT CLR input. The truth table for this chip is given in Table 1. Q H n1 Q L H Qn1

CLR L H H H H

CLK x falling falling failing falling

J x L H L H

K x L L H H

Q L Qn1 H L Qn1

Comment Default Hold Set ReSet Toggle
Table 1: The truth table for the JK ip-op. In this case, the ip-op responds to the falling edge of the clock pulse. In the toggling mode (both J and K high), it is easy to show that the output changes state at one-half the frequency of the clock input. We will take advantage of the toggling output mode to build a digital counter circuit. The basic idea being that output of one JK ip-op will serve as the clock input to the next one. As such,each subsequent ip-op will be clocked at one-half the frequency of the previous one. Procedure We will use the 7473 dual JK ip-op (spec sheet is on the course web site) to build an eight-bit binary counter(pin-out shown in Figure 11). We will use the 555 clock circuit that you set up earlier as the clock input to our circuit.

+ Q0 + Q1

J input clock clk K

J clk K

Figure 10: A two-bit binary counter built using JK ip-ops. This can easily be extended to more bits. Start by setting up the circuit shown in Figure 10 for a two-bit counter. You will nd that the 7473 is a dual-pack (it has two ip-ops on a single chip). Hook the outputs, Q0 and Q1 to LEDs as done earlier in the lab. Use the 555 circuit that you set up as the clock input for the counter. Once you have veried that the circuit is indeed counting, add two more bits to your circuit to build a four-bit counter. You could also try using a switch, rather than your 555 clock, for the input to the counter. However, you would nd that switches produce erratic output due to contact bounce as discussed above. The counter (or any logic circuit) may see many logic pulses, rather than a single pulse, as the mechanical switch makes or breaks contact. This is one example where the de-bouncer 9
discussed above can be used as input to the circuit. Such a de-bouncer circuit is commonly used on momentary push-button switches which change state when they are pressed and released.

A B Q0 Q1 Q2 Q3 GND

1CLK 1CLR 1K VCC 2CLK 2CLR 2J

1J 1Q 1Q GND 2K 2Q 2Q

VCC Q7 Q6 Q5 Q4 MR CP
Figure 11: (Left) The pin-out of the SN7473 JK-ip-op chip. (Right) The pin-out of the SNLS164 8-bit shift register chip. Both the A and B inputs need to be high to set Q0. CP is the clock input and M R is the master reset. The outputs are Q0 through Q7.

The Shift Register

A shift register is a circuit that shifts bits by one bit on each input clock pulse. Section 7.8 of your text book shows how a simple shift register can be built using D ip-ops. In this section, we will use an SN74LS164, which is an 8-bit shift-register chip, rather than building our own. The pin-out for this chip is shown in Figure 11 and its truth table is given in Table 2. Operating Mode Reset Shift Inputs MR A L X H L H L H H H H Outputs Q0 Q1-Q7 L L-L L Q0-Q6 L Q0-Q6 L Q0-Q6 H Q0-Q6

B X L H L H

Table 2: The truth-table for the SN74LS164 8-bit shift register. If the reset line goes low, the chip is reset. If the reset is high, then the contents of Q0 to Q7 are clocked through the shift register. If both A and B are high, then Q0 is turned on during the clock pulse. The shift-register has four inputs and eight outputs. The clock input is labeled CP and there is a reset input labeled M R. If the reset is pulled low, then all of the outputs (Q0 to Q7) are set to zero. As long as the reset is held high, the shift register will clock the bits from lowest (Q0) to highest (Q7), with one shift on each clock pulse. Finally, there two inputs A and B allow one to set the lowest bit high. As long as one of these (A or B) is held low, Q0 will not be set. If both are high, then Q0 will go high on the next clock pulse. 10
Procedure In this section, we are going to set up an eight bit shift register which is driven by the 555 clock circuit from above. Each of the eight bits needs to be connected via an LED to ground. We will then connect the B input to VCC and use a single pole double throw switch to toggle the A input between ground and VCC (see Figure 2). Finally, we need to connect the reset (M R) to VCC. To each of the eight outputs, connect an LED as we did in the left-hand circuit of Figure 4. It is advisable that you sketch the circuit which you want to build in your lab book before starting. You will also need to lay out the real estate on you circuit board carefully so that things t.

33-228

Electronics

Spring 2011

Version of March 22, 2011
Lab 5: AC to DC Conversion and Power Supplies
Reference Reading: Chapter 4, Sections 4.5 and 4.6. Time: Two lab periods will be devoted to this lab. Goals: 1. Understand the use of diodes to convert AC signals with no DC component into oscillatory signals with appreciable DC components. 2. Understand the use of lter circuits to obtain relatively clean DC voltages. 3. Become familiar with the regulation of various constant voltage supply circuits and the advantages of each.

Introduction

Almost any signal processing circuitry requires the establishment of constant bias voltages. Starting with the 60Hz voltage supply from the power company, how do instruments obtain these various DC supply voltages? We will investigate a sequence of circuits for doing this. They all rely on non-linear elements that respond dierently to dierent parts of the AC voltage signal. First, we need to establish some notation (briey addressed in Lab 2). AC sinusoidal signals are frequently referred to in terms of their RMS voltages. RMS stands for root-mean-square or, more explicitly, the square-root of the average (or mean) of the squared voltage. Note that if v(t) = V cos t, then the average voltage, v= 1 T

dt v(t),

is zero, when we take the average over an integer number of periods. The RMS voltage is Vrms 1 = T
since the average value of the cos2 (t) is 1/2.1 We reach the conclusion that V Vpp Vrms = = . 2
Recall that cos2 = (1 + cos 2)/2 (draw yourself a picture to verify this); the second term has average zero and the constant term clearly has an average of 1/2.
Thus, the 110 Volt power outlet (where the 110 Volts refers to the RMS value) corresponds to voutlet (t) = 2(110V ) cos t = 155 cos t Volts or 310 Volts peak-to-peak. One justication for using RMS voltages is that the average power delivered to a resistive load is 1 P = T

V2 V2 cos2 t = rms ; R R

as far as power dissipation is concerned, Vrms acts the same as the corresponding DC voltage. While the oscilloscope displays the details of instantaneous waveforms, typical digital volt meters (DVM) such as the Metex meters read RMS voltages when set on AC Volts scales. The latter meters are only reliable for sinusoidal signals with frequencies in the vicinity of 60 Hz. In this lab, you will use a transformer to generate a roughly 14 Volt (RMS) AC signal from which you will obtain various approximations to a constant DC voltage. While the transformer steps down the 110 Volt line voltage, the output can supply large currents! Be sure to wire and check your circuit before plugging the transformer in and be sure that all three output wires from the transformer are plugged into terminal posts on your protoboards. The secondary side of the transformer is center tapped; we will use one side and the center tap the other wire should just be plugged into a terminal post which is not wired to anything:
14 V center 110 V tap 14 V

Use this as output

Figure 1: A transformer showing two inputs and a center tap on the output. In this lab, we use the center tap and one of the outer taps. One advantage of using a transformer (beyond the obvious reduction in voltage and, thus, danger) is that while the primary voltage oscillates relative to ground potential, the secondary can oat to any necessary level (within the limits of insulation used inside the transformer). This is a useful feature for the measurements you will make on the diode bridge circuits used below. Note that when you measure a voltage signal using the oscilloscope, you are grounding a point in the circuit. You need to think before doing this: you may alter the functioning of the circuit signicantly and you could also cause large currents to ow through circuit elements thus generating a characteristic odor and smoke! You can measure across oating elements more or less with impunity. The Metex meters, on the other hand, are not grounded so they can be connected anywhere in a circuit regardless whether it is oating or not.
Preliminary Lab Questions
The work in this section must be completed and signed o by an instructor before you start working on the lab. Do this work in your lab book.

1. An ideal diode as a diode voltage of Vd = 0 V. If the voltage is above zero, current ows through the diode. If it is below zero, no current ows. If you place an ideal diode into an AC sinusoidal circuit, what is the shape of the output voltage across the diode? Sketch this as a function of time over one full cycle of the sine wave.
2. There is typically a 0.65 V drop across a practical diode. What will this do to the answer that you got in part 1?
3. In section 5.2.4, you will use an electrolytic capacitor. These capacitors have a positive and negative side. Which side of the capacitor corresponds to the large at line in the gure?

Equipment and Parts

In this lab we will utilize the following equipment. This equipment is located at your lab station. 1. The Tektronix TDS 2012B digital oscilloscope. 2. Two P2220 probes for the oscilloscope. 3. One USB memory stick which is no larger than 2GB. 4. The Stanford Research Systems DS335 signal generator. 5. One BNC to alligator cable. 6. The Metex 4650 digital meter. 7. The Global Specialities PB10 protoboard. You will also need the following components in order to carry out this lab. It makes more sense to get them as you need them, rather than all at once before the start of the lab. 1. Four 1N4004 diodes. 2. One transformer. 3. One LM7805 Voltage regulator chip. 4. Additional resistors and capacitors you choose to match your circuit designs.

Procedure

Transformer
Observe, on the oscilloscope, the output waveform of the transformer. Note the frequency and amplitude. Measure this same signal using the Metex meter. Is the Metex reading consistent with the observed waveform? Document what you observe in your lab notebook.

Half wave rectier.

A simple series connected diode which blocks half the AC waveform leaves you with a nite DC or average level. Use the oscilloscope to observe the output waveform of the circuit shown in Fig. 2.
Can you compute the average, or DC, voltage? Is what you see consistent with part (1) and with the diode curves you measured in Lab 1?
Use a load resistor of RL = 1k to make your measurement. Draw a sketch of what you observe in your lab notebook (or capture a sweep and make a plot of the data).

vi RL

Figure 2: A half-wave rectier using a 1N4004 diode. The input voltage, vi , is the AC from the wall outlet.

vi Cf
Figure 3: A full-wave rectier using four 1N4004 diodes, and an electrolytic ltering capacitor. The input voltage, vi is the AC from the wall outlet.

Full wave rectier.

The diode bridge circuit shown in Fig. 3 directs current always in the same direction through the load. Verify this statement by tracing the current path available when the top transformer terminal is positive (and negative) with respect to the bottom terminal. Construct the circuit (without the capacitor Cf ) and observe the waveform. What, roughly, is the DC, or average, voltage?
Conrm your expectation by switching the oscilloscope input to the AC coupled setting. How does this signal change when you use a 1k vs a 10k load resistor? Draw a sketch of what you observe in your lab notebook (or capture).
Full wave rectier with ltering
To smooth the output and better approximate a constant voltage, place a capacitor across the output as shown in Fig. 3.
What is the relevant quantity which determines how constant the voltage is?
Which resistance sets the characteristic time of this low-pass lter?
Do you want a small or a large capacitor? Why?
Try Cf = 0.2F , then a 25F electrolytic capacitor (be sure to observe the polarity here!). In each case, measure the ripple voltage (peak-to-peak uctuation). How does the DC voltage vary with load i.e., characterize the voltage regulation?
Integrated circuit regulator
The simplest way to make a good DC supply for real circuits is to build a rudimentary DC supply such as the one in Sec. 4.4 and then use an integrated circuit (IC) voltage regulator to stabilize it. Construct the circuit shown in Fig. 5 using an LM7805 which is a 5 Volt supply regulator which is sketched in Figure 4. There is also a specication sheet available on line. The diagram above looks at the 7805 from the labelled side, and the three pins are as labeled. We use this IC as a black box and just empirically note the quality of performance (the LM7805 costs $1.18). How does the DC voltage vary with load? You probably own several power supplies of this sort in various pieces of electronics. 7
Output Gnd Input Top View

Side View

Figure 4: The LM7805 voltage regulator pin out.

vi

LM7805
out vo Cf gnd RL

in

Figure 5: A full-wave rectier with four 1N4004 diodes, an electrolytic ltering capacitor, and an LM7805 regulator chip. The input voltage, vi is the AC from the wall outlet.