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Omron CP1H CPU

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webking 2:27am on Sunday, May 16th, 2010 
Works well as just an ethernet drive or works well as just a USB drive. SMB (Samba) Server, FTP, easy to use HTTP admin function. Excellent product overall!! None what so ever!

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Documents

doc1

RS-422A (Expansion) Inverter, etc.
Option Boards for Serial Communications

Appearance

Name RS-232C Option Board

Model CP1W-CIF01

Port One RS-232C port (D-Sub, 9 pins, female)
Serial communications modes Host Link, NT Link (1: N mode), No-protocol, Serial PLC Link Slave, Serial PLC Link Master, Serial Gateway (conversion to CompoWay/F, conversion to Modbus-RTU), peripheral bus

RS-422A/485 Option Board

CP1W-CIF11
One RS-422A/485 port (terminal block for ferrules)
System Configuration Unit Consumption Currents
Unit CPU Unit Model CP1H-XA40DR-A CP1H-XA40DT-D CP1H-XA40DT1-D CP1H-X40DR-A CP1H-X40DT-D CP1H-X40DT1-D Current consumption 5 V DC 0.430 A 0.510 A 0.510 A 0.420 A 0.500 A 0.500 A 24 V DC 0.180 A 0.120 A 0.150 A 0.070 A 0.010 A 0.020 A
External power supply 0.3 A max. ----0.3 A max. -----
(1) The current consumption of the following is included with the current consumption of the CPU Unit: CP1W-ME05M Memory Cassette, CP1W-CIF1 or CP1W-CIF11 Option Board, and CP1W-EXT01 CJ Unit Adapter. (2) CPU Units taking a DC power supply do not provide an external power supply.

System Expansion

A maximum of seven CPM1A Expansion Units or Expansion I/O Units can be connected to a CP1H CPU Unit. This allows for the expansion of various functions such as I/O points or temperature sensor inputs.
A maximum of 7 CPM1A-series Expansion I/O Units or Expansion Units can be added.
When CP1W-CN811 I/O Connecting Cable is used, the cable length can be extended by up to 80 cm, enabling installing the Units in two rows.
SYSMAC CP1H IN BATTERY PERIPHERAL

L1 L2/N COM 00 POWER 11

CP1W-CN811 I/O Connecting Cable
Up to seven Units can be added, and the maximum number of I/O points per Unit is 40, so the maximum total number of expansion I/O points is 280.
System Configuration Maximum Normal I/O Points
Type Power supply voltage 100 to 240 VAC 24 VDC Model Built-in normal inputs 24 DC inputs

X (Basic CPU Units)

CP1H-X40DR-A CP1H-X40DT-D CP1H-X40DT1-D
Max. Max. Max. total number of number of I/O points Expansion expansion I/O Units points 16 relay outputs 320 (7 Units 40 points) 16 transistor outputs (sinking) 16 transistor outputs (sourcing) 16 relay outputs 16 transistor outputs (sinking) 16 transistor outputs (sourcing) 8 transistor outputs (sinking)

Built-in normal outputs

XA 100 to (CPU Units with 240 VAC built-in analog 24 VDC I/O terminals)
CP1H-XA40DR-A CP1H-XA40DT-D CP1H-XA40DT1-D
Y (CPU Unit with dedicated pulse I/O terminals)

24 VDC

12 DC inputs
CPM1A Expansion I/O Units
Appearance Model CPM1A-40EDR CPM1A-40EDT CPM1A-40EDT1 CPM1A-20EDR1

COM NC IN 00 CH CH 11

Normal inputs 24 VDC: 24 inputs
Normal outputs 16 relay outputs

Weight 380 g max.

16 transistor outputs (sink- 320 g max. ing) 16 transistor outputs (sourcing) 8 relay outputs 8 transistor outputs (sinking) 8 transistor outputs (sourcing) None 200 g max. 300 g max.
OUT CH CH NC COM COM COM 03 COM 06

CPM1A-20EDT CPM1A-20EDT1

24 VDC: 12 inputs

CPM1A-8ED

COM 00 IN CH 03

24 VDC: 8 inputs None

04 COM 07
CPM1A-8ER CPM1A-8ET CPM1A-8ET1
8 relay outputs 250 g max. 8 transistor outputs (sinking) 8 transistor outputs (sourcing)

CPM1A Expansion Units

Name and Model appearance Analog I/O Units CPM1A-MAD01
Specifications 2 analog inputs 1 analog output 0 to 10 V/1 to 5 V/4 to 20 mA 0 to 10 V/10 to +10 V/4 to 20 mA 0 to 5 V/1 to 5 V/0 to Resolu10 V/10 to +10 V/0 tion: 6,000 to 20 mA/4 to 20 mA 1 to 5/0 to 10 V/10 to +10 V/0 to 20 mA/ 4 to 20 mA Resolution: 256

Weight 150 g max.

CPM1A-MAD11
2 analog inputs 1 analog output
Name and appearance Temperature Sensor Units
Model CPM1A-TS001 CPM1A-TS002 CPM1A-TS101 CPM1A-TS102
Specifications 2 inputs 4 inputs 2 inputs 4 inputs Thermocouple input K, J Platinum resistance thermometer input Pt100, JPt100

Weight 250 g max.

OUT CH NC NC COM COM COM 03 COM 06 CH

DeviceNet I/O Link Unit

CPM1A-DRT21
As a DeviceNet Slave, 32 inputs and 32 outputs are allocated.

200 g max.

CompoBus/S I/O Link Unit

CPM1A-SRT21

As a CompoBus/S slave, 8 inputs and 8 outputs are allocated.
Number of Allocated Words and Current Consumption for Expansion Units and Expansion I/O Units
Unit Model Number of allocated words Input Output Current consumption (mA) 5 VDC 24 VDC 0.080 A 0.160 A 0.103 A 0.130 A 1 None None 1 0.018 A 0.026 A 0.075 A None 0.066 A 0.083 A 0.040 A 0.090 A --0.044 A ----0.044 A --0.066 A 0.110 A 0.059 A

Expansion I/O Units

40 I/O points 24 inputs 16 outputs 20 I/O points 12 inputs 8 outputs 8 inputs 8 outputs
CPM1A-40EDR CPM1A-40EDT CPM1A-40EDT1 CPM1A-20EDR1 CPM1A-20EDT CPM1A-20EDT1 CPM1A-8ED CPM1A-8ER CPM1A-8ET CPM1A-8ET1

Expansion Units

Analog I/O Units A/D: 2 points D/A: 1 point Temperature Sensor Units Thermocouple inputs K/J Platinum resistance inputs Pt/JPt 8 inputs 8 outputs 32 inputs 32 outputs
CPM1A-MAD01 CPM1A-MAD11 CPM1A-TS001 CPM1A-TS002 CPM1A-TS101 CPM1A-TS102 CPM1A-SRT21 CPM1A-DRT21

Flash Memory Data Transfers

Built-in Flash Memory

Writing to Flash Memory
Data User program and parameter data Transfer method This data is automatically transferred from RAM to flash memory when a project is transferred from the CX-Programmer, when the data is written to RAM from a PT or other external device, or when the data is transferred from a Memory Cassette. This data is transferred to flash memory only when the transfer is specified from the CX-Programmer. This data is written to flash memory when a project is transferred from the CX-Programmer and transferring comment memory is specified. This data is written to flash memory when a project containing one or more function blocks is transferred from the CX-Programmer.
DM Area data Comment memory data Function block source data
Write operation from CX-Programmer or automatic transfer from Memory Cassette at startup. CPU Unit RAM User program area Automatic write Write Built-in flash memory User program area
Write Parameter area Automatic write Parameter area

I/O memory area

Write operation to flash memory DM Area initial values
DM Area Write Battery Backup Write (comment memory specified) Write
Comment memory area FB source memory area

FB = Function block

Reading from Flash Memory
Data User program and parameter data DM Area data Comment memory data Function block source data
CPU Unit RAM Built-in flash memory
Read method This data is automatically read to RAM when power is turned ON. Reading this data when power is turned ON can be enabled or disabled in the PLC Setup. Not read.
Power ON User program area Auto read Power ON Parameter area Auto read

User program area

Parameter area
When power-ON transfer is specified in PLC Setup. DM Area initial values
DM Area Auto read Battery Backup
Comment memory area FB source memory area FB = Function block
Memory Cassette Data Transfers
Data User program and parameter data Comment memory and function block source data DM Area data Method Data is written to a Memory Cassette using write operations from the CX-Programmer. Source Data in the built-in flash memory is written to the Memory Cassette. Either of both of the following can be transferred to the Memory Cassette. Data in the built-in flash memory. Data in RAM.
Memory Cassette write operation from CX-Programmer Built-in flash memory Memory Cassette

I/O refresh Input Input ON (Interrupt to CPU Unit) Cycle time

Instruction execution

Instruction execution Instruction execution

Output ON

Minimum I/O response time
Maximum I/O Response Time
The I/O response time is longest when data is retrieved immediately after I/O refresh period of the CPU Unit. The maximum I/O response time is calculated as follows: Maximum I/O response time = Input ON delay + (Cycle time 2) + Output ON delay
Maximum I/O response time
Calculation Example Conditions: Input ON delay Output ON delay Cycle time 1 ms 0.1 ms 20 ms
Minimum I/O response time = 1 ms + 20 ms + 0.1 ms = 21.1 ms Maximum I/O response time = 1 ms + (20 ms 2) + 0.1 ms = 41.1 ms
Computing the Cycle Time Input Response Times
Input response times can be set in the PLC Setup. Increasing the response time reduces the effects of chattering and noise. Decreasing the response time allows reception of shorter input pulses, (but the pulse width must be longer than the cycle time).
Input response time Input response time Input Input The pulse width is less than the input response time, so it is not detected. I/O refresh CPU Unit
Name Input constants Description Settings Input response times 00 hex: 8 ms 10 hex: 0 ms 11 hex: 0.5 ms 12 hex: 1 ms 13 hex: 2 ms 14 hex: 4 ms 15 hex: 8 ms 16 hex: 16 ms 17 hex: 32 ms Default 00 hex (8 ms)

Interrupt Response Times

The interrupt response time for I/O interrupt tasks is the time taken from when a built-in input has turned ON (or OFF) until the I/O interrupt task has actually been executed. The length of the interrupt response time for I/O interrupt tasks depends on the following conditions.
Item Hardware response Software interrupt response Interrupt response time Rise time: 50 s Fall time: 50 s Minimum: 98 s Maximum: 198 s + Wait time (See note 1.) Counter interrupts ----Minimum: 187 s Maximum: 287 s + Wait time (See note1.)

Input Interrupt Tasks

(1) The wait time occurs when there is competition with other interrupts. As a guideline, the wait time will be 3 to 153 s. (2) I/O interrupt tasks can be executed during execution of the user program (even while an instruction is being executed by stopping the execution of an instruction), I/O refresh, peripheral servicing, or overseeing. The interrupt response time is not affected by which of the above processing operations during which the interrupt inputs turns ON. I/O interrupts, however, are not executed during execution of other interrupt tasks even if the I/O interrupt conditions are satisfied. Instead, the I/O interrupts are executed in order of priority after the current interrupt task has completed execution and the software interrupt response time has elapsed.

The interrupt response time of input interrupt tasks is calculated as follows: Interrupt response time = Input ON delay + Software interrupt response time
Input Input ON delay (Interrupt signal retrieval) Software interrupt response time Interrupt task execution Input interrupt task response time Cyclic task execution (main program) The time from completing the ladder program in the input interrupt task until returning to cyclic task execution is 60 s. Ladder program execution time Return time from input interrupt task Next interrupt signal can be accepted.
Scheduled Interrupt Tasks
The interrupt response time of scheduled interrupt tasks is the time taken from after the scheduled time specified by the MSKS(690) instruction has elapsed until the interrupt task has actually been executed. The length of the interrupt response time for scheduled interrupt tasks is 1 ms max. There is also an error of 80 s in the time to the first scheduled interrupt (0.5 ms min.).
Note Scheduled interrupt tasks can be executed during execution of the user program (even while an instruction is being executed by stopping the execution of an instruction), I/O refresh, peripheral servicing, or overseeing. The interrupt response time is not affected by which of the above processing operations during which the scheduled interrupt time occurs. Scheduled interrupts, however, are not executed during execution of other interrupt tasks even if the interrupt conditions are satisfied. Instead, the interrupts are executed in order of priority after the current interrupt task has completed execution and the software interrupt response time has elapsed.

Scheduled interrupt time

Internal timer Software interrupt response time Scheduled interrupt task

External Interrupt Tasks

The interrupt response time for external interrupt tasks depends on the Unit or Board (CJ-series Special I/O Unit or CJ-series CPU Bus Unit) that is requesting the external interrupt task of the CPU Unit and the type of service requested by the interrupt. For details, refer to the operation manual for the Unit or Board being used.
Serial PLC Link Response Performance
The response times for CPU Units connected via a Serial PLC Link (master to slave or slave to master) can be calculated as shown below. If a PT is in the Serial PLC Link, however, the amount of communications data will not be fixed and the values will change. Maximum I/O response time (not including hardware delay) = Master cycle time + Communications cycle time + Slave cycle time + 4 ms Minimum I/O response time (not including hardware delay) = Slave communications time + 1.2 ms Here,

Types of Interrupt Functions
Input Interrupts (Direct Mode) Input Interrupts (Counter Mode) When one of the CPU Units built-in inputs goes from OFF to ON (or ON to OFF), the corresponding interrupt task is executed. Interrupt tasks 140 to 147 are allocated to the 8 input terminals used for the input interrupts. This function counts input pulses at one of the CPU Units built-in inputs and executes the corresponding interrupt task when the count reaches the SV. The maximum input response frequency for input interrupts (in counter mode) is 5 kHz. Scheduled Interrupts This function executes an interrupt task at a fixed time interval measured by the CPU Units built-in timer. The time interval units can be set to 10 ms, 1 ms, or 0.1 ms. The minimum timer SV is 0.5 ms. Interrupt task 2 is allocated to scheduled interrupt. High-speed Counter Interrupts This function counts input pulses with the CPU Units built-in high-speed counter and executes an interrupt task when the count reaches the preset value or falls within a preset range (target-value or zone comparison). An interrupt task between 0 and 255 can be allocated with an instruction. Refer to 5-2 High-speed Counters for details on high-speed counters. External Interrupts Wen a CJ-series Special I/O Unit or CPU Bus Unit is connected, an interrupt task between 0 and 255 can be specified and executed.
Interrupt Functions Creating an Interrupt Task Program
1. Select NewPLC1 [CP1H] Offline in the project workspace, right-click, and select Insert Program in the pop-up menu. A new program called NewProgram2 (unassigned) will be inserted in the project workspace.
2. Right-click NewProgram2 (unassigned) and select Properties from the pop-up menu to display the Program Properties Window.
3. Set the Task type in the Program Properties Window. In this example, interrupt task 140 was allocated to NewProgram2.
If you click the X Button in the upper-right corner of the window, you can create the program that will be executed as interrupt task 140. The programs allocated to each task are independent and an END(001) instruction must be input at the end of each program.

Interrupt Task Priority

The input interrupts (direct mode and counter mode), high-speed counter interrupts, scheduled interrupts, and external interrupts all have the same priority. If interrupt task A (an input interrupt, for example) is being executed when interrupt task B (a scheduled interrupt, for example) is called, task A processing will not be interrupted. Task B processing will be started when task A is completed. If two different types of interrupt occur simultaneously, they are executed in the following order:
External interrupt > Input interrupt (direct mode or counter mode) > High-speed counter interrupt > Scheduled interrupt
If two of the same type interrupt occur simultaneously, the task with the lower interrupt task number is executed first. Note If a user program is likely to generate multiple interrupts simultaneously, the interrupt tasks will be executed in the order shown above, so it may take some time from the occurrence of the interrupt condition to the actual execution of the corresponding interrupt task. In particular, it is possible that scheduled interrupts will not be executed in the preset time, so the program must be designed to avoid interrupt conflicts if necessary. If a memory address is processed both by a cyclic task and an interrupt task, an interrupt mask must be set to disable interrupts. When an interrupt occurs, execution of the cyclic task will be interrupted immediately, even during execution of a cyclic tasks instruction, and the partially processed data is saved. After the interrupt task is completed, processing returns to the cyclic task and the interrupted processing restarts with the data saved before the interrupt processing. If the interrupt task overwrites a memory address used by one of the interrupted instructions operands, that overwrite may not be reflected after the saved data is restored as processing returns to the cyclic task. To prevent an instruction from being interrupted during processing, enter DI(693) just before the instruction to disable interrupts and EI(694) just after the instruction to enable interrupts again.

1. Connect an input device to input 0.00. 2. Use the CX-Programmer to set input 0.01 as an input interrupt in the PLC Setup. 3. Use the CX-Programmer to create the program to use for interrupt processing and allocate the program to interrupt task 141. 4. Use the CX-Programmer to set a high-speed counter SV of 00C8 hex (200 decimal) in A533. 5. Use the CX-Programmer to write MSKS(690) in the program.
@MSKS(690) 111 #0000 @MSKS(690) 111 #0003
Specifies input interrupt 1. Specifies up-differentiated pulses.
Specifies input interrupt 1. Specifies an incrementing counter, starts counting, and enables the input interrupt.
When execution condition W0.00 goes ON, MSKS(690) is executed to enable operation of the input interrupt in counter mode.
When CIO 0.01 goes from OFF to ON 200 times, processing of the cyclic task that is currently being executed will be interrupted and processing of interrupt task 141 will start. When the interrupt task processing is completed, processing of the interrupted ladder program will restart.
Counter SV (in A533) = 200 (00C8 hex) Counter PV (in A537)

Counting enabled.

Interrupt task 141 executed.

Scheduled Interrupts

This function executes an interrupt task at a fixed time interval measured by the CPU Units built-in timer. Interrupt task 2 is allocated to scheduled interrupt.
Set the PLC Setup. Write the ladder program. Write the program allocated to interrupt task 2 (scheduled interrupt task). Use MSKS(690) to specify the timer SV. Use the CX-Programmer to set the scheduled interrupt timer units in the PLC Setup.
Click the Timings Tab and set the input function to Scheduled Interrupt Interval (the scheduled interrupt timers units). The timing units can be set to 10 ms, 1 ms, or 0.1 ms. The scheduled interrupt timer SV is calculated by multiplying this interval setting by the timer SV set with MSKS(690).
Scheduled Interrupt Interval Setting
(1) Set a scheduled interrupt time (interval) that is longer than the time required to execute the corresponding interrupt task. (2) If the scheduled time interval is too short, the scheduled interrupt task will be executed too frequently, which may cause a long cycle time and adversely affect the cyclic task processing. (3) If an interrupt task is being executed for another interrupt (input interrupt, high-speed counter interrupt, or external interrupt) when the scheduled interrupt occurs, the scheduled interrupt will not be executed until the other interrupt task is completed. When different kinds of interrupts are being used, design the program to handle multiple interrupts smoothly. Even if two interrupts occur at the same time, the scheduled interrupts will continue as programmed, so the scheduled interrupt tasks will continue to occur at the scheduled times even if specific scheduled interrupts are delayed.

Input terminal block Word CIO 0 Bit 10 CIO to 11 --High-speed counter 2 (Phase Z or reset input) High-speed counter 1 (Phase Z or reset input) High-speed counter 0 (Phase Z or reset input) High-speed counter 2 (Phase A, Increment, or Count input) High-speed counter 2 (Phase B, Decrement, or Direction input) High-speed counter 1 (Phase A, Increment, or Count input) High-speed counter 1 (Phase B, Decrement, or Direction input) High-speed counter 0 (Phase A, Increment, or Count input) High-speed counter 0 (Phase B, Decrement, or Direction input) High-speed counter 3 (Phase A, Increment, or Count input) High-speed counter 3 (Phase B, Decrement, or Direction input) High-speed counter 3 (Phase Z or reset input) --Bit function when the high-speed counter is enabled by selecting Use high-speed counter @ in the PLC Setup
Y CPU Units Input Terminal Arrangement
High-speed counter 1 (Phase A, Increment, or Count input) High-speed counter 1 (Phase B, Decrement, or Direction input) High-speed counter 1 (Phase Z or Reset input) High-speed counter 2 (Phase B, Decrement, or Direction input)
High-speed counter 0 (Phase Z or Reset input) High-speed counter 0 (Phase B, Decrement, or Direction input) High-speed counter 0 (Phase A, Increment, or Count input)
High-speed counter 3 (Phase B, Decrement, or Direction input) High-speed counter 2 (Phase Z or Reset input)
+ NC A0+ B0+ Z0+ A1+ B1+ Z1+ COM Z05
High-speed counter terminals
High-speed counter 3 (Phase Z or Reset input)
High-speed counter 3 (Phase A, Increment, or Count input) High-speed counter 2 (Phase A, Increment, or Count input)
Input terminal block Word ------------CIO 0 Bit A0+ B0+ Z0+ A1+ B1+ Z1+ 10 CIO to 05 Bit function when the high-speed counter is enabled by selecting Use high-speed counter @ in the PLC Setup High-speed counter 0 (Phase A, Increment, or Count input) High-speed counter 0 (Phase B, Decrement, or Direction input) High-speed counter 0 (Phase Z or reset input) High-speed counter 1 (Phase A, Increment, or Count input) High-speed counter 1 (Phase B, Decrement, or Direction input) High-speed counter 1 (Phase Z or reset input) --High-speed counter 2 (Phase A, Increment, or Count input) High-speed counter 2 (Phase B, Decrement, or Direction input) High-speed counter 2 (Phase Z or reset input) High-speed counter 3 (Phase A, Increment, or Count input) High-speed counter 3 (Phase B, Decrement, or Direction input) High-speed counter 3 (Phase Z or reset input) ---

Handling Unit Errors

When an error occurs in the built-in analog I/O system, analog input data will be set to 0000 and the analog output will be set to 0 V or 0 mA. If a CPU error occurs, the analog output will be set to is set to 0 V or 0 mA even if the output range is 1 to 5 V or 4 to 20 mA. For any other fatal errors in the CPU Unit, 1 V or 4 mA will be output if the output range is 1 to 5 V or 4 to 20 mA.
!Caution If an interrupt task program is executed continuously for more than 6 ms, the built-in analog function will not operate properly and a Built-in Analog Error will occur. When using the built-in analog function, design the system so that interrupt task programs are not executed too long or too frequently. Test the system thoroughly in trial operation before operating the system.
SECTION 6 Advanced Functions
This section describes all of the advanced functions of the CP1H that can be used to achieve specific application needs. 6-1 Serial Communications. 6-1-1 6-1-2 6-1-3 6-1-4 6-1-5 6-1-6 6-1-7 6-2 6-2-1 6-2-2 6-3 6-4 Overview. No-protocol Communications. Modbus-RTU Easy Master Function. Communications: Smart Active Parts and Function Blocks. Serial PLC Links. 1:N NT Links. Host Link Communications. Analog Adjuster. External Analog Setting Input. 370 371
Analog Adjuster and External Analog Setting Input.
7-Segment LED Display. Battery-free Operation. 6-4-1 6-4-2 Overview. Using Battery-free Operation. Overview. Mounting and Removing a Memory Cassette. Operation Using the CX-Programmer. Memory Cassette Data Transfer Function.
Memory Cassette Functions. 6-5-1 6-5-2 6-5-3 6-5-4 6-5-5
Procedure for Automatic Transfer from the Memory Cassette at Startup 359 Read Protection. Write Protection. Protecting Program Execution Using the Lot Number. Failure Alarm Instructions: FAL(006) and FALS(007). Failure Point Detection: FPD(269). Simulating System Errors. Output OFF Bit.
Program Protection. 6-6-1 6-6-2 6-6-3
Failure Diagnosis Functions. 6-7-1 6-7-2 6-7-3 6-7-4

Clock.

Serial Communications

Section 6-1

The CP1H CPU Units support the following serial communications functions.
Connected devices Standard devices supporting serial communications

Protocol No-protocol

Description

Serial port 1

Serial port 2 OK

RS-232C or RS-422A/485

Communicates with standard OK devices with an RS-232C or RS-422A/485 port without a commandresponse format. Instead the TXD(236) and RXD(235) instructions are executed from the program to transmit data from the transmission port or read data in the reception port. The frame headers and end codes can be specified.
Standard device with serial communications
Serial gate- OMRON components supporting CompoWay/F or Modway (to bus-RTU slave devices CompoWay/ F or ModCP1H CPU Unit bus-RTU)

Bit D100 D101 D102

167 Always 166 Always 0

Temperature Unit Flag (0: C, 1: F) Open-circuit Flag (0: Normal, 1: Error)
A200.11 (First Scan Flag)
MOV(021) #0000 D102 MOV(021) #0100 D103
(1) Sets D103 and D102 to #0100 and #0000, respectively.

P_On (Always ON Flag)

CMP(020) 2 #7FFE
P_EQ 1000.00 ON when input 0 has been initialized. 1000.00 2.13 (open-circuit detected) 1000.01 Open-circuit alarm output 2.15 (leftmost digits)

SET 02001

1000.02 2.15 (leftmost digits) MOV(021) 2 2000

MOVD(083) (3)

(2) Leftmost digits moved to CIO 2000.

2.15 (rightmost digits)

002 #0020 2001

MOVD(083) (4)

Leftmost and rightmost digits rearranged and moved to CIO 2002 and CIO 2001.

2000 #0300 2001

MOVD(083) (5)

2000 #0011 2002

REST 2000.01 SET 2000.02
Data rearrangement completed.
2000.02 2002.07 (non-negative data) BCDL(059) 2001 D100 2002.07 (negative data) CLC(041) C(412) DH0 C(412) DH1 BCDL(059) H0 D100

MOVD(083)

(6) If the temperature data is non-negative, the binary data in CIO 202 and CIO 201 is converted to BCD and placed in D101 and D100. (7) If the temperature data is negative, the 2's complement data in CIO 202 and CIO 201 is converted to binary data representing the absolute value of the temperature input and placed in H1 and H0.
(8) The binary data in H1 and H0 is converted to BCD and placed in D101 and D100. (9) "1" is written to the bit in D101 indicating negative data.

#0008 #0300 D101

REST2000.01
CompoBus/S I/O Link Units
CIO 2: Leftmost 3 digits of temperature data 0 CIO 16

Section 7-4

CIO 2: Rightmost 3 digits of temperature data (3)

16 (2)

(4) (5)

CIO 2002 0

CIO 160
(6) If the temperature data is non-negative, binary data is converted to BCD data.
(8) If the temperature data is negative, binary data is converted to BCD data.
(9) If temperature data is negative, "8" is written here. (1) #0100 D0 D102 (1) #0
CIO 2002 2's complement data 165 164
CIO 2001 2's complement data H160
(7) H1 Binary subtraction
The CP1H can function as a slave to a CompoBus/S Master Unit (or SRM1 CompoBus/S Master Control Unit) when a CPM1A-SRT21 CompoBus/S I/O Link Unit is connected. The CompoBus/S I/O Link Unit establishes an I/O link of 8 inputs and 8 outputs between the Master Unit and the PLC. Up to three CompoBus/S I/O Link Units, including other Expansion I/O Units, can be connected to a CP1H CPU Unit.

Program Transfer

Section 8-1
The CX-Programmer is used to transfer the programs, PLC Setup, I/O memory data, and I/O comments to the CPU Unit with the CPU Unit in PROGRAM mode. The following procedure is used. 1,2,3. 1. Select PLC - Transfer - To PLC. The Download Options Dialog Box will be displayed. 2. Specify the items to transfer. 3. Click the OK Button. Note The program data on a Memory Cassette can be automatic transferred when the power is turned ON.
Trial Operation and Debugging

Forced Set/Reset

The CX-Programmer can force-set (ON) or reset (OFF) specified bits in the CIO Area, Auxiliary Area, and HR Area, as well as timer/counter Completion Flags. Forced status will take priority over status output from the program or I/O refreshing. This status cannot be overwritten by instructions, and will be stored regardless of the status of the program or external inputs until it is cleared from the CX-Programmer. Force-set/reset operations are used to force input and output during a trial operation or to force certain conditions during debugging. Force-set/reset operations can be executed in either MONITOR or PROGRAM modes, but not in RUN mode. Note Turn ON the Forced Status Hold Bit (A500.13) and the IOM Hold Bit (A500.12) at the same time to retain the status of bits that have been force-set or reset when switching the operating mode. Turn ON the Forced Status Hold Bit (A500.13) and the IOM Hold Bit (A500.12), and set the Forced Status Hold Bit at Startup parameter in the PLC Setup to retain the status of the Forced Status Hold Bit hold to retain the status of bits that have been force-set or reset when turning OFF the power.

Input ignored

Forced set
The following areas can be force-set and reset: CIO Area (I/O bits, data link bits, CPU Bus Unit bits, Special I/O Unit bits, and work bits), Work Area, Timer Completion Flags, HR Area, Counter Completion Flags. CX-Programmer Operation Selecting bits for forced setting/resetting Selecting forced set or forced reset status Clearing forced status (also clearing all forced status at the same time)

Program

Forced ON regardless of programming

Section 8-2

Differential Monitoring
When the CPU Unit detects that a bit set by the CX-Programmer has changed from OFF to ON or from ON to OFF, the results are indicated in the Differentiate Monitor Completed Flag (A508.09). The Flag will turn ON when conditions set for the differential monitor have been met. The CX-Programmer can monitor and display these results on screen.
CX-Programmer Detects bit A OFF to ON transition. CPU Unit I/O memory Bit A
Monitored for OFF to ON transition.
CX-Programmer Operation 1,2,3. 1. Right-click the bit for differential monitoring. 2. Click Differential Monitor from the PLC Menu. The Differential Monitor Dialog Box will be displayed. 3. Click Rising or Falling. 4. Click the Start Button. The buzzer will sound when the specified change is detected and the count will be incremented. 5. Click the Stop Button. Differential monitoring will stop.

Serial Communications Settings
Name 1 Communications Settings Default Settings When setting is read by CPU Unit Internal address 144 Bits 15 Settings 0 Standard (9600 Standard (9600 ; Every cycle ; 1,7,2,E) 1,7,2,E)(The standard settings are as follows: 9,600 baud, 1 start bit, 7bit data, even parity, and 2 stop bits.) Custom 2 Mode Host Link Host Link NT Link (1:N) RS-232C ToolBus (peripheral bus) Serial Gateway PC Link (Slave) PC Link (Master) 2-1 Host Link 2-1-1 Baud 9,600 bps 300 bps 600 bps 1,200 bps 2,400 bps 4,800 bps 9,600 bps 19,200 bps 38,400 bps 57,600 bps 115,200 bps 2-1-2 Format (data length, stop bits, parity) 7,2,E: 7-bit 7,2,E: 7-bit data, 2 stop data, 2 stop bits, even parity bits, even parity 7,2,O: 7-bit data, 2 stop bits, odd parity 7,2,N: 7-bit data, 2 stop bits, no parity 7,1,E: 7-bit data, 2 stop bits, even parity 7,1,O: 7-bit data, 1 stop bit, odd parity 7,1,N: 7-bit data, 1 stop bit, no parity 8,2,E: 8-bit data, 2 stop bits, even parity 8,2,O: 8-bit data, 2 stop bits, odd parity 8,2,N: 8-bit data, 2 stop bits, no parity 8,1,E: 8-bit data, 1 stop bit, even parity 8,1,O: 8-bit data, 1 stop bit, odd parity 8,1,N: 8-bit data, 1 stop bit, no parity 2-1-3 Unit Number : 31 Every cycle to 07 Every cycle to 03 Every cycle to hex 02 hex 03 hex 04 hex 05 hex 00 or 06 hex 07 hex 08 hex 09 hex 0A hex 0 hex 1 hex 2 hex 4 hex 5 hex 6 hex 8 hex 9 hex A hex C hex D hex E hex 00 hex : 1F hex Every cycle to 11
hex 5 hex 2 hex 3 hex 4 hex 9 hex 7 hex 8 hex
Name 2 2-2 Default Settings When setting is read by CPU Unit Every cycle Every cycle Internal address 145 150

Bits Settings

NT Link (1:N): 1:N NT Links 2-2-1 2-2-2 Baud NT/PC Link Max: Highest unit number Baud 9,600 (disabled) 0 38,400 (standard) 115,200 (high speed) 0 : to to hex 0A hex 0 hex : 7 hex
RS-232C 2-3-bps 300 bps 600 bps 1,200 bps 2,400 bps 4,800 bps 9,600 bps 19,200 bps 38,400 bps 57,600 bps 115,200 bps 2-3-2 Format (data length, stop bits, parity) 7,2,E: 7-bit 7,2,E: 7-bit data, 2 stop data, 2 stop bits, even parity bits, even parity 7,2,O: 7-bit data, 2 stop bits, odd parity 7,2,N: 7-bit data, 2 stop bits, no parity 7,1,E: 7-bit data, 2 stop bits, even parity 7,1,O: 7-bit data, 1 stop bit, odd parity 7,1,N: 7-bit data, 1 stop bit, no parity 8,2,E: 8-bit data, 2 stop bits, even parity 8,2,O: 8-bit data, 2 stop bits, odd parity 8,2,N: 8-bit data, 2 stop bits, no parity 8,1,E: 8-bit data, 1 stop bit, even parity 8,1,O: 8-bit data, 1 stop bit, odd parity 8,1,N: 8-bit data, 1 stop bit, no parity 2-3-3 2-3-4 Start Code Disable. Start Code 00 hex0x0000 Disable. Set. 0x0000 : 0x00FF 2-3-5 End Code Received Bytes: Receive specified number of bytes. Received Bytes: Receive specified number of bytes. CR,LF Set End Code 2-3-6 Received Bytes 256 bytes 256 bytes 1 byte : 255 bytes Every cycle to 07 Every cycle and 09 Every cycle to 15 Every cycle Every cycle to 03 Every cycle to hex 02 hex 03 hex 04 hex 05 hex 00 or 06 hex 07 hex 08 hex 09 hex 0A hex 0 hex 1 hex 2 hex 4 hex 5 hex 6 hex 8 hex 9 hex A hex C hex D hex E hex 00 hex : FF hex 00

Name 1 Speed Default 0 pps (disabled) 1 pps : 30,000 pps 2 Acceleration Ratio 0 (disabled) 1 (pulses/4 ms) : 65535 (pulses/4 ms) 3 Deceleration Ratio 0 (disabled) 1 (pulses/4 ms) : 65535 (pulses/4 ms) At start of operation to 15 At start of operation to 15 Settings When setting is read by CPU Unit At start of operation Internal address 395 and 394 Bits 00 to 15 Settings hex : hex 0001Hex : FFFF hex 0001 hex : FFFF hex

Pulse Output 3 Settings

Name 1 Default Hold Undefined Search Only Always NC 0 pps (disabled) NC NO 4 Search/Return Initial Speed 0 pps : 30,000 pps 5 Speed Curve Trapezium Trapezium S-shaped When power is turned ON to 15 At start of operation 401 and 400 When power is turned ON At start of operation Settings When setting is read by CPU Unit At start of operation Internal address 410 Bits 12 to to to to 15 Settings 0 hex 1 hex 0 hex 1 hex 0 hex 1 hex hex : hex 0 hex 1 hex Undefined Origin (oper- Hold ation for limit signal turning ON) Limited Input Signal Operation Limit Input Signal Search Only
Name 1 Use define origin operation 1-1 1-2 Search Direction Default Do not use. CW Settings Do not use. Use. CW CCW Detection Method Method 0 Method 0 Method 1 Method 2 1-3 1-4 Search Operation Inverse 1 Operation Mode Mode 0 Inverse 1 Inverse 2 Mode 0 Mode 1 Mode 2 1-5 1-6 1-7 Origin Input Signal Proximity Input Signal Search High Speed NC NC 0 pps (disabled) NC NO NC NO 0 pps : 30,000 pps 1-8 Search Proximity Speed 0 pps (disabled) 1 pps : 100,000 pps (maximum for X/XA CPU Unit)1,000,pps (maximum for Y CPU Unit) 1-9 Search Compensation Value 0 pps At start of operation 405 and to 15 At start of operation 403 and 402 At start of operation 410 At start of operation to to to 15 At start of operation 399 At start of operation to to 03 At start of operation 399 When setting is read by CPU Unit When power is turned ON At start of operation Internal address Bits 00 to to to 11 Settings 0 hex 1 hex 0 hex 1 hex 0 hex 1 hex 2 hex 0 hex 1 hex 0 hex 1 hex 2 hex 0 hex 1 hex 0 hex 1 hex hex : hex hex : hex

407 and 406

00 to 15
hex : hex : 7FFF FFFF hex
0001 hex : FFFF hex 0001 hex : FFFF hex 0000 hex : 270F hex
Name 1 Speed Default 0 pps (disabled) 1 pps : 100,000 pps (maximum for X/XA CPU Unit)1,000,pps (maximum for Y CPU Unit) 2 Acceleration Ratio 0 (disabled) 1 (pulses/4 ms) : 65535 (pulses/4 ms) 3 Deceleration Ratio 0 (disabled) 1 (pulses/4 ms) : 65535 (pulses/4 ms) At start of operation to 15 At start of operation to 15 Settings When setting is read by CPU Unit At start of operation Internal address 413 and 412 Bits 00 to 15 Settings hex : hex
0001Hex : FFFF hex 0001 hex : FFFF hex
Built-in AD/DA: Built-in Analog I/O Settings

 

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