Coprocessor Data Transfers (LDC, STC)...3-53 The Coprocessor Fields....3-54 Addressing Modes....3-54 Address Alignment.....3-54 Data Aborts.....3-54 Assembler Syntax....3-55 Examples.....3-55 Coprocessor Register Transfers (MRC, MCR)...3-56 The Coprocessor Fields....3-56 Transfers to R15....3-57 Transfers from R15.....3-57 Instruction Cycle Times....3-57 Assembler Syntax....3-57 Examples.....3-57 Undefined Instruction....3-58 Instruction Cycle Times....3-58 Assembler Syntax....3-58 Instruction Set Examples....3-59 Using the Conditional Instructions....3-59 Pseudo-Random Binary Sequence Generator...3-61 Multiplication by Constant Using the Barrel Shifter...3-61 Loading a Word from an Unknown Alignment...3-63
Chapter 4 Thumb Instruction Set
Thumb Instruction Set Format....4-1 Format Summary....4-2 Opcode Summary....4-3 Format 1: Move Shifted Register....4-5 Operation....4-5 Instruction Cycle Times....4-6 Examples.....4-6 Format 2: Add/Subtract....4-7 Operation....4-7 Instruction Cycle Times....4-8 Examples.....4-8 Format 3: Move/Compare/Add/Subtract Immediate...4-9 Operations.....4-9 Instruction Cycle Times....4-10 Examples.....4-10 Format 4: ALU Operations....4-11 Operation....4-11 Instruction Cycle Times....4-12 Examples.....4-12
Chapter 4 Thumb Instruction Set (Continued)
Format 5: Hi-Register Operations/Branch Exchange...4-13 Operation....4-13 Instruction Cycle Times....4-14 The Bx Instruction....4-14 Examples.....4-15 Using R15 as an Operand...4-15 Format 6: Pc-Relative Load....4-16 Operation....4-16 Instruction Cycle Times....4-17 Examples.....4-17 Format 7: Load/Store with Register Offset....4-18 Operation....4-19 Instruction Cycle Times....4-19 Examples.....4-19 Format 8: Load/Store Sign-Extended Byte/Halfword...4-20 Operation....4-20 Instruction Cycle Times....4-21 Examples.....4-21 Format 9: Load/Store With Immediate Offset...4-22 Operation....4-23 Instruction Cycle Times....4-23 Examples.....4-23 Format 10: Load/Store Halfword...4-24 Operation....4-24 Instruction Cycle Times....4-25 Examples.....4-25 Format 11: Sp-Relative Load/Store....4-26 Operation....4-26 Instruction Cycle Times....4-27 Examples.....4-27 Format 12: Load Address....4-28 Operation....4-28 Instruction Cycle Times....4-29 Examples.....4-29 Format 13: Add Offset To Stack Pointer...4-30 Operation....4-30 Instruction Cycle Times....4-30 Examples.....4-30 Format 14: Push/Pop Registers...4-31 Operation....4-31 Instruction Cycle Times....4-32 Examples.....4-32 Format 15: Multiple Load/Store....4-33 Operation....4-33 Instruction Cycle Times....4-33 Examples.....4-33
Format 16: Conditional Branch....4-34 Operation....4-34 Instruction Cycle Times....4-35 Examples.....4-35 Format 17: Software Interrupt....4-36 Operation....4-36 Instruction Cycle Times....4-36 Examples.....4-36 Format 18: Unconditional Branch....4-37 Operation....4-37 Examples.....4-37 Format 19: Long Branch With Link....4-38 Operation....4-38 Instruction Cycle Times....4-39 Examples.....4-39 Instruction Set Examples....4-40 Multiplication by a Constant Using Shifts and Adds..4-40 General Purpose Signed Divide....4-41 Division by a Constant.....4-43

Miscellaneous Control DCLK0/1 Control External Interrupt Control Register 0 External Interrupt Control Register 1 External Interrupt Control Register 2 Reserved Reserved External Interrupt Filter Control Register 2 External Interrupt Filter Control Register 3 External Interrupt Mask External Interrupt Pending External Pin Status External Pin Status
Table 1-4. S3C2410A Special Registers (Continued) Register Name RTC RTCCON TICNT RTCALM ALMSEC ALMMIN ALMHOUR ALMDATE ALMMON ALMYEAR RTCRST BCDSEC BCDMIN BCDHOUR BCDDATE BCDDAY BCDMON BCDYEAR A/D converter ADCCON ADCTSC ADCDLY ADCDAT0 ADCDAT1 SPI SPCON0,1 SPSTA0,1 SPPIN0,1 SPPRE0,1 SPTDAT0,1 SPRDAT0,1 0x59000000,20 0x59000004,24 0x59000008,28 0x5900000C,2C 0x59000010,30 0x59000014,34 R
Address (B. Endian) 0x57000043 0x57000047 0x57000053 0x57000057 0x5700005B 0x5700005F 0x57000063 0x57000067 0x5700006B 0x5700006F 0x57000073 0x57000077 0x5700007B 0x5700007F 0x57000083 0x57000087 0x5700008B 0x58000000 0x58000004 0x58000008 0x5800000C 0x58000010
Address (L. Endian) 0x57000040 0x57000044 0x57000050 0x57000054 0x57000058 0x5700005C 0x57000060 0x57000064 0x57000068 0x5700006C 0x57000070 0x57000074 0x57000078 0x5700007C 0x57000080 0x57000084 0x57000088
Read/ Write R/W RTC Control
Tick time count RTC Alarm Control Alarm Second Alarm Minute Alarm Hour Alarm Day Alarm Month Alarm Year RTC Round Reset BCD Second BCD Minute BCD Hour BCD Day BCD Date BCD Month BCD Year W R/W ADC Control ADC Touch Screen Control ADC Start or Interval Delay R ADC Conversion Data ADC Conversion Data W R/W R R/W SPI Control SPI Status SPI Pin Control SPI Baud Rate Prescaler SPI Tx Data SPI Rx Data
Table 1-4. S3C2410A Special Registers (Continued) Register Name SD interface SDICON SDIPRE SDICmdArg SDICmdCon SDICmdSta SDIRSP0 SDIRSP1 SDIRSP2 SDIRSP3 SDIDTimer SDIBSize SDIDatCon SDIDatCnt SDIDatSta SDIFSTA SDIDAT SDIIntMsk 0x5A000000 0x5A000004 0x5A000008 0x5A00000C 0x5A000010 0x5A000014 0x5A000018 0x5A00001C 0x5A000020 0x5A000024 0x5A000028 0x5A00002C 0x5A000030 0x5A000034 0x5A000038 0x5A00003F 0x5A000040 0x5A00003C
SDI Control SDI Baud Rate Prescaler SDI Command Argument SDI Command Control

R/(C) R

SDI Command Status SDI Response SDI Response SDI Response SDI Response
SDI Data / Busy Timer SDI Block Size SDI Data control

R R/(C) R B W R/W

SDI Data Remain Counter SDI Data Status SDI FIFO Status SDI Data SDI Interrupt Mask
Cautions on S3C2410A Special Registers 1. 2. 3. 4. 5. In the little endian mode, L. endian address must be used. In the big endian mode, B. endian address must be used. The special registers have to be accessed for each recommended access unit. All registers except ADC registers, RTC registers and UART registers must be read/written in word unit (32-bit) at little/big endian. Make sure that the ADC registers, RTC registers and UART registers be read/written by the specified access unit and the specified address. Moreover, one must carefully consider which endian mode is used. W : 32-bit register, which must be accessed by LDR/STR or int type pointer(int *). HW : 16-bit register, which must be accessed by LDRH/STRH or short int type pointer(short int *). B : 8-bit register, which must be accessed by LDRB/STRB or char type pointer(char int *).

ASSEMBLY SYNTAX

MRS - transfer PSR contents to a register MRS{cond} Rd,<psr> MSR - transfer register contents to PSR MSR{cond} <psr>,Rm MSR - transfer register contents to PSR flag bits only MSR{cond} <psrf>,Rm
The most significant four bits of the register contents are written to the N,Z,C & V flags respectively.
MSR - transfer immediate value to PSR flag bits only MSR{cond} <psrf>,<#expression>
The expression should symbolise a 32-bit value of which the most significant four bits are written to the N,Z,C and V flags respectively. Key: {cond} Rd and Rm <psr> <psrf> <#expression> Two-character condition mnemonic. See Table 3-2. Expressions evaluating to a register number other than R15 CPSR, CPSR_all, SPSR or SPSR_all. (CPSR and CPSR_all are synonyms as are SPSR and SPSR_all) CPSR_flg or SPSR_flg Where this is used, the assembler will attempt to generate a shifted immediate 8-bit field to match the expression. If this is impossible, it will give an error.
EXAMPLES In User mode the instructions behave as follows: MSR MSR MSR MRS CPSR_all,Rm CPSR_flg,Rm CPSR_flg,#0xA0000000 Rd,CPSR ; ; ; ; CPSR[31:28] <- Rm[31:28] CPSR[31:28] <- Rm[31:28] CPSR[31:28] <- 0xA (set N,C; clear Z,V) Rd[31:0] <- CPSR[31:0]
In privileged modes the instructions behave as follows: MSR MSR MSR MSR MSR MSR MRS CPSR_all,Rm CPSR_flg,Rm CPSR_flg,#0x50000000 SPSR_all,Rm SPSR_flg,Rm SPSR_flg,#0xC0000000 Rd,SPSR ; ; ; ; ; ; ; CPSR[31:0] <- Rm[31:0] CPSR[31:28] <- Rm[31:28] CPSR[31:28] <- 0x5 (set Z,V; clear N,C) SPSR_<mode>[31:0]<- Rm[31:0] SPSR_<mode>[31:28] <- Rm[31:28] SPSR_<mode>[31:28] <- 0xC (set N,Z; clear C,V) Rd[31:0] <- SPSR_<mode>[31:0]
MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA)
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-12. The multiply and multiply-accumulate instructions use an 8-bit Booth's algorithm to perform integer multiplication.

A S Rd

[15:12][11:8][3:0] Operand Registers [19:16] Destination Register [20] Set Condition Code

Overflow in signed multiply with a 32-bit result SMULL TEQ BNE Rd,Rt,Rm,Rn Rt,Rd ASR#31 overflow ; 3 to 6 cycles ; +1 cycle and a register
Overflow in unsigned multiply accumulate with a 32-bit result UMLAL TEQ BNE Rd,Rt,Rm,Rn Rt,#0 overflow ; 4 to 7 cycles ; +1 cycle and a register
Overflow in signed multiply accumulate with a 32-bit result SMLAL TEQ BNE Rd,Rt,Rm,Rn Rt,Rd, ASR#31 overflow ; 4 to 7 cycles ; +1 cycle and a register
Overflow in unsigned multiply accumulate with a 64-bit result UMULL ADDS ADC BCS Rl,Rh,Rm,Rn Rl,Rl,Ra1 Rh,Rh,Ra2 overflow ; ; ; ; 3 to 6 cycles Lower accumulate Upper accumulate 1 cycle and 2 registers
Overflow in signed multiply accumulate with a 64-bit result SMULL ADDS ADC BVS Rl,Rh,Rm,Rn Rl,Rl,Ra1 Rh,Rh,Ra2 overflow ; ; ; ; 3 to 6 cycles Lower accumulate Upper accumulate 1 cycle and 2 registers
NOTE Overflow checking is not applicable to unsigned and signed multiplies with a 64-bit result, since overflow does not occur in such calculations.
PSEUDO-RANDOM BINARY SEQUENCE GENERATOR It is often necessary to generate (pseudo-) random numbers and the most efficient algorithms are based on shift generators with exclusive-OR feedback rather like a cyclic redundancy check generator. Unfortunately the sequence of a 32-bit generator needs more than one feedback tap to be maximal length (i.e. 2^32-1 cycles before repetition), so this example uses a 33-bit register with taps at bits 33 and 20. The basic algorithm is newbit:=bit 33 eor bit 20, shift left the 33-bit number and put in newbit at the bottom; this operation is performed for all the newbits needed (i.e. 32 bits). The entire operation can be done in 5 S cycles: ; ; ; ; ; ; ; Enter with seed in Ra (32 bits), Rb (1 bit in Rb lsb), uses Rc. Top bit into carry 33 bit rotate right Carry into lsb of Rb (involved!) (similarly involved!) new seed in Ra, Rb as before

TST MOVS ADC EOR EOR

Rb,Rb,LSR#1 Rc,Ra,RRX Rb,Rb,Rb Rc,Rc,Ra,LSL#12 Ra,Rc,Rc,LSR#20
MULTIPLICATION BY CONSTANT USING THE BARREL SHIFTER Multiplication by 2^n (1,2,4,8,16,32.) MOV Ra, Rb, LSL #n
Multiplication by 2^n+1 (3,5,9,17.) ADD Ra,Ra,Ra,LSL #n
Multiplication by 2^n-1 (3,7,15.) RSB Ra,Ra,Ra,LSL #n
Multiplication by 6 ADD MOV Ra,Ra,Ra,LSL #1 Ra,Ra,LSL#1 ; Multiply by 3 ; and then by 2
Multiply by 10 and add in extra number ADD ADD Ra,Ra,Ra,LSL#2 Ra,Rc,Ra,LSL#1 ; Multiply by 5 ; Multiply by 2 and add in next digit
General recursive method for Rb := Ra*C, C a constant: 1. If C even, say C = 2^n*D, D odd: D=1: D<>1: MOV MOV Rb,Ra,LSL #n {Rb := Ra*D} Rb,Rb,LSL #n

a2, a2, #0

;Central part is identical code to udiv (without MOV a4, #0 which comes for free as part of signed entry sequence) MOVS a3, a1 BEQ divide_by_zero just_l CMP MOVLS BLO div_l CMP ADC SUBCS TEQ MOVNE BNE MOV MOVS RSBCS RSBMI MOV a2, a3 a4, a4, a4 a2, a2, a3 a3, a1 a3, a3, LSR #1 s_loop2 a1, a4 ip, ip, ASL #1 a1, a1, #0 a2, a2, #0 pc, lr a3, a2, LSR #1 a3, a3, LSL #1 s_loop ; Justification stage shifts 1 bit at a time ; NB: LSL #1 is always OK if LS succeeds
DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code. Thumb Code udiv10 MOV LSR SUB LSR ADD LSR ADD LSR ADD LSR ASL ADD ASL SUB CMP BLT ADD SUB 0 MOV ARM Code udiv10 SUB SUB ADD ADD ADD MOV ADD SUBS ADDPL ADDMI MOV a2, a1, #10 a1, a1, a1, lsr #2 a1, a1, a1, lsr #4 a1, a1, a1, lsr #8 a1, a1, a1, lsr #16 a1, a1, lsr #3 a3, a1, a1, asl #2 a2, a2, a3, asl #1 a1, a1, #1 a2, a2, #10 pc, lr ; Take argument in a1 returns quotient in a1, ; remainder in a2 pc, lr a2, a1 a3, a1, #2 a1, a3 a3, a1, #4 a1, a3 a3, a1, #8 a1, a3 a3, a1, #16 a1, a3 a1, #3 a3, a1, #2 a3, a1 a3, #1 a2, a3 a2, #10 %FT0 a1, #1 a2, #10 ; Take argument in a1 returns quotient in a1, ; remainder in a2

MEMORY CONTROLLER

The S3C2410A's memory controller provides memory control signals required for external memory access. The S3C2410A has the following features: Little/Big endian (selectable by a software) Address space: 128Mbytes per bank (total 1GB/8 banks) Programmable access size (8/16/32-bit) for all banks except bank0 (16/32-bit) Total 8 memory banks Six memory banks for ROM, SRAM, etc. Remaining two memory banks for ROM, SRAM, SDRAM, etc. Seven fixed memory bank start address Adjustable start address for the last bank. Programmable bank size for the last two banks. Programmable access cycles for all memory banks External wait to extend the bus cycles Supporting self-refresh and power down mode for SDRAM

[26:24]

[22:20]

[18:16]

[14:12]

EXTINT1 Reserved EINT15

Bit [31] [30:28] Reserved
Set the signaling method of the EINT15. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered

Reserved EINT14

[27] [26:24]
Reserved Set the signaling method of the EINT14. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered

Reserved EINT13

[23] [22:20]
Reserved Set the signaling method of the EINT13. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered

Reserved EINT12

[19] [18:16]
Reserved Set the signaling method of the EINT12. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered

Reserved EINT11

[15] [14:12]
Reserved Set the signaling method of the EINT11. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered

Reserved EINT10

[11] [10:8]
Reserved Set the signaling method of the EINT10. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered

Reserved EINT9

Reserved Set the signaling method of the EINT9. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered

Reserved EINT8

Reserved Set the signaling method of the EINT8. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered

EXTINT2 FLTEN23 EINT23

Bit [31] [30:28] Filter Enable for EINT23
Description 0 = Disable 1= Enable
Set the signaling method of the EINT23. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT= Disable 1= Enable

FLTEN22 EINT22

Set the signaling method of the EINT22. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT= Disable 1= Enable

FLTEN21 EINT21

Set the signaling method of the EINT21. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT= Disable 1= Enable

ULCONn Reserved Infra-Red Mode

Bit [7] [6]

Determine whether or not to use the Infra-Red mode. 0 = Normal mode operation 1 = Infra-Red Tx/Rx mode

Parity Mode

Specify the type of parity generation and checking during UART transmit and receive operation. 0xx = No parity 100 = Odd parity 101 = Even parity 110 = Parity forced/checked as = Parity forced/checked as 0

Number of Stop Bit

Specify how many stop bits are to be used for end-of-frame signal. 0 = One stop bit per frame 1 = Two stop bit per frame

Word Length

Indicate the number of data bits to be transmitted or received per frame. 00 = 5-bit 10 = 7-bit 01 = 6-bit 11 = 8-bit
UART CONTROL REGISTER There are three UART control registers including UCON0, UCON1 and UCON2 in the UART block. Register UCON0 UCON1 UCON2 Address 0x50000004 0x50004004 0x50008004 R/W R/W R/W R/W Description UART channel 0 control register UART channel 1 control register UART channel 2 control register Reset Value 0x00 0x00 0x00

UCONn Clock Selection

Bit [10]
Description Select PCLK or UEXTCLK for the UART baud rate. 0=PCLK : UBRDIVn = (int)(PCLK / (bps x 16) ) -1 1=UEXTCLK(@GPH8) : UBRDIVn = (int)(UEXTCLK / (bps x 16) ) -1

Tx Interrupt Type

Interrupt request type. 0 = Pulse (Interrupt is requested as soon as the Tx buffer becomes empty in Non-FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode.) 1 = Level (Interrupt is requested while Tx buffer is empty in Non-FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode.)

Rx Interrupt Type

Interrupt request type. 0 = Pulse (Interrupt is requested the instant Rx buffer receives the data in Non-FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode.) 1 = Level (Interrupt is requested while Rx buffer is receiving data in Non-FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode.)

Rx Time Out Enable

Enable/Disable Rx time out interrupt when UART FIFO is enabled. The interrupt is a receive interrupt. 0 = Disable 1 = Enable
Rx Error Status Interrupt Enable
Enable the UART to generate an interrupt upon an exception, such as a frame error, or overrun error during a receive operation. 0 = Do not generate receive error status interrupt. 1 = Generate receive error status interrupt.

RED Lookup Table Register Register REDLUT Address 0X4D000020 R/W R/W Description STN: Red lookup table register Reset Value 0x00000000

REDLUT REDVAL

Description These bits define which of the 16 shades will be chosen by each of the 8 possible red combinations. 000 = REDVAL[3:0], 001 = REDVAL[7:4] 010 = REDVAL[11:8], 011 = REDVAL[15:12] 100 = REDVAL[19:16], 101 = REDVAL[23:20] 110 = REDVAL[27:24], 111 = REDVAL[31:28]
GREEN Lookup Table Register Register GREENLUT Address 0X4D000024 R/W R/W Description STN: Green lookup table register Reset Value 0x00000000

GREENLUT GREENVAL

Description These bits define which of the 16 shades will be chosen by each of the 8 possible green combinations. 000 = GREENVAL[3:0], 001 = GREENVAL[7:4] 010 = GREENVAL[11:8], 011 = GREENVAL[15:12] 100 = GREENVAL[19:16], 101 = GREENVAL[23:20] 110 = GREENVAL[27:24], 111 = GREENVAL[31:28]
BLUE Lookup Table Register Register BLUELUT Address 0X4D000028 R/W R/W Description STN: Blue lookup table register Reset Value 0x0000

BULELUT BLUEVAL

Description These bits define which of the 16 shades will be chosen by each of the 4 possible blue combinations. 00 = BLUEVAL[3:0], 01 = BLUEVAL[7:4] 10 = BLUEVAL[11:8], 11 = BLUEVAL[15:12]
Address from 0x4D00002C to 0x4D000048 should not be used. This area is reserved for Test mode.
Dithering Mode Register Register DITHMODE Address 0X4D00004C R/W R/W Description STN: Dithering mode register. This register reset value is 0x00000 But, user can change this value to 0x12210. (Refer to a sample program source for the latest value of this register.) Reset Value 0x00000

DITHMODE DITHMODE

Bit [18:0]
Description Use one of following value for your LCD: 0x00000 or 0x12210

Initial state 0x00000

Temp Palette Register Register TPAL Address 0X4D000050 R/W R/W Description TFT: Temporary palette register. This register value will be video data at next frame. Reset Value 0x00000000

TPAL TPALEN TPALVAL

Bit [24] [23:0]
Description Temporary palette register enable bit. 0 = Disable 1 = Enable Temporary palette value register. TPALVAL[23:16] : RED TPALVAL[15:8] : GREEN TPALVAL[7:0] : BLUE

Initial state 0 0x000000

LCD Interrupt Pending Register Register LCDINTPND Address 0X4D000054 R/W R/W Description Indicate the LCD interrupt pending register Reset Value 0x0

LCDINTPND INT_FrSyn

Description LCD frame synchronized interrupt pending bit. 0 = The interrupt has not been requested. 1 = The frame has asserted the interrupt request. LCD FIFO interrupt pending bit. 0 = The interrupt has not been requested. 1 = LCD FIFO interrupt is requested when LCD FIFO reaches trigger level.

INT_FiCnt

LCD Source Pending Register Register LCDSRCPND Address 0X4D000058 R/W R/W Description Indicate the LCD interrupt source pending register Reset Value 0x0

WTDAT Count Reload Value

Description Watchdog timer count value for reload.

Initial State 0x8000

WATCHDOG TIMER COUNT (WTCNT) REGISTER The WTCNT register contains the current count values for the watchdog timer during normal operation. Note that the content of the WTDAT register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initially, so the WTCNT register must be set to an initial value before enabling it. Register WTCNT Address 0x53000008 R/W R/W Description Watchdog timer count register Reset Value 0x8000

WTCNT Count Value

Description The current count value of the watchdog timer
MMC/SD/SDIO HOST CONTROLLER
The S3C2410A SD Host controller can support MMC/SD card and SDIO devices.
SD Memory Card Spec. (ver. 1.0) / MMC Spec. (2.11) compatible SDIO Card Spec (ver. 1.0) compatible 16 words (64 bytes) FIFO (depth 16) for data Tx/Rx 40-bit Command Register (SDICARG[31:0]+SDICCON[7:0]) 136-bit Response Register (SDIRSPn[127:0]+ SDICSTA[7:0]) 8-bit Prescaler logic (Freq. = System Clock / (2(P + 1))) CRC7 & CRC16 Generator Polling, Interrupt and DMA Data Transfer Mode (Byte or Word transfer) 1-bit / 4-bit (wide bus) Mode & Block / Stream Mode Switch support Supports up to 25 MHz in data transfer mode for SD/SDIO Supports up to 20 MHz in data transfer mode for MMC
32 PADDR 32 PSEL PCLK APB I/F 32 32
CMD Reg (5byte) Resp Reg (17byte)
CMD Control 8bit Shift Reg TxCMD RxCMD
Prescaler DAT Control 32bit Shift Reg CRC16*4
PWDATA [31:0] PRDATA [31:0]

32 FIFO (64byte) 32

TxDAT[3:0] RxDAT[3:0]

DREQ DACK INT

DMA INT
Figure 19-1. Block Diagram
SDI OPERATION A serial clock line is synchronized with the five data lines for shifting and sampling of the information. Making the appropriate bit settings to the SDIPRE register depends on the transmission frequency. You can modify its frequency to adjust the baud rate data register value. Programming Procedure (common) SDI modules can be programmed, following these basic steps: 1. 2. 3. Set SDICON to configure properly with clock and interrupt. Set SDIPRE to configure with a proper value. Wait 74 SDCLK clock cycle in order to initialize the card.
CMD Path Programming 1. 2. 3. Write command argument (32-bit) to SDICARG register. Determine command types and start command by setting SDICCON[8]. Confirm the end of SDI command operation when the specific flag of SDICSTA is set. If the type of command is no-response, the flag is SDICSTA[11]. If the type of command is with-response, the flag is SDICSTA[9]. Clear the corresponding flag of the SDICSTA register by writing one to the flag bit.

DAT Path Programming 1. 2. 3. 4. 5. 6. 7. Write timeout period to SDIDTIMER register. Write block size (block length) to SDIBSIZE register (normally 0x200 byte). Determine the mode of block, wide bus, DMA, etc. and start data transfer with setting SDIDCON register. Write Tx-data to SDIDAT register while Tx FIFO is available by checking SDIFSTA (available, half or empty) register. Read Rx-data from SDIDAT register while Rx FIFO is available by checking SDIFSTA (available, half or be last data) register. Confirm the end of SDI data operation when the flag of data transfer finish (SDIDSTA[4]) is set. Clear the corresponding flag of SDIDSTA register by writing one to the flag bit. NOTE In case of long response command, CRC error can be wrong by H/W but a user can ignore this. It should be detected by software if it is need to check.
SDIO OPERATION There are two functions of the SDIO operation: SDIO Interrupt receiving and Read Wait Request generation. These two functions can operate when RcvIOInt bit and RwaitEn bit of SDICON register is activated respectively. Detailed steps and conditions for the two functions are described below. SDIO Interrupt In SD 1-bit mode, the interrupt is received through all ranges from SDDAT1 pin. In SD 4-bit mode, SDDAT1 pin is shared between to receive data and interrupts. When interrupt detection ranges (Interrupt Period) are: 1. Single Block: the time between A and B A: 2clocks after the completion of a data packet B: The completion of sending the end bit of the next with-data command 2. Multi Block, SDIDCON[21] = 0: the time between A and B, restart interrupt detection range at C A: 2clocks after the completion of a data packet B: 2clocks after A C: 2clocks after the end bit of the abort command response 3. Multi Block, SDIDCON[21] = 1: the time between A and B, restart at A A: 2clocks after the completion of a data packet B: 2clocks after A In case of last block, interrupt period begins at last A, but it does not end at B (CMD53 case). Read Wait Request Regardless of 1-bit or 4-bit mode, Read Wait Request signal transmits to SDDAT2 pin in the condition below. In read multiple operation, request signal transmission begins in 2clocks after the end of data block. Transmission ends when the user writes one to SDIDSTA[10].
SDI SPECIAL REGISTERS SDI Control (SDICON) Register Register SDICON Address 0x5A000000 R/W R/W Description SDI control register Reset Value 0x0

[11] [10] [9] [8] [7] [6:0]

0 0000000

SDI Data (SDIDAT) Register Register SDIDAT Address 0x5A00003C(Li/W, Li/B, Bi/W) 0x5A00003F(Bi/B) R/W R/W SDI data register Description Reset Value 0x0

SDIDAT Data Register

Description This field contains the data to be transmitted or received over the SDI channel.
NOTES: 1. (Li/W, Li/B): Access by Word/Byte unit when endian mode is Little 2. (Bi/W): Access by Word unit when endian mode is Big 3. (Bi/B) : Access by Byte unit when endian mode is Big
SDI Interrupt Mask (SDIIMSK) Register Register SDIIMSK Address 0x5A000040 R/W R/W Description SDI interrupt mask register Reset Value 0x0
SDIIMSK RspCrc Interrupt Enable CmdSent Interrupt Enable CmdTout Interrupt Enable RspEnd Interrupt Enable RWaitReq Interrupt Enable IOIntDet Interrupt Enable FFfail Interrupt Enable CrcSta Interrupt Enable DatCrc Interrupt Enable DatTout Interrupt Enable DatFin Interrupt Enable BusyFin Interrupt Enable Reserved TFHalf Interrupt Enable TFEmpty Interrupt Enable RFLast Interrupt Enable RFFull Interrupt Enable RFHalf Interrupt Enable
Bit [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Tx FIFO half interrupt. 0 = disable,
Description Response CRC error interrupt. 0 = disable, 1 = interrupt enable Command sent(without response) interrupt. 0 = disable, 1 = interrupt enable Command response timeout interrupt. 0 = disable, 1 = interrupt enable Command response received interrupt. 0 = disable, 1 = interrupt enable Read wait request interrupt. 0 = disable, 1 = interrupt enable SD host receives SDIO Interrupt from the card (for SDIO). 0 = disable, 1 = interrupt enable FIFO fail error interrupt. 0 = disable, 1 = interrupt enable CRC status errors interrupt. 0 = disable, 1 = interrupt enable Data CRC fail interrupt. 0 = disable, 1 = interrupt enable Data timeout interrupt. 0 = disable, 1 = interrupt enable

Initial Value 0 0

Data counter zero interrupt. 0 = disable, 1 = interrupt enable Busy checks complete interrupt. 0 = disable, 1 = interrupt enable
1 = interrupt enable = interrupt enable = interrupt enable

Tx FIFO empty interrupt. 0 = disable, 1 = interrupt enable Rx FIFO has last data interrupt. 0 = disable, 1 = interrupt enable Rx FIFO full interrupt. 0 = disable, Rx FIFO half interrupt. 0 = disable,
SDI Data/Busy Timer Register SDI data/ busy timer register has 16-bit counter. In case of 25MHz operation, the countable maximum time is 2.6ms (40ns * 0x10000). But, some cards have very long access time (TAAC), their TAAC are up to 100ms. In this case the SDI generates data timeout error state. To solve this problem follow the below flow chart.
Read (multil or single block)

Is timeout occurs?

25MHz or 600KHz ?

Send stop command

No Send stop command if multi block Change SDI clock to 600KHz Retry Change SDI clock to 25MHz if 600KHz

600KHz

Real-timeout error

Return

Return error

IIC-BUS INTERFACE

The S3C2410A RISC microprocessor can support a multi-master IIC-bus serial interface. A dedicated serial data line (SDA) and a serial clock line (SCL) carry information between bus masters and peripheral devices which are connected to the IIC-bus. The SDA and SCL lines are bi-directional. In multi-master IIC-bus mode, multiple S3C2410A RISC microprocessors can receive or transmit serial data to or from slave devices. The master S3C2410A can initiate and terminate a data transfer over the IIC-bus. The IIC-bus in the S3C2410A uses Standard bus arbitration procedure. To control multi-master IIC-bus operations, values must be written to the following registers: Multi-master IIC-bus control register, IICCON Multi-master IIC-bus control/status register, IICSTAT Multi-master IIC-bus Tx/Rx data shift register, IICDS Multi-master IIC-bus address register, IICADD When the IIC-bus is free, the SDA and SCL lines should be both at High level. A High-to-Low transition of SDA can initiate a Start condition. A Low-to-High transition of SDA can initiate a Stop condition while SCL remains steady at High Level. The Start and Stop conditions can always be generated by the master devices. A 7-bit address value in the first data byte, which is put onto the bus after the Start condition has been initiated, can determine the slave device which the bus master device has selected. The 8th bit determines the direction of the transfer (read or write). Every data byte put onto the SDA line should be eight bits in total. The bytes can be unlimitedly sent or received during the bus transfer operation. Data is always sent from most-significant bit (MSB) first, and every byte should be immediately followed by an acknowledge (ACK) bit.

Figure 21-2. IIS-Bus and MSB (Left)-justified Data Interface Formats
SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency (PCLK) can be selected by sampling frequency as shown in Table 21-1. Because PCLK is made by IIS prescaler, the prescaler value and PCLK type (256 or 384fs) should be determined properly. Serial bit clock frequency type (16/32/48fs) can be selected by the serial bit per channel and PCLK as shown in Table 21-2. Table 21-1. CODEC clock (CODECLK = 256 or 384fs)
IISLRCK (fs) 8.000 kHz 256fs CODECLK (MHz) 2.0480 384fs 3.0720 4.2336 6.1440 8.4672 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 2.8224 4.0960 5.6448 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 11.025 kHz 16.000 kHz 22.050 kHz 32.000 kHz 44.100 kHz 48.000 kHz 64.000 kHz 88.200 kHz 96.000 kHz
Table 21-2 Usable Serial Bit Clock Frequency (IISCLK = 16 or 32 or 48fs) Serial bit per channel Serial clock frequency (IISCLK) @CODECLK = 256fs @CODECLK = 384fs 16fs, 32fs 16fs, 32fs, 48fs 32fs 32fs, 48fs 8-bit 16-bit
IIS-BUS INTERFACE SPECIAL REGISTERS
IIS CONTROL (IISCON) REGISTER Register IISCON Address 0x55000000 (Li/HW, Li/W, Bi/W) 0x55000002 (Bi/HW) R/W R/W Description IIS control register Reset Value 0x100
IISCON Left/Right channel index (Read only) Transmit FIFO ready flag (Read only) Receive FIFO ready flag (Read only) Transmit DMA service request Receive DMA service request Transmit channel idle command
Bit [8] [7] [6] [5] [4] [3] 0 = Left 1 = Right 0 = empty 1 = not empty 0 = full 1 = not full 0 = Disable 1 = Enable 0 = Disable 1 = Enable
In Idle state the IISLRCK is inactive (Pause Tx). 0 = Not idle 1 = Idle In Idle state the IISLRCK is inactive (Pause Rx). 0 = Not idle 1 = Idle 0 = Disable 1 = Enable 0 = Disable (stop) 1 = Enable (start)
Receive channel idle command
IIS prescaler IIS interface
NOTES: 1. The IISCON register is accessible for each byte, halfword and word unit using STRB/STRH/STR and LDRB/LDRH/LDR instructions or char/short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W): Little/HalfWord/Word (Bi/HW/W): Big/HalfWord/Word
IIS MODE REGISTER (IISMOD) REGISTER Register IISMOD Address 0x55000004 (Li/W, Li/HW, Bi/W) 0x55000006 (Bi/HW) R/W R/W Description IIS mode register Reset Value 0x0
IISMOD Master/slave mode select

Bit [8]

Description 0 = Master mode (IISLRCK and IISCLK are output mode). 1 = Slave mode (IISLRCK and IISCLK are input mode). 00 = No transfer 01 = Receive mode 10 = Transmit mode 11 = Transmit and receive mode 0 = Low for left channel (High for right channel) 1 = High for left channel (Low for right channel) 0 = IIS compatible format 1 = MSB (Left)-justified format 0 = 8-bit 1 = 16-bit 0 = 256fs 1 = 384fs (fs: sampling frequency) 00 = 16fs 01 = 32fs 10 = 48fs 11 = N/A