Offered in 256Mx8bit, the K9F2G08X0A is a 2G-bit NAND Flash Memory with spare 64M-bit. Its NAND cell provides the most costeffective solution for the solid state application market. A program operation can be performed in typical 200s on the (2K+64)Byte page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns(42ns with 1.8V device) cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F2G08X0As extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F2G08X0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
PIN CONFIGURATION (TSOP1)

K9F2G08U0A-PCB0/PIB0

N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C
48-pin TSOP1 Standard Type 12mm x 20mm

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220F

Unit :mm/Inch

0.10 MAX 0.004 #48 ( 0.25 ) 0.010 12.40 0.488 MAX 0.50 0.0197 #24 #25 1.000.05 0.0390.002 0.25 0.010 TYP

+0.075

20.000.20 0.7870.008

0.008-0.001

+0.003

0.20 -0.03

12.00 0.472

0.05 0.002 MIN

0.125 0.035

0.45~0.75 0.018~0.030

( 0.50 ) 0.020

+0.003 0.005-0.001

18.400.10 0.7240.004

1.20 0.047MAX

PIN CONFIGURATION (FBGA)

K9F2G08R0A-JCB0/JIB0

N.C N.C

N.C N.C N.C N.C

A B C D E F G H
/WP NC NC NC NC NC NC Vss ALE /RE NC NC NC I/O0 I/O1 I/O2 Vss CLE NC NC NC NC NC /CE NC NC NC NC NC Vcc /WE NC NC NC NC NC I/O5 I/O6 R/B NC NC NC NC Vcc I/O7 Vss

I/O3 I/O4

Top View

PACKAGE DEMENSIONS(FBGA)

ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH(1) V

Vcc+0.3 0.8xVcc

VOH VOL
K9F2G08R0A: IOH=-100A Vcc-0.1 K9F2G08U0A: IOH=-400A K9F2G08R0A: IOL=100A K9F2G08U0A: IOL=2.1mA 3

IOL(R/B) VOL=0.4V

NOTE : 1. VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc=3.3V, TA=25C. Not 100% tested.

VALID BLOCK

Parameter K9F2G08X0A Symbol NVB Min 2,008 Typ. -

Max 2,048 Unit Blocks

NOTE : 1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC. 3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.

AC TEST CONDITION

(K9F2G08X0A-XCB0 :TA=0 to 70C, K9F2G08X0A-XIB0:TA=-40 to 85C, K9F2G08R0A: Vcc=1.65~1.95V, K9F2G08UA: Vcc=2.7V~3.6V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load K9F2G08R0A 0V to Vcc 5ns Vcc/TTL GATE and CL=30pF K9F2G08U0A 0V to Vcc 5ns Vcc/TTL GATE and CL=50pF
CAPACITANCE(TA=25C, VCC=3.3V, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Condition VIL=0V VIN=0V Min Max Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE H L H L L L X X X X X ALE L H L H L L X X X X

CE L L L L L L X X X X H

RE H H H H H
WP X X H H H X X H H L 0V/VCC
Mode Read Mode Write Mode Data Input Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write Protect Stand-by Command Input Address Input(5clock) Command Input Address Input(5clock)

Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.

Set Block Address = 0

Increment Block Address
Create (or update) Initial Invalid Block(s) Table No Check "FFh" Yes No
Check "FFh" at the column address 2048 of the 1st and 2nd page in the block

Last Block ?

Figure 3. Flow chart to create initial invalid block table
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode Write Read Erase Failure Program Failure Single Bit Failure
Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection

Program Flow Chart

Write 80h

Write Address

Write Data

Write 10h

Read Status Register
I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ?

Program Error

Yes Program Completed
: If program operation results in an error, map out the block including the page in error and copy the target data to another block.

"C" area (3rd sector) 512 Byte
"D" area (4th sector) 512 Byte
"E" area "F" area "G" area "H" area (1st sector) (2nd sector) (3rd sector) (4th sector) 16 Byte 16 Byte 16 Byte 16 Byte
Table 2. Definition of the 528-Byte Sector
Sector 1st 528-Byte Sector 2nd 528-Byte Sector 3rd 528-Byte Sector 4th 528-Byte Sector Main Field (Column 0~2,047) Area Name "A" "B" "C" "D" Column Address 0 ~ ~ 1,023 1,024 ~ 1,535 1,536 ~ 2,047 Spare Field (Column 2,048~2,111) Area Name "E" "F" "G" "H" Column Address 2,048 ~ 2,063 2,064 ~ 2,079 2,080 ~ 2,095 2,096 ~ 2,111
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0.

Page 63

Page 31

Page 2 Page 1 Page 0

(3) (2) (1)

(3) (32) (2)

Data register From the LSB page to MSB page DATA IN: Data (1) Data (64)
Data register Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (64)
System Interface Using CE dont-care.
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of -seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption.
Figure 4. Program Operation with CE dont-care.

CE dont-care

Address(5Cycles)

Data Input

tCS CE

tCH CE

tREA tWP WE I/O0~7 out RE
Figure 5. Read Operation with CE dont-care.

RE ALE R/B tR

WE I/OX
00h Address(5Cycle) 30h Data Output(serial access)
I/O I/Ox I/O 0 ~ I/O 7 DATA Data In/Out 2,112byte Col. Add1 A0~A7 Col. Add2 A8~A11 ADDRESS Row Add1 A12~A19 Row Add2 A20~A27 Row Add3 A28

Device K9F2G08X0A

Command Latch Cycle

CLE tCLS tCS CE tCLH tCH

tWP WE

tALS ALE tDS I/Ox

Command

Address Latch Cycle

tCLS CLE tCS tWC CE tWC tWC tWC
tWP WE tALS ALE tDS I/Ox tDH tWH tALH

tWP tALS tALH tWH

tWP tALS tWH tALH
tWP tALS tWH tALH tALS tALH

Col. Add1

Col. Add2

Row Add1

Row Add2

Row Add3

Input Data Latch Cycle

tWC ALE tALS WE tDS I/Ox

tWH tDH

tWP tDH tDS

DIN 0 DIN 1 DIN final tRC
* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)

CE tREA RE

tCHZ tREA tCOH

tRHZ I/Ox tRR R/B

NOTES : Transition is measured at 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. tRLOH is valid when frequency is higher than 33MHz. tRHOH starts to be valid when frequency is lower than 33MHz.

tRHZ tRHOH

Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L)
tRC tRP RE tREA tCEA I/Ox tRR R/B tRLOH Dout tREA tREH

tCHZ tCOH

Status Read Cycle & EDC Status Read Cycle
tCLR CLE tCLS tCS CE tCH tCEA tWHR RE tDS I/Ox tDH tIR tREA tRHZ

70h or 7Bh

Status Output

Read Operation

tCLR CLE
CE tWC WE tWB tAR ALE tR RE tRR I/Ox
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3

tCOH tCHZ

Dout N+2

Dout N Dout N+1 Dout M

Column Address

Row Address Busy

Read Operation(Intercepted by CE)
CE tCSD WE tWB tAR ALE tR RE tRR I/Ox
00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h

Dout N

Dout N+1
Random Data Output In a Page

CLE tCLR

24 tR tRC tRR

ALE tREA

Column Address Row Address Busy

Col Add1

Col Add2

Dout M

Dout M+1

Page Program Operation

WE tADL ALE tWB tPROG tWHR
Din Din N M 1 up to m Byte Serial Input

Co.l Add1 Col. Add2

Row Add2 Row Add3

10h Program Command

70h Read Status Command
SerialData Column Address Input Command

Read ID Operation

WE tAR

RE tREA I/Ox

90h Read ID Command 00h Address 1cycle ECh Device Code 3rd cyc. 4th cyc. 5th cyc.

Maker Code Device Code

Device K9F2G08R0A K9F2G08U0A
Device Code (2nd Cycle) AAh DAh

3rd Cycle 00h 10h

4th Cycle 15h 95h

5th Cycle 44h 44h

ID Definition Table 90 ID : Access command = 90H
Description 1 Byte 2nd Byte 3rd Byte 4th Byte 5th Byte
Maker Code Device Code Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum Plane Number, Plane Size

3rd ID Data

Description 2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell Not Support Support Not Support Support I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O1

Internal Chip Number

Cell Type
Number of Simultaneously Programmed Pages Interleave Program Between multiple chips Cache Program

4th ID Data

Description Page Size (w/o redundant area ) 1KB 2KB 4KB 8KB 64KB 128KB 256KB 512KB x8 x16 50ns/30ns 25ns Reserved Reserved I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O1
Block Size (w/o redundant area ) Redundant Area Size ( byte/512byte) Organization

Serial Access Minimum

5th ID Data
Description 64Mb 128Mb 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb 1 I/O7 I/O6 I/O5 I/O4

I/O3 I/O1

Plane Number
Plane Size (w/o redundant Area)

Reserved

Device Operation

PAGE READ

Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are transferred to the data registers in less than 25s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 25ns(42ns with 1.8V device) cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page.

Figure 6. Read Operation

ALE R/B RE I/Ox
Address(5Cycle) Col. Add.1,2 & Row Add.1,2,3
Data Output(Serial Access)

Data Field

Spare Field
Figure 7. Random Data Output In a Page

R/B RE I/Ox

00h Address 5Cycles 30h

Data Output

Address 2Cycles Col. Add.1,2
Col. Add.1,2 & Row Add.1,2,3

PAGE PROGRAM

The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive bytes up to 2,112, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.

Figure 10. Page Copy-Back Program Operation

00h Add.(5Cycles) 35h

Add.(5Cycles)

70h/7Bh

I/O0 "1" Fail

"0"

Col. Add.1,2 & Row Add.1,2,3 Source Address
Col. Add.1,2 & Row Add.1,2,3 Destination Address
Note: 1. Copy-Back Program operation is allowed only within the same memory plane. 2. On the same plane, Its prohibited to operate copy-back program from an odd address page(source page) to an even address page(target page) or from an even address page(source page) to an odd address page(target page). Therefore, the copy-back program is permitted just between odd address pages or even address pages.
Figure 11. Page Copy-Back Program Operation with Random Data Input
Add.(2Cycles) Col. Add.1,2
There is no limitation for the number of repetition.

EDC OPERATION

Note that for the user who use Copy-Back with EDC mode, only one time random data input is possible at the same address during Copy-Back program or page program mode. For the user who use Copy-Back without EDC, there is no limitation for the random data input at the same address.
Figure 12. Page Copy-Back Program Operation with EDC & Read EDC Status

EDC Status Output

BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A18 to A28 is valid while A12 to A17 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation
"0" Address Input(3Cycle) Row Add 1,2,3 Fail D0h 70h I/O0 "1" Pass

Two-Plane Page Program

Two-Plane Page Program is an extension of Page Program, for a single plane with 2112 byte page registers. Since the device is equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous programming of two pages. After writing the first set of data up to 2112 byte into the selected page register, Dummy Page Program command (11h) instead of actual Page Program command (10h) is inputted to finish data-loading of the first plane. Since no programming process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (70h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for the other plane is inputted after the 81h command and address sequences. After inputting data for the last plane, actual True Page Program(10h) instead of dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Althougth two planes are programmed simultaneously, pass/fail is not available for each page when the program operation completes. Status bit of I/O 0 is set to "1" when any of the pages fails. Restriction in addressing with Two-Plane Page Program is shown is Figure14.

Figure 14. Two-Plane Page Program

R/B I/O0 ~ 7 tDBSY

Address & Data Input A0 ~ A11 : Valid A12 ~ A17 : Fixed Low A18 : Fixed Low A19 ~ A28 : Fixed Low

11h Note*2

Address & Data Input A0 ~ A11 : Valid A12 ~ A17 : Valid A18 : Fixed High A19 ~ A28 : Valid
NOTE :1. It is noticeable that same row address except for A18 is applied to the two blocks 2. Any command between 11h and 81h is prohibited except 70h and FFh.

Plane 0 (1024 Block)

Plane 1 (1024 Block)

Block 0 Block 2

Block 1 Block 3

Block 2044 Block 2046

Block 2045 Block 2047

Two-Plane Block Erase

Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane. The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/ Busy status bit (I/O 6).
Figure 15. Two-Plane Block Erase Operation

R/B I/OX

60h Address (3 Cycle) A12 ~ A17 : Fixed Low :Fixed Low A18 A19 ~ A28 : Fixed Low 60h Address (3 Cycle) A12 ~ A17 : Fixed Low : Fixed High A18 A19 ~ A28 : valid D0h
Two-Plane Copy-Back Program
Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 2112 byte page registers. Since the device is equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous programming of two pages.
Figure 16. Two-Plane Copy-Back Program Operation
Col. Add.1,2 & Row Add.1,2,3 Source Address On Plane0
Col. Add.1,2 & Row Add.1,2,3 Source Address On Plane1

R/B I/Ox 1

11h Note3
Col. Add.1,2 & Row Add.1,2,3 Destination Address A0 ~ A11 : Fixed Low A12 ~ A17 : Fixed Low A18 : Fixed Low A19 ~ A28 : Fixed Low
Col. Add.1,2 & Row Add.1,2,3 Destination Address A0 ~ A11 : Fixed Low A12 ~ A17 : Valid A18 : Fixed High A19 ~ A28 : Valid

Plane0 Source page

Plane1
Source page Target page (1) (3) Target page (2) (3) (1) : Read for Copy Back On Plane0 (2) : Read for Copy Back On Plane1 (3) : Two-Plane Copy-Back Program
Note: 1. Copy-Back Program operation is allowed only within the same memory plane. 2. On the same plane, Its prohibited to operate copy-back program from an odd address page(source page) to an even address page(target page) or from an even address page(source page) to an odd address page(target page). Therefore, the copy-back program is permitted just between odd address pages or even address pages. 3. Any command between 11h and 81h is prohibited except 70h and FFh.

NOTE : 1. I/Os defined Not use are recommended to be masked out when Read Status is being executed.

READ EDC STATUS

Read EDC status operation is only available on Copy Back Program. The device contains an EDC Status Register which may be read to find out whether there is error during Read for Copy Back. After writing 7Bh command to the command register, a read cycle outputs the content of the EDC Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 4 for specific Status Register definitions. The command register remains in EDC Status Read mode until further commands are issued to it.
Table 4. Status Register Definition for 7Bh Command
I/O I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 Copy Back Program Pass/Fail of Copy Back Program EDC Status Validity of EDC Status Not Use Not Use Not Use Ready/Busy of Copy Back Program Page Program Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Block Erase Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Read Not use Not use Not use Not Use Not Use Not Use Ready/Busy Definition Pass : "0", Fail : "1" No Error : "0", Error : "1" Valid : "1", Invalid : "0" Dont -cared Dont -cared Dont -cared Busy : "0", Ready : "1"
I/O 7 Write Protect of Copy Back Program
Write Protect Protected : "0", Not Protected :"1"
2. More than 2-bit error detection isnt available for each 528 Byte sector. That is to say, only 1-bit error detection is avaliable for each 528 Byte sector.

Read ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 18 shows the operation sequence.

Figure 18. Read ID Operation
CLE CE WE tAR ALE tWHR RE I/OX

90h 00h Address. 1cycle

tCLR tCEA

Device Code Device code

3rd Cyc.

4th Cyc.

5th Cyc.

Maker code

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 19 below.
Figure 19. RESET Operation

Table 5. Device Status

After Power-up Operation mode 00h Command is latched After Reset Waiting for next command

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig.20). Its value can be determined by the following guidance.

Rp VCC

ibusy 1.8V device - VOL : 0.1V, VOH : VCC-0.1V 3.3V device - VOL : 0.4V, VOH : 2.4V Ready Vcc

R/B open drain output

VOL Busy tf tr

GND Device

Figure 19. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 1.8V, Ta = 25C , CL = 30pF

Ibusy [A]

@ Vcc = 3.3V, Ta = 25C , CL = 50pF

300n Ibusy

1.70 0.0.57 1.70 120

200n 100n

tr,tf [s]

2m tr 60

200n tr 100n

0.8 0.6

0.43 1.70

50 1.8 tf 1.8 1.8

1.70 tf

3K Rp(ohm)

Rp value guidance
Rp(min, 1.8V part) = VCC(Max.) - VOL(Max.) IOL + IL VCC(Max.) - VOL(Max.) IOL + IL = = 1.85V 3mA + IL 3.2V 8mA + IL

Rp(min, 3.3V part) =

where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 100s is required before internal circuit gets ready for any command sequences as shown in Figure 21. The two step command sequence for program/erase provides additional software protection.
Figure 21. AC Waveforms for Power Transition
1.8V device : ~ 1.5V 3.3V device : ~ 2.5V VCC High
1.8V device : ~ 1.5V 3.3V device : ~ 2.5V

MR16R1624(8/G)EG0 MR18R1624(8/G)EG0

Change History

Version 0.1 (December 2003) - Preliminary
* First copy. * Based on the 1.0 ver. (July 2002) 256/288Mbit D-die RIMM Module Datasheet

Version 1.0 (May 2004)

* Eliminate "Preliminary"

Page 0

Version 1.0 May 2004
(16Mx16)*4(8/16)pcs RIMM Module based on 256Mb E-die, 32s banks,16K/32ms Ref, 2.5V (16Mx18)*4(8/16)pcs RIMM Module based on 288Mb E-die, 32s banks,16K/32ms Ref, 2.5V

Overview

The RIMM module is a general purpose high- performance memory module suitable for use in a broad range of applications including computer memory, personal computers, workstations and other applications where high bandwidth and low latency are required. The RIMM module consists of 256/288Mb devices. These are extremely high-speed CMOS DRAMs organized as 16M words by 16 or 18 bits. The use of Rambus Signaling Level (RSL) technology permits up to 1066 MHz transfer rates while using conventional system and board design technologies. RDRAM devices are capable of sustained data transfers at 0.94 ns per two bytes (7.5ns per 16 bytes). The RDRAM architecture enables the highest sustained bandwidth for multiple, simultaneous, randomly addressed, memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The RDRAM device's 32-bank architecture supports up to four simultaneous transactions per device. RDRAM
Key Timing Parameters/Part Numbers
The following table lists the frequency and latency bins available for RIMM modules. Table 1: Part Number by Freq. & Latency

Speed Organization Bin

tRAC I/O (Row Freq. Access (MHz) Time) ns 800 32P 32P 32P 40 45

Part Number

-CT9 64M x 16/18 -CM8 -CK8 -CT9 128M x 16/18 -CM8 -CK8 -CT9 256M x 16/18 -CM8 -CK8
MR16/18R1624EG0-CT9 MR16/18R1624EG0-CM8 MR16/18R1624EG0-CK8 MR16/18R1628EG0-CT9 MR16/18R1628EG0-CM8 MR16/18R1628EG0-CK8 MR16/18R162GEG0-CT9 MR16/18R162GEG0-CM8 MR16/18R162GEG0-CK8

Features

High speed up to 1066 MHz RDRAM storage 184 edge connector pads with 1mm pad spacing Module PCB size : 133.35mm x 31.75mm x 1.27mm

Form Factor

The RIMM modules are offered in 184-pad 1mm edge connector pad pitch suitable for 184 contact RIMM connectors. Figure 1 below, shows a sixteen device RIMM module.
(5.25 x 1.25 x 0.05) - 256Mb and 288Mb base PC800 RIMM Module Module PCB size : 133.35mm x 34.93mm x 1.27mm (5.25 x 1.375 x 0.05) - 256Mb and 288Mb base PC1066 RIMM Module Each RDRAM device has 32 banks, for a total of 512, 256, 128 banks on each 512/576MB, 256/288MB, 128/144MB module respectively Gold plated edge connector pad contacts Serial Presence Detect(SPD) support Operates from a 2.5 volt supply (5%) Powerdown self refresh modes Separate Row and Column buses for higher efficiency WBGA lead free package (92/84 balls)
Note: On double sided modules, RDRAM devices are also installed on bottom side of PCB.
Figure 1: RIMM Module shown with heat spreader removed

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Table 2: Module Pad Numbers and Signal Names
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 Pin Name Gnd LDQA8 Gnd LDQA6 Gnd LDQA4 Gnd LDQA2 Gnd LDQA0 Gnd LCTMN Gnd LCTM Gnd NC Gnd LROW1 Gnd LCOL4 Gnd LCOL2 Gnd LCOL0 Gnd LDQB1 Gnd LDQB3 Gnd LDQB5 Gnd LDQB7 Gnd LSCK Vcmos SOUT Vcmos NC Gnd NC Vdd Vdd NC NC NC NC Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 Pin Name Gnd LDQA7 Gnd LDQA5 Gnd LDQA3 Gnd LDQA1 Gnd LCFM Gnd LCFMN Gnd NC Gnd LROW2 Gnd LROW0 Gnd LCOL3 Gnd LCOL1 Gnd LDQB0 Gnd LDQB2 Gnd LDQB4 Gnd LDQB6 Gnd LDQB8 Gnd LCMD Vcmos SIN Vcmos NC Gnd NC Vdd Vdd NC NC NC NC Pin A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 Pin Name NC NC NC NC Vref Gnd SCL Vdd SDA SVdd SWP Vdd RSCK Gnd RDQB7 Gnd RDQB5 Gnd RDQB3 Gnd RDQB1 Gnd RCOL0 Gnd RCOL2 Gnd RCOL4 Gnd RROW1 Gnd NC Gnd RCTM Gnd RCTMN Gnd RDQA0 Gnd RDQA2 Gnd RDQA4 Gnd RDQA6 Gnd RDQA8 Gnd Pin B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 Pin Name NC NC NC NC Vref Gnd SA0 Vdd SA1 SVdd SA2 Vdd RCMD Gnd RDQB8 Gnd RDQB6 Gnd RDQB4 Gnd RDQB2 Gnd RDQB0 Gnd RCOL1 Gnd RCOL3 Gnd RROW0 Gnd RROW2 Gnd NC Gnd RCFMN Gnd RCFM Gnd RDQA1 Gnd RDQA3 Gnd RDQA5 Gnd RDQA7 Gnd

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Table 3: Module Connector Pad Description
Signal Pins A1, A3, A5, A7, A9, A11, A13, A15, A17, A19, A21, A23, A25, A27, A29, A31, A33, A39, A52, A60, A62, A64, A66, A68, A70, A72, A74, A76, A78, A80, A82, A84, A86, A88, A90, A92, B1, B3, B5, B7, B9, B11, B13, B15, B17, B19, B21, B23, B25, B27, B29, B31, B33, B39, B52, B60, B62, B64, B66, B68, B70, B72, B74, B76, B78, B80, B82, B84, B86, B88, B90, B92 B10 B12 B34 A20, B20, A22, B22, A24 A14 A12 I I I I I I RSL RSL VCMOS RSL RSL RSL I/O Type Description
Ground reference for RDRAM core and interface. 72 PCB connector pads.
LCFM LCFMN LCMD LCOL4. LCOL0 LCTM LCTMN LDQA8. LDQA0 LDQB8. LDQB0 LROW2. LROW0 LSCK
Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. Serial Command used to read from and write to the control registers. Also used for power management. Column bus. 5-bit bus containing control and address information for column accesses. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM device. LDQA8 is non-functional on modules with x16 RDRAM devices Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM device. LDQB8 is nonfunctional on modules with x16 RDRAM devices. Row bus. 3-bit bus containing control and address information for row accesses. Serial Clock input. Clock source used to read from and write to the RDRAM control registers. These pads are not connected. These 24 connector pads are reserved for future use. Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. Serial Command Input. Pin used to read from and write to the control registers. Also used for power management.
A2, B2, A4, B4, A6, B6, A8, B8, A10
B32, A32, B30, A30, B28, A28, B26, A26, B24 B16, A18, B18 A34 A16, B14, A38, B38, A40, B40, A43, B43, A44, B44, A45, B45, A46, B46, A47, B47, A48, B48, A49, B49, A50, B50, A77, B79 B83 B81 B59

RSL VCMOS

RCFM RCFMN RCMD

RSL RSL VCMOS

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Signal RCOL4. RCOL0 RCTM RCTMN RDQA8. RDQA0 RDQB8. RDQB0 RROW2. RROW0 RSCK SA0 SA1 SA2 SCL SDA SIN SOUT SVDD SWP VCMOS Vdd Vref
Pins A73, B73, A71, B71, A69 A79 A81 A91, B91, A89, B89, A87, B87, A85, B85, A83 B61, A61, B63, A63, B65, A65, B67, A67, B69 B77, A75, B75 A59 B53 B55 B57 A53 A55 B36 A36 A56, B56 A57 A35, B35, A37, B37 A41, A42, A54, A58, B41, B42, B54, B58 A51, B51

I/O I I I

Type RSL RSL RSL
Description Column bus. 5-bit bus containing control and address information for column accesses. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM device. RDQA8 is non-functional on modules x16 RDRAM devices. Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM device. RDQB8 is non-functional on modules x16 RDRAM devices. Row bus. 3-bit bus containing control and address information for row accesses. Serial Clock input. Clock source used to read from and write to the RDRAM control registers. Serial Presence Detect Address 0. Serial Presence Detect Address 1. Serial Presence Detect Address 2. Serial Presence Detect Clock. Serial Presence Detect Data (Open Collector I/O). Serial I/O for reading from and writing to the control registers. Attaches to SIO0 of the first RDRAM device on the module. Serial I/O for reading from and writing to the control registers. Attaches to SIO1 of the last RDRAM device on the module. SPD Voltage. Used for signals SCL, SDA, SWE, SA0, SA1 and SA2.

I I I I I I I/O I/O I/O

RSL VCMOS SVDD SVDD SVDD SVDD SVDD VCMOS VCMOS
Serial Presence Detect Write Protect (active high). When low, the SPD can be written as well as read. CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT. Supply voltage for the RDRAM core and interface logic. Logic threshold reference voltage for RSL signals.

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LDQA8 LDQA7 LDQA6 LDQA5 LDQA4 LDQA3 LDQA2 LDQA1 LDQA0 LCFM LCFMN LCTM LCTMN LROW2 LROW1 LROW0 LCOL4 LCOL3 LCOL2 LCOL1 LCOL0 LDQB0 LDQB1 LDQB2 LDQB3 LDQB4 LDQB5 LDQB6 LDQB7 LDQB8

LCMD RCMD

Note 1. Rambus Channel signals form a loop through the RIMM module, with the exception of the SIO chain. Note 2. See Serial Presence Detection Specification for information on the SPD device and its contents.
SIN SIO0 SIO1 SCK CMD Vref SIO0 SIO1 SCK CMD Vref SIO0 SIO1 SCK CMD Vref SIO0 SIO1 SCK CMD Vref SOUT
Vdd DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8

RDRAM Device(256/288Mb)

DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 Gnd VREF
2 per RDRAM device 0.22/0.1Fa

RDRAM Device (256/288Mb)

DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 Gnd VCMOS
1 per 2 RDRAM devices Plus one Near Connector 0.22/0.1Fa

DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 Gnd
1 per 2 RDRAM devices 0.22/0.1Fa
0.1 F : 800MHz products for 128/144MB and 256/288MB 0.22 F : the other products
Module Capacity 512/576MB 256/288MB 128/144MB N 4
RDQA8 RDQA7 RDQA6 RDQA5 RDQA4 RDQA3 RDQA2 RDQA1 RDQA0 RCFM RCFMN RCTM RCTMN RROW2 RROW1 RROW0 RCOL4 RCOL3 RCOL2 RCOL1 RCOL0 RDQB0 RDQB1 RDQB2 RDQB3 RDQB4 RDQB5 RDQB6 RDQB7 RDQB8 SVDD SCL SWP 47K SA0 SA1 SA2 Serial Presence Detect Vcc SCL SDA WP A0 A1 A2 SVDD SDA

0.22/0.1Fa

Figure 2: RIMM Module Functional Diagram

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Absolute Maximum Ratings
Table 4: Absolute Maximum Ratings
Symbol VI,ABS VDD,ABS TSTORE TPLATE Parameter Voltage applied to any RSL or CMOS signal pad with respect to Gnd Voltage on VDD with respect to Gnd Storage temperature Plate temperature Min - 0.3 - 0.5 - 50 Max VDD + 0.3 VDD + 1.92 Unit V V C C
DC Recommended Electrical Conditions
Table 5: DC Recommended Electrical Conditions
Symbol VDD VCMOS VREF VSPD Supply voltage CMOS I/O power supply at pad for 2.5V controllers: CMOS I/O power supply at pad for 1.8V controllers: Reference voltage Serial Presence Detector- Positive power supply Parameter and Conditions Min 2.50 - 0.13 VDD 1.8 - 0.1 1.4 - 0.2 2.2 Max 2.50 + 0.13 VDD 1.8 + 0.2 1.4 + 0.2 3.6 Unit V V V V V
Table 6: RIMM Module Capacity and Number of RDRAM device
RIMM Module Capacity: 512/576MB 256/288MB 128/144MB
Number of 256/288Mb RDRAM devices

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RIMM Module Current Profile
Table 7: RIMM Module Current Profile
RIMM Module Capacity IDD Number of 256/288Mb RDRAM devices RIMM Module power conditions a IDD1 One RDRAM device in Readb, balance in NAP mode One RDRAM device in Readb, balance in Standby mode One RDRAM device in Readb, balance in Active mode One RDRAM device in Write, balance in NAP mode One RDRAM device in Write, balance in Standby mode One RDRAM device in Write, balance in Active mode Freq
-1066 -800 -1066 -800 -1066 -800 -1066 -800 -1066 -800 -1066 -800
512/576MB 16 Max 760/810c 620/660 2275/2325 1985/2025 3100/3150 2585/2625 750/800 605/640 2265/2315 1970/2005 3090/3140 2570/2605
256/288MB 8 Max 728/778 588/628 1435/1485 1225/1265 1820/1870 1505/1545 718/768 573/608 1425/1475 1210/1245 1810/1860 1490/1525
128/144MB 4 Max 712/762 mA 572/612 1015/1065 mA 845/885 1180/1230 mA 965/1005 702/752 mA 557/592 1005/1055 mA 830/865 1170/1220 mA 950/985 Unit
a. Actual power will depend on memory controller and usage patterns. Power does not include Refresh Current. b. I/O current is a function of the % of 1s, to add I/O power for 50% 1s for a X16 need to add 257mA or 290mA for X18 ECC module for the following: VDD = 2.5V, VTERM = 1.8V, VREF = 1.4V and VDIL = VREF - 0.5V. c. Current values represent X16(Non-Ecc) / X18(Ecc)

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AC Electrical Specifications
Table 8: AC Electrical Specifications
Symbol ZL ZUL-CMOS TPD Parameter and Conditions Module Impedance of RSL Signals Module Impedance of SCK and CMOS signals Propagation Delay variation of RSL signals. Average clock delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM, and CFMN) Propagation delay variation of RSL signals with respect to TPD b,c for 4 and 8 device modules Propagation delay variation of RSL signals with respect to TPD b,c for 16 device modules Propagation delay variation of SCK signals with respect to an average clock delay Propagation delay variation of CMD signals with respect to SCK signal Attenuation Limit Forward crosstalk coefficient (300ps input rise time @ 20%-80%) Backward crosstalk coefficient (300ps input rise time @ 20%80%) Min 25.2 23.8 Typ Max 30.8 32.2 See Table10a,b See Table10a See Table10a See Table10a Unit

-21 -24 -250 -200

ps ps ps ps % % %
TPD-CMOS TPD-SCK,CMD V/VIN VXF/VIN VXB/VIN
a. Table 10 lists parameters and specifications for different storage capacity RIMM Modules that use 256Mb or 288Mb RDRAM devices. b. TPD or Average clock delay is defined as the delay from finger to finger of RSL signal. c. If the RIMM module meets the following specification, then it is compliant to the specification. If the RIMM module does not meet these specifica tions, then the specification can be adjusted by the Adjusted TPD Specification table 9 below.
Adjusted TPD Specification
Table 9: Adjusted TPD Specification
Symbol Parameter and Conditions Propagation delay variation of RSL signals with respect to TPD for 4 and 8 device modules Propagation delay variation of RSL signals with respect to TPD for 16 device modules Adjusted Min/Max +/-[20+(18*N*Z0)]a +/-[24+(18*N*Z0)]a Absolute Min / Max -30 -50 Unit

a. Where:

N = Number of RDRAM devices installed on the RIMM module Z0 = delta Z0% = (max Z0 - min Z0)/(min Z0) (max Z0 and min Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the modules)

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AC Electrical Specifications for RIMM Modules
Table 10: AC Electrical Specifications for RIMM Modules
RIMM Module Capacity Symbol Number of 256/288Mb RDRAM devices
Parameter and Condition for RIMM Modules
512/576MB 16 Max 2.11 2.11 27.0 25.0 8.0 8.0 2.5 2.5 1.2 1.2
256/288MB 8 Max 1.56 1.56 17.0 16.0 4.0 4.0 2.0 2.0 0.8 0.8
128/144MB 4 Max 1.56 ns 1.56 17.0 % 16.0 4.0 % 4.0 2.0 % 2.0 0.6 0.6 Unit

Freq. -1066

Propagation Delay, all RSL signals -800 -1066 Attenuation Limit -800 Forward crosstalk coefficient (300ps input rise time @ 20%-80%) Backward crosstalk coefficient (300ps input rise time @ 20%-80%) -1066 -800 -1066 -800 -1066

VXF/VIN

VXB/VIN

DC Resistance Limit -800

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Physical Dimensions -1 ( For PCB )

The following defines the RIMM module dimensions. All units are in millimeters with inches in brackets[ ], where appropriate. The dimensions without tolerance specification use the default tolerance of 0.127[0.005].
133.350.127[5.2500.005] 6.35[0.25] 3.00[0.118]
120.65[4.75] DIA 2.44 R 2.00

17.78[0.700]

COMPONENT AREA (A SIDE)

4.000.15 [0.1570.006]

31.75[1.25]

7.468[0.294]

5.68[0.2236]

Min.6.35[0.25]

29.21[1.15]

DETAIL A

1.00[0.039]

DETAIL B 11.50[0.453]

A-92 45.00[1.772] R 1.00 78.175[3.078]
45.00[1.772] 4.50[0.177] 55.1750.08[2.1720.003]

8.60[0.339]

COMPONENT AREA (B SIDE)
Note : The gray area above represents the contact surface of the heat spreader.

0.800.10 [0.0310.004]

Heat spreader
1.00[0.039] Min.4.88 [0.192] 0.150.10 [0.0060.004] 2.990.05 [0.120.002] 3.000.10 [0.120.004]

2.000.10 [0.0790.004]

DETAIL B
Figure 3: 256Mb/288Mb base RIMM Module PCB Physical Dimensions

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Physical Dimensions -2 ( For PCB )

34.93[1.375]

Figure 4: 256Mb/288Mb base RIMM Module PCB Physical Dimensions

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Physical Dimensions -3 ( For Heat Spreader )
1270.25[5.00.009] 120.660.12[4.7480.005] 108.810.12[4.2830.005] 2.9 [0.114]

13.7[0.539]

26.54[1.045]
DIA 2.360.05[0.090.001] Center-Point

WARNING ! HOT SURFACE

http://www.samsungsemi.com

12.70.07[0.50.002]

1.000.07 [0.040.002]
133.350.127[5.2500.005] 1270.25[5.00.009]

A SECTION A-A

Max 4.70 [0.185] Heat Spreader CSP Thermal Conductive Gap Filling Material PCB 1.270.10 [0.0500.004]

SECTION A-A

Max 7.80 [0.307] Heat Spreader CSP Thermal Conductive Gap Filling Material PCB 1.270.10 [0.0500.004]

[ Single side module ]

[ Double side module ]
Figure 5: Heat Spreader Physical Dimensions

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Physical Dimensions -4 ( For Heat Spreader )

16.5[0.649]

29.42[1.158]
Figure 6: Heat Spreader Physical Dimensions

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Standard RIMM Module Marking
The RIMM modules available from Samsung are marked like Figure 7 below. This marking also assists users to specify and verify if the correct RIMM modules are installed in their systems. In the diagram, a label is shown attached to A B C D E F G the RIMM modules heat spreader. Information contained on the label is specific to the RIMM module and provides RDRAM device information without requiring removal of the RIMM modules heat spreader.
KOREA 0420 512MB /16 ECC MR18R162GEG0-CT9 1066-32P 102
Label Field A B C D E F G H Vendor Logo Country Year & Week code Module Memory Capacity Number of RDRAM devices ECC Support Notice! Caution Logo Gerber & SPD Version tRAC Memory Speed Part No.
Marked Text SAMSUNG KOREA yyww 128MB, 256MB, 512MB 4/8/16 blank = 8 bit Bytes ECC = 9 bit Bytes Gerber : 10 = 1.0 ver. Unit RDRAM devices -
Description RIMM Module Vendor SAMSUNG Logo Area Country of origin Manufactured Year & Week code Number of 8-bit or 9-bit MBytes of RDRAM storage in RIMM module Number of RDRAM devices contained in the RIMM module Indicates whether the RIMM module supports 8 (non ECC) or 9 (ECC) bit Bytes Hot surface caution notice. ISO Standard PCB Gerber file & SPD code version used on RIMM Module SPD : Row Access Time Data transfer speed for RDRAM devices SAMSUNG RIMM Module part No.
01 = 0.1 ver. 2 = 1.3 ver.
-32P, -40, -45 1066, 800 See Table 1

ns MHz -

Figure 7: RIMM Module Marking Example

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Table Of Contents
Overview. 1 Features. 1 Key Timing Parameters/Part Numbers. 1 Module Pad Numbers and Signal Names. 2 Module Connector Pad Description. 3 - 4 RIMM Module Functional Diagram. 5 Absolute Maximum Ratings. 6 DC Recommended Electrical Conditions. 6 RIMM Module Supply Current Profile. 7 AC Electrical Specifications. 8 - 9 Physical Dimensions -1, -2 ( For PCB ). 10 - 11 Physical Dimensions -3, -4 ( For Heat Spreader). 12 - 13 Standard RIMM Module Marking. 14
Copyright May 2004, Samsung Electronics. All rights reserved. Direct Rambus, Direct RDRAM and SO-RIMM are trademarks of Rambus Inc. Rambus, RDRAM, RIMM and the Rambus Logo are registered trademarks of Rambus Inc. This document contains advanced information that is subject to change by Samsung Electronics without notice Document Version 1.0 Samsung Electronics Co. Ltd. San #16 Banwol-ri, Taean-Eup Hwasung-City, Gyeonggi-Do, KOREA Telephone: 82-31-208-6369 Fax: 82-31-208-6799 http://www.intl.samsungsemi.com