Equipment Brief Motorola SLVR L7 Launch Announcement LAUNCH DETAILS
Cingular is excited to launch the Motorola SLVR L7 on January 31, 2006. The SLVR L7 is considered an Exclusive Product, under Cingulars exclusive distribution policy and therefore distribution will be limited to Cingular-direct channels and indirect partners that fulfill our exclusive distribution parameters.

PHONE DETAILS

The new ultra-sleek phone with iTunes only at Cingular. The Motorola SLVR L7 is exclusive to Cingular Wireless. This bladelike, RAZR influenced, super-slim device can store and play iTunes music for a combined music experience in a trendy form factor. Features of the Motorola SLVR L7 include the following:
Motorola SLVR L7 Device Overview
iTunes music player: accessed via right soft-key 850/900/1800/1900 MHz Quad band GPRS class 10 Talk time: 6.3 hours Standby time: 420 hours/17 days Removable memory: Micro SD card included Camera: VGA with 4x zoom, video capture Messaging: SMS/MMS IM: AOL, Yahoo!, and ICQ POP3/IMAP4 email Bluetooth class 2 (range up to 100 feet for voice only) 262k colors 176 x 220 TFT screen
Refer to local market pricing for pricing details
KEY SELLING POINTS THE CINGULAR ADVANTAGE
Play iTunes music by playlist, artist, albums, songs and shuffleand it stores about 7 hours of music (up to 100 songs) on the included 512MB Micro SD extended memory card. Customers can personalize their phone with downloads including games and graphics and Music Tone ringtones. Stay in touch with friends and family with AOL, Yahoo! or ICQ Instant Messenger. Capture those special moments with built in VGA camera and video record. The SLVR L7 has Bluetooth allowing conversations up to 100 feet away. (does not support music profile)

CRITICAL MUST KNOW

Orange - Memphis SKU: 64292 Blue Dallas ATC UPC: 723755934016 The Motorola SLVR L7 includes additional in-box content to support iTunes functionality: SLVR L7 phone, Battery, Travel Charger, User Manual, Quick Start Guide & iTunes insert iTunes PC software with USB cable Removable 512 MB Micro SD memory card. (Card is preinstalled in the device & is required to use iTunes) Stereo headset & 3.5 mm headset adaptor Phone Features & Functionality: Features and functionality of the Motorola SLVR L7 are similar to the Motorola RAZR. Refer to FAQs for comparisons. Handset Insurance: Not at launch
MOTOROLA SLVR L7 LAUNCH ANNOUNCEMENT
Equipment Brief COMPETITIVE OVERVIEW
Cingular is the only U.S wireless carrier to offer the Motorola SLVR L7 (iTunes phone)
These music devices range in price from $119 to $299 after 2 yr contract and MIR.
Cingular Data as of 1/17/2006 Motorola L7 Motorola E1 SE W600i Sprint Samsung Sanyo MMAT-Mobile Samsung t809 Verizon "V" LG Motorola VX9800 E815
Size (in) Style Technology Bands Camera BT/ Stereo BT Speakerphone Internal Memory Removable Memory
1.9" x 4.5" x 0.45"
4.25" x 1.81" x 0.80"
3.66" x 1.83" x 0.89"
3.86" x 2.01" x 0.57"
3.41" x 1.94" x 1.11"
3.90" x 2.00" x 0.58"
4.57" x 1.97" x 3.71" x 1.95" x 1.00" 1.01"

Thin Line Bar GPRS

850/900/1800 /1900

Bar GPRS

850/1800/1900

Twist EDGE

Clam EV-DO

Dual mode (850/1900)

Slider EDGE
Clam EV-DO Dual mode (850/1900) 1.3MP w/ flash BT but no A2DP yes 40MB microSD up to 256MB (not included)
VGA BT but no A2DP yes 5MB microSD (512MB card included) hot swappable music tone yes yes

VGA BT but no A2DP yes 5MB microSD (512MB card included) music tone yes yes
1.3MP BT but no A2DP yes 256 MB no
1.3MP BT but no A2DP yes 52MB no
1.3MP w/ flash no BT yes 70MB no
1.3MP BT but no A2DP yes 70MB microSD (included)
1.3MP w/ flash BT but no A2DP yes 128MB mini SD (not included)
Ringtones Video Record Video Player

music tone yes yes

music tone yes Streaming Video

HiFi Ringers yes yes

true tone real true tone real music ringers music ringers yes Streaming Video yes Streaming Video

Music Download

Music Players Dedicated Controls
Sync from PC Sync from PC Sync from PC Sync from PC Sync from PC Sync from PC Sync from PC to to to Sync from PC to to to phone or to phone or phone/memory phone/memor phone/memory to phone phone/memor phone/memor OTA OTA card y card card y card or OTA y card or OTA iTunes (MP3, iTunes (MP3, Walkman MP3 (MP3, MP3 (MP3, MP3 MP3, WMA MP3, WMA AAC) AAC) (MP3, AAC) AAC, AAC+) AAC, AAC+) no =strength music launch button no no no no no no

ACCESSORIES

The Motorola SLVR L7 uses EMU standard mini USB Motorola accessories (same as the RAZR).

Equipment Brief

Orange SKU 64037 Blue SKU 723755640375 Item Description BAT MOTLEXT/DR LI OR BAT MOTLSTD LI OR CAS MOTL7 2PK BL/BW AR CAS MOTL7 BK ARMBAND AR CHR MOTV3 TRAVEL CHR AR CLA MOTV3 VPC OR DAT MOTV220/180/3 USB CABLE OR EBD MOTV3 USB HEADSET OR HDS JAB250v BLUETOOTH AR HDS MOTHS801 BLUETOOTH OR HDS MOTHS815 BLUETOOTH OR HDS MOTHS820 BT W/Y-CABLE OR HDS MOTHS850 BLUETOOTH OR HDS MOTL7 3.5/EMU ADAPTER OR HDS MOTL7 EMU STEREO HDS OR HDS MOTO BT H500 HDS PLA320 EXPLORER BT AR HDS PLA510 VOYAGER BT AR HDS PLA640 DISCOVERY BT AR HDS PLAM2500 BLUETOOTH OR HDS SERHBH-608 BT AR HDS UNIVBLUETOOTH W/CHARGER OR HDS UNIVUNIV BT W/CHARGER AR MISC LG Portable Speakers OR MISC MOTHF800 BT WRLES SPKR OR MISC MOTROKR E1 512MB MICSD AR MISC RAZRWIRE BLACK OR MISC RAZRWIRE MERCURY OR MISC RAZRW IRE ROOTBEER OR SRP $44.99 $41.99 $29.99 $29.99 $29.99 $29.99 $24.99 $21.99 $79.99 $39.99 $49.99 $79.99 $99.99 $19.99 $29.99 $89.99 $49.99 $79.99 $119.99 $49.99 $79.99 $89.99 $69.99 $49.99 $99.99 $69.99 $294.99 $294.99 $294.99

TRAINING

Learning Edge and Cingular University Course code: MOT113 Details, one page training job aid and FAQs can be found on the Description page on CSP, keyword: iTunes Phone specs and equipment pricing can be found in the Equipment Catalog located on CSP
iTunes just like you know it - Heres how easy it is: Load o o Listen o
Install the included iTunes PC software Connect the phone & load up to 100 songs share from your existing iTunes music library
Use the iTunes soft key to play, shuffle & show artist information, just like iPod. Never miss a beat o Pause music when you get a call Resume music with the press of a button once you hang up

Suggested Qualifying Questions: Did you know the SLVR L7 has an Airplane Mode allowing you to listen to your iTunes music when traveling? And speaking of traveling isnt it important for you to rely on your phone regardless of where you are? The SLVR L7 is a Quad Band World Phone which will pick up on any available GSM network on the globe. Are you aware that with a Bluetooth headset, the SLVR L7 allows conversations up to 100 feet away? Most Bluetooth phones can only support up to 30 feet. The SLVR L7 is much more that just a cool looking iTunes device. Did you know this phone also has a VGA camera with 4x zoom and video capture capabilities? Dont you like to personalize? The large non scratch display is great for photos and downloadable graphics. Do you like the look of the RAZR but prefer a candy bar form factor?

K4S640832N K4S641632N

Synchronous DRAM
64Mb N-die SDRAM Specification
54 TSOP-II with Pb-Free and Halogen Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.

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Rev. 1.1 December 2007

Table of Contents

1.0 FEATURES.... 4 2.0 GENERAL DESCRIPTION... 4 3.0 Ordering Information.... 4 4.0 Package Physical Dimension.... 5 5.0 FUNCTIONAL BLOCK DIAGRAM.... 6 6.0 PIN CONFIGURATION.... 7 7.0 Input/Output Function Description... 7 8.0 ABSOLUTE MAXIMUM RATINGS.... 8 9.0 DC OPERATING CONDITIONS.... 8 10.0 CAPACITANCE.... 8 11.0 DC CHARACTERISTICS... 9 12.0 AC OPERATING TEST CONDITIONS.... 11 13.0 OPERATING AC PARAMETER.... 11 14.0 AC CHARACTERISTICS.... 12 15.0 DQ BUFFER OUTPUT DRIVE CHARACTERISTICS... 12 16.0 IBIS SPECIFICATION.... 13 17.0 SIMPLIFIED TRUTH TABLE.... 15

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Year - Release SPEC revision 1.0 - Revised ICC6 SPEC of lowpower History

Revision History

Revision 1.0 1.1 Month December December

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2M x 8Bit x 4Banks / 1M x 16Bit x 4Banks SDRAM 1.0 FEATURES
JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM (x8) & L(U)DQM (x16) for masking Auto & self refresh 64ms refresh period (4K cycle) Pb-free and Halogen-free Package RoHS compliant

2.0 GENERAL DESCRIPTION

The K4S640832N / K4S641632N is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

3.0 Ordering Information

Part No. K4S640832N-LC/L75 K4S641632N-LC/L50 K4S641632N-LC/L60 K4S641632N-LC/L75 4Mb x 16 Orgainization 8Mb x 8 Max Freq. 133MHz(CL=3) 200MHz(CL=3) 166MHz(CL=3) 133MHz(CL=3) LVTTL 54pin TSOP(II) Pb-free & Halogen-Free Interface Package

Organization 8Mx8 4Mx16

Row Address A0~A11 A0~A11
Column Address A0-A8 A0-A7
Row & Column address configuration

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4.0 Package Physical Dimension

Unit : mm

#54 #28 (0.80) (0.50) (10) (10) 0.125 - 0.035

+0.075

10.16 0.10

(1.50)

(0.80)

0.665 0.05

0.210 0.05

1.00 0.10

22.22 0.10

0.1 5)

1.20 MAX

(0.50)

#1 (1.50)

11.76 0.20

(10.76)

0.05 MIN

0. 15 )

(0.71)

0.80TYP [0.80 0.08]

0.35 - 0.05

0.075 MAX

0. 25 )

NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASSY OUT QUALITY
54Pin TSOP(II) Package Dimension

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0.10 MAX

0.45 ~ 0.75 0.25TYP

5.0 FUNCTIONAL BLOCK DIAGRAM

I/O Control

LWE LDQM
Data Input Register Bank Select 2M x 8 / 1M x 16 2M x 8 / 1M x 16 2M x 8 / 1M x 16 2M x 8 / 1M x 16 Refresh Counter

Output Buffer

Row Decoder

Sense AMP

Row Buffer

Address Register

CLK ADD
Column Decoder Col. Buffer Latency & Burst Length Programming Register
LCKE LRAS LCBR LWE LCAS Timing Register

L(U)DQM

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6.0 PIN CONFIGURATION

x16 x8
VSS DQ7 VSSQ N.C DQ6 VDDQ N.C DQ5 VSSQ N.C DQ4 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS N.C/RFU UDQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS
VDD VDD DQ0 DQ0 VDDQ VDDQ DQ1 N.C DQ2 DQ1 VSSQ VSSQ DQ3 N.C DQ4 DQ2 VDDQ VDDQ DQ5 N.C DQ6 DQ3 VSSQ VSSQ DQ7 N.C VDD VDD LDQM N.C WE WE CAS CAS RAS RAS CS CS BA0 BA0 BA1 BA1 A10/AP A10/AP A0 A0 A1 A1 A2 A2 A3 A3 VDD VDD
54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch)
7.0 Input/Output Function Description
Pin CLK CS Name System clock Chip select Description Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : (x8 : CA0 ~ CA8 , x16 : CA0 ~ CA7) Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15) Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device.

Clock enable

A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM DQ0 ~ N VDD/VSS VDDQ/VSSQ N.C/RFU
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No connection /reserved for future use

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Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +50 Unit V V C W mA
8.0 ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current
Note : Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
9.0 DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VDD, VDDQ VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.Max 3.6 VDD+0.3 0.8 0.Unit V V V V V uA IOH = -2mA IOL = 2mA 3 Note
Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

10.0 CAPACITANCE

Pin Clock RAS, CAS, WE, CS, CKE, DQM Address (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~DQ15) Symbol CCLK CIN CADD COUT Min 2.5 2.5 2.5 4.0 Max 4.0 5.0 5.0 6.5
(VDD = 3.3V, TA = 23C, f = 1MHz) Unit pF pF pF pF Note

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11.0 DC CHARACTERISTICS (x8)
(Recommended operating condition unless otherwise noted, TA = 0 to 70C for x8) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns Test Condition Version 15 mA mA 25 mA Unit Note

ICC1 ICC2P ICC2PS ICC2N

CKE VIH(min), CLK VIL(max), tCC = ICC2NS Input signals are stable ICC3P ICC3PS ICC3N ICC3NS CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L
Operating current (Burst mode) Refresh current Self refresh current

ICC4 ICC5 ICC6

mA mA mA uA
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S640832N-LC 4. K4S640832N-LL 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)

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K4S640832N K4S641632N DC CHARACTERISTICS (x16)
(Recommended operating condition unless otherwise noted, TA = 0 to 70C for x16 only) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Symbol Test Condition Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L

Version

ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS

mA mA 25 mA

130 130

110 110

Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S641632N-LC 4. K4S641632N-LL 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)

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(VDD = 3.3V 0.3V, TA = 0 to 70C) Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 Unit V V ns V Parameter

12.0 AC OPERATING TEST CONDITIONS
AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition

Vtt = 1.4V

1200 Output 870 30pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
13.0 OPERATING AC PARAMETER
Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency = 3 CAS latency = Version 2
(AC operating conditions unless otherwise noted) Unit ns ns ns ns us 65 ns CLK CLK CLK CLK ea 1, 6 2,5,Note 1 1

2 CLK + tRP 1

Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. 6. tRC =tRFC, tRDL = tWR.

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(AC operating conditions unless otherwise noted) 50 (x16 only) Min 1.1 Max 1000 4.5 4.(x16 only) Min 2.2.5 2.5 1.1 Max 6 Min 7.2.5 2.5 1.5 0.75 Max 1000 5.5.Unit Note

14.0 AC CHARACTERISTICS

Parameter CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 Symbol
CLK cycle time CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z

tOH tCH tCL tSS tSH tSLZ

ns ns ns ns ns ns ns

3 3, 4 3, 4 2

CAS latency=3 CAS latency=2
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. 4. tSS applies for address setup time, clock enable setup time, commend setup time and data setup time tSH applies for address holde time, clock enable hold time, commend hold time and data hold time

15.0 DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter Output rise time Output fall time Output rise time Output fall time Symbol trh tfh trh tfh Condition Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Min 1.37 1.30 2.8 2.0 3.9 2.9 Typ Max 4.37 3.8 5.6 5.0 Unit Volts/ns Volts/ns Volts/ns Volts/ns Notes 1,2 1,2
Notes : 1. Rise time specification based on 0pF + 50 to VSS, use these values to design to. 2. Fall time specification based on 0pF + 50 to VDD, use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to VSS.

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200MHz/133MHz Pull-up

16.0 IBIS SPECIFICATION

IOH Characteristics (Pull-up)
Voltage (V) 3.45 3.30 3.00 2.70 2.50 1.95 1.80 1.65 1.50 1.40 1.00 0.20 200MHz/133MHz 200MHz/133MHz Min Max I (mA) I (mA) -1.68 -19.11 -0.35 -51.87 -3.75 -90.44 -6.65 -107.31 -13.75 -137.9 -17.75 -158.34 -20.55 -173.6 -23.55 -188.79 -26.2 -199.01 -36.25 -241.15 -46.5 -351.0 -100 -200 mA -300 -400 -500 -600 Voltage
IOH Min (200MHz / 133MHz) IOH Max (200MHz / 133MHz)

200MHz/133MHz Pull-down

IOL Characteristics (Pull-down)
Voltage (V) 3.45 3.30 3.00 1.95 1.80 1.65 1.50 1.40 1.00 0.85 0.65 0.40 200MHz/133MHz 200MHz/133MHz Min Max I (mA) I (mA) 43.92 155.82 43.36 153.72 41.20 148.40 40.56 146.02 39.60 141.75 38.40 136.08 37.28 131.39 30.08 105.84 26.64 93.66 21.52 75.25 14.16 49.14

150 mA 0.1.2.3.5 Voltage

IOL Min (200MHz / 133MHz) IOL Max (200MHz / 133MHz)

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VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V) 0.0 0.2 0.4 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 I (mA) 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.23 1.34 3.02 5.06 7.35 9.83 12.48 15.30 18.31 20
Minimum VDD clamp current (Referenced to VDD)

1 Voltage

I (mA)
Minimum VSS clamp current
VSS Clamp @ CLK, CKE, CS, DQM & DQ
VSS (V) -2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2 0.0 I (mA) -57.23 -45.77 -38.26 -31.22 -24.58 -18.37 -12.56 -7.57 -3.37 -1.75 -0.58 -0.05 0.0 0.0 0.0 0.-10 -20 mA -30 -40 -50 -60

Voltage

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(V=Valid, X=Dont care, H=Logic high, L=Logic low)

CKEn CS RAS CAS WE DQM BA0,1 A10/AP A11, A9 ~ A0 Note CKEn-1
17.0 SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Self refresh Entry Exit H H L H H H H Bank selection All banks Entry Exit Entry Precharge power down mode Exit DQM No operation command L H H X H L H H H L H X H L H X X X X X L H L L L L H L L L L L H L X H L H L L L H X L H H H L X V X X H X V X X H X H L L H X H L L H H X V X X H X V
L H H X H H L L L X V X X H X V X H
X X X X X X X X X X X V X V V V
OP code X X Row address L H L H X L H X X
Column address Column address

1,4,4,5 6

Bank active & row addr. Read & column address Write & column address Burst stop Precharge Clock suspend or active power down Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable

X X V X X X 7

Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

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