TD-LTE and FDD-LTE

A Basic Comparison
Prepared by: Angel Ivanov

Date: 23 Nov 2010

Document: NT10-00185
Ascom (2010) All rights reserved. TEMS is a trademark of Ascom. All other trademarks are the property of their respective holders.

Contents

List of Acronyms... 3 Definition of TDD and FDD.. 4 Differences between FDD-LTE and TD-LTE. 5 Frequency Bands for FDD-LTE and TD-LTE. 6 Peak Downlink and Uplink Data Rates.. 7 Operators Challenges... 9

Ascom (2010)

3GPP ACK CDMA DL EDGE FDD GSM GPRS HARQ HSCSD HSDPA HSPA HSUPA IS-95-B LTE MIMO NACK PUCCH R99 RB RBS RE TDD TD-LTE

List of Acronyms

Definition Third Generation Partnership Project Positive Acknowledgement Code Division Multiple Access Downlink Enhanced Data Rates for GSM Evolution Frequency Division Duplexing Global System for Mobile Communication General Packet Radio Service Hybrid Automatic Repeat Request High Speed Circuit Switch Data High Speed Downlink Packet Access High Speed Packet Access High Speed Uplink Packet Access Interim Standard 95 Revision B Long Term Evolution Multiple Input Multiple Output Negative Acknowledgement Physical Uplink Control Channel WCDMA Release 99 Resource Block Radio Base Station Resource Element Time Division Duplexing Time Division Duplexing LTE Time Division Synchronous CDMA Quadrature Amplitude Modulation Quadrature Phase Shift Keying User Equipment Uplink Wideband CDMA

Term or Acronym

TD-SCDMA QAM QPSK UE UL WCDMA
Definition of TDD and FDD
In communication systems, a user needs to exchange data with one or more parties through a shared resource a common channel. Depending on whether the data is transmitted/received simultaneously, the following transmission techniques exist: 1. Simplex One party transmits data and the other party receives data. No simultaneous transmission is possible the communication is one-way and only one frequency (channel) is used. Examples of simplex communication are traditional (noninteractive) radio and television. 2. Half Duplex Each party can receive and transmit data, but not at the same time. The communication is two-way and only one frequency (channel) is used. Examples of half duplex communication are walkie-talkies or other two-way radio systems. 3. Full Duplex Each party can transmit and receive data simultaneously. The communication is two-way and two frequencies (channels) are used one for transmitting and one for receiving. In the case of cellular networks, a limited shared resource (spectrum) needs to be shared with all users so full duplex communication is possible (Note that full duplex service, like regular phone conversation, can be carried over a half duplex channel). The two main methods used are: 1. Time Division Duplexing (TDD) The communication is done using one frequency, but the time for transmitting and receiving is different. This method emulates full duplex communication using a half duplex link. 2. Frequency Division Duplexing (FDD) The communication is done using two frequencies and the transmitting and receiving of data is simultaneous. The advantages of TDD are typically observed in situations where the uplink and downlink data transmissions are not symmetrical. Also, since the transmitting and receiving is done using one frequency, the channel estimations for beamforming (and other smart antenna techniques) apply for both the uplink and the downlink. A typical disadvantage of TDD is the need to use guard periods between the downlink and uplink transmissions. The advantages of FDD are typically observed in situations where the uplink and downlink data transmissions are symmetrical (which is not usually the case when using wireless phones). More importantly, when using FDD, the interference between neighboring Radio Base Stations (RBSs) is lower than when using TDD. Also, the spectral efficiency (which is a function of how well a given spectrum is used by certain access technology) of FDD is greater than TDD.

Differences between FDD-LTE and TD-LTE
The two versions of LTE are very similar. In fact, they differ only in the physical layer and, as a result, the version implemented is transparent to the higher layers. This means that UEs will be able to support both TD-LTE and FDD-LTE with one chipset with only minor modifications required. All major chipset vendors ST-Ericsson (M700/M710 chipsets), Altair Semiconductor (FourGee-6150 chipset), and Qualcomm (MDM9200/ MDM9600 chipsets) have already released chipsets that support both LTE flavors. UEs based on those chipsets are (or will soon be) available from Sony Ericsson, Huawei, Samsung, Nokia, and others. The following features are unique to TD-LTE: 1. Frame structure 3GPP has specified a special subframe that allows switching between downlink and uplink transmission. 2. Random access Several additional random access formats exist in certain subframes. Also, several random access channels exist in every subframe. 3. Scheduling The scheduling for the uplink is multi-frame. 4. HARQ The number of HARQ processes depends on the uplink/downlink resource allocation. 5. ACK/NACK Multiple acknowledgements and negative acknowledgements are combined on the uplink control channels. This ultimately leads to increased control signaling and lower spectrum/resource utilization. 6. Guard periods These are used in the center of special subframes. They allow for the advance of the uplink transmission timing. Another difference between FDD-LTE and TD-LTE is that in FDD-LTE every downlink subframe can be associated with an uplink subframe. In TD-LTE the number of downlink and uplink subframes is different and such association is not possible. Additionally, the uplink coverage with respect to a specific data rate in TD-LTE is generally worse than FDD-LTE due to the fact that the uplink transmission is not continuous. The percentage of coverage for control and data channels is, however, very similar to that of FDD-LTE. In terms of spectrum efficiency, the performances of TD-LTE and FDD-LTE are similar for non-delay sensitive traffic. The lower performance of TD-LTE is due to the guard periods mentioned above. Finally, TD-LTE and TD-SCDMA work together with minimum interference issues, even if both technologies are deployed in the same frequency band (assuming that the TD-LTE UL:DL configurations are chosen correctly and both systems are synchronized to the same time source).
Frequency Bands for FDD-LTE and TD-LTE

The frequency bands listed in Table 1 are currently defined by 3GPP for TD-LTE and FDD-LTE.
Table 1 LTE Frequency Bands LTE Operating Band Uplink, MHz FUL_low FUL_high Downlink , MHz FDL_low FDL_high Duplex Separation, MHz Duplex Mode
1710 - 915 1749.9 1784.1770 1427.9 1447.2400
1844.9 1879.2170 1475.9 1495.2400
30 N/A N/A N/A N/A N/A N/A N/A N/A
FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD TDD TDD TDD TDD TDD TDD TDD TDD
Typically, a wireless operator will be allowed to operate a LTE network in a certain band and its bandwidth will be allocated in terms of Resource Blocks (RBs), as listed in Table 2.
Table 2 LTE Channel Bandwidth Channel bandwidth, MHz Number of Resource Blocks 1.20 100
Peak Downlink and Uplink Data Rates
The peak data rates for various channel bandwidths and antenna options for both FDD-LTE and TD-LTE are shown in Tables 3 and 4.
Table 3 Peak Downlink Data Rates for FDD-LTE & TD-LTE (frame structure type 1) Channel bandwidth, MHz Number of Resource Blocks Modulation QPSK 16 QAM 64 QAM 64 QAM 64 QAM MIMO Not Used Not Used Not Used 2x2 4x4 1.728 3.456 5.184 10.368 20.736 4.32 8.64 12.96 25.92 51.84 1.5 25

20 100

Data Rate , Mb/s 7.2 14.4 21.6 43.2 86.4 14.4 28.8 43.2 86.4 172.8 21.6 43.2 64.8 129.6 259.2 28.8 57.6 86.4 172.8 345.6
Table 4 Peak Uplink Data Rates for FDD-LTE & TD-LTE (frame structure type 1) Channel bandwidth, MHz Number of Resource Blocks Modulation QPSK 16 QAM 64 QAM MIMO Not Used Not Used Not Used 1.8 3.45 5.184 4.5 8.64 12.96 1.5 25
Data Rate , Mb/s 7.5 14.4 21.28.8 43.2 22.5 43.2 64.57.6 86.4
Assumes no coding and 12 RE per RB for control channels and reference signals Assumes no coding and 12 RE per RB for reference signals (PUCCH will reduce the rate slightly)
Table 5 contains a comparison between the downlink and uplink data rates for the currently active wireless standards:
Table 5 DL and UL Data Rates for various wireless technologies Standard GSM 3 GPRS 4 HSCSD 5 EDGE 6 EDGE Evolution WCDMA R99 HSPA 7 HSPA+ 8 CDMA (IS-95) 9 CDMATD-SCDMA 11 LTE DL Data Rate, Mb/s 0.0096 0.08 0.0432 0.2368 1.89 0.384 14.4 84.4 0.1152 4.9xN 8.4 345.6 UL Data Rate, Mb/s 0.0096 0.02 0.0144 0.0592 1.42 0.384 5.0.0096 1.8xN 5 86.4
Assumes allocation of 4 timeslots in the DL and 1 in the UL Assumes allocation of 3 timeslots in the DL and 1 in the UL 5 Assumes allocation of 4 timeslots in the DL and 1 in the UL 6 Assumes allocation of 8 timeslots in the DL and 6 in the UL 7 Assumes Dual Cell HSDPA (10 MHz) with 64 QAM and 2x2 MIMO 8 Assumes the use of IS-95-B 9 Assumes EVDO Rev B. N is the number of 1.25 MHz carriers that are used. 64 QAM is used in the DL 10 Assumes single carrier TD-SCDMA HSPA+ and 64 QAM 11 Assumes 20 MHz of bandwidth, 64 QAM and 4x4 MIMO in the DL

Operators Challenges

Wireless operators are constantly looking for ways to reduce their operational expenses while increasing their revenue. In recent years, the focus has been on introducing and/or identifying data applications that are attractive to consumers while being inexpensive to implement and support. Additionally, operators such as China Mobile are searching for a nextgeneration technology that will overcome the limitations of TD-SCDMA (limited/expensive handsets available only in the domestic market; multiple mode handsets needed for global roaming). Finally, a technology that will address the continuously growing data traffic is needed. LTE seems to address all these challenges. Even though many operators around the world have committed to deploying LTE as their next-generation wireless network, the possibility of using TD-LTE has not been generally considered. Recently, however, more and more operators (including Aircel (India), China Mobile (China), Aero2 (Poland), and Infotel (RIL India), vividwireless (Australia)) have expressed their support for TD-LTE, which is a clear indication that the technology will become widely accepted. The main reasons for that sudden interest are the following: 1. The differences between FDD-LTE and TD-LTE are minimal, and single devices can support both technologies with one chipset device availability will not be an issue. 2. The TDD spectrum is less expensive. 3. Both offer similar performance/spectral efficiency. 4. Handovers can be performed between FDD-LTE, WCDMA, TD-SCDMA, GSM, and CDMA. 5. Some of the frequency bands for TD-LTE overlap with WiMax bands, making it an attractive evolution path for WiMax operators. 6. TD-LTE is suitable for M2M (machine to machine) applications (such as Point of Sale, Fleet Management, Health Care Monitoring, etc.) due to its adaptable UL and DL configuration. Finally, according to recent estimates of LTE rollout scenarios 12 a medium size tier one operator will need to invest about $8 Billion USD CAPEX to deploy LTE in the first 3 to 5 years. Similarly, the OPEX expenses could increase the operators current OPEX costs by roughly 30%. Overall, TD-LTE offers operators a great alternative to FDD. Its natural suitability for asymmetric applications, low latency, high throughput, and security make it a flexible and cost-effective solution for the next generation wireless networks.

See http://www.aircominternational.com for more information

Preface

The S3C826A/P826A Microcontroller User's Manual is designed for application designers and programmers who are using the S3C826A/P826A microcontroller for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has six chapters: Chapter 1 Chapter 2 Chapter 3 Product Overview Address Spaces Addressing Modes Chapter 4 Chapter 5 Chapter 6 Control Registers Interrupt Structure Instruction Set
Chapter 1, "Product Overview," is a high-level introduction to S3C826A/P826A with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations. Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the S3C8-series CPU. Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. Chapter 5, "Interrupt Structure," describes the S3C826A/P826A interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II. Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3C8-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each instruction are presented in a standard format. Each instruction description includes one or more practical examples of how to use the instruction when writing an application program. A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part II. If you are not yet familiar with the S3C8-series microcontroller family and are reading this manual for the first time, we recommend that you first read Chapters 13 carefully. Then, briefly look over the detailed information in Chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary. Part II "hardware Descriptions," has detailed information about specific hardware components of the S3C826A/P826A microcontroller. Also included in Part II are electrical, mechanical, OTP, and development tools data. It has 15 chapters: Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Clock Circuit RESET and Power-Down I/O Ports Basic Timer and Timer 0 Timer 1 8-bit Timer 2 8-bit Timer 3 Watch Timer Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 Chapter 21 LCD Controller/Driver 10-bit Analog-to-Digital Converter Serial I/O Interface Electrical Data Mechanical Data S3P826A OTP Development Tools

List of Tables (Continued)
Table Number 20-1 20-2 20-3 21-1 21-2 Title Page Number
Descriptions of Pins Used to Read/Write the EPROM... 20-3 Comparison of S3P826A and S3C826A Features.. 20-3 Operating Mode Selection Criteria.... 20-3 Power Selection Settings for TB826A.. 21-4 The SMDS2+ Tool Selection Setting... 21-4

List of Programming Tips

Description Chapter 2: Address Spaces Page Number
Using the Page Pointer for RAM clear (Page 0, Page1)...2-5 Setting the Register Pointers....2-9 Using the RPs to Calculate the Sum of a Series of Registers...2-10 Addressing the Common Working Register Area...2-14 Standard Stack Operations Using PUSH and POP....2-19 Chapter 5: Interrupt Structure
How to Clear an Interrupt Pendign Bit....5-15 Chapter 7: Clock Circuit
Switching the CPU clock.....7-6
List of Register Descriptions
Register Identifier ADCON BTCON CLKCON FLAGS IMR INTPND IPH IPL IPR IRQ LCON LMOD OSSCON P0CONH P0CONL P0INT P0PND P0EDGE P1CONH P1CONL P1PUR P2CONH P2CONL P2PUR P3CONH P3CONL P3INT P3PUR PG0CON PG1CON PG2CON PG3CON PG4CON PP RP0 RP1 SIOCON SPH SPL STPCON SYM T0CON TACON TBCON T2CON T3CON WTCON Full Register Name Page Number
A/D Converter Control Register... 4-5 Basic Timer Control Register... 4-6 System Clock Control Register.... 4-7 System Flags Register.... 4-8 Interrupt Mask Register.... 4-9 Interrupt Pending Register.... 4-10 Instruction Pointer (High Byte).... 4-11 Instruction Pointer (Low Byte)... 4-11 Interrupt Priority Register... 4-12 Interrupt Request Register.... 4-13 LCD Control Register.... 4-14 LCD Mode Control Register.... 4-15 Oscillator Control Register.... 4-16 Port 0 Control Register (High Byte)... 4-17 Port 0 Control Register (Low Byte)... 4-18 Port 0 Interrupt Control Register... 4-19 Port 0 Interrupt Pending Register... 4-20 Port 0 Interrupt Edge Selection Resgister... 4-21 Port 1 Control Register (High Byte)... 4-22 Port 1 Control Register (Low Byte)... 4-23 Port 1 Pull-up Control Register.... 4-24 Port 2 Control Register (High Byte)... 4-25 Port 2 Control Register (Low Byte)... 4-26 Port 2 Pull-up Control Register.... 4-27 Port 3 Control Register (High Byte)... 4-28 Port 3 Control Register (Low Byte)... 4-29 Port 3 Interrupt Control Register... 4-30 Port 3 Pull-up Control Register.... 4-31 Port Group 0 Control Register... 4-32 Port Group 1 Control Register... 4-33 Port Group 2 Control Register... 4-34 Port Group 3 Control Register... 4-35 Port Group 4 Control Register... 4-36 Register Page Pointer... 4-37 Register Pointer 0... 4-38 Register Pointer 1... 4-38 SIO Control Register... 4-39 Stack Pointer (High Byte)... 4-40 Stack Pointer (Low Byte).... 4-40 Stop Control Register.... 4-41 System Mode Register.... 4-42 Timer 0 Control Register.... 4-43 Timer 1/A Control Register.... 4-44 Timer B Control Register.... 4-45 Timer 2 Control Register.... 4-46 Timer 3 Control Register.... 4-47 Watch Timer Control Register... 4-48

S3C826A

(144-QFP-2828-AN)
SEG21/P11.2 SEG22/P11.1 SEG23/P11.0 SEG24/P10.7 SEG25/P10.6 SEG26/P10.5 SEG27/P10.4 SEG28/P10.3 SEG29/P10.2 SEG30/P10.1 SEG31/P10.0 SEG32/P9.7 SEG33/P9.6 SEG34/P9.5 SEG35/P9.4 SEG36/P9.3 SEG37/P9.2 SEG38/P9.1 VDD2 VSS2 SEG39/P9.0 SEG40/P8.7 SEG41/P8.6 SEG42/P8.5 SEG43/P8.4 SEG44/P8.3 SEG45/P8.2 SEG46/P8.1 SEG47/P8.0 SEG48/P7.7 SEG49/P7.6 SEG50/P7.5 SEG51/P7.4 SEG52/P7.3 SEG53/P7.2 SEG54/P7.1
Figure 1-2. S3C826A Pin Assignments (144-QFP-2828-AN)
P1.3/AD3 P1.4/SCK P1.5/SO P1.6/SI P1.7/BUZ VLC1 VLC2 VLC3 VLC4 VLC5 AVDD SEG79/P4.0 SEG78/P4.1 SEG77/P4.2 SEG76/P4.3 SEG75/P4.4 SEG74/P4.5 SEG73/P4.6 SEG72/P4.7 SEG71/P5.0 SEG70/P5.1 SEG69/P5.2 SEG68/P5.3 SEG67/P5.4 SEG66/P5.5 SEG65/P5.6 SEG64/P5.7 SEG63/P6.0 SEG62/P6.1 SEG61/P6.2 SEG60/P6.3 SEG59/P6.4 SEG58/P6.5 SEG57/P6.6 SEG56/P6.7 SEG55/P7.0
The package of S3C826A is only for engineer sample.

PIN DESCRIPTIONS

Table 1-1. S3C826A Pin Descriptions Pin Names P0.0-P0.7 Pin Type I/O Pin Description 1-bit-programmable I/O port. Schmitt trigger input or push-pull, opendrain output and software assignable pullups. 1-bit-programmable I/O port. Schmitt trigger input or push-pull, opendrain output and software assignable pull-ups. 1-bit-programmable I/O port. Schmitt trigger input or push-pull, opendrain output and software assignable pullups. Circuit Type E-4 Pin Numbers 26-33 Share Pins INT0-INT7
P1.0-1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0P4.7

F-16A E-4

34-37 38-41
AD0-AD3 SCK SO SI BUZ T0CLK

T0OUT/T0PWM/T0CAP

T1CLK TAOUT TBOUT T2CLK T2OUT T3CLK

T3OUT/T3PWM/T3CAP

1-bit-programmable I/O port. Schmitt trigger input or push-pull, opendrain output and software assignable pullups.
INT8 INT9 INT10 INT11 SEG79-72
4-bit-programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. Same as Port 4 Same as Port 4 Same as Port 4 Same as Port 4 Same as Port 4 Same as Port 4 Same as Port 4 8-bit-programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. Same as Port 12 Same as Port 12 Same as Port 12
P5.0P5.7 P6.0P6.7 P7.0P7.7 P8.0P8.7 P9.0P9.7 P10.0-P10.7 P11.0-P11.7 P12.0-P12.7
I/O I/O I/O I/O I/O I/O I/O I/O

FFH Set 1 FFH FFH 32 Bytes Bank 1 FFH FFH FFH Page 1 Page 0

Page 7

Bank 0 System and Peripheral Control System and Registers Peripheral Control Registers (Register Addressing Mode)
Set 2 Registers (Indirect Register, Indexed Mode, and Stack Operations) 256 Bytes C0H BFH Page 0

64 Bytes

E0H DFH D0H CFH System Registers (Register Addressing Mode) Working Registers (Working Register Addressing Only)
~ Page Bytes Prime Data Registers (All Addressing Modes) ~ ~

176 Bytes 00H

Prime Data Registers (All Addressing Modes) LCD Display Register
Figure 2-2. Internal Register File Organization
REGISTER PAGE POINTER (PP) The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH). In the S3C826A microcontroller, a paged register file expansion is implemented for LCD data registers, and the register page pointer must be changed to address other pages. After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always "0000", automatically selecting page 0 as the source and destination page for register addressing.
Register Page Pointer (PP) DFH ,Set 1, R/W MSB.7.6.5.4.3.2.1.0 LSB
Destination register page selection bits: 0000 Destination: Page 0
Source register page selection bits: 0000 Source: Page 0
A hardware reset operation writes the 4-bit destination and source values shown above to the register page pointer. These values should be modified to address other pages.
Figure 2-3. Register Page Pointer (PP)
F PROGRAMMING TIP Using the Page Pointer for RAM clear (Page 0, Page 1)
LD SRP LD CLR DJNZ CLR LD LD CLR DJNZ CLR PP,#00H #0C0H R0,#0FFH @R0 R0,RAMCL0 @R0 PP,#10H R0,#0FFH @R0 R0,RAMCL1 @R0 ; Destination 0, Source 0 ; Page 0 RAM clear starts

RAMCL0

; R0 = 00H ; Destination 1, Source 0 ; Page 1 RAM clear starts

RAMCL1

; R0 = 00H
NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.
REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0HFFH. The upper 32-byte area of this 64-byte space (E0HFFH) is expanded two 32-byte register banks, bank 0 and bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware reset operation always selects bank 0 addressing. The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0HFFH) contains 61 mapped system and peripheral control registers. The lower 32-byte area contains 16 system registers (D0HDFH) and a 16-byte common working register area (C0HCFH). You can use the common working register area as a scratch area for data operations being performed in other areas of the register file. Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte working register area can only be accessed using working register addressing (For more information about working register addressing, please refer to Chapter 3, "Addressing Modes.") REGISTER SET 2 The same 64-byte physical space that is used for set 1 locations C0HFFH is logically duplicated to add another 64 bytes of register space. This expanded area of the register file is called set 2. For the S3C826A, the set 2 address range (C0HFFH) is accessible on pages 0-7. The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register Indirect addressing mode or Indexed addressing mode. The set 2 register area of page 0 is commonly used for stack operations.

Interrupt Mask Register (IMR) DDH, Set 1, R/W MSB.7.6.5.4.3.2.1.0 LSB

IRQ2 IRQ6 IRQ5 IRQ4 IRQ3

Interrupt level enable bits 0 = Disable (mask) interrupt level 1 = Enable (un-mask) interrupt level
Before IMR register is changed to any value, all interrupts must be disable. Using DI instruction is recommended.
Figure 5-6. Interrupt Mask Register (IMR)
INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontrollers interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine. When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two sources belong to the same interrupt level, the source with the lower vector address usually has the priority (This priority is fixed in hardware). To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register priority definitions (see Figure 5-7): Group A Group B Group C IRQ0, IRQ1 IRQ2, IRQ3, IRQ3 IRQ5, IRQ6, IRQ7

IPR Group A

IPR Group B

IPR Group C

B1 B21

B2 B22 IRQ4

C1 C21 IRQ5 IRQ6

C2 C22 IRQ7

IRQ2 IRQ3
Figure 5-7. Interrupt Request Priority Groups As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C. For example, the setting "001B" for these bits would select the group relationship B > C > A. The setting "101B" would select the relationship C > B > A. The functions of the other IPR bit settings are as follows: IPR.5 controls the relative priorities of group C interrupts. Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5, 6, and 7. IPR.6 defines the subgroup C relationship. IPR.5 controls the interrupt group C. IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.

The diagram below shows one example of how to use an ENTER statement.
Before Address IP 0050 Address PC 43 Enter Address H Address L Address H Data 1F PC 0110 Data Address IP 0043

After Data

Address Enter Address H Address L Address H

Data 1F 01 10

Data Stack

Memory

IPH IPL Data Stack

Routine Memory

EXIT Exit
EXIT Operation: IP SP PC IP @SP SP + 2 @IP IP + 2
This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. Flags: Format: Bytes opc 1 Cycles 14 (internal stack) 16 (internal stack) Opcode (Hex) 2F No flags are affected.
The diagram below shows one example of how to use an EXIT statement.
Before Address IP 0050 Address PC 51 SP 22 IPH IPL Data Stack Exit 2F PCL old PCH SP 0022 Data PC 0060 Data Address IP 0052

Address 60 Main

IDLE Idle Operation
IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. In application programs, a IDLE instruction must be immediately followed by at least three NOP instructions. This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructons are not used after IDLE instruction, leakage current could be flown because of the floating state in the internal bus. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 6F Addr Mode dst src No flags are affected.
The instruction IDLE NOP NOP NOP ; stops the CPU clock but not the system clock

INC Increment

INC Operation: dst dst dst + 1 The contents of the destination operand are incremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected.

LDC/LDE Examples: (Continued) Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: LDC LDE R0,@RR2 R0,@RR2 ; R0 contents of program memory location 0104H ; R0 = 1AH, R2 = 01H, R3 = 04H ; R0 contents of external data memory location 0104H ; R0 = 2AH, R2 = 01H, R3 = 04H ; 11H (contents of R0) is loaded into program memory ; location 0104H (RR2), ; working registers R0, R2, R3 no change ; 11H (contents of R0) is loaded into external data memory ; location 0104H (RR2), ; working registers R0, R2, R3 no change ; R0 contents of program memory location 0105H ; (01H + RR2), ; R0 = 6DH, R2 = 01H, R3 = 04H ; R0 contents of external data memory location 0105H ; (01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H ; 11H (contents of R0) is loaded into program memory location ; 0105H (01H + 0104H) ; 11H (contents of R0) is loaded into external data memory ; location 0105H (01H + 0104H)

LDC (note) @RR2,R0

@RR2,R0

R0,#01H[RR2]

LDC (note) #01H[RR2],R0 LDE LDC LDE LDC LDE #01H[RR2],R0
R0,#1000H[RR2] ; R0 contents of program memory location 1104H ; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H R0,#1000H[RR2] ; R0 contents of external data memory location 1104H ; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H R0,1104H R0,1104H ; R0 contents of program memory location 1104H, R0 = 88H ; R0 contents of external data memory location 1104H, ; R0 = 98H ; 11H (contents of R0) is loaded into program memory location ; 1105H, (1105H) 11H ; 11H (contents of R0) is loaded into external data memory ; location 1105H, (1105H) 11H
LDC (note) 1105H,R0 LDE 1105H,R0
NOTE: These instructions are not supported by masked ROM type devices.
LDCD/LDED Load Memory and Decrement
LDCD/LDED Operation: dst,src dst src rr rr 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected. LDCD references program memory and LDED references external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory. Flags: Format: Bytes opc dst | src 2 Cycles 10 Opcode (Hex) E2 Addr Mode dst src r Irr No flags are affected.

OR Logical OR

OR Operation: dst,src dst dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected.
Format: Bytes opc dst | src 2 Cycles opc src dst 6 opc dst src Opcode (Hex) 46 Addr Mode dst src r r R R R r lr R IR IM
Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH: OR OR OR OR OR R0,R1 R0,@R2 00H,01H 01H,@00H 00H,#02H R0 = 3FH, R1 = 2AH R0 = 37H, R2 = 01H, register 01H = 37H Register 00H = 3FH, register 01H = 37H Register 00H = 08H, register 01H = 0BFH Register 00H = 0AH
In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in destination register R0. The other examples show the use of the logical OR instruction with the various addressing modes and formats.

POP Pop From Stack

POP Operation: dst dst @SP SP SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: Format: Bytes opc dst 2 Cycles Opcode (Hex) Addr Mode dst R IR No flags affected.
Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH, and stack register 0FBH = 55H: POP POP 00H @00H Register 00H = 55H, SP = 00FCH Register 00H = 01H, register 01H = 55H, SP = 00FCH
In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads the contents of location 00FBH (55H) into destination register 00H and then increments the stack pointer by one. Register 00H then contains the value 55H and the SP points to location 00FCH.
POPUD Pop User Stack (Decrementing)
POPUD Operation: dst,src dst src IR IR 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented. Flags: Format: Bytes opc src dst 3 Cycles 8 Opcode (Hex) 92 Addr Mode dst src R IR No flags are affected.

RR Rotate Right

RR Operation: dst C dst (0) dst (7) dst (0) dst (n) dst (n + 1), n = 06 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected.
Format: Bytes opc dst 2 Cycles Opcode (Hex) E0 E1 Addr Mode dst R IR
Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H: RR RR 00H @01H Register 00H = 98H, C = "1" Register 01H = 02H, register 02H = 8BH, C = "1"
In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and overflow flag are also set to "1".
RRC Rotate Right Through Carry
RRC Operation: dst dst (7) C C dst (0) dst (n) dst (n + 1), n = 06 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB).
Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0" cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected.
Format: Bytes opc dst 2 Cycles Opcode (Hex) C0 C1 Addr Mode dst R IR
Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0": RRC RRC 00H @01H Register 00H = 2AH, C = "1" Register 01H = 02H, register 02H = 0BH, C = "1"

Format: Bytes opc dst | src 2 Cycles opc src dst 6 opc dst src Opcode (Hex) B2 B3 B4 B5 B6 Addr Mode dst src r r R R R r lr R IR IM
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: XOR XOR XOR XOR XOR R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H R0 = 0C5H, R1 = 02H R0 = 0E4H, R1 = 02H, register 02H = 23H Register 00H = 29H, register 01H = 02H Register 00H = 08H, register 01H = 02H, register 02H = 23H Register 00H = 7FH
In the first example, if working register R0 contains the value 0C7H and if register R1 contains the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and stores the result (0C5H) in the destination register R0.

CLOCK CIRCUIT

The S3C826A microcontroller has two oscillator circuits: a main clock and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU clock frequency of S3C826A is determined by CLKCON register settings. SYSTEM CLOCK CIRCUIT The system clock circuit has the following components: External crystal, ceramic resonator, RC oscillation source, or an external clock source Oscillator stop and wake-up functions Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16) System clock control register, CLKCON STOP control register, STPCON CPU Clock Notation In this document, the following notation is used for descriptions of the CPU clock; fx: main clock fxt: sub clock fxx: selected system clock

MAIN OSCILLATOR CIRCUITS

SUB OSCILLATOR CIRCUITS

XOUT 32.768 kHz

Figure 7-1. Crystal/Ceramic Oscillator (fx)
Figure 7-4. Crystal/Ceramic Oscillator (fxt)
Figure 7-2. External Oscillator (fx)
Figure 7-5. External Oscillator (fxt)

XIN R XOUT

Figure 7-3. RC Oscillator (fx)
CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset operation or an external interrupt (with RC delay noise filter). In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers, timer/ counters, and watch timer. Idle mode is released by a reset or by an external or internal interrupt.

Stop Release INT

Main-System Oscillator Circuit
Sub-system Oscillator Circuit
Watch Timer LCD Controller

Selector 1 fXX Stop

OSCCON.3 OSCCON.0 STOP OSC inst. STPCON 1/8-1/4096 Basic Timer Timer/Counters Frequency Dividing Circuit Watch Timer LCD Controller SIO A/D Converter 1/1 1/2 1/8 1/16 System Clock CLKCON.4-.3 Selector 2 CPU Clock Stop OSCCON.2

Timer 0 Control Register (T0CON) E5H, Set 1, Bank 0, R/W MSB.7.6.5.4.3.2.1.0 LSB
Timer 0 input clock selection bits: 000 = fxx/= fxx/= fxx/= fxx/= fxx 101 = External clock (P2.0/T0CLK) falling edge 110 = External clock (P2.0/T0CLK) rising edge 111 = Counter stop
Timer 0 overflow interrupt enable bit: 0 = Disable overflow interrupt 1 = Enable overflow interrupt Timer 0 match/capture interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Timer 0 counter clear bit: 0 = No effect 1 = Clear the timer 0 counter (when write)
Timer 0 operating mode selection bits: 00 = Interval mode (P2.1/T0OUT) 01 = Capture mode (capture on rising edge, counter running, OVF can occur) 10 = Capture mode (capture on falling edge, counter running, OVF can occur) 11 = PWM mode (OVF and match interrupt can occur)
Figure 10-3. Timer 0 Control Register (T0CON)
Interrupt Pending Register (INTPND) D0H, Set 1, R/W MSB.7.6.5.4.3.2.1.0 LSB

Not used

Timer 0 overflow interrupt pending bit Timer 0 match/capture interrupt pending bit Timer 3 overflow interrupt pending bit Timer 3 match/capture interrupt pending bit
0 = Interrupt request is not pending, pending bit clear when write "0". 1 = Interrupt request is pending
Figure 10-4. Interrupt Pending Register (INTPND)
TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts (IRQ0, Vectors E0H and E2H) The timer 0 can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/ capture interrupt (T0INT). T0OVF is belongs to interrupt level IRQ0, vector E2H. T0INT also belongs to interrupt level IRQ0, but is assigned the separate vector address, E0H. A timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or should be cleared by software in the interrupt service routine by writing a 0 to the INTPND.0 interrupt pending bit. However, the timer 0 match/capture interrupt pending condition must be cleared by the applications interrupt service routine by writing a "0" to the INTPND.1 interrupt pending bit. Interval Timer Mode In interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector E0H) and clears the counter. If, for example, you write the value "10H" to T0DATA, the counter will increment until it reaches 10H. At this point, the timer 0 interrupt request is generated, the counter value is reset, and counting resumes. With each match, the level of the signal at the timer 0 output pin is inverted (see Figure 10-5).
Capture Signal CLK 8-Bit Up Counter R (Clear)
Interrupt Enable/Disable T0CON.1

8-Bit Comparator

Interrupt Enable/Disable T3CON.1
T3INT (IRQ2) INTPND.3 Pending T3OUT (P3.3) (Match INT)
Timer 3 Buffer Register Match Signal T3CON.2 T3OVF Timer 3 Data Register

T3CON.4-.3

Figure 13-3. Simplified Timer 3 Function Diagram: Interval Timer Mode
Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T3PWM (P3.3) pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 3 data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs continuously, overflowing at "FFH", and then continues incrementing from "00H". Although you can use the match signal to generate a timer 3 overflow interrupt, interrupts are not typically used in PWM-type applications. Instead, the pulse at the T3PWM (P3.3) pin is held to Low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to tCLK 256 (see Figure 13-4).
T3CON.0 T3OVF(IRQ2) CLK 8-Bit Up Counter INTPND.2 (Overflow INT)
T3INT (IRQ2) INTPND.3 Pending (Match INT) T3PWM Output (P3.3) High level when data > counter, Lower level when data < counter
Figure 13-4. Simplified Timer 3 Function Diagram: PWM Mode
Capture Mode In capture mode, a signal edge that is detected at the T3CAP (P3.3) pin opens a gate and loads the current counter value into the timer 3 data register. You can select rising or falling edges to trigger this operation. Timer 3 also gives you capture input source: the signal edge at the T3CAP (P3.3) pin. You select the capture input by setting the values of the timer 3 capture input selection bits in the port 3 control register, P3CONL.7.6, (set 1, bank 1, EDH). When P3CONL.7.6 is "00", the T3CAP input is selected. Both kinds of timer 3 interrupts can be used in capture mode: the timer 3 overflow interrupt is generated whenever a counter overflow occurs; the timer 3 match/capture interrupt is generated whenever the counter value is loaded into the timer 3 data register. By reading the captured data value in T3DATA, and assuming a specific value for the timer 3 clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T3CAP pin (see Figure 13-5).