4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29
List of Figures(Continued)
Figure Number 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 4-42 4-43 4-44 4-45 4-46 4-47 4-48 4-49 4-50 7-1 7-2 7-3 Title Page Number
LP104V2-W Connection with S3C2440A (LG Philips 10.4 TFT LCD)..4-33 V16C6448AB Connection with S3C2440A (TFT LCD)...4-34 ADC and Touch Screen Interface Functional Block Diagram.4-35 ADC and Touch Screen Operation signal...4-37 RTC Connection....4-38 Example.....4-39 Unused RTC Connection Example...4-39 SD CARD CIRCUIT DIAGRAM....4-42 Circuit Diagram when not using SD card..4-42 IIC Connection Circuit Example...4-44 IIS Interface Signal....4-45 AC97 Interface Signal....4-46 IIS or AC97 Interface Example...4-47 Keyboard with SPI Interface....4-48 Camera Interface with Voltage Translation Example..4-50 Camera Module: S5X3A1 V4220...4-50 Camera Module: S5X532 STD-18...4-51 MULTI-ICE Interface of JTAG Connector..4-52 MULTI-ICE Interface Design Example...4-53 CF+ type HDD connection with S3C2440A...4-54 PIO mode timing....4-55 S3C2440A Pin Assignments (289-FBGA)...7-1 289-FBGA-1414 Package Dimensions 1 (Top View)..7-22 289-FBGA-1414 Package Dimensions 2 (Bottom View)..7-23

List of Tables

Table Number 2-1 2-2 3-1 3-2 3-3 3-4 3-5 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 7-1 7-2 7-3 Title Page Number
Bank 6/7 Addresses....2-4 SDRAM Bank Address Configuration Example..2-5 Recommended Operating Conditions..3-1 Normal I/O PAD DC Electrical Characteristics...3-2 USB DC Electrical Characteristics....3-4 S3C2440 Power Supply Voltage and Current..3-4 Power on Reset Timing Specifications...3-7 DVS voltage level...4-2 Core current Consumption....4-5 Data Bus Width for ROM Bank 0...4-6 Relationship ROM Image and Endian..4-7 SDRAM Bank Address Configuration...4-15 Booting device selection...4-19 Booting device H/W Information...4-19 NAND Flash Signal Description...4-21 SDI Signal Description...4-40 SD CARD SOCKET SIGNALS...4-41 SDI CONTROLLER SUPPORTED SOCKETS AND DEVICES..4-41 SD CARD PULL-UP AND PULL-DOWN RESISTORS...4-43 Camera Interface Signal Description...4-49 The timing specification of HITACHI microdrive..4-55 Comparison S3C2440A and HITACHI microdirve...4-55 289-Pin FBGA Pin Assignments Pin Number Order (Sheet 1 of 3).7-2 S3C2440A 289-Pin FBGA Pin Assignments..7-5 S3C2440A Signal Pin Descriptions (Sheet 1 of 6)...7-16

Impedance Mismatching Inductance

Latency LVDS

Measuring Signal Delay Micro Blind Via Microstrip Line Monotonicity Network
Network Length Oscillation
Terminology Overshoot Definition Temporary phenomenon in which output waveform goes above the maximum base line if pulse waveform goes up in the electronic circuit (that is, signal exceeds the maximum voltage (Vdd) of the device pad). Excessive Under/Over Shoot has proportionally severe ring-back noise and the receiver component might be damaged. Part created for wiring from the outside on Chip or PCB. point of component package where it is possible to measure Signal Quality/ timing, and connect trace on the board. Refers to a phenomenon that signal and information generated from one place move to another place. For example, signal generated from Tx party through communication line is delivered to the Rx party. In addition, signal from one logic element in logic circuit is transmitted to the input of other logic elements. Generated by the impedance mismatching of wiring and circuit element. Noise rebound in reverse direction after Under/Overshoot. It might cause a functional failure due to logic violation. Based on High/Low Threshold Voltage, it is required to analyze how much margin exists. Waveform of output circuit is temporarily unstable because of a sudden change of input signal in electric/electronic circuits. It refers to noise rebound in reverse direction after Under/Overshoot and might cause a functional failure due to logic violation. Based on High/Low threshold voltage, it is required to analyze how much margin exits. For signal received from input end, reference electrical potential is set up in advance. If input exceeds reference electrical potential, the circuit outputs value 1, and if input signal is less than reference electrical potential, it outputs value 0. Level (Setting Limit) that does not cause the increase of next transition flight time, and it means time until oscillation is weakened. Time difference generated between multiple signals. Multiple signals may have quite a big time difference at destination point due to the difference of load condition in the path. For sequential circuit, if you want to increase dynamic frequency, it is absolutely important to reduce clock skew. Simultaneous Switching Output (SSO) Noise means that if all bits are changed to Vdd or Vss in the output circuit at the same time, there will be a big change of current in power circuit in a moment, and at this time, Ground Bounce is generated by inductance element on the ground side.

Pad Pin Propagation

Reflection Noise Ring-back

Ringing

Schmitt-trigger

Settling Time Skew

Terminology Stack-Up Strip line TBD Topology Layer layout between layers on PCB. Signal line is inserted between upper and lower power planes in order to implement transmission line. To Be Defined Overall architecture of each device connected through any communication medium. For example, the architecture of peripherals connected through bus or that of computer connected through data communication network. Temporary phenomenon in which output waveform goes below the minimum base line if pulse waveform drops in the electronic circuit (that is, signal does not exceed the minimum voltage (Vss) of the device pad). Excessive Under/Over Shoot proportionally has severe ring-back noise and the receiver component might be damaged. Definition

S3C2440A ADDR[13:1] ADDR[13:1] BA DATA[31:0] DATA[15:0] SCLK nRAS[0]/nSCS[0] nCAS3/nSRAS nCAS2/nSCAS nWE nWBE[1:0]/DQM[1:0] DQM[1:0]
Figure 4-13. Halfword SDRAM Design with Halfword Component
SYNC DRAM A[12:0] BA DQ[15:0] CLK nCS nSRAS nSCAS nWE LDQM/UDQM
S3C2440A ADDR[14:2] ADDR[14:2] BA DATA[31:0] DATA[15:0] SCLK nRAS[0]/nSCS[0] nCAS3/nSRAS nCAS2/nSCAS nWE nWBE[3:0]/DQM[3:0] DQM[1:0] CLK nCS
SYNC DRAM A[12:0] BA DQ[15:0]
nSRAS nSCAS nWE LDQM/UDQM SYNC DRAM ADDR[14:2] A[12:0] BA DQ[15:0] DATA[31:16] CLK nCS nSRAS nSCAS nWE LDQM/UDQM DQM[3:2]
Figure 4-14. Word SDRAM Design with Half-word Component

3. NAND

Boot Rom Selection Guide
After the system reset, the S3C2440A accesses 0x00000000 address and configuring some system variables. Therefore, this special code (boot ROM image) should be located on the address 0x00000000. Booting device can be selected by setting OM [1:0] pins (Refer to Table 4-6). Table 4-6. Booting device selection OMOMBoot Memory NAND boot NOR boot (AMD) Intel Strata boot
And also, H/W Information must be selected for Booting using flash memory. Table 4-7. Booting device H/W Information Pins NCON Description NAND flash memory selection (Normal / Advance) 0: Normal NAND flash (256Words/512Bytes page size, 3/4 address cycle) 1: Advance NAND flash (1KWords/2KBytes page size, 4/5 address cycle) NAND flash memory page capacitance selection 0: Page=256Words(NCON = 0) or Page=1KWords(NCON = 1) 1: Page=512Bytes(NCON = 0) or Page=2KBytes(NCON = 1) NAND flash memory address cycle selection 0: 3 address cycle (NCON = 0) or 4 address cycle (NCON = 1) 1: 4 address cycle (NCON = 0) or 5 address cycle (NCON = 1) NAND flash memory bus width selection 0: 8-bit bus width 1: 16-bit bus width
NAND FLASH MEMORY CONFIGURATION
RnB nFRE nFCE CLE ALE nFWE

R/ B RE CE CLE ALE WE

I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0]
Figure 4-15. An 8-bit NAND Flash Memory Interface
When you write the address, the same address is issued from data [7:0] and data [15:8]
Rn B nFRE nFCE CLE ALE nFWE
DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8]
Figure 4-16. Two 8-bit NAND Flash Memory Interface
I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

VFRAME VLINE VCLK VD0 VD1 VD2 VD3 (From S3C2440A) R 10K VEE VDD VEE
FG NC x FLM CL1 CL2 VSS D0 D1 D2 D3 VSS VDD V0 VEE VSS

UG-32-F04-WCBN0-A

Figure 4-26. UG-32F04 Connection with S3C2440A (320x240 Mono STN LCD)
VFRAME VLINE VCLK PORT(DISPON) VM 3.3V

VD0 VD1 VD2 VD3 3.3V

PORT(nEL-ON)
VSS1 FPFRAME FPLINE VSS2 FPSHIFT VSS3 DOFF DRDY VCC VSS4 VEE VL D0 D1 D2 D3 VSS5 X2 Y1 X1 Y2 VSS6 EL-VCC EL-ON

x x x x

(From S3C2440A)

UG24U03A

Figure 4-27. UG24U03A Connection with S3C2440A (320x240 Mono STN LCD)
VFRAME VLINE VCLK VM VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0

DISPOFF VDD

VM V0 V1 V2 V3 V4 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0
FLM LOAD CP DISP VDD VDD VSS DF V0 V1 V2 V3 V4 V5 D7 D6 D5 D4 D3 D2 D1 D0

KHS038AA1AA-G24-95-14

Figure 4-28. KHS038AA1AA-G24 Connection with S3C2440A (256 Color STN LCD)

LAVDD LDVDD

LVFRAME LVLINE LLEND LD18 LD19 LD20 LD21 LD22 LD23 LD10 LD11 LD12 LD13 LD14 LD15 LVCLK
INV VREF0 VREF1 VREF2 VREF3 VREF4 VREF5 VREF6
LVM LD2 LD3 LD4 LD5 LD6 LD7

FH12_50P

Figure 4-29. LTS350Q1-PE1 Connection with S3C2440A (Samsung 3.5 Transflective TFT LCD)
VCLK VLINE VFRAME VD18 VD19 VD20 VD21 VD22 VD23 VD10 VD11 VD12 VD13 VD14 VD15 VD2 VD3 VD4 VD5 VD6 VD7 VM PVDD_LCDI PVDD_LCDI
GND CLK Hsync Vsync GND R0 R1 R2 R3 R4 R5 GND G0 G1 G2 G3 G4 G5 GND B0 B1 B2 B3 B4 B5 GND DTMG VDD VDD NC NC

DF9B-31S-1V

Figure 4-30. LP104V2-W Connection with S3C2440A (LG Philips 10.4 TFT LCD)

VCLK HSYNC VSYNC

VD11 VD12 VD13 VD14 VD15 VD5 VD6 VD7 VD8 VD9 VD10
VD0 VD1 VD2 VD3 VD4 VDEN VDD_LCDI(5V)
GND CLK Hsync Vsync GND R0 R1 R2 R3 R4 R5 GND G0 G1 G2 G3 G4 G5 GND B0 B1 B2 B3 B4 B5 GND DENB VCC VCC R/L U/D

V16C6448AB

Figure 4-31. V16C6448AB Connection with S3C2440A (TFT LCD)

Not Used

- All Pin leave as a No Connect. - VD [23:0], LCD_PWREN, VCLK, VFRAME, VLINE, VM, VSYNC, HSYNC, VDEN, LEND, STV, CPV, LCD_HCLK, TP, STH, LCD_LPCOE, LCD_LPCREV, LCD_LPCREVB

C1 X T Ir tc CP C2 32768Hz X T O r tc

Figure 4-35. Example

If you choose a crystal with small CL, you can make C1 and C2 small and most characteristics will be improved.

Unused RTC Unit

The schematics for an unused RTC connection are shown in Figure 4-36.

VDDRTC

VDDRTC X T Ir tc

X T O r tc VSSOP

Figure 4-36. Unused RTC Connection Example
XTOrtc pin leaves as a No Connect.
9. SDI (Secure Digital Interface)
The SD Card is a low cost data storage and communication media. The SD Card supports the translation protocol from a standard SDI or Serial Peripheral Interface (SPI) bus to an application bus. The SDI controller in the applications processor is compliant with The SD Memory Card Spec, Version1.0 System Specification and The MultiMedia Card System Specification, Version 2.11 and SDIO Card Spec, Version1.0. The SDI controller is capable of communicating with a card in SD or SPI mode. Your application is responsible for specifying the SDI controller communication mode.

Signal Description

SDI controller signal functions are described in Table 4-9. The signals defined in the Physical Layer Specification of the SD Memory Card Specifications for an SD Card device are CLK, CMD, and DAT0-DAT3. The obvious difference is the number of DAT signals. In addition, the socket for an SD Card contains mechanical switches for write protect (WP) and card detect (CD). Table 4-9. SDI Signal Description Signal Name SDCLK SDCMD SDDATA0 ~ SDDATA3 Input/Output Output Bidirectional Bidirectional Description Clock signal to SD Card Command line Data line

How to Wire

Notice in the example schematic (Figure 4-10, Applications Processor SD Card Signal Connections) an SD Card socket is used. The signals on the socket are defined in Table 4-10. Table 4-10. SD Card Socket Signals Signal Name CD/DAT3 CMD VSS1 VDD CLK VSS2 DAT0 DAT1 DAT2 Pin # 9
The SDI controller can be connected to either an MMC device or an SD Card device, but you are limited to which device installs in which socket. Refer to Table 4-11 for information on sockets and device supported by the SDI controller. Table 4-11. SDI Controller Supported Sockets and Devices Sockets SD Card socket Devices supported SD Card device MMC device MMC device

MMC socket

Simplified Schematic
Figure 4-37 shows another SD Card socket. In this case, all applications processor signals are connected to the socket. This socket does not have a common signal for the write protect and card detect. Inserting a card into the socket may cause the write protect signal and will cause the card detect signal to change states and must be interpreted by the CPLD software.

GPE2/X2sCDCLK/X97RESETn Earphone Jack GPE1/X2sCLK/X97BITCLK
GPE0/X2sLRCK/X97SYNC IIS Codec GPE3/X2sDI/X97SDI

Mic Jack

GPE4/X2sDO/X97SD0

Line-in Jack

Figure 4-40. IIS Interface Signal
When Using As AC97 interface In this case, just connect the corresponding pins like a diagram below. The A97 codec of this diagram is an arbitrary codec that supports A97 audio interface, and you can select any codec that is appropriate for your application.
GPE0/X2sLRCK/X97SYNC AC97 Codec GPE3/X2sDI/X97SDI
Figure 4-41. AC97 Interface Signal
When Using For IIS or AC97 Selectively In this case, you should connect the pins with a selective codec by means of resisotrs, and should get rid of resistors that connecting the pins with unselective codec. In this diagram, for example, if you want to use the pins for IIS codec interface, you should remove resistors, R6 ~R10, You can also use a simple Mux/Demux chip instead of resistors.
R2 R3 IIS Codec R4 Earphone Jack GPE2/X2sCDCLK/X97RESETn R5 GPE1/X2sCLK/X97BITCLK Mic Jack GPE0/X2sLRCK/X97SYNC R6 GPE3/X2sDI/X97SDI R7 Line-in Jack

R8 AC97 Codec R9

Figure 4-42. IIS or AC97 Interface Example

12. SPI Description

The S3C2440A Serial Peripheral Interface (SPI) can interface with the serial data transfer. The S3C2440A includes two SPI, each of which has two 8-bit shift registers for transmission and receiving, respectively. During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). 8-bit serial data at a frequency is determined by its corresponding control register settings. If you only want to transmit, receive data can be kept dummy. Otherwise, if you only want to receive, you should transmit dummy '1' data. There are 4 I/O pin signals associated with SPI transfers: SCK (SPICLK0, 1), MISO (SPIMISO0, 1) data line, MOSI (SPIMOSI0,1) data line and active low /SS (nSS0,1) pin (input).

SPI Keyboard Interface

The schematics for a SPI-compatible keyboard encoder connection are shown in Figure 4-43.

VDD3.3V Master

Slave L5 L10 R11 K10 M16
GPG6 SPICLK1 SPIMOSI1 SPIMISO1 EINT1 S3C2440A
_SS SCK MOSI MISO _ATN UR5HCSPI-SA01
Figure 4-43. Keyboard with SPI Interface
These five signals implement the SPI interface. SPI keyboard encoder device acts as a slave on the SPI bus and S3C2440A as a Master. The _SS (Slave Select) pin must go high between successive characters in an SPI message or a write collision error results. The _ATN pin is asserted low each time the UR5HCSPI-SA01 has a packet ready for delivery. When using SPI Master connected from GPIO pin of S3C2440A to SPI Chip Select pin, and when Slave connected to nSS pin. The S3C2440A L5 pin connection 0 ohm resister is series protection resister. So, The resister value is used the right value resister in accordance with application.

13. CAMERA INTERFACE

DESCRIPTION
CAMIF (CAMera InterFace) within the S3C2440A consists of 7 parts pattern mux, capturing unit, preview scaler, codec scaler, preview DMA, codec DMA, and SFR. The CAMIF supports ITU-R BT.601/656 YCbCr 8-bit standard. Maximum input size is 4096x4096 pixels (2048x2048 pixels for scaling) and two scalers exist. Preview scaler is dedicated to generate smaller size image like PIP (Picture In Picture) and codec scaler is dedicated to generate codec useful image like plane type YCbCr 4:2:0 or 4:2:2. Two-master DMAs can do mirror and rotate the captured image for mobile environments. These features are very useful in folder type cellular phones and the test pattern generated can be useful in calibration of input sync signals as CAMHREF, CAMVSYNC. Also, video sync signals and pixel clock polarity can be inverted in the CAMIF side by using register setting.

SIGNAL DESCRIPTION

Table 4-13. Camera Interface Signal Description Name CAMPCLK CAMVSYNC CAMHREF CAMDATA [7:0] CAMCLKOUT CAMRESET I/O I I I I O O Active H/L H/L H/L Description Pixel clock, driven by the camera processor Frame sync, driven by the camera processor Horizontal sync, driven by the camera processor Pixel data driven by the camera processor Master clock to the camera processor Software reset or power down to the camera processor
NOTE: I/O direction is on the AP side. I: input, O: output

SCHEMATICS

The S3C2440 Camera Interface signal level is 3.3V. So if you use other signal level camera, you must translate the signal level using the Voltage Translator. (Refer to Figure 4-44)
Figure 4-44. Camera Interface with Voltage Translation Example The examples of S3C2440 Camera Interface are following.
Figure 4-45. Camera Module: S5X3A1 V4220
Figure 4-46. Camera Module: S5X532 STD-18
If not use Camera Interface, leave all pin as no connect.
14. JTAG / DEBUG PORT Description
The S3C2440A has an Embedded ICE logic that provides debug solution from ARM. Embedded ICE logic is accessed through the Test Access Port (TAP) controller on the S3C2440A using the JTAG interface. JTAG is testable via the IEEE 1149.1. Many use JTAG to control the address/data bus for Flash programming. JTAG is also a hardware debug port.

Interrupt Control Unit

Table 7-3. S3C2440A Signal Pin Descriptions (Sheet 3 of 6) Signal UART RxD[2:0] TxD[2:0] nCTS[1:0] nRTS[1:0] UARTCLK ADC AIN [7:0] Vref IIC-Bus IICSDA IICSCL IIS-Bus I2SLRCK I2SSDO I2SSDI I2SSCLK CDCLK Touch Screen nXPON XMON nYPON YMON USB Host DN [1:0] DP [1:0] USB Device PDN0 PDP0 SPI SPIMISO [1:0] SPIMOSI [1:0] SPICLK [1:0] nSS [1:0] IO IO IO I SPIMISO is the master data input line, when SPI is configured as a master. When SPI is configured as a slave, these pins reverse its role. SPIMOSI is the master data output line, when SPI is configured as a master. When SPI is configured as a slave, these pins reverse its role. SPI clock SPI chip select (only for slave mode) IO IO DATA () for USB peripheral DATA (+) for USB peripheral IO IO DATA () from USB host DATA (+) from USB host O O O O Plus X-axis on-off control signal Minus X-axis on-off control signal Plus Y-axis on-off control signal Minus Y-axis on-off control signal IO O I IO O IIS-bus channel select clock IIS-bus serial data output IIS-bus serial data input IIS-bus serial clock CODEC system clock IO IO IIC-bus data IIC-bus clock AI AI ADC input [7:0]. If it is not used pin, it has to be low (Ground). ADC Vref I O I O I UART receives data input UART transmits data output UART clear to send input signal UART request to send output signal UART clock signal I/O Descriptions
Table 7-3. S3C2440A Signal Pin Descriptions (Sheet 4 of 6) Signal SD SDDAT [3:0] SDCMD SDCLK General Port GPn [116:0] TIMMER/PWM TOUT [3:0] TCLK [1:0] JTAG TEST LOGIC nTRST I nTRST(TAP Controller Reset) resets the TAP controller at start. If debugger is used, A 10K pull-up resistor has to be connected. If debugger (black ICE) is not used, nTRST pin must be issued by a low active pulse (Typically connected to nRESET). TMS (TAP Controller Mode Select) controls the sequence of the TAP controller's states. A 10K pull-up resistor has to be connected to TMS pin. TCK (TAP Controller Clock) provides the clock input for the JTAG logic. A 10K pull-up resistor must be connected to TCK pin. TDI (TAP Controller Data Input) is the serial input for test instructions and data. A 10K pull-up resistor must be connected to TDI pin. TDO (TAP Controller Data Output) is the serial output for test instructions and data. O I Timer output [3:0] External timer clock input IO General input/output ports (some ports are output only) IO IO O SD receive/transmit data SD receive response/ transmit command SD clock I/O Description

TMS TCK TDI TDO

I I I O
Table 7-3. S3C2440A Signal Pin Descriptions (Sheet 5 of 6) Signal XTOpll I/O AO Description Crystal output for internal OSC circuit. When OM [3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source. When OM [3:2] = 01b, XTIpll is used for MPLL CLK source only. When OM [3:2] = 10b, XTIpll is used for UPLL CLK source only. If it is not used, it has to be a floating pin. Loop filter capacitor for main clock. Loop filter capacitor for USB clock. 32 kHz crystal input for RTC. If it is not used, it has to be High (3.3V). 32 kHz crystal output for RTC. If it is not used, it has to be Float. Clock output signal. The CLKSEL of MISCCR register configures the clock output mode among the MPLL CLK, UPLL CLK, FCLK, HCLK, and PCLK. nRESET suspends any operation in progress and places S3C2440A into a known reset state. For a reset, nRESET must be held to L level for at least 4 FCLK after the processor power has been stabilized. For external device reset control (nRSTOUT = nRESET & nWDTRST & SW_RESET) 1.2V core power on-off control signal Probe for battery state (Does not wake up at Sleep mode in case of low battery state). If it isnt used, it has to be High (3.3V). OM [3:2] determines how the clock is made. OM [3:2] = 00b, Crystal is used for MPLL CLK source and UPLL CLK source. OM [3:2] = 01b, Crystal is used for MPLL CLK source and EXTCLK is used for UPLL CLK source. OM [3:2] = 10b, EXTCLK is used for MPLL CLK source and Crystal is used for UPLL CLK source. OM [3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source. External clock source. When OM [3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source. When OM [3:2] = 10b, EXTCLK is used for MPLL CLK source only. When OM [3:2] = 01b, EXTCLK is used for UPLL CLK source only. If it is not used, it has to be High (3.3V). Crystal Input for internal OSC circuit. When OM [3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source. When OM [3:2] = 01b, XTIpll is used for MPLL CLK source only. When OM [3:2] = 10b, XTIpll is used for UPLL CLK source only. If it is not used, XTIpll has to be High (3.3V).

AMD Flash Memory(SOCKET) INTEL StrataFlash Memory(SMD Unload)
A[25:0] A[25:0] DATA[31:0] DATA[31:0] A[25:0] DATA[31:0]
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 VSS0 VSS1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 nCE nOE nWE nRY/BY nRESET nBYTE VDD0
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 nCE_A16 nOE nWE nRESET
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 R1 0
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VCC0 VCC1 VCCQ nBYTE STS nRP nOE nWE nCE0 nCE1 nCE2 VPEN
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15
AM29LV800BB-90EC (1MB, With Socket)

nCE_S32

nRESET nOE nWE
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 R2 0
DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31

GND0 GND1 GND2

48 R(Unload) R5 4.7K
E28F128J3A150 (16MB,Unload) 1 C139 + 10uF/16V C1 100nF 2 C2 100nF 1
E28F128J3A150 (16MB,Unload)

R(Unload) R6 4.7K

C3 100nF 2 2

C4 100nF 2

C5 100nF 2

C6 100nF 2

C7 100nF 2

1 C8 100nF

DATA[31:0]

VCC VCC VSS VSS

K6X4016T3F(unload)

C101 100nF 2 2

C102 100nF
Title SMDK2440 (S3C2440 Evaluation Board) Size A3 Date: Document Number AMD & INTEL(NOR) FLASH MEMORY / SRAM Monday, June 28, 2004 Sheet 1 of 12 Rev 1.0

WE LB UB OE

nWE nWBE0 nWBE1 nOE

R270 OPEN R11 R12

4.7K nCE_S32
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16
"Silk" Boot setting
VDD3.3V VDD3.3V OM0(J1) OM1(J2) 32bit(J3) 16bit(J4) AMD(D) INTEL 1-2 2-3 2-3 1-2 2-3 1-2 1-2 2-3 NAND 2-3 2-3 2-3 2-3 Test mode 1-2 1-2 -

R7 10K

"5V"

VDD_LCDI

22uF/36V (or 10uF/36V) 3 MAX629 1

Header

VR1 CVR 10K 1

LLEND TSXP TSYP

"3.3V"

10uF/16V TSXM TSYM 2

3.3V/24V DC/DC CONVERTER (STN LCD)
LD0 LD1 LD2 LD16 LD17 LD18

HEADCONN_40P

LD3 LD4 LD5 LD6 LD7 LD10 LD11 LD12 2
2 LLCD_PWREN 4 LDLDLCD_LPCOE 10 LCD_LPCREV 12 LCD_LPCREVB 1
R73 VCCA DIR A0 A1 A2 A3 A4 A5 A6 A7 GND GND VCCB VCCB nOE B0 B1 B2 B3 B4 B5 B6 B7 GND 14 13

VD[23:0]

C100nF 1 4.7K
VD3 VD4 VD5 VD6 VD7 VD10 VD11 VD12

10uF/16V 2

AIN0 AIN2 TSYM TSXM EINT10 AIN1 AIN3 TSYP TSXP
HEADCONN_12P C46 100nF LD[23:0]

74LVC4245 phillips

LVFRAME LVCLK LVM 18 20

2.54mm header 10pin

LD13 LD14 LD15 LD19 LD20 LD21 LD22 LD2
R74 4.7K 1 VCCA DIR A0 A1 A2 A3 A4 A5 A6 A7 GND GND VCCB VCCB nOE B0 B1 B2 B3 B4 B5 B6 B7 GND
LVLINE LnDIS_OFF LD1 LD3 LD5 LD7 2

10uF/16V

"1-2 Short Default"
VD13 VD14 VD15 VD19 VD20 VD21 VD22 VD23 2

C100nF

LD0 LD2 LD4 LD6

HEADCONN_20P

LD[23:0]
TSYP TSYM TSXM TSXP 2 C2 1nF 2 C45 1nF M60-04-30-134P Mitsumi
LD0 LD1 LD2 LD8 LD9 LD16 LD17 LD2
R75 4.7K 1 VCCA DIR A0 A1 A2 A3 A4 A5 A6 A7 GND GND VCCB VCCB nOE B0 B1 B2 B3 B4 B5 B6 B7 GND 14 13

VDD3.3V VDD3.3V

VD0 VD1 VD2 VD8 VD9 VD16 VD17 VDLVFRAME LVLINE LVCLK LnDIS_OFF

R161 R162

C100nF LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7

C53 10uF/16V 2 100nF

VDD_LCDI R76
4.7K 2 CLVFRAME LVLINE LVCLK LVM LnDIS_OFF LLEND LLCD_PWREN 11 12
VCCA DIR A0 A1 A2 A3 A4 A5 A6 A7 GND GND VCCB VCCB nOE B0 B1 B2 B3 B4 B5 B6 B7 GND 14 13
BOXCONN_16P (Unload) VFRAME VLINE VCLK VM nDIS_OFF LEND LCD_PWREN R77 R4.7K Size A3 Date:
film connector for LCBHBT161M MOLEX 52207-1690
Title SMDK2440 (S3C2440 Evaluation Board) Document Number External LCD interface / Touch screen / ADC Monday, June 28, 2004 Sheet 5 of 12 Rev 1.0
3. SMDK2440 Schematic Diagram (Base Board) - Sheet 6 of 12

VDD1.8V VDD3.3V

CAMDATA0 CAMDATA1 CAMDATA2 CAMDATA3 CAMDATA4 CAMDATA5 CAMDATA6 CAMDATA13 VCCB VCCB nOE B0 B1 B2 B3 B4 B5 B6 B7 GND VCCA DIR A0 A1 A2 A3 A4 A5 A6 A7 GND GND XCAM_Y0 XCAM_Y1 XCAM_Y2 XCAM_Y3 XCAM_Y4 XCAM_Y5 XCAM_Y6 XCAM_Y7 C60

LP3965-ADJ 2 RR4 4.7K

(1.8V)

C61 100pF 2

+ C62 10uF/16V 2

<10uF/16V

10K R84

VDD2.8V VDD5V

IICSDA XIICSDA OEn1 VCC 1A OEn2 1B 2B GND 2A CBTD5

VDD2.8V

DATA[31:0] A[25:0]

XIICSCL IICSCL

<->
10K XCAM_Y1 XCAM_Y3 XCAM_Y5 XCAM_Y7 XPCLK XVSYNC

XIICSCL nXDACK0

VCCB VCCB nOE B0 B1 B2 B3 B4 B5 B6 B7 GND VCCA DIR A0 A1 A2 A3 A4 A5 A6 A7 GND GND XPCLK XHSYNC XVSYNC

FORCEON FORCEOFF VCC MAX3243/SO GND 25 TP15 UART_CLK 1 TP16 TOUT01 IrTxD 1

KEYBOARD

2 VCC + C69 0.1uF/16V 2
"Silk" C73 RXD1 0.1uF/16V IrRxD
BOXCONN_DBC76 C77 330pF C78 330pF

C79 330pF

(Female) COM2

RTS1 CTS1

R107 R158

DMAMODE0 DMAMODE1

UART Interface
C81 + R108 4.7uF/16V 1 R109 5.2 74LV08 IrTxD 74LV04 R113
GND0 LED LEDDRV NC0 LEDVCC TXD GND1 NC1 PWDOWN RXDSIR BIAS VCC PINVCC RPM851A 1

5 nIrDATXDEN

10K 11

74LV08

1 R114 0

10 74LV08 IrRxD

C82 0.33uF 1

C83 3.3nF

T1IN R1OUT T2IN R2OUT

2 RTS1 CTS1

SIO 9P J16,J18 J17,J19 COM2 UART1 2-3(D) COM2 UART2 1-2 2-3 IrDA 1-2

IrDA Interface

SMDK2440 (S3C2440 Evaluation Board) Document Number UART / IrDA Monday, June 28, 2004 Sheet 7 of 12 Rev 1.0
3. SMDK2440 Schematic Diagram (Base Board) - Sheet 8 of 12
J1 J2 KBDSPIMISO KBDSPIMOSI KBDSPICLK KBDINT R120

R115 10K

C[13:0]

R117 4.7K RnSS_KBD

C[13:0] R116 10K C8 C9 C10 C11
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C14 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 HEADER14

R119 150K 2

J24 Header

0 (Unload)

R44 PWR_OK NC0 OSCO OSCI VCC NC3 NC4 _RESET _WKU VX C7
_ATN _SS SCK MOSI MISO XSW SW0 C8 C9 C10/WUKO C11/_LID
X2 R126 1M R123 15K R127 15K KEYBOARD 2 R124 15K R150K C84 22pF C85 22pF 2MHz

UR5HCSPI-SA

NC2 C12 C13 GIO0 _IOTEST VSS NC1 R7 R6 R5 R4

C12 C13

R122 150K

J25 Header

R[7:0]
R0 R1 R2 R3 R4 R5 R6 R7 R[7:0] R0 R1 R2 R3 R4 R5 R6 R7 HEADER8
C6 C5 C4 C3 C2 C1 C0 R0 R1 R2 R3

R0 R1 R2 R3

C6 C5 C4 C3 C2 C1 C0

R4 R5 R6 R7

"Silk" Default J24:1-2 J25:2-3

KEY BOARD BLOCK

R101 10K R102 10K R103 10K R104 10K R105 10K R106 10K 9 C704 10pF C705 10pF C706 10pF C707 10pF C708 10pF C709 100nF SD CARD SOCKET (SKT SD/MMC Standard Type)
SPICLK SPIMOSI SPIMISO nSS_SPI
nCD_SD WP_SD SDDATA1 SDDATA0 SDCLK SDCMD SDDATA3 SDDATA2

TANTAL

SMD 1uF/16V 3216
TANTAL USB PORT USB PORT X-TAL
SMD 220uF/16V 7343 USB JACK B type USB JACK Dual USB Port - A type Crystal 32.768kHz
4. SMDK2440 Part List (CPU Board) - Sheet 4 of 4
ITEMS 63 X-TAL PCB UNLOAD DESCRIPTION SMD Crystal 7050 94SMXD(16.9344Mhz) 108x99x2t, FR-4, 8LAYER,Gold Plated OPEN (Unload) C1~C7, R22, R23, R24, R26, R28, R30, R38, R44, R46, R64, R65, R66, R76, R88, R93, R98, R324, R325, U10 X2 LOCATION QTY 26
4. SMDK2440 Part List (Base Board) - Sheet 1 of 7
ITEMS BEAD CERAMIC CAP DESCRIPTION SMD BLM31P601SG 3216 SMD 0.1uF 2012 LOCATION FB3, FB4 C1~C10, C12~20,C22, C28~C36, C38, C40, C43~C46, C48~C59, C63, C80, C88, C89, C97, C99, C101~C104, C140~C142, C180, C181, C191, C602, C613, C640 C61, C189 C37 C107, C109, C111, C113, C115, C117, C603, C604, C606, C614, C615, C618, C620, C622, C625, C626, C628, C630, C632, C633, C635, C636 C616, C629 C84, C85 C83 C82 C70, C71, C74, C75, C76, C77, C78, C79, C621 C617 C601, C609, C612 C605 C21 C95 C94 CON6 CON14, CON22 QTY 2 64
CERAMIC CAP CERAMIC CAP CERAMIC CAP
SMD 100pF 2012 SMD 150pF 2012 SMD 1uF 2012
CERAMIC CAP CERAMIC CAP CERAMIC CAP CERAMIC CAP CERAMIC CAP
SMD 2.2uF 2012 SMD 22pF 2012 SMD 3.3nF 2012 SMD 330nF 2012 SMD 330pF 2012
CERAMIC CAP CERAMIC CAP CERAMIC CAP CERAMIC CAP CONDENSER CONDENSER CONNECTOR CONNECTOR
SMD 33pF 2012 SMD 4.7uF 3528 SMD 47nF 2012 SMD 560pF 2012 Electrolytic 220uF/10V (5x11) SHL Electrolytic 680uF/16V (10x12.5) SHL 5268-02,RIGHT ANGLE, BOX BOX CONNECTOR DBED-9S (FEMALE)
4. SMDK2440 Part List (Base Board) - Sheet 2 of 7
ITEMS CONNECTOR CONNECTOR CONNECTOR CONNECTOR DESCRIPTION BTE-060-03-L-D-A HEADER 1x2 PCMCIA 68PIN FRAME and SCOKET SMART MEDIA CARD CN015R-3123-0 (TYPE31) 4P CON Pitch=1.25mm 14PIN Pitch=1.25mm 8PIN Female HEADER 2x16 MAIL HEADER 1x3 LOCATION CON23, CON24 J14, J21, J22, J23, J601 CON3 CON1 QTY 1 1
CONNECTOR FPC CONNECTOR FPC CONNECTOR FPC CONNECTOR HEADER CONNECTOR HEADER
CON603 CON16 CON17 CON19 J1~J9, J11, J12, J16~J19, J24, J25 CON15 CON7 CON10, CON11, CON12 CON4 CON8, CON5 CON18 CON21 CON2 CON20 CON25 CON602 CON13 D3 D601
CONNECTOR HEADER CONNECTOR HEADER CONNECTOR HEADER CONNECTOR HEADER CONNECTOR HEADER CONNECTOR JACK CONNECTOR JACK CONNECTOR LAN CONNECTOR LCD CONNECTOR LCD CONNECTOR LCD CONNECTOR SOCKET DIODE DIODE
MAIL HEADER 1x5 MAIL HEADER 2x10 MAIL HEADER 2x17 MAIL HEADER 2x20 MAIL HEADER 2x5 DC JACK STEREO JACK RT-30AWX XF10B11A-COMBO1-4S 14_5602_020_001_829 (20P) 14_5602_024_000_829 (24P) 50Pin SD CARD SOCKET DC-PMS-1.0 1N4148 SMD 1SS355
4. SMDK2440 Part List (Base Board) - Sheet 3 of 7
ITEMS DIODE DIODE DIODE DIODE FUSE IC DESCRIPTION SMD DUAL Schottky Diode SMD Schottky Diode MCL4148-TR3 SMD Schottky Diode MBRD320 SMD Schottky Diode MBRS130L POLY SWITCH miniSMDM150/24 (4836) Dual bus switch with level shifting CBTD3306 (SO8) Hex Inverter 74LV04 (14SOP) Hex inverting Schmitt-trigger 74LV14 (14SOP) Octal dual supply translating transceiver 3state 74LVC4245 (24SSOP) PC Card Host Adapters CL-PD6710 (144VQFP) PC Card power-interface Switch TPS2211 (16SOP) Quad 2-input AND gate 74LV08 (14SOP) Quad 2-input OR gate 74LV32 (14SOP) RS-232 Line Driver/Receivers MAX3232C (16SOP) RS-232 Line Driver/Receivers MAX3243 (28SSOP) Very low-power SPI-interface keyboard encoder UR5HCSPI-SA (44QFP) White LED driver MP1521/MSOP-10P Economy audio CODEC for MiniDisc (MD) home stereo and portable applications UDA1341TS (28SSOP) IC COMPERATOR AD8542AR (8SOIC) LOCATION DN601, DN602, DN603 D602 D2 D1 FP1 U37 QTY 1 1

Table 1-4. S3C2413X Special Registers (Sheet 9 of 23) Register Name FRCPAT31 FRCPAT32 FRCPAT33 FRCPAT34 FRCPAT35 FRCPAT36 FRCPAT37 FRCPAT38 FRCPAT39 FRCPAT40 FRCPAT41 FRCPAT42 FRCPAT43 FRCPAT44 FRCPAT45 FRCPAT46 FRCPAT47 FRCPAT48 FRCPAT49 FRCPAT50 FRCPAT51 FRCPAT52 FRCPAT53 FRCPAT54 FRCPAT55 FRCPAT56 FRCPAT57 FRCPAT58 FRCPAT59 FRCPAT60 FRCPAT61 FRCPAT62 FRCPAT63 Address (B. Endian) 0X4D000130 0X4D000134 0X4D000138 0X4D00013C 0X4D000140 0X4D000144 0X4D000148 0X4D00014C 0X4D000150 0X4D000154 0X4D000158 0X4D00015C 0X4D000160 0X4D000164 0X4D000168 0X4D00016C 0X4D000170 0X4D000174 0X4D000178 0X4D00017C 0X4D000180 0X4D000184 0X4D000188 0X4D00018C 0X4D000190 0X4D000194 0X4D000198 0X4D00019C 0X4D0001A0 0X4D0001A4 0X4D0001A8 0X4D0001AC 0X4D0001B0 Address (L. Endian) Acc. Unit W Read/ Write R/W Function
LCD Controller(continue) FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register FRC Pattern Register
Table 1-4. S3C2413X Special Registers (Sheet 10 of 23) Register Name Camera Interface CISRCFMT CIWDOFST CIGCTRL CIDOWSFT2 CICOYSA1 CICOYSA2 CICOYSA3 CICOYSA4 CICOCBSA1 CICOCBSA2 CICOCBSA3 CICOCBSA4 CICOCRSA1 CICOCRSA2 CICOCRSA3 CICOCRSA4 CICOTRGFMT CICOCTRL CICOSCPRERATIO CICOSCPREDST CICOSCCTRL CICOTAREA CICOSTATUS CIIMGCPT CICOCPTSEQ COCOSCOS CIIMGEFF 0x4D800000 0x4D800004 0x4D800008 0x4D800014 0x4D800018 0x4D80001C 0x4D800020 0x4D800024 0x4D800028 0x4D80002C 0x4D800030 0x4D800034 0x4D800038 0x4D80003C 0x4D800040 0x4D800044 0x4D800048 0x4D80004C 0x4D800050 0x4D800054 0x4D800058 0x4D80005C 0x4D800064 0x4D8000A0 0x4D8000A4 0x4D8000A8 0x4D8000B0

Read/ Write RW

Input Source Format Window offset register Global control register Window option register 2 Y 1st frame start address for codec DMA Y 2nd frame start address for codec DMA Y 3rd frame start address for codec DMA Y 4th frame start address for codec DMA Cb 1st frame start address for codec DMA Cb 2nd frame start address for codec DMA Cb 3rd frame start address for codec DMA Cb 4th frame start address for codec DMA Cr 1st frame start address for codec DMA Cr 2nd frame start address for codec DMA Cr 3rd frame start address for codec DMA Cr 4th frame start address for codec DMA Target image format of codec DMA Codec DMA control related Codec pre-scaler ratio control Codec pre-scaler destination format Codec main-scaler control Codec scaler target area Codec path status Image capture enable command Codec dma capture sequence related Codec scan line offset related Image Effects related

Bit [31:4] IDCY [3:0]

Description Read undefined. Write as zero. Idle or turnaround cycles. Default to 1111 at reset. This field controls the number of bus turnaround cycles added between read and write accesses to prevent bus contention on the external memory data bus.
Initial State 0x0000_000 0xF
Turnaround time = IDCY x SMMEMCLK period *note : SMMEMCLK is internal Memory Clock for SSMC.
BANK READ WAIT STATE CONTROL REGISTERS 0-7 Register SMBWSTRDR0 SMBWSTRDR1 SMBWSTRDR2 SMBWSTRDR3 SMBWSTRDR4 SMBWSTRDR5 SMBWSTRDR6 SMBWSTRDR7 Address 0x4F000004 0x4F000024 0x4F000044 0x4F000064 0x4F000084 0x4F0000A4 0x4F0000C4 0x4F0000E4 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bank0 read wait state control register Bank1 read wait state control register Bank2 read wait state control register Bank3 read wait state control register Bank4 read wait state control register Bank5 read wait state control register Bank6 read wait state control register Bank7 read wait state control register Reset Value 0x0000_001 F 0x0000_001 F 0x0000_001 F 0x0000_001 F 0x0000_001 F 0x0000_001 F 0x0000_001 F 0x0000_001 F

Bit [31:5] WSTRD [4:0]

Description Read undefined. Write as zero. Read wait state. Defaults to 11111 at reset. For SRAM and ROM, the WSTRD field controls the number of wait states for read accesses, and the external wait assertion timing for reads. For burst ROM, the WSTRD field controls the number of wait states for the first read access only. Wait state time = WSTRD x SMMEMCLK period
Initial State 0x0000_000 0x1F
BANK WRITE WAIT STATE CONTROL REGISTERS 0-7 Register SMBWSTWRR0 SMBWSTWRR1 SMBWSTWRR2 SMBWSTWRR3 SMBWSTWRR4 SMBWSTWRR5 SMBWSTWRR6 SMBWSTWRR7 Address 0x4F000008 0x4F000028 0x4F000048 0x4F000068 0x4F000088 0x4F0000A8 0x4F0000C8 0x4F0000E8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bank0 write wait state control register Bank1 write wait state control register Bank2 write wait state control register Bank3 write wait state control register Bank4 write wait state control register Bank5 write wait state control register Bank6 write wait state control register Bank7 write wait state control register Reset Value 0x0000_001 F 0x0000_001 F 0x0000_001 F 0x0000_001 F 0x0000_001 F 0x0000_001 F 0x0000_001 F 0x0000_001 F Initial State 0x0000_000 0x1F

The operating mode mainly is classified into four categories according to the boot mode. The boot code can be placed in NAND, NOR, and OneNAND, since the S3C2413 memory controller can support them as an external device. Each boot mode contains several sub-groups according to the each characteristic. PHASE LOCKED LOOP (PLL) The MPLL and the UPLL within the clock generator, as an analog circuit, synchronizes an output signal with a reference input signal in frequency and phase. In this application, it includes the following basic blocks as shown in Figure 6-2 The Voltage Controlled Oscillator (VCO) generates the output frequency proportional to input DC voltage. The pre-divider divides the input frequency (Fin) by P. The main divider divides the VCO output frequency by M, which is input to Phase Frequency Detector (PFD). The post scaler divides the VCO output frequency by S, which is MPLLFOUT (the output frequency from MPLL block)/UPLLFOUT (the output frequency from UPLL block). The phase difference detector calculates the phase difference and the charge pump increases/decreases the output voltage. The output clock frequencies MPLLFOUT and UPLLFOUT are related to the reference input clock frequency MPLLFIN and UPLLFIN by the following equation: FOUTMPLL = (2m X FIN) / (p x 2s) where, m = (MDIV + 8), p = (PDIV + 2), s = SDIV FOUTUPLL = (m x FIN) / (p x 2s) where, m = (MDIV + 8), p = (PDIV + 2), s = SDIV
The following sections describe the operation of the PLL, including the phase difference detector, the charge pump, the Voltage controlled oscillator (VCO), and the loop filter.
Off-chip loop filter FIN Pre-Divider PFD Charge Pump VCO Post Scaler FOUT

Main Divider

Figure 6-2. S3C2413 internal PLL block diagram PHASE FREQUENCY DETECTOR (PFD) The PFD monitors the phase difference between Fref and Fvco, and generates a control signal (tracking signal) when it detects a difference. The Fref means the reference frequency as shown in the Figure XXX. CHARGE PUMP (PUMP) The charge pump converts PFD control signals into a proportional charge in voltage across the external filter that drives the VCO. LOOP FILTER The control signal, which the PFD generates for the charge pump, may generate large excursions (ripples) each time the FVCO is compared to the FREF. To avoid overloading the VCO, a low pass filter samples and filters the high-frequency components out of the control signal. The filter is typically a single-pole RC filter with a resistor and a capacitor. VOLTAGE CONTROLLED OSCILLATOR (VCO) The output voltage from the loop filter drives the VCO, causing its oscillation frequency to increase or decrease linearly as a function of variations in average voltage. When the Fvco matches Fref in terms of frequency as well as phase, the PFD stops sending control signals to the charge pump, which in turn stabilizes the input voltage to the loop filter. The VCO frequency then remains constant, and the PLL remains fixed onto the system clock. USUAL CONDITIONS FOR PLL & CLOCK GENERATOR PLL & Clock Generator generally uses the following conditions. Loop filter capacitance MPLL : 820 pF UPLL : 1500 pF External X-tal frequency External capacitance used for X-tal

R /CLEAR
Correspond to endpoint 0 interrupt. Set by the USB under the following conditions: 1. OUT_PKT_RDY bit is set. 2. IN_PKT_RDY bit is cleared. 3. SENT_STALL bit is set 4. SETUP_END bit is set 5. DATA_END bit is cleared (it indicates the end of control transfer).
INTERRUPT REGISTER (EP_INT_REG/USB_INT_REG) (Continued) Register USB_INT_REG Address 0x52000158(L) 0x5200015B(B) R/W R/W (byte) Description USB interrupt pending/clear register Reset Value 0x00
USB_INT_REG RESET Interrupt RESUME Interrupt

Bit [2] [1]

MCU R /CLEAR R /CLEAR

USB SET SET

Description Set by the USB when it receives reset signaling. Set by the USB when it receives resume signaling, while in Suspend mode. If the resume occurs due to a USB reset, then the MCU is first interrupted with a RESUME interrupt. Once the clocks resume and the SE0 condition persists for 2.5us, USB RESET interrupt will be asserted. Set by the USB when it receives suspend signalizing. This bit is set whenever there is no activity for 3ms on the bus. Thus, if the MCU does not stop the clock after the first suspend interrupt, it will continue to be interrupted every 3ms as long as there is no activity on the USB bus. By default, this interrupt is disabled.

SUSPEND Interrupt

NOTE: If the RESET interrupt is occurred, all USB device registers should be re-configured.
INTERRUPT ENABLE REGISTER (EP_INT_EN_REG/USB_INT_EN_REG) Corresponding to each interrupt register, The USB device controller also has two interrupt enable registers (except resume interrupt enable). By default, usb reset interrupt is enabled. If bit = 0, the interrupt is disabled. If bit = 1, the interrupt is enabled. Register EP_INT_EN_REG Address 0x5200015C(L) 0x5200015F(B) R/W R/W (byte) Description Determine which interrupt is enabled Reset Value 0xFF
EP_INT_EN_REG EP4_INT_EN EP3_INT_EN EP2_INT_EN EP1_INT_EN EP0_INT_EN

Bit [4] [3] [2] [1] [0]

MCU R/W R/W R/W R/W R/W

USB R R R R R

Description EP4 Interrupt Enable bit 0 = Interrupt disable EP3 Interrupt Enable bit 0 = Interrupt disable EP2 Interrupt Enable bit 0 = Interrupt disable EP1 Interrupt Enable bit 0 = Interrupt disable EP0 Interrupt Enable bit 0 = Interrupt disable 1 = Enable

Initial State 1 1

1 = Enable = Enable = Enable = Enable

Register USB_INT_EN_ REG

Address 0x5200016C(L) 0x5200016F(B)

R/W R/W (byte)

Description Determine which interrupt is enabled

Reset Value 0x04

INT_MASK_REG RESET_INT_EN Reserved SUSPEND_INT_ EN

Address 0X4D000400. 0X4D0007FC 0X4D000404
R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
Table 14-5. 5:5:5:1 Format INDEX\Bit Pos. 00H 01H. FFH Number of VD R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 BI
Address 0X4D000400 0X4D000404. 0X4D0007FC
R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
NOTES: 1. 0x4D000400 is Palette start address. 2. VD18, VD10 and VD2 have the same output value, I. 3. DATA[31:16] is invalid.
Palette Read/Write The Read/Write operation on the palette must be written only while ENVID bit set 0. Temporary Palette Configuration The S3C2413X allows the user to fill a frame with one color without complex modification to fill the one color to the frame buffer or palette. The one colored frame can be displayed by the writing a value of the color which is displayed on LCD panel to TPALVAL of TPAL register and enable TPALEN.
A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 R4 B3 B2 B1 B0 I

G0 A[6]

A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7]
A[5] A[4] A[3] A[2] A[1] A[0]
LCD Panel 16BPP 5:5:5+1 Format(Non-Palette)
A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
A[15] A[14] A[13] A[12]A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] LCD Panel 16BPP 5:6:5 Format(Non-Palette)
Figure 14-5. 16BPP Display Types (TFT)

INT_FrSyn

VBPD+1 VSPW+1

LINEVAL +Frame

VFPD+1

1 Line

LEND HBPD+1 HSPW+1

HOZVAL+1

HFPD+1
Figure 14-6. TFT LCD Timing Example
SAMSUNG TFT LCD PANEL (3.5 PORTRAIT / 256K COLOR / REFLECTIVE A-SI/TRANSFLECTIVE A-SI TFT LCD) The S3C2413X supports following SEC TFT LCD panels. 1. SAMSUNG 3.5 Portrait / 256K Color /Reflective a-Si TFT LCD. LTS350Q1-PD1: TFT LCD panel with touch panel and front light unit LTS350Q1-PD2: TFT LCD panel only 2. SAMSUNG 3.5 Portrait / 256K Color /Transflective a-Si TFT LCD. LTS350Q1-PE1: TFT LCD panel with touch panel and front light unit LTS350Q1-PE2: TFT LCD panel only The S3C2413X provides timing signals as follows to use LTS350Q1-PD1 / PD2 and LTS350Q1-PE1 / PE2 LTS350Q1-PD1 / PD2 STH: Horizontal Start Pulse TP: Source Driver Data Load Pulse INV: Digital Data Inversion LCD_HCLK: Horizontal Sampling Clock CPV: Vertical Shift Clock STV: Vertical Start Pulse OE: Gate On Enable REV: Inversion Signal REVB: Inversion Signal LTS350Q1-PE1 / PE2 STH: Horizontal Start Pulse TP: Source Driver Data Load Pulse INV: Digital Data Inversion LCD_HCLK: Horizontal Sampling Clock CPV: Vertical Shift Clock STV: Vertical Start Pulse LCCINV: Source drive IC sampling inversion signal REV: VCOM modulation Signal REVB: Inversion Signal

STNCOL

PNRMODE

BPPMODE

LCD Control 2 Register Register LCDCON2 Address 0X4D000004 R/W R/W Description LCD control 2 register Reset Value 0x00000000

LCDCON2 VBPD

Bit [31:24]
Description TFT: Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period. STN: These bits should be set to zero on STN LCD. TFT:These bits determine the vertical size of LCD panel. STN: LCD VERTICAL SIZE (Panel Y size) TFT: Vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period. STN: These bits should be set to zero on STN LCD. TFT: Vertical sync pulse width determines the VSYNC pulse's high level width by counting the number of inactive lines. STN: These bits should be set to zero on STN LCD.

LINEVAL VFPD

[23:14] [13:6]
LCD Control 3 Register Register LCDCON3 Address 0X4D000008 R/W R/W Description LCD control 3 register Reset Value 0x00000000
LCDCON3 Reserved HBPD (TFT) WDLY (STN) HOZVAL
Bit [27] [25:19] Should be 0
Description TFT: Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data. STN: WDLY (Base on System Clock) TFT: These bits determine the horizontal size of LCD panel. HOZVAL has to be determined to meet the condition that total bytes of 1 line are 4n bytes. If the x size of LCD is 120 dot in mono mode, x=120 cannot be supported because 1 line consists of 15 bytes. Instead, x=128 in mono mode can be supported because 1 line is composed of 16 bytes (2n). LCD panel driver will discard the additional 8 dot. STN: LCD HORIZONTAL SIZE (Panel X size)

Initial state 0 0

[18:8]
HFPD (TFT) LINEBLANK (STN)
TFT: Horizontal front porch is the number of VCLK periods between the end of active data and the rising edge of HSYNC. STN: LINE BLANK (Base on System Clock)
LCD Control 4 Register Register LCDCON4 Address 0X4D00000C R/W R/W Description LCD control 4 register Reset Value 0x00000000

LCDCON4 VMMODE

Bit [18:16] STN: VMMODE [18] VM Enable [17] VMode
[16] Reset per Frame when VMMODE[21:20] is all high [15:8] Valid Line Number when VMMODE[21:20] is all high (Minimum 1). MVAL HSPW(TFT) WLH(STN) [15:8] [7:0] STN: These bit define the rate at which the VM signal will toggle if the VMMODE[18:17] bit is set to logic '0x3'. ( Minimum value : 1) TFT: Horizontal sync pulse width determines the HSYNC pulse's high level width by counting the number of the VCLK. STN: WLH (Base on System Clock, Minimum=1) 0 0

LCD Control 5 Register Register LCDCON5 Address 0X4D000010 R/W R/W Description LCD control 5 register Reset Value 0x00000000

LCDCON5 Reserved VSTATUS

Bit [31:17] [16:15]
Description This bit is reserved and the value should be 0. TFT: Vertical Status (read only). 00 = VSYNC 01 = BACK Porch 10 = ACTIVE 11 = FRONT Porch TFT: Horizontal Status (read only). 00 = HSYNC 01 = BACK Porch 10 = ACTIVE 11 = FRONT Porch TFT: This bit determines the order of 24 bpp video memory. 0 = LSB valid 1 = MSB Valid TFT: This bit selects the format of 16 bpp output video data. 0 = 5:5:5:1 Format 1 = 5:6:5 Format STN/TFT: This bit controls the polarity of the VCLK active edge. 0 = The video data is fetched at VCLK falling edge 1 = The video data is fetched at VCLK rising edge STN/TFT: This bit indicates the VLINE/HSYNC pulse polarity. 0 = Normal 1 = Inverted STN/TFT: This bit indicates the VFRAME/VSYNC pulse polarity. 0 = Normal 1 = Inverted STN/TFT: This bit indicates the VD (video data) pulse polarity. 0 = Normal 1 = VD is inverted. TFT: This bit indicates the VDEN signal polarity. 0 = normal 1 = inverted This bit is reserved and the value should be 0. TFT: This bit indicates the LEND signal polarity. 0 = normal 1 = inverted This bit is reserved and the value should be 0. TFT: LEND output signal enable/disable. 0 = Disable LEND signal 1 = Enable LEND signal STN/TFT: Byte swap control bit. 0 = Swap Disable STN/TFT: Half-Word swap control bit. 0 = Swap Disable 1 = Swap Enable

HSTATUS

BPP24BL FRM565 INVVCLK

[12] [11] [10]

INVVLINE INVVFRAME

[9] [8]

INVVD INVVDEN Reserved INVLEND Reserved ENLEND BSWP HWSWP
[7] [6] [5] [4] [3] [2] [1] [0]

1 = Swap Enable

FRAME Buffer Start Address 1 Register Register LCDSADDR1 Address 0X4D000014 R/W R/W Description STN/TFT: Frame buffer start address 1 register Reset Value 0x00000000

LCDSADDR1 LCDBANK

Bit [29:21]
Description These bits indicate A[30:22] of the bank location for the video buffer in the system memory. LCDBANK value cannot be changed even when moving the view port. LCD frame buffer should be within aligned 4MB region, which ensures that LCDBANK value will not be changed when moving the view port. So, care should be taken to use the malloc() function. For dual-scan LCD : These bits indicate A[21:1] of the start address of the upper address counter, which is for the upper frame memory of dual scan LCD or the frame memory of single scan LCD. For single-scan LCD : These bits indicate A[21:1] of the start address of the LCD frame buffer.

LCDBASEU

[20:0]

0x000000

FRAME Buffer Start Address 2 Register Register LCDSADDR2 Address 0X4D000018 R/W R/W Description STN/TFT: Frame buffer start address 2 register Reset Value 0x00000000

LCDSADDR2 LCDBASEL

32.768KHZ X-TAL CONNECTION EXAMPLE The Figure 16-2 shows a circuit of the RTC unit oscillation at 32.768 kHz.
15~ 22pF XTIrtc 32768Hz XTOrtc
Figure 16-2. Main Oscillator Circuit Example
REAL TIME CLOCK SPECIAL REGISTERS
REAL TIME CLOCK CONTROL (RTCCON) REGISTER The RTCCON register consists of 4 bits such as the RTCEN, which controls the read/write enable of the BCD registers, CLKSEL, CNTSEL, and CLKRST for testing. RTCEN bit can control all interfaces between the CPU and the RTC, so it should be set to 1 in an RTC control routine to enable data read/write after a system reset. Also before power off, the RTCEN bit should be cleared to 0 to prevent inadvertent writing into RTC registers. Register RTCCON Address 0x57000040(L) 0x57000043(B) Bit [4] R/W Description Reset Value 0x0
R/W RTC control register (by byte) Description

RTCCON TICsel

Tick Time clock select. 0 = clock period of 1/2048 second 1 = clock period of 1/32768 second RTC clock count reset. 0 = No reset, 1 = Reset BCD count select. 0 = Merge BCD counters 1 = Reserved (Separate BCD counters) BCD clock select. 0 = XTAL 1/215 divided clock 1 = Reserved (XTAL clock only for test) RTC control enable. 0 = Disable 1 = Enable NOTE: Only BCD time count and read operation can be performed.

CLKRST CNTSEL

CLKSEL
NOTES: 1. All RTC registers have to be accessed for each byte unit using STRB and LDRB instructions or char type pointer. 2. (L): Little endian. (B): Big endian.
TICK TIME COUNT (TICNT0) REGISTER 0 Register TICNT0 Address 0x57000044(L) 0x57000047(B) Bit [7] [6:0] R/W Description Reset Value 0x0
R/W Tick time count register (by byte) Description
TICNT TICK INT ENABLE TICK TIME COUNT 0

Initial State 0 000000

Tick time interrupt enable. 0 = Disable 1 = Enable Upper 7bits of 15-bit tick time count value
TICK TIME COUNT (TICNT1) REGISTER 1 Register TICNT1 Address 0x5700004C(L) 0x5700004F(B) R/W Description Reset Value 0x0

b ResetHandler

;handler for Reset

b HandlerUndef ;handler for Undefined mode b HandlerSWI ;handler for SWI interrupt
b HandlerPabort ;handler for PAbort b HandlerDabort ;handler for DAbort
Reset Handler Disable WDT; Setting Clock;

Enable WDT;

TASK 1

TASK 2

TASK N
Figure 2 Simple flow chart
Timer4 is selected for this workaround example. An InitFiq in figure 3 is to set Timer4 interrupt to FIQ interrupt. The Timer4 interrupt will be considered to FIQ interrupt when the bit 14 of INTMOD (0x4A000004) register on Interrupt Controller is set to 1. InitFiq PROC ; Setup Timer4 Interrupt to FIQ ldr r0, =INTMOD ; Set Interrupt Mode 1 #(1 14) Figure 3 An implementation of InitFiq
An OS Timer will operate tasks related with the operating system. In addition, it also should stop and restart the Timer4 and reload the Watch-Dog Timer as shown in figure 4. OS Timer ; To do something Reload WDT St Ti 4 Figure 4 The implementation of OS Timer If the system gets hung for some unknown reason, the timer4 will be expired. Then timer4 interrupt will be asserted. A ServiceFiq in figure 5 will be invoked because the timer4 interrupt is FIQ interrupt. The SYSCLK (system clock) is changed to EXTCLK from FOUT and software reset is issued in the FIQ service routine. Finally, the S3C2413X01 will be reset. The reason why FIQ is used for the timer4 interrupt, FIQ will not be blocked by any exception such as IRQ, Abort, Undefined, and SWI. We recommend that the FIQ service routine, ServiceFiq should reside in a NOR Flash to avoid SDRAM corruption. ServiceFiq PROC ; FIQ Service Routine ldr r0, =CLKSRC ; Change Clock ;source to External Clock mov r1, #0x0 str r1, [r0] ldr r0 =SWRSTCON ; Issue Software Reset Figure 5 The implementation of ServiceFiq (FIQ Service Routine)

MMC/SD/SDIO CONTROLLER

SD Memory Card Spec(ver 1.0) / MMC Spec(2.11) compatible SDIO Card Spec(Ver 1.0) compatible 16 words(64 bytes) FIFO for data Tx/Rx 40-bit Command Register 136-bit Response Register 8-bit Prescaler logic(Freq = System Clock / (P + 1)) Normal, and DMA data transfer mode(byte, halfword, word transfer) DMA burst4 access support(only word transfer) 1-bit / 4-bit(wide bus) mode & block / stream mode switch support

- Type A : (Access by Word) D[7:0] (Access by Halfword) D[7:0]
D[15:8] D[23:16] D[31:24] D[15:8]
- Type B : (Access by Word) D[31:24] D[23:16] D[15:8] D[7:0] (Access by Halfword) D[15:8] D[7:0]
SDI Baud Rate Prescaler Register(SDIPRE) Register SDIPRE Address 0x5A000004 R/W R/W Description SDI Buad Rate Prescaler Register Reset Value 0x01

SDIPRE Prescaler Value

Description Determines SDI clock(SDCLK) rate as above equation.

Initial Value 0x01

Baud rate = PCLK / (Prescaler value + 1) * Prescaler Value should be greater than zero. SDI Command Argument Register(SDICmdArg) Register SDICmdArg Address 0x5A000008 R/W R/W Description SDI Command Argument Register Reset Value 0x0

SDICmdArg CmdArg

Bit [31:0] Command Argument

Initial Value 0x00000000

SDI Command Control Register(SDICmdCon) Register SDICmdCon Address 0x5A00000C R/W R/W Description SDI Command Control Register Reset Value 0x0
SDICommand Reserved Abort Command (AbortCmd) Command with Data (WithData) LongRsp
Bit [31:13] [12] [11] [10]
Description Determines whether command type is for abort(for SDIO). 0 = normal command, 0 = without data, 1 = abort command(CMD12, CMD52) Determines whether command type is with data(for SDIO). 1 = with data Determines whether host receives a 136-bit long response or not 0 = short response, 1 = long response Determines whether host waits for a response or not 0 = no response, 1 = wait response Determines whether command operation starts or not. This bit is automatically clear 0 = command ready, 1 = command start Command index with start 2bit(8bit)

Initial Value 0

WaitRsp Command Start(CMST) CmdIndex
SDI Command Status Register(SDICmdSta) Register SDICmdSta Address 0x5A000010 R/W R/(C) Description SDI Command Status Register Reset Value 0x0
SDICmdSta Reserved Response CRC Fail(RspCrc) Command Sent (CmdSent) Command Time Out (CmdTout) Response Receive End (RspFin) CMD line progress On (CmdOn) RspIndex
Bit [31:13] [12] R/C [11] R/C [10] R/C [9] R/C [8] [7:0]
Description CRC check failed when command response received. This flag is cleared by setting to one this bit. 0 = not detect, 1 = crc fail Command sent(not concerned with response). This flag is cleared by setting to one this bit. 0 = not detect, 1 = command end Command response timeout(64clk). This flag is cleared by setting to one this bit. 0 = not detect, 1 = timeout Command response received. This flag is cleared by setting to one this bit. 0 = not detect, 0 = not detect, 1 = response end Command transfer in progress 1 = in progress Response index 6bit with start 2bit(8bit)

0 0x00

SDI Response Register 0(SDIRSP0) Register SDIRSP0 Address 0x5A000014 R/W R Description SDI Response Register 0 Reset Value 0x0

SDIRSP0 Response0

Description Card status[31:0](short), card status[127:96](long)
SDI Response Register 1(SDIRSP1) Register SDIRSP1 Address 0x5A000018 R/W R Description SDI Response Register 1 Reset Value 0x0

SDIRSP1 RCRC7 Response1

Bit [31:24] [23:0]
Description CRC7(with end bit, short), card status[95:88](long) unused(short), card status[87:64](long)
Initial Value 0x00 0x000000
SDI Response Register 2(SDIRSP2) Register SDIRSP2 Address 0x5A00001C R/W R Description SDI Response Register 2 Reset Value 0x0

SDIRSP2 Response2

Description unused(short), card status[63:32](long)
SDI Response Register 3(SDIRSP3) Register SDIRSP3 Address 0x5A000020 R/W R Description SDI Response Register 3 Reset Value 0x0

SDIRSP3 Response3

Description unused(short), card status[31:0](long)
SDI Data / Busy Timer Register(SDIDTimer) Register SDIDTimer Address 0x5A000024 R/W R/W Description SDI Data / Busy Timer Register Reset Value 0x0
SDIDTimer Reserved DataTimer

Bit [31:23] [22:0]

Description Data / Busy timeout period

Initial Value 0x10000

SDI Block Size Register(SDIBSize) Register SDIBSize Address 0x5A000028 R/W R/W Description SDI Block Size Register Reset Value 0x0

SDIBSize Reserved

Bit [31:12]

Initial Value 0x000

BlkSize [11:0] Block Size value(0~4095 byte) , dont care when stream mode * In Case of multi block, BlkSize must be aligned to word(4byte) size.(BlkSize[1:0] = 00)
SDI Data Control Register(SDIDatCon) Register SDIDatCon SDIDatCon Reserved Burst4 enable (Burst4) Data Size (DataSize) Address 0x5A00002C Bit [31:25] [24] Enable Burst4 mode in DMA mode. This bit should be set only when Data Size is word. 0 = disable, 1 = Burst4 enable Indicates the size of the transfer with FIFO, which is typically byte, halfword or word. 00 = Byte transfer, 01 = Halfword transfer 10 = Word transfer, 11 = reserved Determines whether SDIO Interrupt period is 2 cycle or extend more cycle when last data block is transferred(for SDIO). 0 = exactly 2 cycle, 1 = more cycle(likely single block) Determines when data transmit start after response receive or not 0 = directly after DatMode set, 1 = after response receive(assume DatMode sets to 2b11) Determines when data receive start after command sent or not 0 = directly after DatMode set, 1 = after command sent (assume DatMode sets to 2b10) Determines when busy receive start after command sent or not 0 = directly after DatMode set, 1 = after command sent (assume DatMode sets to 2b01) Data transfer mode 0 = stream data transfer, 1 = block data transfer R/W R/W Description SDI Data control Register Description Reset Value 0x0 Initial Value

atadev_irq_al dma_dir

Device interrupt signal level 0: active high DMA transfer direction 0 : Host read data from device 1 : Host write data to device 1: active low

ata_class

ATA transfer class select 00 : transfer class is PIO 01 : transfer class is PIO DMA

ata_iordy_en

Determines whether IORDY input can extend data transfer. 0 : IORDY disable( ignored ) 1 : IORDY enable ( can extend )

ata_rst

ATA device reset by this host. 0 : no reset 1 : reset
ATA_PIO_TIME Register ATA_PIO_TIME Address 0x4B80002C R/W R/W Description ATA_PIO_TIME register Reset Value 0x0001_C238
BANKCFG Reserved pio_teoc pio_t2 pio_t1
Bit [31:20] [19:12] [11:4] [3:0] Reserved bits
Description PIO timing parameter, teoc, end of cycle time It shall not have zero value. PIO timing parameter, t2, DIOR/Wn pulse width It shall not have zero value. PIO timing parameter, t1, address valid to DIOR/Wn

Initial State 0x23 0x08

ATA_XFR_NUM Register ATA_XFR_NUM Address 0x4B800034 R/W R/W Description ATA_XFR_NUM register Reset Value 0x0000_0000

BANKCFG xfr_num Reserved

Bit [31:1] [0] Data transfer number. Reserved bits
ATA_XFR_CNT Register ATA_XFR_CNT Address 0x4B800038 R/W R/W Description ATA_XFR_CNT register Reset Value 0x0000_0000

BANKCFG xfr_cnt

Bit [31:1]
Description Current remaining transfer counter. This value counts down from ATA_XFR_NUM. It goes to zero when pre-defined all data has been transferred. Reserved bits
ATA_TBUF_START Register ATA_TBUF_ START Address 0x4B80003C R/W R/W Description ATA_TBUF_START register Reset Value 0x0000_0000
BANKCFG track_buffer_start Reserved
Bit [31:2] [1:0] Reserved bits
Description Start address of track buffer (4byte unit)
ATA_TBUF_SIZE Register ATA_TBUF_SIZE Address 0x4B800040 R/W R/W Description ATA_TBUF_SIZE register Reset Value 0x0000_0000
BANKCFG track_buffer_size Reserved
Bit [31:5] [4:0] Reserved bits

BANKCFG Reserved pio_dev_lhr
Description 8-bit PIO LBA high (command block) register
ATA_PIO_DVR Register ATA_PIO_DVR Address 0x4B80006C R/W R/W Description ATA_PIO_DVR register Reset Value 0x0000_0000
BANKCFG Reserved pio_dev_dvr
Description 8-bit PIO device (command block) register
ATA_PIO_CSD Register ATA_PIO_CSD Address 0x4B800070 R/W R/W Description ATA_PIO_CSD register Reset Value 0x0000_0000
BANKCFG Reserved pio_dev_csd
Description 8-bit PIO device command/status (command block) register
ATA_PIO_DAD Register ATA_PIO_DAD Address 0x4B800074 R/W R/W Description ATA_PIO_DAD register Reset Value 0x0000_0000
BANKCFG Reserved pio_dev_dad
Description 8-bit PIO device control/alternate status (control block) register
ATA_PIO_READY Register ATA_PIO_READY Address 0x4B800078 R/W R Description ATA_PIO_READY register Reset Value 0x0000_0000
BANKCFG Reserved dev_acc_ready
Bit [31:2] [1] Reserved bits
Description Indicates whether host can start access to device register 0 : not ready to start access ATA device register 1 : ready to start access ATA device register

pio_data_ready

Indicates whether data is valid in ATA_PIO_DATA register 0 : no valid data in ATA_PIO_DATA register 1 : valid data in ATA_PIO_DATA register
ATA_PIO_RDATA Register ATA_PIO_RDATA Address 0x4B80007C R/W R/W Description ATA_PIO_RDATA register Reset Value 0x0000_0000
BANKCFG Reserved pio_rdata
Bit [31:16] [15:0] Reserved bits
Description PIO read data register while HOST read from ATA device register
BUS_FIFO_STATUS Register BUS_FIFO_ STATUS Address 0x4B800090 R/W R Description BUS_FIFO_STATUS register Reset Value 0x0000_0000
BANKCFG Reserved bus_state
Bit [31:19] [18:16] Reserved bits 000 : IDLE 001 : BUSYW 010 : PREP 011 : BUSYR 100 : PAUSER 101 : PAUSEW
Reserved bus_fifo_rdpnt Reserved bus_fifo_wrpnt
[15:14] [13:8] [7:6] [5:0]
Reserved bits bus fifo read pointer Reserved bits bus fifo write pointer
ATA_FIFO_STATUS Register ATA_FIFO_ STATUS Address 0x4B800094 R/W R Description ATA_FIFO_STATUS register Reset Value 0x0000_0000
BANKCFG Reserved ata_state pio_state pdma_state Reserved Reserved
Bit [31] [30:28] [27:26] [25:24] [23:21] [20:0] Reserved bits
Description PIO read data register while HOST read from ATA device register 00 : IDLE 10 : T: IDLE 10 : T2 Reserved bits Reserved bits 01 : T: TEOC 01 : T: TEOC

ELECTRICAL DATA

Parameter DC Supply Voltage