1-1. GSM General Specification
EG SM 0 Pha s e 2 F r eq. B a n d [M Hz ] Up l in k / Do w n li n k A RF C N r a n g e 0 ~~~4 & 5 ~ D CS Pha s e 0 ~~2 ~5 PC S Ph a s e 1 1850~1910 1930~1960 512~810
T x /R x s p ac in g Mo d. B i t r at e/ Bi t Pe r i o d Ti me Sl o t P er io d / F r am e P er i o d Mo d u l a ti o n M S P o we r Po w er C l as s Se n si t iv i t y TDM A M u x C el l Ra d iu s O p er a ti n g T em p er a tu r e
MH z 0.3 k b p s 3.2 u s 6.9 u s 4. 5 ms 0. 3 GMS K d B m~5 d B m 5 p cl ~ p c l - 2 d Bm 8 35Km
MH z 0.3 k b p s 3.2 u s 6.9 u s 4. 5 ms 0. 3 GMS K d B m~0 d B m 0pcl ~ 15pcl - 0 d Bm 8 2Km - C ~ +C
M Hz 0.3 k b p s 3.2 u s 6.9 u s 4.5 m s 0.3 GM SK d B m~ 0 d B m 0pcl ~ 15pcl -100dBm Km
SAMSUNG Proprietary-Contents may change without notice
2-1. SGH-C210 RF Circuit Description

2-1-1. RX PART

ASM(F101) Switching Tx, Rx path for GSM900, DCS1800 and PCS1900 by logic controlling.
ASM Control Logic Truth Table VC1 EGSM TX DCS/PCS TX PCS_RX H L L VC2 L H L VC3 L L H
Saw FILTER To convert Electromagnetic Field Wave to Acoustic Wave and then pass the specific frequency band. - GSM FILTER (F100) - DCS FILTER (F100) - PCS FILTER (F102) Crystal (X101) To generate the 26MHz reference clock to drive the logic and RF. After additional process, the reference clock applies to the U801 Rx IQ demodulator and Tx IQ modulator. The oscillator for RX IQ demodulator and Tx modulator are controlled by serial data to select channel and use fast lock mode for GPRS high class operation. Si4210 (U102) The receive section integrates four differential-input low noise amplifiers LNAs supporting the GSM850, EGSM900, DCS1800 and PCS1900 bands. The LNA inputs are matched to the 150 ohm balanced-output SAW filters through externa LC matching network. A quadrature Image-reject mixer downconverts the RF signal to a 200 KHz intermediate frequency(IF). The mixer output is amplified with an analog programmable gain amplifier(PGA) that is controlled with the AGAIN. The quadrature IF is digitized with high resolution analog-to-digital converts (ADC). The ADC output is downconverted to baseband with a digital quadrature LO signal. Digital decimation and FIR filters perform digital filtering and remove ADC quantization noise, blockers and reference interferers. After filtering, the digital output is scaled with a digital PGA, which is controlled with the DGAIN. DACs drive a differential I and Q analog signal onto the BIP, BIN, BQP and BQN pins to interface to standard analog-input baseband ICs. For filtering the frequency band between 925 and 960 MHz. For filtering the frequency band between 1805 and 1880 MHz For filtering the frequency band between 1930 and 1990 MHz.

2-1-2. TX PART

Baseband IQ signal fed into offset PLL, this function is included inside of U801 chip. The transmit section of U801 consist of an I/Q baseband upconverter, an offset phase-locked loop (OPLL) and two 50 ohm output buffers that can drive an external Power Amplifier(PA). Si4210 chip generates modulator signal which power level is about 1.5dBm and fed into Power Amplifier(U900). The PA output power and power ramping are well controlled by Auto Power Control circuit. We use offset PLL below.
GSM 200kHz offset 30 kHz bandwidth DCS PCS GSM Modulation Spectrum 400kHz offset 30 kHz bandwidth DCS PCS GSM 600kHz ~ 1.8MHz offset 30 kHz bandwidth DCS PCS
-35dBc -35dBc -35dBc -66dBc -65dBc -66dBc -75dBc -68dBc -75dBc
2-2. Baseband Circuit description of SGH-C210

2-2-1. CSP2200B1

Power Management Seven low-dropout regulators designed specifically for GSM applications power the terminal and help ensure optimal system performance and long battery life. A programmable LDO provides support for 1.8V, 3.0V SIMs, while a selfresetting, electronically fused switch supplies power to external accessories. Ancillary support functions, such as two LED drivers and two call-alert drivers, aid in reducing both board area and system complexity. A four-wire serial interface unit(SIU) provides access to control and configuration registers. This interface gives a microprocessor full control of the CSP2200B1 and enables system designers to maximize both standby and talk times. Error reporting is provided via an interrupt signal and status register. Supervisory functions. including a reset generator, an input voltage monitor, and a thermal monitor, support reliable system design. These functions work together to ensure proper system behavior during start-up or in the event of a fault condition(low microprocessor voltage, insufficient battery energy, or excessive die temperature). Battery Charge Management A battery charge management block, incorporating an internal PMOS switch, and an 8-bit ADC, provides fast, efficient charging of single-cell Li-Ion battery. Used in conjunction with a current-limited voltage source, this block safely conditions near-dead cells and provides the option of having fast-charge and top-off controlled internally or by the system's microprocessor.

Backlight LED Driver The backlight LED driver is a low-side, programmable current source designed to control the brightness of the keyboard illumination. LED1_DRV is controlled via LED1_[0:2] and can be programmed to sink from 15mA to 60mA in 7.5mA steps. LED2_DRV is controlled via LED2_[0:2] and can be programmed to sink from 5mA to 40mA in 5mA steps. Both LED drivers are capable of sinking their maximum output current at a worst-case maximum output voltage of 0.6V. For efficient use, the LEDs is connected between the battery and the LED_DRV output. Vibrator Motor Driver The vibrator motor driver is a independent voltage regulator to drive a small dc motor that silently alerts the user of an incoming call. The driver is a 3.3V constant source while sinking up to 140mA and controlled by enable signal of main chip. For efficient use and safety, the vibrator motor should be connected between the regulator output and the ground.

2-2-2. Connector

JTAG Connector Trident has two JTAG ports which are for ARM core and DSP core(DSP16000). So this system has two port connector for these ports. Pins' initials for ARM core are 'CP_' and pins' initials for DSP core are 'DSP_'. CP_TDI and DSP_TDI signal are used for input of data. CP_TDO and DSP_TDO signals are used for the output of the data. CP_TCK and DSP_TCK signals are used for clock because JTAG communication is a synchronous. CP_TMS and DSP_TMS signals are test mode signals. The difference between these is the RESET_INT signal which is for ARM core RESET.
Keypad connector This is consisted of key interface pins in the trident, KEY_ROW[0~4] and KEY_COL[0~4]. These signals compose the matrix. Result of matrix informs the key status to key interface in the trident. Some pins are connected to varistor for ESD protection. And power on/off key is seperated from the matrix. So power on/off signal is connected with CSP2200 to enable CSP2200. Nine key LED use the +VBATT supply voltage. These are connected to BACKLIGHT signal in the CSP2200. This signal enables LEDs with current control.
EMI Filtering This system uses the EMI Filter to reduce noise from LCD part. Some control signals are connected to LCD without EMI filtering.

2-2-3. IF connetor

It is 24-pin connector, and separated into two parts. One is a power supply part for main system. And the other is designed to use SDS, DEBUG, DLC-DETECT, JIG_ON, VEXT, VTEST, VF, and GND. They connected to power supply IC, microprocessor and signal processor IC.

2-2-4. Audio

AOUTAP, AOUTAN from CSP2200 is connected to the speaker via analog switch. AOUTBP and AOUTBN are connected to the ear-mic speaker via ear-jack. MICIN and MICOUT are connected to the main MIC. And AUXIN and AUXOUT are connected to the Ear-mic. YMU762MA3 is a LSI for portable telephone that is capable of playing high quality music by utilizing FM synthesizer and ADPCM decorder that are included in this device. As a synthesis, YMU762MA3 is equipped 16 voices with different tones. Since the device is capable of simultaneously generating up to synchronous with the play of the FM synthesizer, various sampled voices can be used as sound effects. Since the play data of YMU762MA3 are interpreted at anytime through FIFO, the length of the data(playing period) is not limited, so the device can flexibly support application such as incoming call melody music distribution service. The hardware sequencer built in this device allows playing of the complex music without giving excessive load to the CPU of the portable telephones. Moreover, the registers of the FM synthesizer can be operated directly for real time sound generation, allowing, for example, utilization of various sound effects when using the game software installed in the portable telephone. YMU762 includes a speaker amplifier with high ripple removal rate whose maximum output is 550mW (SPVDD=3.6V). The device is also equipped with conventional function including a vibartor and a circuit for controlling LEDs synchornous with music. For the headphone, it is provided with a stereophonic output terminal. For the purpose of enabling YMU762MA3 to demonstrate its full capabilities, Yamaha purpose to use "SMAF:Synthetic music Mobile Application Format" as a data distribution format that is compatible with multimedia. Since the SMAF takes a structure that sets importance on the synchronization between sound and images, various contents can be written into it including incoming call melody with words that can be used for training karaoke, and commercial channel that combines texts, images and sounds, and others. The hardware sequencer of YMU762MA3 directly interprets and plays blocks relevant to synthesis (playing music and reproducing ADPCM with FM synthesizer) that are included in data distributed in SMAF.

2-2-5. Memory

This system uses SHARP's memory, LRS18B0. It is consisted of 256M bits flash memory and 64M bits SCRAM. It has 16 bit data line, D[0~15] which is connected to trident, LCD or CSP2200. It has 23 bit address lines, A[1~23]. They are also connected. CP_CSROMEN signal, chip select signal in the trident, enable flash memories. They use supply voltages, VCCD and VCC_1.8A. During wrting process, CP_WEN is low and it enables writing process to flash memory and SCRAM. During reading process, CP_OEN is low and it output information which is located at the address from the trident in the flash memory or SCRAM to data lines. Each chip select signals in the trident select flash memory or SCRAM. Reading or writing procedure is processed after CP_WEN or CP_OEN is enabled. Memories use FLASH_RESET, which is buffered signal of RESET from CSP2200, for ESD protection. A[0] signal enables lower byte of SCRAM and UPPER_BYTE signal enables higher byte of SCRAM.

2-2-6. Trident

Trident is consisted of ARM core and DSP core. It has 20K*16bits RAM 144K*16bits ROM in the DSP. It has 4K*32bits ROM and 2K*32bits RAM in the ARM core. DSP is consisted of timer, one bit input/output unit(BIO), JTAG, EMI and HDS(Hardware Development System). ARM core is consisted of EMI, PIC(Programmable Interrupt Controller), reset/power/clock unit, DMA controller, TIC(Test Interface Controller), peripheral bridge, PPI, SSI(Synchronous Serial Interface), ACCs(Asynchronous communications controllers), timer, ADC, RTC(Real-Time Clock) and keyboard interface. DSP_AB[0~8], address lines of DSP core and DSP_DB[0~15], data lines of DSP core are connected to CSP2200. A[0~20], address lines of ARM core and D[0~15], data lines of ARM core are connected to memory, LCD and YMU762. ICP(Interprocessor Communication Port) controls the communication between ARM core and DSP core. CSROMEN, CSRAMEN and CS1N to CS4N in the ARM core are connected to each memory. WEN and OEN control the process of memory. External IRQ(Interrupt ReQuest) signals from each units, such as, YMU, Ear-jack, Ear-mic and CSP1093, need the compatible process. Some PPI pins has many special functions. CP_KB[0~9] receive the status from key FPCB and are used for the communications using data link cable(DEBUG_DTR/RTS/TXD/RXD/CTS/DSR). And UP_CS/SCLK/SDI, control signals for CSP2200 are outputted through PPI pins. It has signal port for charging(CHG_DET), SIM_RESET and FLIP_SNS with which we knows open.closed status of folder. It has JTAG control pins(TDI/TDO/TCK) for ARM core and DSP core. It recieves 13MHz clock in CKI pin from external TCXO and receives 32.768KHz clock from X1RTC. ADC(Analog to Digital Convertor) part receives the status of temperature, battery type and battery voltage. And control signals(DSP_INT, DSP_IO and DSP_RWN) for DSP core are used. It enables main LCD with DSP IP pins.

2-2-7. CSP2200

CSP2200 is integrated the timing and control functions for GSM 2+ mobile application with the ADC and DAC functions, and power management block. The CSP2200 interfaces to the trident, via a 16-bit parallel interface. It serves as the interface that connects a DSP to the RF circuitry in a GSM 2+ mobile telephone. DSP can load 148 bits of burst data into CSP2200 s internal register, and program CSP2200 s event timing and control register with the exact time to send the burst. When the timing portion of the event timing and control register matches the internal quarter-bit counter and internal frame counter, the 148 bits in the internal register are GMSK modulated according to GSM 2+ standards. The resulting phase information is translated into I and Q differential output voltages that can be connected directly to an RF modulator at the TXOP and TXON pins. The DSP is notified when the transmission is completed. For receiving baseband data, a DSP can program CSP2200 s event timing and control register with the exact time to start receiving I and Q samples through TXIP and TXIN pins. When that time is reached, the control portion of the event timing and control register will start the baseband receive section converting I and Q sample pairs. The samples are stored in a double-buffered register until the register contains 32 sample pairs. CSP2200 then notifies the DSP which has sample time to read the information out before the next 32 sample pairs are stored. The voice band ADC converter issues an interrupt to the DSP whenever it finishes converting a 16-bit PCM word. The DSP then reads the new input sample and simultaneously loads the voice band output DAC converter with a new PCM output word. The voice band output can be connected directly to a speaker via AOUTAN and AOUTAP pins and be connected to a Ear-mic speaker via AOUTBN and AOUTBP pins. There are 7 LDOs which are power sources of microprocessor, LCD, etc. These 7 LDOs output are programmable.

3-1. Exploded View

QSP01 QMO01 QMP01 QLC01 QME01 QMI01

QRE01 QRF01 QCR31

3-2. Parts List

Location NO.

QFR01 QKP01 QSP01 QMO01 QMP01 QLC01 QME01 QMI01 QAN01 QRE01 QRF01 QCR31 QBA01 KEYPAD SPEAKER MOTOR DC PBA MAIN LCD UNIT METAL DOME MICROPHONE ASSY INTENNA REAR COVER TAPE PC RF SCREW BATTERY

Description

FRONT COVER

SEC CODE

GH75-06802A GH75-06998A 3001-001760 GH31-00163A GH92-02142A GH07-00701A GH59-02090A GH30-00186A GH42-00552A GH75-06804A GH74-14175A 6001-001795 GH43-01817A

Remark

3-3. Test Jig (GH80-00865A)
3-3-1. RF Test Cable (GH39-00283A)
3-3-2. Test Cable (GH39-00127A)

3-3-3. Serial Cable

3-3-4. Power Supply Cable
3-3-5. DATA CABLE (GH39-00143B)

3-3-6. TA (GH44-00184A)

5-1. RF Solution Block Diagram
5-2. Base Band Solution Block Diagram
6-1. Main PCB Top Diagram
6-2. Main PCB Bottom Diagram

7-1. Power On

7-2. Initial

7-3. SIM Part

7-4. Charging Part

R301 C302

C301 C303 C304
CNG GG G 0 C306 C307 C308 C309
AUX_ADC3 D13 GNDS1 F7 GNDS2 F8 GNDS3 F9 GNDS4 F10 GNDS5 G7 GNDS6 G8 GNDS7 G9 GNDS8 G10 GNDS9 H6 GNDS10 H7 GNDS11 H8 GNDS12 H9 GNDS13 J7 GNDS14 J8 GNDS15 J9 GNDS16 J10 GNDS17 K10 NCNC6 2
C10 B13 E8 B15 K15 F11 J3 M3 N6 N5 J4 G5 K4 R2 P6 N11 M10 A6 F6 L11 P13 C4 B4 VDD5 VDD67 GNDQ GND_PSC1 GND_PSC2 GND_HCUR VDD1 VDD2 VDD3 VDD_IO1 VDD_IO2 VSS1 VSS2 VSS3 VSS4 VDDD GNDD VDDB GNDB VDDV GNDV VDD_OCTL GND_OCTL
DSP_DB(0:15) DSP_DB(15) DSP_DB(14) DSP_DB(13) DSP_DB(12) DSP_DB(11) DSP_DB(10) DSP_DB(9) DSP_DB(8) DSP_DB(7) DSP_DB(6) DSP_DB(5) DSP_DB(4) DSP_DB(3) DSP_DB(2) DSP_DB(1) DSP_DB(0) DSP_AB(8) DSP_AB(7) DSP_AB(6) DSP_AB(5) DSP_AB(4) DSP_AB(3) DSP_AB(2) DSP_AB(1) DSP_AB(0) D2 D3 E3 E2 F3 F2 F1 F4 G4 G3 H5 J6 J5 K3 K2 K1 K5 K7 M1 M2 N2 N1 L5 P1 K6 L3 L2 R3 E6 C5 F5 E5 A4 G6 B3 A3 B1 A2 C1 C2
VDD34 C11 VDD12 J13 C305 UP_CLK UP_RST UP_IO SIM_IO SIM_RST SIM_CLK VSIM VRTC LED2_DRV LED1_DRV RING_DRV VIB_DRV VLDO_7 VLDO_6 VL5S_B VL5S_A VLDO_5 VL4S_B VL4S_A VLDO_4 VLDO_3 VLDO_2 VLDO_1 VACC CSN_PSC SCLK_PSC SDO_PSC SDI_PSC VEXT VBAT CH_BDRV CH_ISEN CH_RES ADC_AUX2 ADC_AUX1 VREF CREF RTC_ALMN N9 R10 P10 J11 K11 K14 K12 H11 G12 G13 F13 F15 C12 A14 C9 D10 B10 B11 A12 B12 A13 J12 G11 F14 K8 L8 N7 M7 E14 E13 E11 F12 D14 R305 D15 E10 A10 E9 H10 R306 VREF TP305 SIMCLK SIMRST SIMDATA

DSP_AB(0:8)

DSP_IO DSP_RWN FLASH_RESET