GPRS/EDGE TELEPHONE

SGH-D500 SGH-D500E
GPRS/EDGE TELEPHONE 1. 2. 3. 4. 5. 6. 7.
CONTENTS Specification Circuit Description Exploded Views and Parts List Electrical Parts List Block Diagrams PCB Diagrams Flow Chart of Troubleshooting
This Service Manual is a property of Samsung Electronics Co.,Ltd. Any unauthorized use of Manual can be punished under applicable International and/or domestic law.
Samsung Electronics Co.,Ltd. Dec. 2004 Printed in South Korea.
Code No.: GH68-05955A BASIC.
1. GSM General Specification
GS M0 Ph a se 1 F r eq. B a n d [M Hz ] Up l in k / Do w n li n k A RF C N r a n g e 0 ~~~4 E GS M 0 Ph a se ~~0 0~124 & 5 ~MHz 0.3 k b p s 3.2 u s 6.9 u s 4.5 m s 0.3 G MS K d Bm ~5 d B m 5pcl ~ 19pcl - 2 d Bm 5 Km DC S P h as e 0 ~~2 ~5 PC S~~2 ~0 MH z 0.3 k b p s 3.2 u s 6.9 u s 4.5 ms 0.3 GM SK d B m~0 d B m 0pcl ~ 15pcl -100dBm 8 -
T x /R x s p ac in g Mod. Bit rate / Bi t Pe r i o d Ti me Sl o t Pe r i o d / F r am e P er io d Mo d u l a ti o n M S P o we r Po w er C l as s Se n si t iv i t y TDM A M u x C el l Ra d iu s
MHz 270.833kbps 3.692us 576.9us 4.5 m s 0.3 G MS K d Bm ~5 d B m 5 p cl ~ p c l -102dBm 5 Km
M Hz 270.833kbps 3.692us 576.9us 4.5 m s 0.3 GM SK d B m ~0 d B m 0pcl ~ 15pcl -100dBm Km
SAMSUNG Proprietary-Contents may change without notice

2. GSM TX power class

TX Power control level

GSM900

DCS1800

PCS1900

8 4dBm
1. SGH-D500,SGH-D500E RF Circuit Description

1) RX PART

1. ANTENNA SWITCH (U100 SWICHPLEXER) Switching Tx, Rx path for GSM900, DCS1800 and PCS1900 by logic controlling. 2. ANTENNA SWITCH Control Losic (U100) VC1 Tx Mode (GSM900) Tx Mode (DCS1800/1900) Rx Mode (GSM900) Rx Mode (DCS1800) Rx Mode (PCS1900) L L(H) L L H Truth Table VC2 H L L L L VC3 L H L L L
3. FILTER To convert Electromagnetic Field Wave to Acoustic Wave and then pass the specific frequency band. - GSM FILTER (F100) - DCS FILTER (F102) - PCS FILTER (F101) 4. VC-TCXO (U101) This module generates the 26MHz reference clock to drive the logic and RF. It is turned on when the supply voltage Vcc(SYN) is applied. After buffering a reference clock of 26MHz is supplied to the other parts of the system through the transceiver pin CLKOUT. 5. TRANSCEIVER (U102) This chip is fully integrated GSM GPRS quad-band transceiver with transmit baluns, loop filters and most of the passive component in it. And also fully integrated fractional N RF synthesizer with AFC control possibility, RF VCO with integrated supply regulator. Semi integrated reference oscillator with integrated supply regulator. RF Receiver front-end amplifies the E-GSM900, DCS1800 and PCS1900 aerial signal, convert the chosen channel down to a low IF of 100kHz. In IF section, further amplifies the wanted channel output level to the desired value and rejects DC. For filtering the frequency band between 925 and 960 MHz For filtering the frequency band between 1805 and 1880 MHz. For filtering the frequency band between 1930 and 1990 MHz.

2) TX PART

The transmitter is fully differential using a direct up conversion architecture. It consists of a signal side band power up mixer. Gain is controlled by 6 dB via 3-wire serial bus programing. The fully integrated VCO and power mixer achieve LO suppression, quadrature phase error, quadrature amplitude balance and low noise floor specification. Output matching/balun components drive a standard 50 ohms single ended load.
2. Baseband Circuit description of SGH-D500,SGH-D500E
1. PCF50603 (U400) 1.1. Power Management Eight low-dropout regulators designed specifically for GSM applications power the terminal and help ensure optimal system performance and long battery life. A programmable boost converter provides support for 1.8V, 3.0V SIMs, while a self-resetting, electronically fused switch supplies power to external accessories. Ancillary support functions, such as RTC module and High Voltage Charge pump, Clock generator, aid in reducing both board area and system complexity. I2C BUS serial interface provides access to control and configuration registers. This interface gives a microprocessor full control of the PCF50603 and enables system designers to maximize both standby and talk times. Supervisory functions. including a reset generator, an input voltage monitor, and a temperature sensor, support reliable system design. These functions work together to ensure proper system behavior during start-up or in the event of a fault condition(low microprocessor voltage, insufficient battery energy, or excessive die temperature). 1.2. Backlight Brightness Modulator The Backlight Brightness Modulator (BBM) contains a programmable Pulse-width modulator (PWM) and FET to modulate the intensity of a series of LEDs or to control a DC/DC converter that drives LCD backlight. This phone (SGH-D500,SGH-D500E) use PWM control to contrast the backlight brightness. 1.3. Clock Generator The Clock Generator (CG) generates all clocks for internal and external usage. The 32.768 kHz crystal oscillator provides an accurate low clock frequency for the PCF50603 and other circuitry. 2. LCD Connector LCD is consisted of main LCD(color 26K TFT LCD). Chip select signals in the U305, LCD_CS, can enable LCD. BACKLIGHT signal enables white LED of main LCD. These signal is from U400. 16-bit data lines(LD(0)~LD(15)) transfers data and commands to LCD. Data and commands use "RS" signal. If this signal is high, Inputs to LCD are commands. If it is low, Inputs to LCD are data. The signal which informs the input or output state to LCD, is required. But this system is not necessary this signal. So "L_WR" signal is used to write data or commands to LCD. Power signals for LCD are "VDD_IO_HIGH". 3. IRDA This system uses IRDA module, HSDL_3209, Agilent's. This has signals, "IRDA_EN"(enable signal), "IRDA_RXD"(input data) and "IRDA_TXD"(output data). These signals are connected to PCF5213EL1 through BT Module.

4. Key This is consisted of key interface pins KEY_ROW(0:4) and KEY_COL(0:4) in PCF5213EL1. These signals compose the matrix. Result of matrix informs the key status to key interface in the PCF5213EL1. Power on/off key is seperated from the matrix. So power on/off signal is connected with PCF50603 to enable PCF50603. Key LED is consisted of LEDs for sub key and twelve white LEDs for main key. White LED for sub key use the VBAT voltage. "SLIDER_KEY_ON" signal enables Transistor for sub key backlight. Main key LED use the 3.3V LDO for a supply voltage. KEY_LED_ON signal enables eight white LED. "FLIP" informs the status of slide (open or closed) to the PCF5213EL1. This uses the hall effect IC, A3212ELH. A magnet under LCD enables A3212ELH. 5. EMI ESD Filter This system uses the EMI ESD filter, U500 to protect noise from IF CONNECTOR part. 6. IF connetor It is 18-pin connector. They are designed to use VBAT, V_EXT_CHARGE, USB_D+, +VBUS, USB_D-, TXD1, RXD1, AUX_ON, EXT1, EXT2, HFK_SPK, HFK_MIC and GND. They connected to power supply IC, microprocessor and signal processor IC. 7. Battery Charge Management A complete constant-current/constant-voltage linear charger for single cell lithium-ion batteries. If TA connected to phone, "V_EXT_CHARGE" enable charger IC and supply current to battery. When fault condition caused, "CHG_ON" signal level change low to high and charger IC stop charging process. 8. Audio HFR_P and HFR_N from PCF5213El1 are connected to the main speaker via analog switches. MIC_P and MIC_N are connected to the main MIC as well. EAR1 is the source of External Speaker. YMU765 is a synthesizer LSI for mobile phones. This LSI has a built-in speaker amplifier for outputting sounds that are used by mobile phones in addition to game sounds and ringing melodies that are replayed by a synthesizer. The synthesizer section adopts Table voices. It provides simultaneous generation of up to 64 tones by stereophonic hybrid synthesizer. YMU765 has built a speaker amplifier of which maximum out is 580 mW at SPVDD=3.6V in this device. There is Stereophonic analog output for Headphone. 9. Memory This system uses Samsung's memory, KBJ10KB00M. The KBJ10KB00M is a Multi Chip Package Memory which combines 256Mbit Synchronous Burst Multi Bank NOR Flash Memory and two 512Mbit OneNAND Flash and 128Mbit Synchronous Burst U tRAM. It has 16 bit data line, HD[1~16] which is connected to PCF5213 and MV319, also has 24 bit address lines, HA[1~24]. There are 3 chip select signals, CS0n_FLASH, CS4n_NAND, and CS1n_RAM. In the Wrting process, WEn is fallen to low and it enables writing process to operate. During reading process, OEn is fallen to low and it enables reading process to operate. Each chip select signals in the PCF5213 choose different memories. stereophonic hybrid synthesizer system that are given advantages of both FM synthesizers and Wave Table synthesizers to allow simultaneous generation of up to 32 FM voices and 32 Wave six white

10. PCF5213EL1 The PCF5213EL1 is mainly composed of embeded DSP and ARM core. The DSP subsystem includes the Saturn DSP core with embedded RAM and ROM, and a set of peripherals. It has 24kx16 bits PRAM, 104k*16 bits, 32k*16 XYRAM and 63k*16 XYROM in the DSP. The ARM946E-S consists of an ARM9E-S processor core, 8 kbyte instruction cache and 8 kbyte data cache, tghtly-coupled ITCM(Instruction Tightly Coupled Memory) and DTCM(Data Tightly Coupled Memory) memories, a memory protection unit, and an AMBA(Advanced Microcontroller Bus Architecture) AHB(Advanced High-performance Bus) bus interface with a write buffer. HD(0:15), data lines and HA(0:23), address lines are connected to KBJ10KB00M (memory), MV319DNQ (image dsp) and YMU765 (melody IC). It has 64 kbyte SC RAM (0.5 Mbit) and 32 kbyte SC program ROM for bootstrap loader in the ARM core. HD(0:15), data lines and HA(0:23), address lines are connected to memory and YMU765 to communicate. MV319DNQ(Camera DSP Chip) controls the communication between ARM core and DSP core. OEn, WEn control the access of memory. KROW, and KCOL recognize the key string input status. The system communicates with IrDA via IrDA_TXD, IrDA_RXD. It has J-TAG control pins (TDI/TDO/TCK) for ARM and DSP core. J-SEL signal controls different access to ARM and DSP core. ADC(Analog to Digital Convertor) receives the condition of temperature, battery type and battery voltage. 11. TCO-5871U(26MHz) This system uses the 26MHz TCXO, TCO-5871U, Toyocom. AFC control signal form PCF5213 controls frequency from 26MHz x-tal. It generates the clock frequency. This clock is connected to PCF5213, YMU765 and UAA3587.
12. Camera DSP(MV319DNQ) MV319DNQ provides rich video functions up to 30-frame display with minimized tasks in the handset main processor as well as hardware based real-time JPEG compression and decompression. MV319DNQ directly transmits and previews the RGB data to the LCD graphic memory by processing the sensor output data according to the handset's command. It can save the raw RGB data up to VGA resoultion into its image buffer and allows the host processor to download with scalable sized compressed data. It utilizes 16 bit data bus for communication with the main processor, including bus interface types.

QKP02 QCA01 QSP01

QLC01 QME02
QPC01 QIF01 QCR08 QKP01 QCR16 QFL01 QMP01 QMI01 QME01

QCR11 QCR11

QSC18 QCR16

QCR11 QBA19

1. Power On

C405 100N F

ONKEYN C406 470nF

C407 9PF

OSC400 MC-146(32.768KHz,20ppm ) ML-414RM/F9M E 2 R403 10M C408 C428 100PF

C409 9PF

V400 VC040205X150R
C410 22U F F95OJ226MPAAQ2

C411 33PF

R+VDD_RX_TX

C413 4.7U F

R405 33nH +VCC_SYN
CHGCUR/BATMA X CHGDRV _ONKEY CPVBAT VSAVE OSCO REFC VBAT VCHG OSCI VINT
VDD_SLEE P C414 470nF R406 100K +VDD_IO_LOW

CPVD D

36 SCP SCN
C416 F 4.7U +VDD_IMAGE 22 C417 470nF 19 +AVDD C418 470nF 16 15
RF2VDD RF12VBAT RF1VDD D1VD D LPD1VBAT LPVD D HCVBAT
D3VDD 39 SIMD3VBATSIMVCC 42 SIMIOCD
SIM_VCC SIM_IO SIM_CL K SIM_RST
+VDD_IO_HIGH +VDD_IO_HIGH

U400 PCF50603HN/11

43 SIMCKCD 44 _SIMRSCD SIMEN SCV_LED_ON

SIM4 G G G G 8 7

HCVDD GPO3 D2VD D GPO2 IOD2VBAT GPO1 GND GND GND GND NC NC 1

R409 11K

C419 5

C421 NC

C422 C

ENG-CD-292292-9-OLD 2

4.7U FN 100NF
14 IOVDD +AVDD_HFA 13 _REC 2
CLK32K PWREN 1 PWREN 2 _RSTH C _REC1
4 LCD_BL_ON R421 100K 2 U401 TC7SH08FU-TE85L BACKLIGHT 3

C424 4.7U F

_SIMRSH C

SIMIOHC

MICBIAS

SIMCKH C

12 R+VDD_IO_HIGH C425 4.7U F C426 470nF
AUX_ON SC L SDA 32KHz_DIGIT

R+VDD_IO_LOW

PON_TX REF_O N C427 470nF SIMRST SIMCL K

R413 510

MIC_BIAS

IT_PM U

2. Initial
+AVDD_HFA +VDD_IO_LO W +VDD_GSM_CORE +VDD_IO_HIGH +AVDD BB_PW R TP200 +VDD_IO_LOW +VDD_USB

BT_RST TXD 1

+AVDD C200 4.7UF
B10 D14 E10 E12 E18 J18 K8
U6 VDDB B B11 VDDC M4 VDDC M15 VDDC P12 VDDC R7 VDDC U10 VDDCLK
NC NC NC NC NC NC NC NC NC

R216 8.2K LCD_RESET

Q200 SI1012R 3D
32KHz_DIGIT LOUD_EN EXTSPK_EN

A14 L15 B16 V16 L14 B15

BBPW R

+VDD_IO_HIGH

+VDD_IO_LO W

RSTRTC

R10 VDDRE F V13 VDDV B GVDDVBO G5 BE3 N5 TXD 1
C2 VDDE 1 D6 VDDE 1 E9 VDDE 1 E14 VDDE 1 GVDDE 1 H2 VDDE 1 H9 VDDE 1 J12 VDDE 1 M9 VDDE 1
N2 VDDE 2 N4 VDDE 2 T17 VDDE 2 T18 VDDE 2 U2 VDDE 2 U11 VDDE 2

A13 VDDA2 A15 VDDRTC

H15 VDDE 3 H12 VDDE 4
CK I MCLKSEL XIN32K CLK32O GPIOB11 XOUT32K
M8 GPIOA11 M7 GPIOA1 P10 GPIOA2 L10 GPIOA10 H8 GPON 0 MGPON R13 RFSIG0 M12 RFSIG1 M11 RFSIG2 V5 GPIOA3 P9 GPIOA4 L11 GPIOA5 R11 RFSIG6 P11 RFSIG7 T2 GPIOA21 R2 GPIOA22 R5 GPIOA23 U18 RFCLK1 R17 RFDO1 G1 GPIOA9 V18 RFEN 0 RESET MCLK H1 TP206 TP207 TP208

B12 K14 M2 R12 U5 A12 D2 D7 D11 D12 E15 F15 G9 H10 J2 M10 P2 P4 P17 R18 U3 U12
PIPESTAT(0) PIPESTAT(1) PIPESTAT(2) TRCPKT(0) TRCPKT(1) TRCPKT(2) TRCPKT(3) TRCPKT(4) TRCPKT(5) TRCPKT(6) TRCPKT(7)

V6 H14 V9 P13 K17 U9 U13

KEY_COL(0:4)
VSSBB VSSVB VSSA4 VSSA5 VSSVBO VSSCLK VSSREF
KEY_ROW(0) KEY_ROW(1) KEY_ROW(2) KEY_ROW(3) KEY_ROW(4) KEY_COL(0) KEY_COL(1) KEY_COL(2) KEY_COL(3) KEY_COL(4)

USB Interface

HDP 0 HDP 1 HDP 2 HDP 3 HDP 4 HDP 5 HDP 6 HDP 7 HDP 8 HDP 9 HDP10 HDP11 HDP12 TMS TCK TDI TDO TRST RTCK JSEL
GNDC GNDC GNDC GNDC GNDC GNDE GNDE GNDE GNDE GNDE GNDE GNDE GNDE GNDE GNDE GNDE GNDE GNDE GNDE GNDE GNDE GNDE
RTCK +VDD_IO_LO W R210 4.7K R217 NC +VDD_GSM_CORE
PIPESTAT(0:2) TRCPKT(0:7) TRCSYN C TRCCLK

J_SE L

TP225 TP226 TP227 TP228 TP229 TP230 R212 0

TRSTn TDO TDI TCK TMS

3. Charging Part
R508 VBAT R506 100K,1% MES_BATT ZD500 UDZS5.1B +VDD_IO_HIGH U503 LT4068EDD-4. 2 R510 2K 1 ITERM 2 BAT END_OF_CHG 3 _CHRG 4 GND GG GG R513 2.7K 1% R514 1K,1% R512 4.7K,1% _EN 8 _ACPR 7 VCC 6 CHG_O N AUX_O N R507 62K,1% C501 330NF U5 4
S1/S2 VIN 1 T VOU GND ON/OFF 2 G1/GR520 100K

+VBUS USB_CHG_ON PEMD1 0

FDC6332L +VDD_IO_HIGH 6 E2 B2 C1 U506 R511 18K +VBUS C502 F951A106MPAAQ 2 C503 100NF V_EXT_CHARGE CR509 100K BE+VBU S USB_IN

PRO 5 G Q500 DTC144EM

+VDD_IO_HIGH R515 68K Q506 DTC144EM 1 USB_CHG_O N

BATTERY CHARGING

ZD501 UDZS8.2B

2 Q505 DTC144EM

4. Sim Part
OSC400 MC-146(32.768KHz,20ppm ) ML-414RM/F9M E 2 C408 C428 100PF R403 10M

C410 22UF F95OJ226MPAAQ2

CHGCUR/BATMA X CHGDRV _ONKEY CPVBAT VSAVE REFC OSCO VBAT VCHG OSCI VINT
C416 4.7U F +VDD_IMAGE 22 C417 470nF 19 +AVDD C418 470nF 16 15
RF2VDD RF12VBAT RF1VDD D1VD D LPD1VBAT LPVD D HCVBAT HCVDD
D3VDD SIMD3VBAT 41 SIMVCC 42 SIMIOCD
43 SIMCKCD 44 _SIMRSCD 45 SIMEN GPOSCV_LED_ON
D2VD D GPO2 IOD2VBAT GPO1

4.7UFN 100N F

SIMCKH C CLK32K PWREN 1 PWREN 2 _RSTH C _REC1
GND 49 GND 50 GND 51 GND 52 NC 53 NC 54 1
AUX_ON SC L SD A 32KHz_DIGIT

5. Microphone Part

MIC_BIA S MIC_BIAS Close to microphone R601 NC C100NF MIC_BIAS_B B Close to MCP C601 22UF 6.3V C602 NC
C600 U601 10PF 1 MIC_CP C606 1.8PF C27PF IN V+ GND DG2011 U4 C611 10PF MIC_BIA S 3 GND DG3 JACK_EN ZD600 GMF05C-HS 3 R621 100K R39K NC IN V+ NO COM NO COM NC 4

MIC600

MIC_P C68PF MIC_N R1K

C609 100NF

R603 12PF

C610 NC

MICROPHONE
LOUD_EN R+AVDD_HF A C628 5PF C18PF C619 47PF C5PF R608 100K C634 18PF R180K

10. Key Back Light 1) Main Key Part

2) Sub Key Part

U610 LMS5214IMG-3. VIN 4 VOUT C620 4.7U F R82 R82 RRRRR82 RRR626 82

VE N 1

N/C GND 2 3

KEY_LED_ON R627 100K

LED606 LED607 LED60 LED60
0 LED610 LED611 LED604 LED60 LED60 5

LED601

LED810

LED805

LED801

LED807

Q802 2SC5658T2LR R812 15K SLIDER_KEY_O N R829 R814 100K V803 VC040205X150R V802 VC040205X150R

LED806

LED808

KEY_LED

11. Camera part
CN802 AXK8L24115S NC NC 4 2

0 +VDD_IMAGE

FVALID LVALID Y(7) Y(6) Y(5) Y(4) Y(3) Y(2) Y(1) Y(0)
PCLK +VDD_IMAGE M_CL K M_SC L M_SD A
+VDD_IMAGE L802 100nH CIH05TR10JNC

S_RST_IMAGE C807 100U F

1M CAM
U305 M8 M5 L5 K2 J10 H9 F3 D3 C9 C8 B3 A7 F10 HD(0) HD(1) HD(2) HD(3) HD(4) HD(5) HD(6) HD(7) HD(8) HD(9) HD(10) HD(11) HD(12) HD(13) HD(14) HD(15) D2 E1 E2 E3 F1 F2 G1 G2 H1 H2 H3 J1 J2 J3 K1 K3 M4 B1 B2 C2 C4 C5 C7 D8 D10 E9 K5 K6 L6 M6 M7 Y(0) Y(1) Y(2) Y(3) Y(4) Y(5) Y(6) Y(7) A3 B4 A4 B5 A5 B6 A6 B7 DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS2 DVSS DVSS AVSS MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 STROBE/GPIO3 GPIO2 GPIO1 GPIO0 LRS LCS1 LCS2 LREN LWEN DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 M10 LD0 M9 LD1 L10 LD2 L9 LD3 L8 LD4 K10 LD5 K9 LD6 K8 LD7 K7 LD8 J9 LD9 J8 LD10 H8 LD11 G9 LD12 G8 LD13 F9 LD14 F8 LD15 MINT MWEN MREN MCS MA0 MA1 L2 M2 M1 L1 D1 C1 RLD(0) LD(1) LD(2) LD(3) LD(4) LD(5) LD(6) LD(7) LD(8) LD(9) LD(10) LD(11) LD(12) LD(13) LD(14) LD(15)

LD(0:15)

+VDD_IMAG E

HD(0:15)

R315 4.7K

R316 4.7K

IMAGE_INT WE n OEn CS3n_IMAG E HA(1 ) HA(2 ) 26M_DIGIT M_CLK PCLK LVALID FVALID M_SDA M_SCL
G10 CLKI H10 CLKO C10 SMCLK A8 PCLK A9 HREF B9 VSYNC A10 SDA B10 SCL M3 APPCLK A1 RESET MVDD L3 MVDD C3 RVDD G3 RVDD E8 LVDD K4 LVDD D9 SVDD B8 SVDD A2 CVDD L4 CVDD C6 CVDD L7 CVDD E10 NC NC 1 2
+VDD_IO_LOW IMAGE_RESET +VDD_IO_HIGH R321 100K