SMDK2443 Evaluation Board for S3C2443X

1. PCB Revision

Date 2006. 05. 29 2006. 08. 12 2006. 09. 19 2007. 06. 29
Description Preliminary Version Modified USB, CF, IIC circuit and etc. Modified USB, CF, GPIO, UART, SMC_CS circuits and added moviNAND Modified OneNAND, USB, LCD ,CAM

Rev Rev Rev Rev

0.0 0.1 0.2 1.0

2. Table of Contents

CPU Board Page Function 01 S3C2443-Memory/System 02 S3C2443-EINT/LCD/ADC/Camera 03 S3C2443-Power 04 Memory(mSDR&mDDR) 05 Memory(OneNand)/JTAG/CLK 06 Buffers(SROM I/F) 07 USB/HS_MMC/HS_SPI 08 CPU B/D Power1(ARM, INT) 09 CPU B/D Power2(Alive, I/O) 0A Board to Board Connector (CPU)

3. Part Reference

<Component><Number> U - COMPONENT IC & REGURATOR IC C - CAPACITOR CT- TANTAL CAPACITOR R - RESISTER RP - RESISTOR PACK VR - VARIABLE RESISTER J - JUMPER L - INDUCTOR F - FERRITE BEAD Y - OSCILLATOR X - CRYSTAL Q - TRANSISTOR/FET D - DIODE SW - TACT/PUSH SWITCH CON - CONNECTOR CFG - DIP SWITCH
Base Board 01 NOR/SRAM/NAND/Config 02 CF+/External Bus IF 03 Ethernet Controller 04 LCD:Landscape(640X480) 05 LCD:RGB/CPU/CSTN 06 LCD:STN_EXT/TSP/ADC 07 Camera IF/I2C 08 Audio Control/AC97/SDMMC 09 I2S/Audio IO 0A UART/IrDA/SPI 0B Base B/D Power & LED 0C Board to Board Connector (Base)

Ext. OneNand

RDATA[15:0] RDATA0 RDATA1 RDATA2 RDATA3 RDATA4 RDATA5 RDATA6 RDATA7 RDATA8 RDATA9 RDATA10 RDATA11 RDATA12 RDATA13 RDATA14 RDATA15
RADDR[25:0] RADDR0 RADDR1 RADDR2 RADDR3 RADDR4 RADDR5 RADDR6 RADDR7 RADDR8 RADDR9 RADDR10 RADDR11 RADDR12 RADDR13 RADDR14 RADDR15 RADDR16 RADDR17 RADDR18 RADDR19 RADDR20 RADDR21 RADDR22 RADDR23 RADDR24 RADDR25

R57 100K 5

<Silk>

SN74LVC1G17DBV 4

nBATT_FLT
2 C5 D6 B5 A5 B6 G8 A6 B7 C7 A7 B8 C8 A8 D8 B9 H9 A9 G9 C9 J10 B10 G10 A10 J11 C10 D10 J1 K8 K3 J7 K4 H1 J3 J4 H3 J8 H2 H7 G1 G3 G2 H4 SWRADDR0/GPA0 RADDR1 RADDR2 RADDR3 RADDR4 RADDR5 RADDR6 RADDR7 RADDR8 RADDR9 RADDR10 RADDR11 RADDR12 RADDR13 RADDR14 RADDR15 RADDR16/GPA1 RADDR17/GPA2 RADDR18/GPA3 RADDR19/GPA4 RADDR20/GPA5 RADDR21/GPA6 RADDR22/GPA7 RADDR23/GPA8 RADDR24/GPA9 RADDR25/GPA10 RDATA0 RDATA1 RDATA2 RDATA3 RDATA4 RDATA5 RDATA6 RDATA7 RDATA8 RDATA9 RDATA10 RDATA11 RDATA12 RDATA13 RDATA14 RDATA3

1 push

SADDR[12:0]
TP17 SADDRSADDR14 SADDR15
SADDR0 SADDR1 SADDR2 SADDR3 SADDR4 SADDR5 SADDR6 SADDR7 SADDR8 SADDR9 SADDR10 SADDR11 SADDR12 SADDR14 SADDR15 SDATA0 SDATA1 SDATA2 SDATA3 SDATA4 SDATA5 SDATA6 SDATA7 SDATA8 SDATA9 SDATA10 SDATA11 SDATA12 SDATA13 SDATA14 SDATA15 SDATA16 SDATA17 SDATA18 SDATA19 SDATA20 SDATA21 SDATA22 SDATA23 SDATA24 SDATA25 SDATA26 SDATA27 SDATA28 SDATA29 SDATA30 SDATA31
H14 A14 G13 D15 B13 A13 H13 D14 G12 B12 C12 A12 H12 D12 G11 D11 C18 D18 B18 B19 A20 D20 A21 A22 B20 B21 B22 C21 A23 B23 C23 D21 E22 D23 G20 E21 F20 E23 F23 G22 F21 G21 H21 H22 J17 H23 K15 J22
SADDR0 SADDR1 SADDR2 SADDR3 SADDR4 SADDR5 SADDR6 SADDR7 SADDR8 SADDR9 SADDR10 SADDR11 SADDR12 SADDR13 SADDR14 SADDR15

U16A S3C2443X

nBATT_FLT nRESET nRSTOUT PWR_EN

R20 P22 M16 R23

TP15 nXBACK 1
TP16 nXBREQ 1 nXBACK nXBREQ
nXBACK/GPB5 nXBREQ/GPB6 nXDACK1/GPB7 nXDREQ1/GPB8 nXDACK0/GPB9 nXDREQ0/GPB10

AC4 Y5 AC5 AA5 AB6 U8

nXDACK1 nXDREQ1 nXDACK0 nXDREQ0

TP18 CLKOUT0 1

TP19 CLKOUTCLKOUT0 CLKOUT1

SDATA[31:0]

RSMVAD/GPA24 RSMCLK RSMBWAIT/GPM0
B11 nWE_CF/GPA27 H11 nOE_CF/GPA11
FCLE/GPA17 FALE/GPA18 nFWE/GPA19 nFRE/GPA20 nFCE/GPA21 FRnB/GPM1

D17 nSCS1 H15 nSCS0

nSWE nSRAS nSCAS nSCLK

A15 SCKE A16 SCLK

DQS1 DQS0 DQM3 DQM2 DQM1 DQM0
SDATA0 SDATA1 SDATA2 SDATA3 SDATA4 SDATA5 SDATA6 SDATA7 SDATA8 SDATA9 SDATA10 SDATA11 SDATA12 SDATA13 SDATA14 SDATA15 SDATA16/GPK0 SDATA17/GPK1 SDATA18/GPK2 SDATA19/GPK3 SDATA20/GPK4 SDATA21/GPK5 SDATA22/GPK6 SDATA23/GPK7 SDATA24/GPL8 SDATA25/GPK9 SDATA26/GPK10 SDATA27/GPK11 SDATA28/GPK12 SDATA29/GPK13 SDATA30/GPK14 SDATA31/GPK15
CLKOUT0/GPH13 CLKOUT1/GPH14

AC9 AB10

OM0 OM1 OM2 OM3 OM4

V22 V23 W23 U17 Y20

C110 100nF
nRCS0 nRCS1/GPA12 nRCS2/GPA13 nRCS3/GPA14 nRCS4/GPA15 nRCS5/GPA16 nRBE0 nRBE1 nROE nRWE nWAIT
A2 A1 B3 C1 C4 E4 A4 D5 B4 A3 D2
nGCS0 nGCS1 nGCS2 nGCS3 nGCS4 nGCS5 nRBE0 nRBE1 nROE nRWE

VDD_RMOP

R119 100K
R58 4.7K nWAIT 4 SWpush 2
VCC nRESET nMR GND SRT 4 1

nRESET

MAX6412UK22

C111 100nF

B16 G14 C14 B15

B17 C17 G16 C16 H16 A17

F3 D3 G4 E1 F4 F2

C2 B2 B1

nOE_CF nWE_CF nSCS1 nSCS0 SCKE SCLK nSWE nSRAS nSCAS nSCLK

R59 4.7K

nFCE nFRE nFWE ALE CLE

R60 4.7K

RSMBWAIT RSMCLK RSMAVD
SAMSUNG ELECTRONICS CO.,LTD
Title SMDK2443 (S3C2443 Evaluation Board) Size A3 Date: Document Number S3C2443 (SROM_BUS/DRAM_BUS/SYSTEM) Monday, October 15, 2007 Sheet

Rev 1.of 11

LCDVF2 LCDVF1 LCDVF0 RGB_VDEN RGB_VSYNC RGB_HSYNC RGB_VCLK LEND SD0_nWP SD0_nCD SD0_LED SD0_CLK SD0_CMD SD0_DAT[7:0] SD0_DAT0 SD0_DAT1 SD0_DAT2 SD0_DAT3 SD0_DAT4 SD0_DAT5 SD0_DAT6 SD0_DAT7 VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 VD16 VD17 VD18 VD19 VD20 VD21 VD22 VD23 VD[23:0]
AC16 AA15 U15 AA16 R15 AB16 U16 AC17

AB15 R14 AA14 U14 AC15

SYS_OE/LCD_LEND/GPC0 RGB_VCLK/VEN_FIELD/SYS_WE/LCD_VCLK/GPC1 RGB_HSYNC/VEN_HSYNC/SYS_CS0/LCD_VLINE/GPC2 RGB_VSYNC/VEN_VSYNC/SYS_CS1/LCD_VFRAME/GPC3 RGB_VDEN/VEN_HREF/SYS_RS/LCD_VM/GPC4 LCDVF0/GPC5 LCDVF1/GPC6 LCDVF2/GPC7
SD0_DAT0/GPL0 SD0_DAT1/GPL1 SD0_DAT2/GPL2 SD0_DAT3/GPL3 SD0_DAT4/GPL4 SD0_DAT5/GPL5 SD0_DAT6/GPL6 SD0_DAT7/GPL7
SD0_CMD/GPL8 SD0_CLK/GPL9 SD0_LED/GPJ13 SD0_nCD/GPJ14 SD0_nWP/GPJ15
VD0/GPC8 VD1/GPC9 VD2/GPC10 VD3/GPC11 VD4/GPC12 VD5/GPC13 VD6/GPC14 VD7/GPC15 VD8/GPD0 VD9/GPD1 VD10/GPD2 VD11/GPD3 VD12/GPD4 VD13/GPD5 VD14/GPD6 VD15/GPD7 VD16/GPD8 VD17/GPD9 VD18/GPD10 VD19/GPD11 VD20/GPD12 VD21/GPD13 VD22/GPD14 VD23/GPD15
P2 P7 T1 P9 R3 T2 T3 R7 U1 R8 V1 T7 U3 T8 V2 V3 W1 W3 W2 Y3 Y4 AB1 AB2 AA2

N1 M9 R4 P3 N7 N8 P1 N9

SD1_DAT3 SD1_DAT2 SD1_DAT1 SD1_DAT0 SD1_CMD SD1_CLK

KBDINT

VBUS_DET
IICSDA IICSCL I2SSDO I2SSDI I2SSCLK I2SLRCK I2SCDCLK
Title SMDK2443 (S3C2443 Evaluation Board) Size A3 Date: Document Number S3C2443 (LCD/CAM/USB/UART/IIS/IIC/TIMER.) Monday, October 15, 2007 Sheet
E2 L4 W21 H17 C19 D16 A11 D7 Y13 Y15

U21 M17

N4 N2 R1 U2 Y2 AB4 Y7 Y8 Y10

J21 L22 K22 K21 J20

D4 E3 J9 D9 G7

VDD_RTC VDD_SD

VDD_RTC VDD_SD VDD_SD Y23

VDD_RTC

VDD_SD

VDD_CAM

VSS_SRAM VSS_SRAM VSS_SRAM VSS_SRAM VSS_SRAM
VSSIP_UDEV VSSA33C VSSA33T2 VSSA33T2 VSSA33T2
VSSIARM VSSIARM VSSIARM VSSIARM VSSIARM VSSIARM VSSIARM VSSIARM VSSIARM

VSSA_UPLL

VSSA_ADC

VSSALIVE VSSALIVE

VSSI VSSI VSSI VSSI VSSI VSSI VSSI VSSI VSSI VSSI

AA17 AC13

CT6 + 10uF

C44 100nF

CT7 + 10uF

CT8 + 10uF

C47 100nF
A18 J12 J13 J14 G15 D19 D22 F22 J16 AB17 R12 Y9 U7 M21 T17 AB19 AA1 R2 L1
VSS_SDRAM VSS_SDRAM VSS_SDRAM VSS_SDRAM VSS_SDRAM VSS_SDRAM VSS_SDRAM VSS_SDRAM VSS_SDRAM VSS_SD VSS_SD VSS_OP2 VSS_OP2 VSS_OP1 VSS_OP1 VSSA_MPLL VSS_LCD VSS_LCD VSS_CAM

100nF 100nF

VDD_LCD
M4 P8 W4 U22 M20 U10 AB5 G17 D13 C13 J15 C15 C20 C22 E20 H20 Y21 AA19 AC20

U16C S3C2443X

VDD_CAM VDD_LCD VDD_LCD VDD_OP1 VDD_OP1 VDD_OP2 VDD_OP2 VDD_SDRAM VDD_SDRAM VDD_SDRAM VDD_SDRAM VDD_SDRAM VDD_SDRAM VDD_SDRAM VDD_SDRAM VDD_SDRAM VDDA_ADC VDDA_UPLL VDDA_MPLL

VDD_OP1 VDD_OP2 VDD_SMOP

CT9 + 10uF C48 C49 CT10 C50 + 10uF C51 CT11 C52 + 10uF C53

VDD_OP1

VDD_UPLL VDD_ADC VDD_MPLL

VDD_SMOP

VDDA33T1 VDDA33T1 VDDA33C VDDI_UDEV
U20 VDDALIVE M22 VDDALIVE L20 VDDALIVE
M1 VDDIARM P4 VDDIARM T4 VDDIARM U4 VDDIARM V4 VDDIARM Y1 VDDIARM AC3 VDDIARM Y6 VDDIARM AC8 VDDIARM AB11 VDDIARM
VDD_SRAM VDD_SRAM VDD_SRAM VDD_SRAM VDD_SRAM
D1 L3 T16 G23 A19 B14 C11 H8 Y12 T15

SADDR14 SADDR15

mSDR_CS nSRAS nSCAS nSWE

DQM2 DQM3 SCLK SCKE

A3 B7 C3 D7
nSCS0 nSCS5 SW-SLIDE4 mSDR_CS SADDR[12:0] mDDR_CS SADDR0 SADDR1 SADDR2 SADDR3 SADDR4 SADDR5 SADDR6 SADDR7 SADDR8 SADDR9 SADDR10 SADDR11 SADDR12 SADDR14 SADDR15 DQM0 DQM1 DQS0 DQS1 SCKE SCLK nSCLK SADDR14 SADDR15 J8 J9 K7 K8 K2 K3 J1 J2 J3 H1 J7 H2 H3 H8 H9 F8 F2 E8 E2 G1 G2 G3 A9 F9 K9 VDD_SMEM C9 E9 A7 B1 D1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 BA0 BA1 LDM UDM LDQS UDQS CKE CK nCK VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nCS nRAS nCAS nWE NC NC VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ K4X51163PC-LGC3 A8 B7 B8 C7 C8 D7 D8 E7 E3 D2 D3 C2 C3 B2 B3 A2 H7 G9 G8 G7 F3 F7 A1 F1 K1 C1 E1 A3 B9 D9 SDATA0 SDATA1 SDATA2 SDATA3 SDATA4 SDATA5 SDATA6 SDATA7 SDATA8 SDATA9 SDATA10 SDATA11 SDATA12 SDATA13 SDATA14 SDATA15
SDATA[31:0] C37 100nF C38 100nF

C35 100nF 2 2

C36 100nF

1001(D) mSDR

0110 mDDR

Default : 1001

SADDR0 SDATA0 SCKE nSCLK nSWE nSCAS nSRAS DQM0 DQM1 DQM2

SADDR0 SDATA0

TP31 SADDR0 TP32 SDATA0 TP33 SCKE TP34 nSCLK TP35 nSWE TP36 nSCAS TP37 nSRAS TP38 DQM0 TP39 DQM1 TP40 DQM2 TP41 DQM3 TP42 DQS0 TP43 DQS1 TP48 SCLK
C39 100nF mDDR_CS nSRAS nSCAS nSWE

C40 100nF 2

C41 100nF 2

1 C42 100nF

!!SAME ROUTE LENGTH

DQM3 DQS0 DQS1 SCLK

Title SMDK2443 (S3C2443 Evaluation Board) Size A3 Date: Document Number mSDR/mDDR Monday, October 15, 2007 Sheet

Just Only PADS on Lines

VDD_RMEM

100nF Slide SW5

SW-SLIDE2

nCS_EXT_ONE nCS_SROM0

OM0 OM1

R1 R2 R3 R4 R5

100K 100K 100K 100K 100K
CFG1:CS0 1:OFF, 2:ON 1:ON, 2:OFF
One NAND& SROM I/F Base B'd Ext. OneNAND

RADDR[15:0]

OM60 RADDR[15:0] RADDR1 RADDR3 RADDR5 RADDR7 RADDR9 RADDR11 RADDR13 RADDR15 OM3 OM4
RADDR0 RADDR2 RADDR4 RADDR6 RADDR8 RADDR10 RADDR12 RADDR14
R6 100K nCS_EXT_ONE nRWE RSMAVD B_nONE_RST

RSMCLK RDATA[15:0]

RDATA0 RDATA2 RDATA4 RDATA6 RDATA8 RDATA10 RDATA12 RDATA14

<Silk> [5]

nROE B_ONE_INT RSMBWAIT RDATA[15:0]
OFF [5] : ON & [4] : OFF OneNAND/ROM OFF ON OFF ON OFF ON OFF Muxed OneNAND 16 bit ON ROM & Demuxed OneNAND 8 bit 16 bit OFF Advanced page 1KB page 2KB ADDR4 ADDR5 NAND ON Normal page 256B page 512B

1 XTIRTC

RDATA1 RDATA3 RDATA5 RDATA7 RDATA9 RDATA11 RDATA13 RDATA15

C [4] F G 2 [3]

32.768KHz(SMD) XTORTC C2 15pF 1 C3 15pF

[2] [1]

ADDR3 ADDR4
XTiPLL (MPLL/UPLL) EXTCLK (MPLL/UPLL)

QSH-030-01-F-D-A

QTH/QSH Series ( 0.5mm)

2 C4 100nF

R204 NC 4 1

VDD OE OUT GND 3 2

XTIPLL EXTCLK

C16 RDATA[15:0] RDATA0 RDATA1 RDATA2 RDATA3 RDATA4 RDATA5 RDATA6 RDATA7 RDATA8 RDATA9 RDATA10 RDATA11 RDATA12 RDATA13 RDATA14 RDATA28 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 1OE 2OE GND0 GND1 GND2 GND3 SN74AVCA164245 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 1DIR 2DIR GND7 GND6 GND5 GND21 B_DATA0 B_DATA1 B_DATA2 B_DATA3 B_DATA4 B_DATA5 B_DATA6 B_DATA7 B_DATA8 B_DATA9 B_DATA10 B_DATA11 B_DATA12 B_DATA13 B_DATA14 B_DATA15 BUF_DIR

VCCA0 VCCA1

VCCB0 VCCB1

100nF B_DATA[15:0]

TS5A3159_SPDT
SN74AUC2G08 Propagation Delay (CL30pF) Typ: 1.5nS ( 1.2 ~ 2.1)

nRWE nROE nRBE0 nRBE1

nCF_MOE 6

nOE_URDIR

4 SN74AUC2G08
RR643 NC BUF_DIR 100K (NC) SN74AUC2G08 RADDR25 (RDATA_OEN)
B_nRWE B_nROE B_nRBE0 B_nRBE1 R24 100K

100K (NC) R25 0

R619R620R621R622 100K100K100K100K

nCS_SROM0 nGCS1

SN74AUC2G08 nGCS5 nGCS2

R623 100K R624 100K

R641 10K

BCtrl_I0

nXBREQ R642 NC 6

4 SN74AUC2G08 GPB6

3 SN74AUC2G08

3 BCtrl_I1 SN74AUC2G08

BCtrl_I1

nGCS2 nGCSSN74AUC2G08

U607A BCtrl_I0
7 nREG_CF SN74AUC2G08 nFCE

R625 100K R626 100K

SN74AUC2G08 Size A3 Date:

SN74AUC2G08

Title SMDK2443 (S3C2443 Evaluation Board) Document Number BUFFERS(SROM IF) Monday, October 15, 2007 Sheet

C_PWR_5V

R29 R41 DN0 DP0 R42

15K 3 4

VBUS DD+ GND USB(HOST) SOCKET

Dual USB Port - A type

DN and DP should be routed evenly

TP1 TP2

SD0_DAT[7:0] SD0_DAT2 SD0_DAT3
R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40
NC NC DAT2 DAT3 DAT4 NC CMD NC DAT5 NC VSS NC NC VDD NC NC CLK NC DAT6 NC VSS NC DAT7 NC DAT0 DAT1 SD_CD SD_WP
SD0_CMD SD0_DAT0 SD0_DAT1

R632 VBUS_DET 0

R633 R634
SD0_DAT4 SD0_DAT5 SD0_DAT6 SD0_DAT7

300K DN_UDEV DP_UDEV

VBUS DD+ GND
ferrite Bead EXC-3225U USB(Device) SOCKET SD0_CLK

P30/GND

SDDATA & CLK path must be same length and route
10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K

USB Port B type 6

BG2 BG1
L2 NC R47 ferrite Bead EXC-3225U
SD0_nCD SD0_nWP XI_UDEV C20 3.4K 1% NC NC XO_UDEV C19 REXT R48
fundermental Oscillator tolerance +-100ppm peak jitter 100ps duty cycle 40/60~60/40 swing 3.3V

VDD OE OUT GND

SD Socket [Taisol]

OSCILLATOR 48Mhz

P29/GND

For USB Clock

SDR1005-6R8M 5 Q2B FDSR97 RNC 3
10K 10K R98 TPS0 TPS1 120K
C103 470pF C104 0.22uF R101 R103 NC 0

1 VGATE-PAD

Document Number CPU B'D POWER(ARM/INT) Monday, October 15, 2007 Sheet

CT39 100uF/16V + 11 12

IN IN EN GND GND GND GND GND GND GND PG OUT OUT FB/NC NC NC NC NC GND GND R106 R107 53.6K 1% + 30.1K 1% 100uF/16V 2 Vo = 1.1834[Vref] x (1 + R1/R2) (R1 : OUT-FB, R2 : FB-GND) 100nF R104 240K
J1 J1 CJJJ1 VREF C109 + POK OUT OUT SET GND MAX1806EUAR109 100K 4.7uF/6.3V 1 J1

(3.3V)

TPS76801QPWP
L5 4.7uH LQH3C4R7MJJ11 C107 4.7uF 2 JJ1
VIN RUN MODE GND SW Vfb 3 5

1 C105

2 22pF

C106 33uF/6.3V +

SHDN IN IN

R110 R111 30.1K 1%

15.0K 1%

(1.2V)

CT42 +

LTC3405A 2

VRNC 1

R108 120K

CT41 10uF/16V

10uF/16V

VDD_USBS

CLKOUT1 RUSB20_EN R627

USB20_EN 2 CT43 + SHDN IN IN

R645 NC

POK OUT OUT SET GND

100K J1

R114 R115 30.1K 1%

CT44 +

R646 0

MAX1806EUA15

R1=R2[(Vout/0.8)-1]
2 SHDN IN IN POK OUT OUT SET GND MAX1806EUAR116 100K

R117 R118 24.3K 1%

75.0K, 1%

CT46 +

CT45 10uF/16V
Document Number CPU B'D POWER(ALIVE/IO) Monday, October 15, 2007 Sheet
B_ADDR[25:0] B_ADDR25 B_ADDR24 B_ADDR23 B_ADDR22 B_ADDR21 B_ADDR20 B_ADDR19 B_ADDR18 B_ADDR17 B_ADDR16 B_ADDR15 B_ADDR14 B_ADDR13 B_ADDR12 B_ADDR11 B_ADDR10 B_ADDR9
B_DATA[15:0] B_DATA15 B_DATA14 B_DATA13 B_DATA12 B_DATA11 B_DATA10 B_DATA9 B_DATA8 B_DATA7 B_DATA6 B_DATA5 B_DATA4 B_DATA3 B_DATA2 B_DATA1 B_DATA0 B_nRBE1 B_nRBE0 B_nROE B_nRWE B_nWE_CF B_nOE_CF nWAIT B_nFCE B_CLE B_ALE B_nFRE B_nFWE RnB CD_CF nIRQ_CF nINPACK_CF nREG_CF RESET_CF PWREN_CF nXDREQ1 nXDREQ0 nXDACK1 nXDACK0 nXBACK nXBREQ nCD_SD1 SD1_CLK SD1_CMD SD1_DAT0 SD1_DAT1 SD1_DAT2 SD1_DAT3 (WP_SD1) IICSDA IICSCL EINT0 EINT11 CAMPCLKOUT CAMRESET CAMVSYNC CAMHREF CAMPCLK CAMDATA[7:0] CAMDATA0 CAMDATA1 CAMDATA2 CAMDATA3 CAMDATA4 CAMDATA5 CAMDATA6 CAMDATA119 RXD0 RXD1 RXD2 RXD3 TXD0 TXD1 TXD2 TXD3 UARTCLK CTS0 CTS1 RTS0 RTS1 LCDVF0 LCDVF1 LCDVF2 LEND RGB_VCLK RGB_VSYNC RGB_HSYNC RGB_VDEN VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 VD16 VD17 VD18 VD19 VD20 VD21 VD22 VD23 VD[23:0]
B_ADDR8 B_ADDR7 B_ADDR6 B_ADDR5 B_ADDR4 B_ADDR3 B_ADDR2 B_ADDR1 B_ADDR0 B_nCS5 B_nCS4 B_nCS3 B_nCS2 B_SROM_nCS1 B_SROM_nCS0 KBDINT KEYBOARD IRQ_LAN nRSTOUT nRESET CLKOUT0 CLKOUT1
nSS1 R_nSS0 SPIMOSI1 R_SPIMOSI0 SPIMISO1 R_SPIMISO0 SPICLK1 R_SPICLK0

118 120

117 119
L3CLOCK L3DATA L3MODE I2SCDCLK I2SSDO I2SSDI I2SSCLK I2SLRCK nLED_1 nLED_2 nLED_4 nLED_8 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 TSXP TSXM TSYP TSYM TCLK TOUT1 BACKLIGHT_PWM nDIS_OFF LCD_PWREN
TP44 TP PROBE TP45 TP PROBE TP46 TP PROBE TP47 TP PROBE
place TPs to each corner.

BSE-060-01

10uF/16V 2
Document Number B2B CONNECTOR(CPU) Monday, October 15, 2007 Sheet

AMD Flash Memory(SOCKET)

B_ADDR[25:0] B_DATA[15:0]
B_ADDR[25:0] U221 B_DATA[15:0]

VDD3.3V

I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O38 B_DATA0 B_DATA1 B_DATA2 B_DATA3 B_DATA4 B_DATA5 B_DATA6 B_DATA7 B_DATA8 B_DATA9 B_DATA10 B_DATA11 B_DATA12 B_DATA13 B_DATA14 B_DATA15
B_ADDR0 B_ADDR1 B_ADDR2 B_ADDR3 B_ADDR4 B_ADDR5 B_ADDR6 B_ADDR7 B_ADDR8 B_ADDR9 B_ADDR10 B_ADDR11 B_ADDR12 B_ADDR13 B_ADDR14 B_ADDR15 B_ADDR16 B_ADDR17 B_ADDR18 B_ADDR19 B_ADDR20
46 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 VSS0 VSS1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 nCE nOE nWE nRY/BY nRESET nBYTE VDD47 37
B_DATA0 B_DATA1 B_DATA2 B_DATA3 B_DATA4 B_DATA5 B_DATA6 B_DATA7 B_DATA8 B_DATA9 B_DATA10 B_DATA11 B_DATA12 B_DATA13 B_DATA14 B_DATA15 nCS_AMD B_nROE B_nRWE nRESET C2 CT1 + 10uF/16V C1 100nF 100nF +

VDD3.3V VDD3.3V

B_ADDR0 B_ADDR1 B_ADDR2 B_ADDR3 B_ADDR4 B_ADDR5 B_ADDR6 B_ADDR7 B_ADDR8 B_ADDR9 B_ADDR10 B_ADDR11 B_ADDR12 B_ADDR13 B_ADDR14 B_ADDR15 B_ADDR16 B_ADDR17
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 VCC VCC VSS VSS

R1 R3 R275R276R277

B_SROM_nCS0 B_nFCE
100K100K100K100K100K nCS_AMD nCS_NAND nCS_XD nCS_EXT nCS_SRAM

Slide-SW6

CT2 10uF/16V

WE LB UB OE CS

B_nRWE B_nRBE0 B_nRBE1 B_nROE nCS_SRAM
B_SROM_nCS1 nCS_AMD nCS_NAND nCS_XD nCS_EXT nCS_SRAM nCS_CS8900 Slide-SW6
AM29LV800BB (with Socket) (1MB) OR AM29LV160BB

K6X4016T3F_1

R279R280R278
100K100K100K B_nCS2 B_nCS3 B_nCS4 B_nCS5 R281 R282 R283 R0 NC NC nCS_CF0 nCS_CF1 nCS_CS8900 nCS_SRAM
NAND Flash memory (SOCKET )
U24 NC0 NC1 NC2 NC3 NC4 NC5 nR/B nRE CE NC6 NC7 VCC0 VSS0 NC8 NC9 CLE ALE nWE WP NC10 NC11 NC12 NC13 NC14 NC29/ VSS2 NC28/ IO15 NC27/ IO7 NC26/ IO14 IO7/ IO6 IO6/ IO13 IO5 IO4/ IO12 NC25/ IO4 NC24 NC23 VCC1 VSS/ NC22 NC21 NC20 NC19/ IO11 IO3 IO2/ IO10 IO1/ IO2 IO0/ IO9 NC18/ IO1 NC17/ IO8 NC16/ IO0 NC15/ VSS25 R26 OPEN R4 R5 RIO7/IO6 IO6/IO13 R11 B_DATA5 IO4/IO12 B_DATAIO6/IO13
R281~R284 place on top VDD3.3V

B_DATA[15:0]

XD PICTURE CARD
<Silk> CFG1: nCS0 CON1 CFG2: nCS1 [6] [5] [4] [3] [2] [1] SROM Selector CS8900(CS1) SRAM External XD card NAND NOR(AMD)
B_DATA15 B_DATA7 B_DATA14

IO7/IO6

R6 R8 R10 R0

B_DATA6 B_DATA7

B_DATA[15:0] R9 B_DATA7 B_DATA6 B_DATA5 B_DATA4 B_DATA3 B_DATA2 B_DATA1 B_DATA0 4.7K 19
RnB B_nFRE nCS_NAND R14 10K

B_DATA13 B_DATA6

IO4/IO12

R13 R15 0

B_DATA12 B_DATA4
IO2/IO10 RIO2/IO10 IO1/IO2 IO0/IOB_DATA11 B_DATA3 IO1/IO2 B_DATA1 B_DATA8 B_DATA0

R16 R18 R19 R0

B_DATA10 B_DATA2 B_nFWE B_ALE B_CLE nCS_XD B_nFRE RnB

B_CLE B_ALE B_nFWE

B_DATA2 B_DATA1

R20 R22 R23

IO0/IO9

R24 R25 0

B_DATA9 B_DATA0
VCC D7 D6 D5 D4 D3 D2 D1 D0 GND WP WE ALE CLE CE RE R/B GND GND

K9F1208U0M

Socket
16-bit: R6,10,13,16,19,24 8-bit: R8,12,15,18,21,25
xD_CARD Socket 1 C3 100nF 1 C4 100nF

RnB B_nFRE

1 TP1 RnB 1 TP2 nFRE 1 TP3 ALE 1 TP4 CLE 1 TP5 nFWE

C5 + 10uF/16V

B_ALE C7 100nF B_CLE B_nFWE

C6 100nF 2 2

Document Number NOR/NAND/SRAM/CONFIG Monday, October 15, 2007 Sheet

Rev 1.of 12

R29 10K

R30 10K

R28 10K

CT3 + 10uF

C8 100nF

VDD_CF

B_DATA[15:0] PWREN_CF B_nROE B_ADDR[25:0] B_ADDR[25:0] B_DATA3 B_DATA4 B_DATA5 B_DATA6 B_DATA7 B_ADDR10 nCS_CF0
25 GND CD1 D3 D11 D4 D12 D5 D13 D6 D14 D7 D15 nCE1 nCE2 A10 nVS1/GND nOE nIORD A9 nIOWR A8 nWE A7 IREQ VCC VCC A6 nCSEL A5 nVS2/OPEN A4 RESET A3 nWAIT A2 nINPACK A1 nREG A0 nSPKR D0 nSTSCHG D1 D8 D2 D9 WP D10 CD2 GND CF050-YAMAICHI 50 CD1_CF B_DATA11 B_DATA12 B_DATA13 B_DATA14 B_DATA15
nCS_EXT B_nRWE B_ADDR[25:0]
B_ADDR0 B_ADDR2 B_ADDR4 B_ADDR6 B_ADDR8 B_ADDR10 B_ADDR12 B_ADDR14 B_ADDR16 B_ADDR18 B_ADDR20 B_ADDR22 B_ADDR24
B_ADDR1 B_ADDR3 B_ADDR5 B_ADDR7 B_ADDR9 B_ADDR11 B_ADDR13 B_ADDR15 B_ADDR17 B_ADDR19 B_ADDR21 B_ADDR23 B_ADDR25 B_DATA1 B_DATA3 B_DATA5 B_DATA7 B_DATA9 B_DATA11 B_DATA13 B_DATA15 SPI_KEYMOSI SPI_KEYCLK nXBACK nRSTOUT nWAIT R36 R37 nXDREQ0 nXDREQ1
nCS_CF1 B_nROE B_nRWE B_nWE_CF nIRQ_CF R31 R32 RESET_CF nWAIT nINPACK_CF nREG_CF R33 R34
B_ADDR9 B_nOE_CF B_ADDR8 B_ADDR7 B_ADDR6 B_ADDR5 B_ADDR4 B_ADDR3 B_ADDR2 B_ADDR1 B_ADDR0 B_DATA0 B_DATA1 B_DATA2 R35 CD2_CF TP22 nIRQ_CF B_nWE_CF B_nRWE RXD0 TXD0 B_nROE nCS_CF0 nCS_CF1 B_nOE_CF 1 TPTP10K

TLCD_D[17:0] LCD_nRESET LCD_nOE LCD_nWE LCD_RS LCD_nCS0 LCD_nCS1 SPI_LCDnSS

R153 68K 1 C54 1

LCD_nRESET 3 4

R154 R155 R1171

0 JAE_FF0140SA1 NC NC

nSHDN POL REF FB

VCC LX GND ISET

C57 100nF 2

Main LCD Touch Screen

+ C55 10uF/16V

C56 C58 + 100nF

22uF/36V 2 VDD3.3V 3

MAX629 1

VR1 CVR 10K 1

VDD3.3V + R156 10K BACKLIGHT_PWM R157 10K C60 4.7uF/6.3V 5

10uH 1

IN EN REF BRT/PWM FB3 SW GND OLS FB1 FB7 6
D11 1SS355 VLED_Anode + C61 1uF/25V
3.3V/24V DC/DC CONVERTER (STN LCD)

TP10 TP11

2Pin FPC Solder Type Back-Light Max 20mA (230mW)

B_PWR_5V

2.2uH LQH32CN2R2M33
Vo = 0.6V * (1+R2/R1)= 2.8V R2 = (Vo/0.6V - 1) * R1
VDD_DISP B_PWR_5V C63 33uF/6.3V C64 100nF + + C65 33uF/6.3V 1 VDD3.3V JVDD_DISP JJVDD_LCDI R158 Unload(10K)
MPS MP1521EK/MSOP-10P VLED_Cathode R159 20

R160 0

3 RUN GND SW VOUT VIN 1

R161 Unload

+ C62 4.7uF/6.3V

LTC3406ES5

(600mA) (R1)

R162 100K

VR2 500K
SMDK2443 (S3C2443 Evaluation Board)

Size A3 Date:

Document Number
TFT LCD(CPU/RGB portrait type) / CSTN LCD
Monday, October 15, 2007 Sheet

Rev 1.0 of 12

LD[23:0] LD[23:0] LCD_VCLK LCD_LVFRAME LD20 LD22 LCD_VLINE LnDIS_OFF LCD_nRESET LD1 LD3 LD5 LD7 LD11 LD13 LD15 LD4 LD6 + C66 10uF/16V LCD_LEND LCD_nRESET TSXP TSYP 39
LD19 LD21 LD23 LD10 LD12 LD14 LD3 LD5 LD7

LD[23:0] LCD_VLINE

LCD_LVFRAME LCD_VCLK LCD_LVM LD0 LD2 LD4 LD20

LCD_LVM

1 + C67 10uF/16V LLCD_PWREN 2

HEADCONN_20P

TSXM TSYM

HEADCONN_40P

AIN1 AIN3 AIN5 TSYP TSXP LD0 LD1 LD2 LD16 LD17 LD12 LD8 LD0 0

AIN0 AIN2 AIN4 TSYM TSXM

R163 R164 R165 1

2.54mm header 10pin

LCDVF0 LCDVF1 LCDVF2 2

+ C68 10uF/16V

HEADCONN_12P
Title SMDK2443 (S3C2443 Evaluation Board) Size A4 Date:
Document Number LCD External connector (TFT, CSTN, TSP) Monday, October 15, 2007 Sheet
B_CAMDATA[7:0] B_CAMDATA0 B_CAMDATA1 B_CAMDATA2 B_CAMDATA3 B_CAMDATA4 B_CAMDATA5 B_CAMDATA6 B_CAMDATA7 B_CAMPCLK B_CAMHREF B_CAMVSYNC 48 25
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 1DIR 2DIR 1OE 2OE
L : B to A H : A to B 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 VCCB VCCB VCCA VCCA 31 42
CAMDATA[7:0] CAMDATA0 CAMDATA1 CAMDATA2 CAMDATA3 CAMDATA4 CAMDATA5 CAMDATA6 CAMDATA7 VDD_CAM_EXT CAMPCLK CAMHREF CAMVSYNC 2

Camera Interface

VDD_CAM_EXT
R166 10K B_CAMDATA[7:0] B_CAMDATA1 B_CAMDATA3 B_CAMDATA5 B_CAMDATA7 B_CAMPCLK B_CAMVSYNC IICSCL 38 40
B_CAMDATA[7:0] B_CAMDATA0 B_CAMDATA2 B_CAMDATA4 B_CAMDATA6 B_CAMCLK B_CAMHREF IICSDA B_CAMRST

AC97_LINE_R

R196 C108 220pF

8.2K R198 8.2K

RCT11 + 1 10uF/16V AC97_OUT_L AC97_OUT_R
3.3uF NC 3.3uF NC 3.3uF NC 220uF 6.3V 220uF 6.3V 0 (NC) R202 R203 47K 47K

nCD_SDSMD TYPE (BLUE)

R204 R205 R206 R207
100K(NC) 100K(NC) 100K(NC) 100K(NC)

WM9710EFT

XTLOUT
AC97_SDO AC97_BITCLK AC97_SDI AC97_SYNC AC97_nRESET

SD <Silk>

24.576MHz C109 22pF C110 22pF
Title SMDK2443 (S3C2443 Evaluation Board) Size A3 Date: Document Number Audio Codec - AC97 Monday, October 15, 2007 Sheet
IIS Interface (Audio Codec)

IIS_LINE_L

10uF/6.3V

IIS_LINE_R

C111 100nF CT18 100uF/16V 100nF AVSS(ADC) VINL1 AVDD(ADC) VINR1 Vnref(ADC) VINL2 Vpref(ADC) VINR2 OVERFL DVDD DVSS SYSCLK L3MODE L3CLOCK UDA1341TS CT19 10uF/6.3V + +

L+ CT20 2

<--LINE!!

+ CT21 10uF/6.3V

BLM18PG121 10uF/6.3V

R208 R(NC) 100

RR211 R213 6.8K 6.8K CT26 47uF/16V R216 6.8K(NC) + CT22 + CT24 + R215 R0 47uF/16V 47uF/16V
C113 100nF Vref(ADC&DAC) AVSS(DAC) VOUTL AVDD(DAC) VOUTR QMUTE AGCSTAT TEST2 TEST1 DATAI DATAO WS BCK L3DATA RCT23 CT25 47uF/16V 47uF/16V R+ IIS_OUT_L IIS_OUT_R

L2 BLM18PG121

VDD_ext R218 4.7K R219 4.7K R220 4.7K R221 10K R222 10K 1 B_PWR_5V VDD3.3V

CT28 + +

CT29 + IIS_MIC IIS_CDCLK
47uF/16V 47uF/16V 47uF/16V (NC)
IN GND EN ADJ 4 R223 169K 1% R224 243K 1% 280K => 3.3V OUT 5 CT30 + 10uF/6.3V 2 3

JUMPER3

100nF IIS_SCLK IIS_LRCK IIS_SDI IIS_SDO R225 100K(NC) R226 100K(NC) R227 100K(NC) R228 100K(NC) 1 VDD_ext TP12 AGC

+ CT31 10uF/6.3V

L3MODE L3CLOCK L3DATA
1A 2A 3A GND VDD 1Y 2Y 3Y

MIC5219BM5

SN74LVC3G34DCT

1.24(1+R224/R223)

IIS_OUT_R IIS_OUT_L

1 ST-JACK

RR230 + CT34 47uF 6.8K

0 : NC ON 1 : NO ON

+ CT33

+ CT32 10uF/16V C115

U31 J18
IIS_LINE_L IIS_LINE_R AC97_LINE_L ST-JACK AC97_LINE_R 6 NC1 NC2 COM1 NO1 NO2 IN1 GND IN2 COM2 VCC 7 nI2S/AC2 1

Speaker Out

R231 1.5K
IIS_MIC C117 220pF 6 GND NC1 NC2 COM1 AC97_MIC NO1 NO2 IN1 IN2 COM2 VCC

ST-JACK

AC97_OUT_R AC97_OUT_L 1 ST-JACK

R232 + CT35 10uF

MAX4764ETB

Mic In

Line In
Document Number Audio Codec - IIS Monday, October 15, 2007 Sheet
28 + CT37 C118 100nF C119 100nF 0.1uF/16V + CT41 C1C2+ C1+

V+ 27 V3

CT36 +
0.1uF/16V CT38 0.1uF/16V J9 JUMPER 2 +
16 + CT39 0.1uF/16V CT42 0.1uF/16V 15 CON2_TXD CON2_RXD CON2_RTS CON2_CTS GND T1IN R1OUT T2IN R2OUT C2T1OUT R1IN T2OUT R2IN 8 C124 MAX3232CSE 330pF C125 330pF C126 330pF C127 330pF + V+ VC1C2+ + CT43 0.1uF/16V VCC C1+ 1 + CT40 0.1uF/16V

COM1 port UART0 Only J10

5 BOXCONN_DB9
0.1uF/16V 2 TXD0 RTS0 DTR0 R233 10K R234 10K 15 26
C2T1IN T2IN T3IN T1OUT T2OUT T3OUT 11 21

COM2 port UART1/2/3 J11

nFORCEOFF nINVALID FORCEON R2OUTB R1OUT R2OUT R3OUT R4OUT R5OUT VCC MAX3243CAI R1IN R2IN R3IN R4IN R5IN GND

RXD0 CTS0 DSR0

C120 330pF

C121 330pF

C122 330pF

C123 330pF

16 VCC 1B1 2B1 3B1 4B14 TXD1 RXD1 RTS1 CTS1
16 VCC 1B1 2B1 3B1 4B14 TXD3 (RTS2) RXD3 (CTS2) C130 100nF + CT44 6.8uF

LCDVF1 LCDVF2

R235 R236

DTR0 DSR0

CON2_TXD CON2_RXD CON2_RTS CON2_CTS

R237 2.7

R238 100K
TXD MD0 MD1 RXD FIR_SEL NC AGND GND
C131 CFG5 SW-SLIDE4 R241 100K R242 100K R243 100K TXD2 RXD12 1A 2A 3A 4A
100nF R239 R240 100K 100K

1B2 2B2 3B2 4B2

TXD3 RXD3
S - L : B1 port, H : B2 port OE - L : Output enable H : all disconnect

HSDL-7

COM2 port CFG3 Control Func(CFG3) UART1 UART2 UART3

SIR mode only

<Silk> PIN1 OFF ON ON X PIN2 X OFF ON ON PIN3 X OFF X ON

R244 100K UEXTCLK 3

IrDA(U2)
OUT VDD GND SMD (NC) OE 1

UEXTCLK CLKOUT0

R245 R246

0(NC) 0

UARTCLK
Title SMDK2443 (S3C2443 Evaluation Board) Size A3 Date: Document Number UART/IrDA/SPI Monday, October 15, 2007 Sheet

R247 B_PWR_5V

MMBT3904

SMD TYPE (BLUE)

P G G POWER JACK 3
SWPOLY SWITCH/1.5A C132 100nF R248 47K R249 10K 3

4 SI4423DY

RSMD TYPE (BLUE)
5 VCC OUT GND 4 ININ+ 3 R252 12.7K 10K R254 330

SMD TYPE (BLUE) R255 10K nLED_1 nLED_2 nLED_4 nLED_8 R256 10K 10K R257

R258 10K

MAX6458 R253

SMD TYPE (RED)

R264 B_PWR_5V B_PWR_5V R260 10K D6 100K EINT0

C139 100nF

LS8JEM-T + CT45 22uF/16V + CT46 4.7uF/16V + CT47 4.7uF/16V Silk EINT0 VDD3.3V J13 L1.5uH 2 SDR1005 R268 RESISTOR VAR (NC) R269 57.6K(1%) EINT2 VDD3.3V
100nF R261 1K R262 39K R263 100K R265 20K R(NC) C136 100pF C137 R10nF 7 100pF C9 R272 10
RUN/SS VON PGOOD VRNG ITH FCB SGND ION VFB EXTVCC LTC3778 400K BOOST TG SW SENSE+ SENSEPGND BG DRVCC INTVCC VIN 18 17

C134 220nF

CMPSH-FDS6982 3

2 FDS6982 1

JUMPER + CT48 + CT49 + CT50 220uF/6.3V 220uF/6.3V 10uF/6.3V

R273 100K

R271 + CT51 C140 4.7uF 100nF 12.7K(1%)

LS8JEM-T 1 2

R270 1

C143 100nF

Silk EINT11
Document Number Base board Power & LED Monday, October 15, 2007 Sheet
B_ADDR[25:0] B_ADDR25 B_ADDR24 B_ADDR23 B_ADDR22 B_ADDR21 B_ADDR20 B_ADDR19 B_ADDR18 B_ADDR17 B_ADDR16 B_ADDR15 B_ADDR14 B_ADDR13 B_ADDR12 B_ADDR11 B_ADDR10 B_ADDR9 B_ADDR8 B_ADDR7 B_ADDR6 B_ADDR5 B_ADDR4 B_ADDR3 B_ADDR2 B_ADDR1 B_ADDR0 B_nCS5 B_nCS4 B_nCS3 B_nCS2 B_SROM_nCS1 B_SROM_nCS0 KBDINT KEYBOARD IRQ_LAN nRSTOUT nRESET CLKOUT0 CLKOUT1 nSS1 R_nSS0 SPIMOSI1 R_SPIMOSI0 SPIMISO1 R_SPIMISO0 SPICLK1 R_SPICLK119 B_DATA[15:0] B_DATA15 B_DATA14 B_DATA13 B_DATA12 B_DATA11 B_DATA10 B_DATA9 B_DATA8 B_DATA7 B_DATA6 B_DATA5 B_DATA4 B_DATA3 B_DATA2 B_DATA1 B_DATA0 B_nRBE1 B_nRBE0 B_nROE B_nRWE B_nWE_CF B_nOE_CF nWAIT B_nFCE B_CLE B_ALE B_nFRE B_nFWE RnB CD_CF nIRQ_CF nINPACK_CF nREG_CF RESET_CF PWREN_CF nXDREQ1 nXDREQ0 nXDACK1 nXDACK0 nXBACK nXBREQ nCD_SD1 SD1_CLK SD1_CMD SD1_DAT0 SD1_DAT1 SD1_DAT2 SD1_DAT3 IICSDA IICSCL EINT0 EINT11 CAMPCLKOUT CAMRESET CAMVSYNC CAMHREF CAMPCLK CAMDATA[7:0] CAMDATA0 CAMDATA1 CAMDATA2 CAMDATA3 CAMDATA4 CAMDATA5 CAMDATA6 CAMDATA120
RXD0 RXD1 RXD2 RXD3 TXD0 TXD1 TXD2 TXD3 UARTCLK CTS0 CTS1 RTS0 RTS1 LCDVF0 LCDVF1 LCDVF2 LEND RGB_VCLK RGB_VSYNC RGB_HSYNC RGB_VDEN VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 VD16 VD17 VD18 VD19 VD20 VD21 VD22 VD23 VD[23:0] TP18 TP PROBE TP19 TP PROBE
B_ADDR23 For CS8900 access
TP20 TP PROBE TP21 TP PROBE

Place TPs to each corner

BSE-060-03

C148 + 10uF/16V 2

nRESET CLKOUT1

TP17 nRESET TP13 CLKOUT1

C145 +
C146 + TCLK TOUT1 TP14 TCLK TP15 TOUT1

C147 +

Document Number Board to Board connector Monday, October 15, 2007 Sheet

SMDK 6400 OVERVIEW

The SMDK 6400 (6400 Development Kit) highlights the basic system-based hardware design which uses the S3C6400X. It can evaluate the basic operations of the S3C6400X and assist in developing codes. SMDK 6400 is manufactured by MERITECH Co., Ltd and company website is www.mcukorea.com
Figure 1 SMDK6400 Function Diagram

FEATURES

The features of SMDK6400 include: S3C6400X : 16/32 bit RISC microcontroller, ARM1176JZF-S X-tal operation or oscillator Boot Device : AMD 8Mbit 1EA (support halfword size boot ROM) SAMSUNG NAND flash 1EA(socket) SAMSUNG OneNAND 1EA(External Board) SAMSUNG 8Mbit SRAM 1EA Internal ROM (TBD) Modem Boot ( External Connector) SDRAM : Memory Port0 : 64MB mDDR(K4X51163) Memory Port1 : 128MB mDDR( 64MB x 2, K4X51163) JTAG port RTC X-tal input TFT LCD & Touch panel interface ADC interface TV Out interface ( S-Video, Composite) USB Host , USB OTG 2.0 interface High Speed MMC interface High Speed SPI interface 2 port UART interface IIS/AC97/PCM Interface : WM9713, WM8753 Camera Interface EINT interface Ethernet Interface : CS8900 CF/ATA interface Keypad interface

CIRCUIT DESCRIPTION

The SMDK 6400 is designed to test S3C6400 and develop software while hardware is being developed. Figure 13 highlights the SMDK 6400's block diagram. POWER SUPPLY SMDK 6400 is operated by 1.0V for Internal, 1.8V for Memory and 3.3V for Input/Output pad and several peripherals. SMDK 6400 is supplied by 5V/2A DC Adaptor Power. The SMDK 6400 has distributed power plane, with power going separately to the MCU and the main power plane. Due to this specific reason, power jumpers including JA01~JA20 and J901, J926 on the CPU board, J4~J9 and J14, J22 on the base board are inserted.
Figure 2 SMDK6400 Power Plane
Figure 3 SMDK6400 Board Diagram
SMDK6400 CPU BOARD TYPE1 REAL VIEW

USB JTAG USB OTG

FPC cable

SD/MMC

CFG0 MMC MOVINAND

ONENAND

Figure 4 SMDK6400 CPU Board Type1 real view
SMDK6400 BASE BOARD REAL VIEW

ADC EXT LCD

CAMERA

UART1/2/3

CFGB9 LCD UART0 CFGB8 EXT KEYPAD
ETHERNET CON6 CFG3 J3 CFG4 CFG2 CFG1 CFGB3 SPK OUT CFGB2 CFGB1 CFGB7 CFGB6 CFGB5 CFGB4 xD card HS MMC

MIC IN

LINE IN

S-VIDEO

COMPOSITE

EXT ROM BUS

Figure 5 SMDK6400 BASE Board real view
SMDK6400 SYSTEM CONFIGURATIONS rev0.1
Perform the following steps to use SMDK6400 board:
1. Set the Jumper , J503, J515, J516 on CPU board
Please refer to JUMPER SETTING CONFIGURATION ON page 22
2. Select the Clock source

LTC3714 (U901, U902) Voltage VID4 1.300V 1.250V 1.200V 1.150V 1.100V 1.050V 1.000V 0.975V 0.950V 0.925V 0.900V 0.875V 0.850V 0.825V 0.800V 0.775V VID1 VID0 VID0 VID0
Samsung Confidential 0.750V 0.725V 0.700V 1
CONFIGURATION SWITCH DESCRIPTION IN BASE BOARD
CFGB1 : SROM BANK0 SELECTOR CFGB1 component is used to select devices as SROM BUS I/F 0(Xm0CSn0). CFGB1 Description [3] Nor(AMD) Flash SRAM External Device OFF OFF ON [2] OFF ON OFF [1] ON OFF OFF
CFGB2 : SROM BANK1 SELECTOR CFGB2 component is used to select devices as SROM BUS I/F 1(Xm0CSn1). CFGB2 Description [4] Nor(AMD) Flash SRAM CS8900 External Device OFF OFF OFF ON [3] OFF OFF ON OFF [2] OFF ON OFF OFF [1] ON OFF OFF OFF
CFGB3 : SROM BANK2 SELECTOR CFGB3 component is used to select devices as SROM BUS I/F 2(Xm0CSn2). CFGB3 Description [4] NAND Flash XD Picture Card CS8900 External Device OFF OFF OFF ON [3] OFF OFF ON OFF [2] OFF ON OFF OFF [1] ON OFF OFF OFF
Samsung Confidential CFGB4 : SROM BANK3 SELECTOR CFGB4 component is used to select devices as SROM BUS I/F 3(Xm0CSn3). CFGB4 Description [4] NAND Flash XD Picture Card CS8900 External Device OFF OFF OFF ON [3] OFF OFF ON OFF [2] OFF ON OFF OFF [1] ON OFF OFF OFF
CFGB5 : SROM BANK4 SELECTOR CFGB5 component is used to select devices as SROM BUS I/F 4(Xm0CSn4). CFGB5 Description [4] CF0 Nor(AMD) Flash SRAM CS8900 OFF OFF OFF ON [3] OFF OFF ON OFF [2] OFF ON OFF OFF [1] ON OFF OFF OFF
CFGB6 : SROM BANK5 SELECTOR CFGB6 component is used to select devices as SROM BUS I/F 5(Xm0CSn5). CFGB6 Description [4] CF1 Nor(AMD) Flash SRAM CS8900 OFF OFF OFF ON [3] OFF OFF ON OFF [2] OFF ON OFF OFF [1] ON OFF OFF OFF
Samsung Confidential CFGB7 : CF CARD TRANSFER MODE SELECTOR CFGB7 component is used to select CF transfer mode. CFGB7 Description [2] Direct Mode Indirect Mode OFF ON [1] ON OFF
Note. * Direct Mode: Mode which has Control signal for CF through the dedicated CF pin * Indirect Mode: Mode which has Control signal for CF through the EBI * Sequence for using CF 1. Turn ON CFGB5[1], CFGB6[1] 2. Turn ON CFG4[2] 3. Connect JA20[1] & JA20[2] in CPU Board

LCD_SPI

EXT_SPI
Note. * If you select EXT_SPI, It will be connected with CON6 CONNECTOR.

CONNECTORS

CPU BOARD TYPE1 REV0.0
JTAG Part Name: J501 (CPU)

Figure 6 JTAG Connector

CPU BASE
USB Two Dual USB ports A-type (CON7A & CON7B, HOST) and one USB OTG port mini AB-type(CON8) are supported by the SMDK 6400.
Figure 7 Dual USB ports & OTG port
Hi Speed SPI IEEE-1394 connector is used as a Hi Speed- SPI connecter
Figure 8 Hi Speed SPI socket(IEEE1394 type)
FPC cable for MIPI HSI FPC cable is used as a MIPI HIS connector
Figure 9 FPC cable connector
SD/MMC host (Ver1.0) High speed MMC interface SD (MMC) is provided by the 6400 and SD card socket (CON802) is supported in the SMDK 6400

Figure 10 SD card Socket

EXTERNAL MMC & MOVI-NAND & CE-ATA connector External MMC interface is supported for MMC, Movi-Nand and CE-ATA
Figure 11 External MMC,MOVI-NAND & CE-ATA Bd Connector
EXTERNAL ONE-NAND connector External connector is supported for connecting ONE_NAND external board
Figure 12 External ONE-NAND Bd Connector

BASE BOARD REV0.0

COMPOSITE & S-VIDEO Connector SMDK 6400 provides COMPOSITE & S-VIDEO output connector
Figure 13 Composite & S-VIDEO Connector
LINE IN, MIC IN & SPEAKER OUT connector SMDK 6400 provides LINE IN, MIC IN and SPEAKER OUT as an audio connector
Figure 14 Audio Line In, Mic In & Speaker Out Connector
ETHERNET connector SMDK 6400 provides LINE IN, MIC IN and SPEAKER OUT as an audio connector.
Figure 15 Ethernet Socket
UART interface The S3C6400 UART unit provides three independent asynchronous serial I/O (SIO) ports including IrDA. In SMDK 6400 board, COM1 port is only used for UART0. No jumper setting is required. You can change UART by setting related jumpers.

Figure 16 UART Sockets

Samsung Confidential CAMERA INTERFACE connector SMDK 6400 provides CAMERA INTERFACE connector.
Figure 17 Camera Interface Connector

ADC connector

Figure 18 ADC Connector
MMC SMDK 6400 provides Hi Speed MMC connector.
Figure 19 Hi Speed MMC Connector
xD Picture Card Connector SMDK 6400 provides xD Picture Card Connector.
Figure 20 xD Picture Card Socket
PWM connector SMDK 6400 provides PWM out0&1.

Figure 21 PWM out pins

External SPI connector SMDK 6400 provides External SPI connector which can be selected by setting J3 jumper.
Figure 22 External SPI Connector
TFT LCD Connector TFT LCD controllers are equipped in the S3C6400X. TFT LCD, touch panel and LCD backlight driver are supported in the SMDK 6400X. Part Name Model Name Pannel Size #pixels I/F type Back-Light Unit Connector type CON1320 LTE480WV-F01 4.8 800x480 24bit RGB 14 LED(4pin) 45pin(0.5mm pitch) CON4 LTV350QV_F06 3.5 320x240 24bit RGB + SPI 6 LED(2pin) 60pin(0.5mm pitch) CON7 LTS222QV-F01 2.22 240x320 16bit CPU 4 LED(2pin) 40pin(0.5mm pitch)

EXTERNAL KEYPAD

Figure 29 External KEYPAD Connector # of pin Descriptions VDD_3.3V VDD_3.3V VDD_3.3V VDD_3.3V Kp_COL0 Kp_ROW0 Kp_COL1 Kp_ROW1 Kp_COL2 Kp_ROW2 Kp_COL3 Kp_ROW3 # of pin Descriptions GND GND # of pin Descriptions GND GND # of pin Descriptions -
Samsung Confidential Kp_COL4 Kp_ROW4 Kp_COL5 Kp_ROW5 Kp_ROW6 Kp_ROW80 GND GND
Note. Rev0.1 SMDK Base board has a external KEYPAD which can validate KP_COL0 ~ 5
SMDK SCHEMATIC REVISION POINTS
This document contains information of corrected points on the schematic of SMDK6400. The corrected points are highlighted in red-circled in schematic of SMDK6400 Rev 0.1

REVISION POINTS TABLE

Boards Page 3 CPU Board 2 Base Board 15 Contents OTG Power Selection S/W of NAND & OneNAND Buffer Glue Logic HS-SPI DeMux S/W OTG Power CF LCD Connector LCD Power 4.8 LCD I/F Selecting PCM Separating Keypad TV Encoder IROM Boot Corrected points VDD_OTG0 & VDD_OTG1 are separated. Selecting logic of NAND & OneNAND is replaced as Dip Switch. Logic for Buffers direction is changed. 0 ohms are added for testing. Input voltage of OTG Powers regulator. Selecting logic for VDD_CF is changed. Logic for LCD Bypass test is included. VDD_Disp is changed as 3.3V and is separated with VDD_LCDI. 4.8 WVGA LCD I/F is included. Using PCM of WM8753. Keypad I/F is arranged on a connector. 0 ohms are added. Logic for IROM Boot is included.
ADJUSTMENT OF VDD_APLL, VDD_MPLL, AND VDD_EPLL
The voltages for PLLs (APLL, MPLL, and EPLL) are different in accordance with the version of S3C6400. Therefore a adjustment of RA02 for changing the voltage of PLLs is required. Figure 30 describes the schematic of this part, and Figure 31 & Figure 32 represents real pictures.
Figure 30 schematic of VDD_xPLL part

Refer to Figure 32

Figure 31 Bottom View of SMDK6400 CPU Board
Resister value of RA02 must be selected according to the version of AP. This information is included in Table 1 An appropriate resister value should be reflected in this part according to the version of AP. Refer to Table 1 in order to select right resister value.
Figure 32 RA02 for VDD_xPLL adjustment

VDD_xPLL RA02 1.0V 42.2K

0.85V 11K

1.0V 42.2K

Table 1 Resister Value of RA02

SMDK SCHEMATIC

There are 2 parts of SMDK Schematic. 1. CPU Board 2. Base Board
Note. It is easy to find schematic parts by using Bookmarks on PDF
SMDK6400 Evaluation Board for S3C6400

1. PCB Revision

Date 2006. 12. 12 2007. 05. 10
Description Preliminary Version Release Version

Rev 0.0 Rev 0.1

2. Table of Contents
CPU Board Page Function 01 S3C6400(Addr/Data) 02 S3C6400(Functional I/O) 03 S3C6400(Power) 04 Memory Port (mDDR) 05 Memory(OneNand)/JTAG/CLK 06 Buffers(SROM I/F) 07 USB/USB OTG/MIPI 08 HS_MMC/HS_SPI 09 CPU B/D Power1(ARM, INT) 0A CPU B/D Power2(Alive, I/O) 0B Board to Board Connector (CPU) Base Board 00 Board to Board Connector (Base) 01 NOR/SRAM/NAND/Config 02 CF+ 03 CF+/Ext. Bus/Modem I/F 04 Ethernet Controller 05 LCD:RGB 24bpp_320XLCD:RGB CPU18bpp_RGB666_240xLCD:4.8inch/Ext. 08 Camera IF/I2C 09 Audio(AC97/PCM) 0A Audio(IIS) 0B UART/IrDA/SPI 0C Keypad 0D HSMMC/TV 0E Base B'd Power

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 BA0 BA1 LDM UDM LDQS UDQS CKE CK nCK VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nCS nRAS nCAS nWE NC NC VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ K4X51163PC-LGC3 A8 B7 B8 C7 C8 D7 D8 E7 E3 D2 D3 C2 C3 B2 B3 A2 H7 G9 G8 G7 F3 F7 A1 F1 K1 Xm0DATA0 Xm0DATA1 Xm0DATA2 Xm0DATA3 Xm0DATA4 Xm0DATA5 Xm0DATA6 Xm0DATA7 Xm0DATA8 Xm0DATA9 Xm0DATA10 Xm0DATA11 Xm0DATA12 Xm0DATA13 Xm0DATA14 Xm0DATA15

Xm0DATA[15:0]

Xm1ADDR14 H8 Xm1ADDR15 H9 F8 F2 E8 E2 G1 G2 G3 A9 F9 K9 C9 E9 A7 B1 D1

!!SAME ROUTE LENGTH

Xm0DQM0/BE0 Xm0DQM1/BE1 Xm0DQS0 Xm0DQS1 Xm0CKE Xm0SCLK Xm0SCLKn
Xm0CSn6 Xm0RASn Xm0CASn Xm0WEndmc

VDD_DMEM

VDD_SMEM

CT1 + 10uF

CT2 + 10uF
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF

C1 E1 A3 B9 D9

Just Only PADS on Lines
Xm1ADDR[15:0] Xm1ADDR0 Xm1ADDR1 Xm1ADDR2 Xm1ADDR3 Xm1ADDR4 Xm1ADDR5 Xm1ADDR6 Xm1ADDR7 Xm1ADDR8 Xm1ADDR9 Xm1ADDR10 Xm1ADDR11 Xm1ADDR12 Xm1ADDR14 Xm1ADDR15 Xm1DQM2 Xm1DQM3 Xm1DQS2 Xm1DQS3 Xm1CKE0 Xm1SCLK Xm1SCLKn J8 J9 K7 K8 K2 K3 J1 J2 J3 H1 J7 H2 H3
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 BA0 BA1 LDM UDM LDQS UDQS CKE CK nCK VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nCS nRAS nCAS nWE NC NC VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ K4X51163PC-LGC3 A8 B7 B8 C7 C8 D7 D8 E7 E3 D2 D3 C2 C3 B2 B3 A2 H7 G9 G8 G7 F3 F7 A1 F1 K1 C1 E1 A3 B9 D9 Xm1DATA16 Xm1DATA17 Xm1DATA18 Xm1DATA19 Xm1DATA20 Xm1DATA21 Xm1DATA22 Xm1DATA23 Xm1DATA24 Xm1DATA25 Xm1DATA26 Xm1DATA27 Xm1DATA28 Xm1DATA29 Xm1DATA30 Xm1DATA31
Xm1DATA[31:0] Xm1ADDR0 Xm1DATA0 Xm1CKE0 Xm1CKE1 Xm1SCLK Xm1SCLKn Xm1WEn Xm1CASn Xm1RASn Xm1DQM0 Xm1CSn0 Xm1RASn Xm1CASn Xm1WEn Xm1DQM1 Xm1DQM2 Xm1DQM3 Xm1DQS0 Xm1DQS1 Xm1DQS2 Xm1DQS3 Xm1CSn1 Xm1ADDR13

Xm1ADDR0 Xm1DATA0

TP1 TP3 TP5 TP7 TP9
M1A0 M1D0 M1CKE0 M1CKE1 M1SCLK
Xm0ADDR0 Xm0DATA0 Xm0CKE Xm0SCLK Xm0SCLKn Xm0WEndmc Xm0CASn Xm0RASn Xm0DQM0/BE0 Xm0DQM1/BE1 Xm0DQS0 Xm0DQS1 Xm0AP Xm0CSn7 Xm0ADDR10

Xm0ADDR0 Xm0DATA0

TP2 TP4 TP6 TP8

M0A0 M0D0 M0CKE0 M0SCLK

TP10 M0SCLKn TP12 M0WEn TP14 M0CASn TP16 M0RASn TP18 M0DQM0 TP20 M0DQM1 TP22 M0DQS0 TP24 M0DQS1 TP26 M0AP TP28 M0CSn7 TP102 Xm0A10
TP11 M1SCLKn TP13 M1WEn TP15 M1CASn TP17 M1RASn TP19 M1DQM0 TP21 M1DQM1 TP23 M1DQM2 TP25 M1DQM3 TP27 M1DQS0 TP29 M1DQS1 TP30 M1DQS2 TP31 M1DQS3 TP32 M1CSn1 TP103 Xm1A13

CT3 + 10uF

Xm1CSn0

TP1500Xm1CSn0

100nF 100nF 100nF 100nF 100nF 100nF

NC NC DAT2 DAT3 DAT4 NC CMD NC DAT5 NC VSS NC NC VDD NC NC CLK NC DAT6 NC VSS NC DAT7 NC DAT0 DAT1 SD_CD SD_WP
XmmcDATA1_0/ADDR_CF2 XmmcDATA1_1 XmmcDATA1_2 XmmcDATA1_3 XmmcCLK1/ADDR_CF0 nSEL_MMC1 MMC_Enable

P30/GND

1A1 2A1 3A1 4A1 5A1 1A2 2A2 3A2 4A2 5A2 BX nBE
1B1 2B1 3B1 4B1 5B1 1B2 2B2 3B2 4B2 5B2 GND
SDDATA & CLK path must be same length and route
10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K

CON802

HSMMC_DAT2 HSMMC_DAT3

HSMMC_CMD

SN74CBTLV3383DGVRE4
U802 VCC 1A1 2A1 3A1 4A1 5A1 1A2 2A2 3A2 4A2 5A2 BX nBE 1B1 2B1 3B1 4B1 5B1 1B2 2B2 3B2 4B2 5B2 GND EXT_MMC_D4 EXT_MMC_D5 EXT_MMC_D6 EXT_MMC_D7 EXT_MMC_CMD HSMMC_DAT4 HSMMC_DAT5 HSMMC_DAT6 HSMMC_DAT7 HSMMC_CMD C802 100nF
HSMMC_DAT4 HSMMC_DAT5 HSMMC_DAT6 HSMMC_DAT7 HSMMC_CLK
XmmcCMD0/ADDR_CF1 XmmcDATA1_4/mmcDATA2_0/ADDR_CF0 XmmcDATA1_5/mmcDATA2_1/ADDR_CF1 XmmcDATA1_6/mmcDATA2_2/ADDR_CF2 XmmcDATA1_7/mmcDATA2_3 XmmcCMD1/ADDR_CF1 nSEL_MMC1 MMC_Enable
XmmcCDN0/mmcCDN1 XPWM_ECLK R822 N.C SD0_nWP

SD Socket [Taisol]

SW-DIP3 R801 100K nSEL_MMC1 MMC_Enable R802 100K

CFG5 [1] [2]

OFF MMC1-Socket MMC Enable
ON MMC0-Socket MMC Disable
EXT_MMC_D0 EXT_MMC_D1 EXT_MMC_D2 EXT_MMC_D3 EXT_MMC_D4 EXT_MMC_D5 EXT_MMC_D6 EXT_MMC_D60 EXT_MMC_CMD EXT_MMC_CLK XmmcCDN0/mmcCDN1 SD0_nWP

CT801 + 10uF

C804 100nF

CON801 For HS-SPI test

D1+ D1D2+ DIEEE1394-4 C803 100nF

16 VCC 1B1 2B1 3B1 4B1

For Normal SPI test
B_SPI0_CSn B_SPI0_MISO/ADDR_CF0 B_SPI0_MOSI/ADDR_CF2 B_SPI0_CLK/ADDR_CF1 XEINT11 XEINT12 XEINT13 XEINT14 XEINT15
Xhi_A8/CE_CF0 Xhi_A9/CE_CF1 Xhi_A10/IORD_CF XspiCLK1/mmcCLK2 XspiMOSI1 XspiMISO1/mmcCMD2 XspiCS1

RP1A 2A 3A 4A

XspiCS0 XspiMISO0/ADDR_CF0 XspiMOSI0/ADDR_CF2 XspiCLK0/ADDR_CF1

SW-DIP15 S nOE

1B2 2B2 3B2 4B2 GND
XspiCS1 XspiMISO1/mmcCMD2 XspiMOSI1 XspiCLK1/mmcCLK2

RC_PWR_5V 1

For Loop test
SN74CBTLV3257 R807 100K R808 100K

SMD TYPE (BLUE) 2

XmmcCDN0/mmcCDN1 XspiCS1 XspiMISO1/mmcCMD2 XspiMOSI1 XspiCLK1/mmcCLK2 RPB_SPI1_CSn B_SPI1_MISO/MMC2_CMD B_SPI1_MOSI B_SPI1_CLK/MMC2_CLK
XmmcDATA0_0/ADDR_CF2 XmmcDATA0_1 XmmcDATA0_2 XmmcDATA0_3
B_MMC0_DATA0/ADDR_CF2 B_MMC0_DATA1 B_MMC0_DATA2 B_MMC0_DATA3

P29/GND

B_SPI1_MISO/MMC2_CMD B_SPI1_CSn B_SPI1_MOSI B_MMC0_DATA0/ADDR_CF2 B_MMC0_DATA2 B_CDn0/CDn1 B_MMC1_CMD/KP_COL1/ADDR_CF1 B_MMC1_DATA1/KP_COL3 B_MMC1_DATA3/KP_COL5 B_MMC1_DATA5/MMC2_DATA1/KP_COL7/ADDR_CF1 B_MMC1_DATA6/MMC2_DATA2/ADDR_CF2 B_MMC1_DATA7/MMC2_DATA3 XdacOUT_1 Xadc_AIN1 Xadc_AIN3 Xadc_AIN5 VDD3.3V Xadc_AIN7

QTS-075-03-F-D-A

J1 XPWM_TOUT1 XPWM_TOUT0 XPWM_ECLK CON4 Size A3 Date:
Title SMDK6400 (S3C6400 Evaluation Board) Document Number B-to-B Connector Tuesday, May 29, 2007 Sheet

Rev 0.of 15

R1 R5 SW-SLIDE4
100K 100K VDD3.3V nCS_AMD nCS_SRAM nCS_EXT

AMD Flash Memory(SOCKET)

B_ADDR[26:0] U1 B_DATA[15:0] B_ADDR[26:0] U2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 nCE nOE nWE nRY/BY nRESET nBYTE VDD+ OR AM29LV160BB 10uF/16V 100nF B_DATA0 B_DATA1 B_DATA2 B_DATA3 B_DATA4 B_DATA5 B_DATA6 B_DATA7 B_DATA8 B_DATA9 B_DATA10 B_DATA11 B_DATA12 B_DATA13 B_DATA14 B_DATA15 nCS_AMD B_OEn/IORD_CF VDD3.3V B_WEn/nIOWR_CF XnRESET C1 CT2 C2 100nF 10uF/16V + CT1 VDD3.3V B_ADDR1 B_ADDR2 B_ADDR3 B_ADDR4 B_ADDR5 B_ADDR6 B_ADDR7 B_ADDR8 B_ADDR9 B_ADDR10 B_ADDR11 B_ADDR12 B_ADDR13 B_ADDR14 B_ADDR15 B_ADDR16 B_ADDR17 B_ADDR34 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 VCC VCC VSS VSS

B_CSn_0

CFGB1:nCS0 SROM Selector [3]
B_DATA0 B_DATA1 B_DATA2 B_DATA3 B_DATA4 B_DATA5 B_DATA6 B_DATA7 B_DATA8 B_DATA9 B_DATA10 B_DATA11 B_DATA12 B_DATA13 B_DATA14 B_DATA15

External SRAM NOR(AMD)

B_CSn_1
B_ADDR1 B_ADDR2 B_ADDR3 B_ADDR4 B_ADDR5 B_ADDR6 B_ADDR7 B_ADDR8 B_ADDR9 B_ADDR10 B_ADDR11 B_ADDR12 B_ADDR13 B_ADDR14 B_ADDR15 B_ADDR16 B_ADDR17 B_ADDR18 B_ADDR19 B_ADDR20 B_ADDR21

[2] [1]

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 VSS0 VSS1
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16
SW-SLIDE4 R3 R4 R5 R5 SW-SLIDE4 100K 100K 100K 100K nCS_AMD nCS_SRAM nCS_CS8900 nCS_EXT
CFGB2:nCS1 SROM Selector [4] [3] [2] [1] External CS8900 SRAM NOR(AMD)

B_CSn_2

WE LB UB OE CS
B_WEn/nIOWR_CF B_nBE0/Xm0DQM0 B_nBE1/Xm0DQM1 B_OEn/IORD_CF nCS_SRAM
CFGB3:nCS2 SROM Selector CFGB4:nCS3 External [4] [3] [2] [1] CS8900 XD card NAND

B_CSn_3

nCS_NAND nCS_XD nCS_CS8900 nCS_EXT
AM29LV800BB (with Socket) (1MB)
SW-SLIDE4 R5 SW-SLIDE4 100K nCS_NAND nCS_XD nCS_CS8900 nCS_EXT

K6X4016T3F_1

B_ADDR1 B_ADDR3 B_ADDR5 B_ADDR7 B_ADDR9 B_ADDR11 B_ADDR13 B_ADDR15 B_ADDR17 B_ADDR19 B_ADDR21 B_ADDR23 B_ADDR25 B_DATA1 B_DATA3 B_DATA5 B_DATA7 B_DATA9 B_DATA11 B_DATA13 B_DATA15 SPI_KEYMOSI SPI_KEYCLK
XhiWEn/CF_IOWR Xhi_A1/ADDR_CF1/KP_COL1 Xhi_A3/KP_COL3 Xhi_A5/KP_COL5 Xhi_A7/KP_COL7 Xhi_A9/CE_CF1 Xhi_A11/IOWR_CF B_DATA[15:0] 2 J1302
XhiCSn_sub/CF_IORD XhiOEn/CF_IORDY
Xhi_A0/ADDR_CF0/KP_COL0 Xhi_A2/ADDR_CF2/KP_COL2 Xhi_A4/KP_COL4 Xhi_A6/KP_COL6 Xhi_A8/CE_CF0 Xhi_A10/IORD_CF Xhi_A12/IORDY_CF
TP20 TP21 TP22 Xhi_D1/DATA_CF1 Xhi_D3/DATA_CF3 Xhi_D5/DATA_CF5 Xhi_D7/DATA_CF7 Xhi_D9/DATA_CF9/KP_ROW1 Xhi_D11/DATA_CF11/KP_ROW3 Xhi_D13/DATA_CF13/KP_ROW5 Xhi_D15/DATA_CF15/KP_ROW7 Xhi_D17/DATA_CF9 XEINT8/ADDR_CF0
Xhi_D0/DATA_CF0 Xhi_D2/DATA_CF2 Xhi_D4/DATA_CF4 Xhi_D6/DATA_CF6 Modem_nReset Xhi_D8/DATA_CF8/KP_ROW0 Xhi_D10/DATA_CF10/KP_ROW2 Xhi_D12/DATA_CF12/KP_ROW4 Xhi_D14/DATA_CF14/KP_ROW6 Xhi_D16/DATA_CF8
SPI_KEYMISO SPI_KEYnSS 1 XEINT4/KP_ROW4 XEINT3/KP_ROW3 B_nBE1/Xm0DQM1 B_nBE0/Xm0DQM0 XuTXD_2/ExdACK/IrTXD/ADDR_CF1 XuTXD_3/ExdACK/IrTXD TP23

XnRSTOUT B_WAITn/IORDY

R82 R83

XuRXD_0 XuTXD_0

XuRXD_2/ExdREQ/IrRXD/ADDR_CF0 XuRXD_3/ExdREQ/IrRXD/ADDR_CF2 XhiINTR AP_nReset LCD_nReset_byHost XuTXD_2/ExdACK/IrTXD/ADDR_CF1 XuTXD_3/ExdACK/IrTXD R(N.C)

QTE-040-01-L-D-EM2

0(N.C)
XuRXD_2/ExdREQ/IrRXD/ADDR_CF0 XuRXD_3/ExdREQ/IrRXD/ADDR_CF2
1 B_SPI0_MOSI/ADDR_CF2 B_SPI0_MISO/ADDR_CF0 B_SPI0_CSn B_SPI0_CLK/ADDR_CF1 R84 R85 R86 R0 SPI_KEYMOSI SPI_KEYMISO SPI_KEYnSS SPI_KEYCLK External Keyboard B/D JF01/JF02.

QSE-040-01-L-D-EM2

JFSMDK6400 Base B/D

JF01 1

Title SMDK6400 (S3C6400 Evaluation Board) Size A3 Date: Document Number External Bus connector Tuesday, May 29, 2007 Sheet 4 of 15 Rev 0.1

B_OEn/IORD_CF

2 SN74LVC1G32DBV 3

RVDD3.3V

B_ADDR12 R90 NC B_WEn/nIOWR_CF 2 SN74LVC1G32DBV 3 VDD3.3V nCS_CS8900 B_WAITn/IORDY B_DATA[15:0] B_DATA0 B_DATA1 B_DATA2 B_DATA3 B_DATA4 B_DATA5 B_DATA6 B_DATA7 B_ADDR19 B_ADDR18 B_ADDR17 B_ADDR16 B_ADDR15 B_ADDR14 B_ADDR13 VDD3.3V B_ADDR[26:0] 5

XnRSTOUT

SN74LVC1G04DBV 51 VDD3.3V RESET SD7 SD6 SD5 SD4 DVSS4 DVDD4 SD3 SD2 SD1 SD0 IOCHRDY AEN nIOW nIOR SA19 SA18 SA17 DVSS3A DVDD3 DVSS3 SA16 SA15 SA14 SA13
Header Unload TPR1% 1 nHC1 (nHC1) (nPWDN_ETH)

CT6 + 10uF/16V

C15 100nF

C16 100nF

C17 100nF

C18 100nF

C19 560pF R93 R95 CT_T2 TDCT_T1 TD+ RD+ CT_R1 RDCT_R1% 4.99K,1%

1 RD2 2

TP25 IRQ_LAN

Shield Shield

20.0Mhz
AVSS0 nELCS EECS EESK EEDATAOUT EEDATAIN nCHIPSEL DVSS1 DVDD1 DVSS1A DMARQ2 nDMACK2 DMARQ1 nDMACK1 DMARQ0 nDMACK0 nCSOUT SD15 SD14 SD13 SD12 DVDD2 DVSS2 SD11 SD10
nTEST nSLEEP nBSTAT/nHC1 DI+ DICI+ CIDO+ DOAVDD2 AVSS2 TXD+ TXDAVSS1 AVDD1 RXD+ RXDRES AVSS3 AVDD3 AVSS4 XTAL1 XTAL2 nLINKED/nHC0 nLANLED

C100nF

R114 VDD3.3V C31 2.2nF (N.C) 0 (N.C) RNRDY FB INITG IN GND REF FBP FBN MAX1779 VDD3.3V VGL RVDD3.3V R122 12K D7 BAT54S C43 XVSYNC XHSYNC XVCLK XVDEN 1uF VGH VGL 2 R119 36K R120 180K 0 C39 1uF SC6 C40 1uF AVDD C42 C100nF 1uF TGND LX PGND SUPP DRVP SUPN DRVN NSHDN C29 D5 BAT54S 2.2uF C32 C35 1uF D6 BAT54S 1uF VGH R118 C38 1uF SC5 C37 1uF SC4 C36 1uF SC3 C30 1uF SC1 C33 1uF SC2 XVD[23:0]

SN74AVCA164245DGG

LD[23:0] LD16 LD17 LD18 LD19 LD20 LD21 LD22 LD24 VDD_LCDI 2 C49 100nF 1 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 1DIR 2DIR 1OE 2OE 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 VCCB VCCB VCCA VCCA XVD16 XVD17 XVD18 XVD19 XVD20 XVD21 XVD22 XVD23

XVD[23:0]

VSYNC_nCS_Sub HSYNC_nCS_Main VCLK_nWE VDEN_RS

SC4 SC3 XEINT5/KP_ROW5

LCD_nRESET

0 VDD3.3V

SC2 SC1

0 VDD_LCDI

Xadc_AIN4 Xadc_AIN5 Xadc_AIN6 Xadc_AIN7

R124 R126 R127 R128

TSYM TSYP TSXM TSXP
XVDEN C44 C45 1uF (N.C) 1uF C46 1uF C47 1uF C48 1uF

JAE:FF0360SA1

ADC CON5

LTV350QV_F06

Xadc_AIN1 Xadc_AIN3 Xadc_AIN5 Xadc_AIN7
Xadc_AIN0 Xadc_AIN2 Xadc_AIN4 Xadc_AIN6

2.54mm header 10pin

16 VCC 1B1 2B1 3B1 4B4 5
VDD3.3V L2 LED+ 10uH R129 CZHCS750 C51 106
5 HEADCONN_5P 1B2 2B2 3B2 4B2 GND 8 SPI_LCDCLK SPI_LCDMOSI SPI_LCDnSS TP26 SPI_LCDMISO

0.28V ~ 3.56V

1K RU20 20K R135 20K R131 VCOM 5.6K XPWM_TOUT1 4
B_SPI1_CLK/MMC2_CLK B_SPI1_MOSI B_SPI1_MISO/MMC2_CMD VDD3.3V B_SPI1_CSn

1A 2A 3A 4A

1N4148

(4.9V)

1K R133 SHDN FB FB 3 LED-

R134 100K

JUMPERR137 3.3K

3.28V ~ 0.08V

SN74CBTLV3257

LM2733

R136 62

LM8261M5_0 2

LCD_SPI J3 1-2

EXT_SPI 2-3

R138 200
Title SMDK6400-BASE (S3C6400)Evaluation Board) Size A3 Date: Document Number LANDSCAPE / RGB24bit LCD Tuesday, May 29, 2007 Sheet

LD22 LD23

R139 R140 R141 R142 R143 R144 R145 R146 R147 R148 R149 R150
SYS_VSYNC RGB_LD22 SYS_nOE RGB_LD23 SYS_RS RGB_VDEN SYS_nWE RGB_VCLK SYS_nCS_Sub RGB_VSYNC SYS_nCS_Main RGB_HSYNC
* Note: Samsung LCD LTS222QV-F01 (2.22")
Logic Voltage : 1.7/2.8/3.3V DC/DC Voltage : 2.5/2.8/3.3V Current : Stand-by 30 ~ 100uA Current : Still 5 ~ 9mA Current : Full 6 ~ 10mA

VDEN_RS

VCLK_nWE VSYNC_nCS_Sub HSYNC_nCS_Main

SW-SLIDE8

SW-SLIDE4 C52 + 10uF/10V 100nF C53
VCI40_2.8V VCC39_2.8V RGB/CPUn IF_SHARE DOTCLK HSYNC VSYNC SCL SI BWS2 DTX1 DTX2 BWS0 BWS1 PSX D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 nRESET nRD nWR RS nCS GND2 GND1
LD0 LD18 LD1 LD19 LD2 LD20 LD3 LD21 LD4 LD22 LD5 LD23 LD6 LD7
R151 R501 R152 R502 R153 R503 R154 R504 R155 R505 R156 R506 R157 R158 R159 R168 R169 R170 R171 R172 R173 R174 R176 R177
0 open 0 open 0 open 0 open 0 open 0 open 0 0
TLCD_D0 TLCD_D1 TLCD_D2 TLCD_D3 TLCD_D4 TLCD_D5 TLCD_D6 TLCD_D7 TLCD_D8 TLCD_D9 C54 TLCD_D10 1nF TLCD_D11 TLCD_D12 TLCD_D13 TLCD_D14 TLCD_D15 TLCD_D16 TLCD_D1 TSYM TSXM TSYP TSXP M60-04-30-134P Mitsumi C55 1nF
RGB_VCLK RGB_HSYNC RGB_VSYNC SPI_LCDCLK SPI_LCDMOSI
R160R161R162R163R164R165R166R167
LD8 LD9 LD10 LD11 LD18 LD19 LD20 LD1 TP27 TP28 TP29 TP30 LD12 LD13 LD14 LD15 LD16 LD17
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
TLCD_D17 TLCD_D16 TLCD_D15 TLCD_D14 TLCD_D13 TLCD_D12 TLCD_D11 TLCD_D10 TLCD_D9 TLCD_D8 TLCD_D7 TLCD_D6 TLCD_D5 TLCD_D4 TLCD_D3 TLCD_D2 TLCD_D1 TLCD_D0 R175

Main LCD Touch Screen

LCD_nRESET_byHost LCD_nRESET

R1307 R1306

TLCD_D[17:0]
070507: Changed for LCD By-Pass Test
SYS_nOE SYS_nWE SYS_RS SYS_nCS_Main SYS_nCS_Sub

R178 R179

0 JAE_FF0140SA1 NC
+ C56 C57 10uF/16V 2 VDD3.3V + C58 100nF

10uH 1

2.2uH LQH32CN2R2M33
Vo = 0.6V * (1+R2/R1)= 3.3V R2 = (Vo/0.6V - 1) * R1
J2 VDD_DISP XPWM_TOUT1 TP31 TP32 C61 33uF/6.3V B_PWR_5V C62 100nF C63 33uF/6.3V + VDD3.3V J2 J2 VDD_LCDI

R180 10K

R181 Unload(10K)

4.7uF/6.3V 3

IN EN REF BRT/PWM FB3 SW GND OLS FB1 FB7 6
D10 1SS355 VLED_Anode + C59 1uF/25V

R3 + C60 4.7uF/6.3V

RUN GND SW VOUT VIN 5 4

R183 450K

R500 10K
2Pin FPC Solder Type Back-Light Max 20mA (230mW)

LTC3406ES5

(600mA) (R1)
MPS MP1521EK/MSOP-10P R184 Unload(10K) RVLED_Cathode

R185 100K

07/05/07 R138 has been changed to 450K to make output voltage 3.3V
07/05/07 VDD_DISP has been separated from VDD_LCDI to be used for only WVGA Main LCD power
SMDK6400 (S3C6400) Evaluation Board

Size A3 Date:

Document Number
LCD-CPU18bpp/RGB666_240x320
Tuesday, May 29, 2007 Sheet

VDD_LCDI VDD3.3V

R365 0

R(N.C)

C64 100nF R189 SYS_VSYNC SYS_nWE SYS_nCS_Main 0 (N.C)
SYS_nCS_Sub SYS_nOE C1310 100nF

VDD_DISP

CT1310 + 10uF
VDD_DISP R1320 L45 CON1320 GND GND VCC VCC PD16(R0) PD17(R1) PD18(R2) PD19(R3) PD20(R4) PD21(R5) PD22(R6) PD23(R7) PD8(G0) PD9(G1) PD10(G2) PD11(G3) PD12(G4) PD13(G5) PD14(G6) PD15(G7) PD0(B0) PD1(B1) PD2(B2) PD3(B3) PD4(B4) PD5(B5) PD6(B6) PD7(B7) GND DOTCLK PCI HSYNC VSYNC DE GND GND Y2 X2 Y1 X1 GND LED1LED1+ LED2LED2+ molex: 51296-4593 XPWM_TOUT1 100K C1311 LED1+ R+ C1313 1uF/25V R+ C1314 1uF/25V 0.1uF R1327 R2 10uH 1
U1320 VIN CTRL LED CAP LT3491 GND3 GND2 GND1 SW 2 1
SYS_RS RGB_HSYNC R191 R193 R195 R0 RGB_VDEN TSXP TSYP TSXM TSYM LD1 LD3 LD5 LD7 LD9 LD11 LD13 LD15 LD17 LD19 LD21 XPWM_TOUT1 RGB_LD23 RXVCLK XEINT5/KP_ROW5 XHSYNC XVSYNC XVDEN TSYP TSXM TSYM TSXP LED1+ R1321 R1322 R1323 R0 XVD16 XVD17 XVD18 XVD19 XVD20 XVD21 XVD22 XVD23 XVD8 XVD9 XVD10 XVD11 XVD12 XVD13 XVD14 XVD15 XVD0 XVD1 XVD2 XVD3 XVD4 XVD5 XVD6 XVD7
RGB_VSYNC RGB_VCLK SPI_LCDnSS SPI_LCDCLK SPI_LCDMOSI LD0 LD2 LD4 LD6 LD8 LD10 LD12 LD14 LD16 LD18 LD20 R190 R192 R0 0

R197 R199

R198 R200
VDD_DISP L1311 R1331 XPWM_TOUT1 100K C1312 LED2+ R+ C1315 1uF/25V R+ C1316 1uF/25V 0.1uF R2 10uH 1
LCD_nRESET RGB_LD22 R201 0
C65 100nF QTE-040-01-L-D-EM2
U1321 VIN CTRL LED CAP LT3491 GND3 GND2 GND1 SW 2 1

RR1326 0

JF02 1
JF070507: These are added for WVGA 4.8inch LCD Module I/F

S3C6400 Base B/D

JF02/JF03.
Title SMDK6400-BASE (S3C6400 Evaluation Board) Size A3 Date:
Document Number LCD 4.8inch/LCD Ext Tuesday, May 29, 2007 Sheet
VDD_CAM VDD_CAM B_XciYDATA[7:0] 2 U31 B_XciYDATA0 B_XciYDATA1 B_XciYDATA2 B_XciYDATA3 B_XciYDATA4 B_XciYDATA5 B_XciYDATA6 B_XciYDATA7 B_XciPCLK B_XciHREF B_XciVSYNC B_XciCLK B_XciHREF Xi2cSDA B_XciRSTn GND0 GND1 GND2 GND3 SN74AVCA164245 GND7 GND6 GND5 GND21 VCCA0 VCCA1 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 1OE 2OE L : B to A H : A to B VCCBVCCB1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 1DIR 2DIR 1 24

VDD3.3V XciYDATA[7:0]

C66 100nF

Camera Interface

C67 100nF 1

VDD_CAM

XciYDATA0 XciYDATA1 XciYDATA2 XciYDATA3 XciYDATA4 XciYDATA5 XciYDATA6 XciYDATA7 XciPCLK XciHREF XciVSYNC
R204 10K B_XciYDATA[7:0] B_XciYDATA1 B_XciYDATA3 B_XciYDATA5 B_XciYDATA7 B_XciPCLK B_XciVSYNC Xi2cSCL 38 40

3.9K (N.C)

kp_COL0 kp_COL1 kp_COL2 kp_COL3 kp_COL4 kp_COL5

R308 kp_COL7

SKQYPCE010
R311 R312 R313 R314 R315 R316 R317 20K 20K C165 1nF C166 1nF C167 1nF C168 1nF C169 1nF C170 1nF C171 1nF 20K 20K 20K 20K 20K 20K
kp_ROW7 kp_ROW6 kp_ROW5 kp_ROW4 kp_ROW3 kp_ROW2 kp_ROW1 kp_ROW0

C172 1nF

30pin connecter
Document Number KeyPad Tuesday, May 29, 2007 Sheet

C176 100nF

+ C175 10uF/6.3V 6 U49 V+ GND VIN POWER VOUT VSAG 3

R322 4.7K

R323 XdacOUT_0 0
C177 33uF/10V C179 33uF/10V + +

R324 R75 R1

GND VIDEO

100nF R327 150

NJM2561

C181 100nF

+ C180 10uF/6.3V 6 U51 V+ GND VIN POWER VOUT VSAG 3

R328 4.7K

R329 XdacOUT_1 0
C182 33uF/10V C184 33uF/10V + +

CNY 4 C

100nF R331 150

Yn Cn 1

CONN_SVIDEO_12P

VDD3.3V VDD3.3V

CT29 +
C185 100nF B_MMC1_DATA0/KP_COL2/ADDR_CF2 B_MMC1_DATA1/KP_COL3 B_MMC1_DATA2/KP_COL4 B_MMC1_DATA3/KP_COL5 B_MMC1_DATA4/MMC2_DATA0/KP_COL6/ADDR_CF0 B_MMC1_DATA5/MMC2_DATA1/KP_COL7/ADDR_CF1 B_MMC1_DATA6/MMC2_DATA2/ADDR_CF2 B_MMC1_DATA7/MMC2_DATA3

TP53 TP54 TP55 TP56

B_MMC1_CMD/KP_COL1/ADDR_CF1 B_MMC1_CLK/KP_COL0/ADDR_CF0 B_CDn0/CDn1 VDD3.3V
B_SPI1_CLK/MMC2_CLK B_SPI1_MISO/MMC2_CMD
B_MMC0_CLK/ADDR_CF0 B_MMC0_CMD/ADDR_CF1 B_MMC0_DATA1
B_MMC0_DATA0/ADDR_CF2 B_MMC0_DATA2 B_MMC0_DATA3

HEADER (N.C)

Document Number HSMMC/TV Tuesday, May 29, 2007 Sheet
R332 B_PWR_5V 2 SMD TYPE (BLUE)

MMBT3904

P G G 3 SWPOLY SWITCH/1.5A C186 100nF R334 47K R335 10K 3

4 SI4423DY

RSMD TYPE (BLUE)

POWER JACK 5

VCC OUT GND 4 ININ+ 3 R342 12.7K 10K R337 330
SMD TYPE (BLUE) R338 10K XEINT12 XEINT13 XEINT14 XEINT15 R339 10K 10K R340

R341 10K

MAX6458 R343

RSMD TYPE (RED) B_PWR_5V

B_PWR_5V R346 10K D6 VDD3.3V
R345 + CT30 22uF/16V + CT31 4.7uF/16V + CT32 4.7uF/16V VDD3.3V J22 L1.5uH 2 SDR1005 R353 RESISTOR VAR (NC) R354 57.6K(1%)
100nF R347 1K R348 39K R349 100K R350 20K R(NC) C190 100pF C191 R10nF 7 100pF C9 R359 10
RUN/SS VON PGOOD VRNG ITH FCB SGND ION VFB EXTVCC LTC3778 400K BOOST TG SW SENSE+ SENSEPGND BG DRVCC INTVCC VIN 18 17

100K XEINT9/ADDR_CF1

C189 220nF

CMPSH-FDS6982 3

2 LS8JEM-T

C187 100nF

11 R2 FDS6982 1
JUMPER + CT33 + CT34 + CT35 220uF/6.3V 220uF/6.3V 10uF/6.3V

Silk EINT9

R358 + CT36 C193 4.7uF 100nF R355 100K VDD3.3V XEINT10/ADDR_CF2 R356 100K XEINT11 12.7K(1%) VDD3.3V VDD3.3V

TP60 GND