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ICX424AL

Diagonal 6mm (Type 1/3) Progressive Scan CCD Solid-state Image Sensor with Square Pixel for B/W Cameras
Description The ICX424AL is a diagonal 6mm (Type 1/3) interline CCD solid-state image sensor with a square pixel array suitable for EIA black-and-white cameras. Progressive scan allows all pixel's signals to be output independently within approximately 1/60 second. This chip features an electronic shutter with variable charge-storage time which makes it possible to realize full-frame still images without a mechanical shutter. High sensitivity and low dark current are achieved through the adoption of the HAD (HoleAccumulation Diode) sensors. This chip is suitable for applications such as FA and surveillance cameras. Features Progressive scan allows individual readout of the image signals from all pixels. High vertical resolution (480 TV-lines) still images without a mechanical shutter Square pixel Supports VGA format Horizontal drive frequency: 24.54MHz No voltage adjustments (reset gate and substrate bias are not adjusted.) High resolution, high sensitivity, low dark current Continuous variable-speed shutter Low smear Excellent anti-blooming characteristics Horizontal register: 5.0V drive 16-pin high precision plastic package (enables dual-surface standard) 16 pin DIP (Plastic)

Pin 1 2

Pin 9 H 31
Optical black position (Top View)
Device Structure Interline CCD image sensor Image size: Diagonal 6mm (Type 1/3) Number of effective pixels: 659 (H) 494 (V) approx. 330K pixels Total number of pixels: 692 (H) 504 (V) approx. 350K pixels Chip size: 5.79mm (H) 4.89mm (V) Unit cell size: 7.4m (H) 7.4m (V) Optical black: Horizontal (H) direction: Front 2 pixels, rear 31 pixels Vertical (V) direction: Front 8 pixels, rear 2 pixels Number of dummy bits: Horizontal 16 Vertical 5 Substrate material: Silicon
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

E01Z09B35

Block Diagram and Pin Configuration (Top View)
VOUT GND GND CGG V1 V2 V3 NC

Vertical register

Note) Horizontal register Note) 9

: Photo sensor

SUBCIR
Pin Description Pin No. Symbol V3 V2 V1 NC GND CGG GND VOUT GND Output amplifier gate1 GND Signal output Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Pin No. Symbol VDD SUBCIR GND SUB VL RG H1 H2 Description Supply voltage Supply voltage for the substrate voltage generation GND Substrate clock Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock
1 DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance of 1000pF.
Absolute Maximum Ratings Item Substrate clock SUB GND Supply voltage Clock input voltage VDD, VOUT, CGG, SUBCIR GND VDD, VOUT, CGG, SUBCIR SUB V1, V2, V3 GND V1, V2, V3 SUB Ratings 0.3 to +36 0.3 to +to +to +16 to +10 to +15 to +to +to +to +to +0.3 0.3 to +27.5 0.3 to +20.5 0.3 to +17.to +to +to +75 Unit V V V V V V V V V V V V V V C C C 2 Remarks
Voltage difference between vertical clock input pins Voltage difference between horizongal clock input pins H1, H2 V3 H1, H2 GND H1, H2 SUB VL SUB V2, V3 VL RG GND V1, H1, H2, GND VL Storage temperature Performance guarantee temperature Operating temperature 2 +24V (Max.) when clock width < 10s, clock duty factor < 0.1%. +16V (Max.) is guaranteed for power-on and power-off.

Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock Symbol VDD VL SUB RG Min. 14.55 Typ. 15.Max. 15.45 Unit V Remarks
1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same voltage as the VL power supply for the V driver should be used. 2 Set SUBCIR pin to open when applying a DC bias to the substrate clock pin. 3 Do not apply a DC bias to the reset gate clock pins, because a DC bias is generated within the CCD. DC Characteristics Item Supply current Symbol IDD Min. Typ. 7 Max. 9 Unit mA Remarks
Clock Voltage Conditions Item Readout clock voltage VVT VVH02 VVH1, VVH2, VVH3 VVL1, VVL2, VVL3 VVL1, VVL2, VVL3 Vertical transfer clock voltage V1, V2, V3 | VVL1 VVL3 | VVHH VVHL VVLH VVLL VH Horizontal transfer clock voltage VHL VCR VRG Reset gate clock voltage VRGLH VRGLL VRGL VRGLm Substrate clock voltage VSUB 21.5 22.5 4.75 0.05 0.8 4.5 5.2.5 5.0 5.5 0.8 0.5 23.5 Symbol Min. 14.55 0.05 0.2 7.8 8.0 6.8 Typ. 15.0 7.5 7.5 7.5 Max. Unit 15.45 0.05 0.05 7.2 7.0 8.05 0.1 1.0 2.3 1.0 1.0 5.25 0.05 V V V V V V V V V V V V V V V V V V Waveform Diagram Low-level coupling Low-level coupling Cross-point voltage High-level coupling High-level coupling Low-level coupling Low-level coupling VVL = VVL1 (VVL3)/2 (During 24.54MHz) VVL = VVL1 (VVL3)/2 (During 12.27MHz) VVH = VVH02 Remarks
Clock Equivalent Circuit Constants Item Symbol CV1 Capacitance between vertical transfer clock and GND CV2 CV3 CV12 Capacitance between vertical transfer clocks CV23 CV31 Capacitance between horizontal transfer clock and GND CH1, CH2 Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistor Vertical transfer clock ground resistor Horizontal transfer clock series resistor Reset gate clock series resistor CHH CRG CSUB R1 , R 2 R3 RGND RH1, RH2 RRG Min. Typ. 39 Max. Unit pF pF pF pF pF pF pF pF pF pF Remarks

CV12 CV1 RGND CV31 CV3 CV23 CV2

RH1 H1 CHH CH1 CH2

RH2 H2
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
Reset gate clock equivalent circuit 5
Drive Clock Waveform Conditions (1) Readout clock waveform

100% 90%

M VVT 10% 0% tr twh tf 0V M 2
Note) Readout clock is used by composing vertical transfer clocks V2 and V3.
(2) Vertical transfer clock waveform

VVHL VVH1 VVHH VVH

VVLH VVL01 VVL1 VVLL VVL

VVHH VVHL

VVLH VVL2 VVLL VVL

VVL03 VVLL

VVH = VVH02 VVL = (VVL01 + VVL03)/2 VVL3 = VVL03
VV1 = VVH1 VVL01 VV2 = VVH02 VVL2 VV3 = VVH3 VVL03
(3) Horizontal transfer clock waveform

H1, H2

H2 90% VCR VH twl VH 2 10% H1 two VHL tr twh tf
Cross-point voltage for the H1 rising side of the horizontal transfer clocks H1 and H2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks H1 and H2 is two. (4) Reset gate clock waveform

tr twh tf

VRGH RG waveform twl VRG Point A VRGLH VRGLL VRGLm VRGL
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VRG = VRGH VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform
M VSUB 10% VSUB 0% (A bias generated within the CCD) M 2 tf
Clock Switching Characteristics (Horizontal drive frequency: 24.54MHz) twh Item Readout clock Vertical transfer clock Horizontal transfer clock Symbol VT V1, V2, V3 H1 H2 10.5 14.6 10.5 14.8 10.5 14.6 10.5 14.6 25.8 6.4 10.5 6.4 10.0.5 twl tr tf Unit s 250 6.4 10.5 6.4 10.0.5 ns ns ns s When draining charge Remarks During readout When using CXD3400N tf tr 2ns
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 2.3 2.5 0.0.5
Reset gate clock RG Substrate clock SUB

0.75 0.9

Item Horizontal transfer clock

Symbol H1, H2

two Min. Typ. Max. 10.5 14.6

Unit ns

Remarks 1
Clock Switching Characteristics (Horizontal drive frequency: 12.27MHz) twh Item Readout clock Vertical transfer clock Horizontal transfer clock Symbol VT V1, V2, V3 H1 H31.30 62.17.3 0.26.5 31.13 twl tr tf Unit s 17.3 0.ns ns ns s When draining charge Remarks During readout When using CXD3400N tf tr 2ns

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 4.6 5.0 0.0.5

1.5 1.8

two Min. Typ. Max. 21.5 25.5
1 The overlap period of twh and twl of horizontal transfer clocks H1 and H2 is two.
Image Sensor Characteristics Item Sensitivity Saturation signal Smear Symbol Min. S Vsat Sm 2 0.5 0.5 Typ. Max. Unit 880 mV mV dB % % mV mV % Measurement method Zone 0, I Zone 0 to II' Ta = 60C Ta = 60C Ta = 60C Remarks

(Ta = 25C)

1/30s accumulation conversion value
Video signal shading SH Dark signal Dark signal shading Lag Vdt Vdt Lag
Note) All image sensor characteristic data noted above is for operation in 1/60s progressive scan mode.
Zone Definition of Video Signal Shading

659 (H) 12 H 8 V 10 H 8

494 (V)
Zone 0, I Zone II, II' V 10
Ignored region Effective pixel region

Measurement System

CCD signal output [A]

Signal output [B]

Note) Adjust the amplifier gain so that the gain between [A] and [B] equals 1.
Image sensor readout mode The diagram below shows the output methods for the following three readout modes.
(1) Progressive scan mode

(2) Field readout mode

1. Progressive scan mode In this mode, all pixel signals are output in non-interlace format in 1/60s. All pixel signals within the same exposure period are read out simultaneously, making this mode suitable for high resolution image capturing. 2. Field readout mode All pixels are readout, 2-line transfer is performed during H blanking period and 2 pixels are added by horizontal register. (However, guarantees only at the time of a 12MHz drive.) (3) Center scan mode
Undesired portions (Swept by vertical register high-speed transfer)
Picture center cut-out portion
3. Center scan mode This is the center scan mode using the progressive scan method. The undesired portions are swept by vertical register high-speed transfer, and the picture center portion is cut out. There are the mode (120 frames/s) which outputs 222 lines of an output line portion, and the mode (240 frames/s) which outputs 76 lines. 10
Image Sensor Characteristics Measurement Method Measurement conditions (1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. (2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value measured at point [B] of the measurement system. Definition of standard imaging conditions (1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. (2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After setting the electronic shutter mode with a shutter speed of 1/250s, measure the signal voltage (Vs) at the center of the screen, and substitute the value into the following formula. S = Vs 250 [mV] 30 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with the average value of the signal output, 150mV, measure the minimum value of the signal output. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the luminous intensity to 500 times the intensity with the average value of signal output, 150mV. Then after the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (VSm [mV]) of the signal output and substitute the value into the following formula. Sm = 20 log VSm 10 [dB] (1/10V method conversion value)

4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 150mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax Vmin)/[%] 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 11
6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. Vdt = Vdmax Vdmin [mV] 7. Lag Adjust the signal output generated by strobe light to 150mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/150) 100 [%]
Light Strobe light timing
Signal output 150mV Output

Vlag (lag)

Drive Circuit

15V 100k

0.1 7.5V 1/35V 1 NC V3 V2 V1 CGG 0.1 GND GND 0.1 VOUT 8 4.7k H2 H1 RG VL SUB ICX424 (BOTTOM VIEW) GND 1000p 2SC4250 CCD OUT

H2 2200p 0.1 3.3/16V 1M

CXD3400N

3.3/20V 0.01 9

Spectral Sensitivity Characteristics (Excludes lens characteristics and light source characteristics)
1.0 0.9 0.8 0.7 Relative Response 0.6 0.5 0.4 0.3 0.2 0.Wave Length [nm] 1000
Drive Timing Chart (Vertical Sync)

Progressive Scan Mode

"a"
Drive Timing Chart (Vertical Sync "a" Enlarged)
Progressive Scan Mode/Center Scand Mode

"a" Enlarged

Drive Timing Chart (Horizontal Sync)

Center Scan Mode 1

"d"
"a" "b" "c"

"b"

245 246

356 357

136 137
Center Scan Mode 1 (Frame Shift) ("b")

10920 bits = 14H

Center Scan Mode 1 (High-speed Sweep) ("d")

12480 bits = 16H

Center Scan Mode 2

105 106

283 284

209 210

Center Scan Mode 2 (Frame Shift) ("b")

15600 bits = 20H

Center Scan Mode 2 (High-speed Sweep) ("d")

18720 bits = 24H

Field Readout Mode

273 274

Drive Timing Chart (Vertical Sync "a", "b" Enlarged)

"b" Enlarged

Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W soldering iron with a ground wire and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero-cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operations as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.)

Cover glass

50N Plactic package Compressive strength

1.2Nm Torsional strength

b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. 27
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) The notch of the package is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch of the package. e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD characteristics. d) This package has 2 kinds internal structure. However, their package outline, optical size, and strength are the same.
Structure A Package Chip Metal plate (lead frame)

Structure B

Cross section of lead frame
The cross section of lead frame can be seen on the side of package for structure A.

Package Outline

Unit: mm

16 pin DIP (450mil)

0 to 9

11.43 2.5

V 2-R0.5

H 10.3 12.2 0.1 B'

1.2 3.35 0.15

9.5 11.4 0.1

1.2 11.6

1.27 3.5 0.3

1. A is the center of the effective image area.
2. The two points B of the package are the horizontal reference. The point B' of the package is the vertical reference. 3. The bottom C of the package, and the top of the cover glass D are the height reference. 4. The center of the effective image area relative to B and B' is (H, V) = (6.1, 5.7) 0.15mm. 5. The rotation angle of the effective image area relative to H and V is 1. 6. The height from the bottom C to the effective image area is 1.41 0.10mm. The height from the top of the cover glass D to the effective image area is 1.94 0.15mm. 7. The tilt of the effective image area relative to the bottom C is less than 50m. The tilt of the effective image area relative to the top D of the cover glass is less than 50m. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 9. The notches on the bottom of the package are used only for directional index, they must not be used for reference of fixing.

0.69 1.27 0.46

(For the first pin only)

PACKAGE STRUCTURE

PACKAGE MATERIAL

Plastic

LEAD TREATMENT

GOLD PLATING

LEAD MATERIAL

42 ALLOY

PACKAGE MASS

Sony Corporation

DRAWING NUMBER

AS-C2.2-01(E)