Technical Reference
DPOJET PCI Express Setup Library Methods of Implementation (MOI) for Verification, Debug and Characterization 077-0267-00

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Methods of Implementation

Table of Contents

Introduction to the DPOJET PCI Express Setup Library.. 3 PCI Express Specifications... 4
2.1 2.2 2.3 2.4 2.5 2.6 2.7 Differential Transmitter (TX) Output Specifications..4 Differential Receiver (RX) Input Specifications..3 Add-In Card Transmitter Path Compliance Specifications.5 System Board Transmitter Path Specifications..7 PCI ExpressModule Specifications..9 PCI Express External Cabling Specifications..12 PCMCIA ExpressCardTM Specifications..14
Preparing to Take Measurements... 16
3.1 3.2 Required Equipment...16 Probing Options for Transmitter Testing...17 SMA Input Connection...17 ECB pad connection...18 Dual Port Connection...19 3.3 Running the Test...20
PCI Express Library Contents... 22 Parameter Definitions and Method of implementation.. 23
5.1 5.2 5.3 5.4 5.5 5.6 5.7 UI (Unit Interval) MOI...23 TX Differential Pk-Pk Output Voltage MOI...24 TX De-Emphasis Ratio...25 TX Minimum Pulse Width MOI..27 TX Rise/Fall Time Mismatch MOI...28 Minimum TX Eye Width MOI...28 TX Median-to-Max Jitter MOI..30
DPOJET PCI Express Measurements 1

Revision History

MOI Version 1.0 Date 12/17/2008 Summary of Change(s) Initial Document DPOJET Version
1 Introduction to the DPOJET PCI Express Setup Library1
This document provides the procedures for making PCI Express measurements with Tektronix DPO/DSA70000 Series Oscilloscopes with DPOJET (Jitter and Eye Analysis Tools) and probing solutions. DPOJET and its PCI Express Setup Library provide transmitter path measurements (amplitude, timing, and jitter), waveform mask, and limits testing described in multiple variants of the PCI Express specifications.
Table 1 Supported Specifications in the DPOJET Setup Library Test Methods Spec Revision Rev 1.1 PCI Express Specification Title Test Points Defined

Rev1.1

Base Specification
Transmitter & Receiver (Section 4.3)

Rev 1.1

CEM Specification
System and Add-In Card (Section 4.7) Reference Clock (Section 2.1)

Rev 1.0 Rev 1.0

Express Module Specification PCMCIA Express Card Standard
Transmitter Path and System Board (Section 5.4) Host System Transmitter Express Card Transmitter (Section 4.2.1.2)

Rev 1.0 Rev2.0 Rev 2.0

External Cabling Specification
Transmitter and Receiver Path (Section 3.3) Transmitter & Receiver (Section 4.4) Mobile Low Power Transmitter (Section 4.4)

Rev 2.0

System and Add-In Card (3.5 & 6dB DeEmphasis) (Section 4.7)

Rev3.0

Rev 0.5
Transmitter (Section 4.1.2)
Refer to http://www.pcisig.com/specifications/pciexpress/ for the latest specifications.
Disclaimer: The tests provided in DPOJET (which are described in this document) do not guarantee PCI Express compliance. The test results should be considered Pre-Compliance. Official PCI Express compliance and PCI-SIG Integrator List qualification is governed by the PCI-SIG (Special Interest Group) and can be achieved only through official PCI-SIG sanctioned testing.
In this document, for all references to the PCI Express Base Specifications and Card Electrical Mechanical (CEM) specifications, refer to all versions of the Spec. (Rev 1.1, 2.0, and 3.0). Differences between the specifications are specifically called out when appropriate. In the subsequent sections, step-by-step procedures are described to help you perform PCI Express measurements. Each measurement is described as a Method of Implementation (MOI). For further reference, consult the Compliance checklists and tools offered to PCI-SIG members at www.pcisig.com.

2 PCI Express Specifications
As shown in Table 1, Electrical Specifications for PCI Express are provided in multiple documents. This section provides a summary of the measurement parameters measured in the DPOJET Setup Library module and how they are related to the symbol and test limits in the specification.
Differential Transmitter (TX) Output Specifications
The following table shows the available measurements in the PCE Module and their test limits defined in each of the Base Specifications.
Table 2- Supported Base Specification transmitter measurements Specification Parameter Symbol(s) NA DPOJET Measurement
See Setup by Data Rate >>

2.5GT/s Rev1.1/Rev2.0

1st Order PLL Fc: 1MHz Emulates 1st Order filter at 1.5MHz with 75% edge density of Compliance Pattern

5.0 GT/s Rev2.0

2nd Order PLL CDR w/.707 Damping Fc: 1.0MHz - And 3rd Order LPF Fc: 1.5MHz Emulates Step Function Filter at 1.5MHz

8.0 GT/s Rev3.0

1st Order PLL Fc: 10MHz Assumes Scrambled Compliance Pattern with 50% Edge Density

Clock Recovery

Unit interval
PCIe UI (min/max) SSC filtered with 3rd order HPF: Fc = 198kHz PCIe T-Tx-Diff-PP
399.98 (min) 400.12 (max)
199.94 (min) 200.06 (max)
124.9625 (min) 125.0375 (max)
Differential p-p TX voltage swing

VTX DIFFp p

VTX-SWING VTX-EYE-FULL VTX-SWING-LOW VTX-EYE-HALF

0.8 V (min) 1.2 V (max)

TBD 1.2 V (max)

Eye Height

Low power differential p-p TX voltage swing De-emphasized output voltage ratio

PCIe T-Tx-Diff-PP

Not Specified

0.4 V (min) 0.7 V (max)

Eye Height PCIe T/nT Ratio -3.0 dB (min) -4.0 dB (max)

0.1 V (min) 0.8 V (max)

VTX DE RATIO
-5.5 dB (min) -6.5 dB (max) or -3.0 dB (min) -4.0 dB (max)
Methods of Implementation Specification Parameter Instantaneous lane pulse width Transmitter eye including all jitter sources Maximum time between the jitter median and maximum deviation from the median Deterministic jitter Symbol(s) TMIN-PULSE DPOJET Measurement PCIe Tmin-Pulse 2.5GT/s Rev1.1/Rev2.0 Not Specified 5.0 GT/s Rev2.0 0.9UI (min) 150 ps (min) 8.0 GT/s Rev3.0 Not Specified

TTX EYE

tTX-EYE_TJ
For Rev1.1: Eye Width For Rev2/3: PCIe T-TXA PCIe Med-Mx Jitter
.75 UI (min) 300 ps (min).125 UI (min/max)
.75 UI (min) 150 ps (min) Not Specified
TTX-EYEMEDIAN-toMAXJITTER

TTX-DJ-DD

0.15 UI (max) 30 ps (max)
Tx RMS jitter < 1.5MHz

TTX-LF-RMS

TIE1 Jitter w/ 3rd Order LPF Fc: 1.5 MHz Std. Deviation PCIe T-Tx-Rise PCIe T-Tx-Fall PCIe T-RF-Mismch Common Mode Pk-Pk

3.0 ps (max)

D+/D- TX output rise/fall Time 2

Tx rise/fall mismatch

TTX RISE TTX FALL
TRF-MISMATCH VTX-CM-AC-PP
0.125 UI (min) 50 ps (min) Not Specified Not Specified
0.15 UI (min) 30 ps (min) 0.1 UI (max) 100 mV (max)
Not Specified 100 mV (max)
AC common mode output voltage AC common mode output voltage Absolute delta of DC common mode voltage between D+ and D-

VTX-CM-AC-P

Common Mode Rev1.1 : StdDev
20mV RMS (max) 0 V (min) 25 mV (max)

20mV RMS (max)

VTX CM DC LINE DELTA

Common Mode Mean

0 V (min) 25 mV (max)
Rise/Fall time measurements in DPOJET are compliant to the Rev1.0a and Rev1.1 specification. For Gen2, rise and fall time is limited to TF2 and TR2 as defined in section 4.3.3.8 of the Base Specification
Differential Transmitter (TX) Compliance Eye Diagrams
Figure 1a shows the eye mask definitions for the Rev1.1 Base specification. It provides an example of a transmitter mask for a signal with de-emphasis. Transition and non-transition bits must be separated to perform the mask testing. The amplitude and jitter mask geometries are derived from the amplitude and jitter specifications. Low power transmitter variants in both Gen1 and Gen2 do not use de-emphasis (This is shown in Figure 1b).

Fail Pass Voltage

Fail 0.0 X1 1XNormalized Time (UI) 1X1.0
Rev1.1/2.0 Transmitter eye masks for transition and non-transition bits
Rev1.1/2.0 transmitter eye mask for low power variant where deemphasis is not used
Rev3.0 transmitter eye mask definition Mask Geometries TBD for Gen3.
Figure 1: PCI Express Transmitter Eye Mask Definitions
Differential Receiver (RX) Input Specifications
The following table shows the available measurements in the PCE Module and their test limits defined in each of the Base specifications.
Table 3 Supported base specification receiver measurements DPOJET Measurement

Eye height of transition bits

Eye Height1

.514 V (min) 1.2 V (max)

3.5dB De-emphasis

.380 V (min) 1.2 V (max)

6.0dB De-emphasis

.306 V (min) 1.2 V (max) Eye height of nontransition bits VTXA_d Eye Height2.360 V (min)
.260 V (min) 1.2 V (max) Eye width with sample size of 106 UI Jitter eye opening at BER 10-12 Maximum median-max jitter outlier with sample size of 106 UI Total Jitter at BER 10-12 Deterministic Jitter at BER 10-12 TTXA In Rev1.1 TTXA In Rev2.0 Eye Width For Rev1.1: Eye Width For Rev2/3: PCIe T-TXA JTXA-MEDIAN-toMAX-JITTER
287 ps (min) 274 ps (min) Informative 56.5 ps (max)
Not Specified 123 ps (min) with Crosstalk Not Specified

TBD TBD

Tj at BER 10-12 Max Dj

TJ@BER DJ

Not Specified Not Specified

77 ps (max) 57 ps (max)

Add-In Card Eye Diagrams
The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 4.
Figure 3: Add-in card compliance eye masks
System Board Transmitter Path Specifications
Table 5 is derived from the Electrical Mechanical Specifications (CEM). See the CEM Specification for additional notes and test definitions.
Table 5 Supported CEM System Board Measurements DPOJET Parameter Symbol Measurement Clock Recovery NA
2nd Order PLL CDR w/.707 Damping Fc: 1.0MHz - And 1st Order LPF Fc: 1.5MHz Emulates 3rd Order 3500:250 Method
Explicit Clock 2nd Order PLL Clock Multiplier=50 CDR w/.707 Damping Fc: 1.0MHz Emulates Step Function Filter at 1.5MHz 199.94 (min) 200.06 (max)
VTXS VTXS_d TTXS In Rev1.1 TTXS In Rev2.0 JTXAMEDIAN-toMAX-JITTER

. Eye Height1

.274 V (min) 1.2 V (max)
.250 V (min) 1.2 V (max).250 V (min) Not Specified 95 ps (min) with Crosstalk Not Specified
Eye height of non-transition bits Eye width with sample size of 106 UI Jitter eye opening at BER 10-12 Maximum median-max jitter outlier with sample size of 106 UI Total Jitter at BER 10-12
Eye Height2 Eye Width For Rev1.1: Eye Width For Rev2/3: PCIe T-TXA PCIe Med-Mx Jitter
.253 V (min) 246 ps (min) 233 ps (min) Informative 77 ps (max)

TBD TBD TBD TBD

Deterministic Jitter at BER 10-12
System Board Eye Diagrams
The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 5.
Figure 4: System Board Compliance Eye Masks
PCI ExpressModule Specifications
The specifications in this section are taken from the PCI Express ExpressModule specification, which is a companion specification to the PCI Express Base specification. Its primary focus is the implementation of a modular I/O form factor that is focused on the needs of workstations and servers. Measurements in the PCE module support add-in card and system transmitter path measurements at the PCI Express connector.

ExpressModule Add-In Card Transmitter Path Specifications
Table 6 is derived from Section 5.4.1 of the ExpressModule Electro-Mechanical Specifications Rev. 1.0.
Table 6 Supported ExpressModule Add-In Card Measurements DPOJET Parameter Symbol Measurement Clock Recovery NA
See Setup by Data Rate >> 1st Order PLL Fc: 1MHz Emulates 1st Order filter at 1.5MHz with 75% edge density of Compliance Pattern

Rev1.0

Eye height of transition Bits
VTXA VTXA_d TTXA In Rev1.1
Eye height of non-transition Bits Eye width with sample size of 106 UI Jitter eye opening at BER 10-12 Maximum median-max jitter outlier with sample size of 106 UI
Eye Height2 Eye Width Eye Width@BER
.360 V (min) 287 ps (min) 274 ps (min) Informative 56.5 ps (max)

JTXA-MEDIAN-toMAX-JITTER

ExpressModule Add-In Card Eye Diagrams
The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 6.
Figure 5: ExpressModule add-in card compliance eye masks
ExpressModule System Board Transmitter Path Specifications
Table 7 is derived from Section 5.4.3 of the ExpressModule Electro-Mechanical Specifications Rev. 1.0.
Table 7 Supported ExpressModule system board measurements DPOJET Parameter Symbol Measurement Clock Recovery NA

Gen1 Rev1.0

VTXS VTXS_d TTXS
Eye height of non-transition bits Eye width with sample size of 106 UI Jitter eye opening at BER 10-12 Maximum median-max jitter outlier with sample size of 106 UI
.253 V (min) 246 ps (min) 233 ps (min) 77 ps (max)

JTXA-MEDIANto-MAX-JITTER

TIE Jitter
Express Module System Board Compliance Eye Diagrams
The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table6.
Figure 6: ExpressModule system board compliance eye masks
PCI Express External Cabling Specifications
The specifications in this section are taken from the PCI Express External Cabling Specification. Its primary focus is the implementation of a cabled interconnect. Measurements in the PCE module support transmitter path and receiver path measurements. These measurements represent the test points at the transmitter end of the cable and the receiver end of the cable respectively.
External Cabling Transmitter Path Specifications
Table 8 is derived from Section 3.3.1 of the External Cabling Specification Rev. 1.0.
Table 8 Supported external cabling transmitter path measurements Parameter Symbol Clock Recovery NA DPOJET Measurement

VTXA VTXA_d TrxA @ BER 10

.654 V (min) 1.2 V (max)

Eye height of non-transition bits Jitter eye opening at BER 10-12 Eye width with sample size of 106 UI
Eye Height2 Eye Width@BER Eye Width
.450 V (min) 296 ps (min) 309 ps (min)

TrxA @ 10 Samples

Cable (Transmitter Side) Eye Diagrams
The amplitude and jitter masks are derived from the amplitude and jitter specifications.
Figure 7: Cable (transmitter side) compliance eye masks
External Cabling Receiver Path Specifications
Table 9 is derived from Section 3.3.2 of the External Cabling Specification Rev. 1.0.
Table 9 Supported CEM system board measurements Parameter Symbol DPOJET Measurement Clock Recovery NA
VRXA VRXA_d TrxA @ BER 10

.208 V (min) 1.2 V (max)

.192 V (min) 234 ps (min) 247 ps (min)
Cable (Receive Side) Eye Diagrams
Figure 8: Cable (receiver side) compliance eye masks
PCMCIA ExpressCardTM Specifications
The specifications in this section are taken from the PCMCIA ExpressCard Standard (Release 1.0). Its primary focus is a small modular add-in card technology based on PCI Express and USB interfaces. Measurements in the PCE module support host system and ExpressCard transmitter path measurements.
ExpressCard - Module Transmitter Path Specifications
Table 10 is derived from Section 4.2.1.3.2 of the ExpressCard Specification Release 1.0.
Table 10 Supported ExpressCard transmitter path measurements DPOJET Parameter Symbol Measurement Clock Recovery NA

Release 1.0

VTXA VTXA_d TTXA

538 V (min) 1.2 V (max)

Eye height of non-transition bits Eye width across any 250 UIs
Eye Height2 Eye Width@BER
.368 V (min) 237 ps (min)
ExpressCard Transmitter Path Eye Diagrams
The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 10.
Figure 9: ExpressCard Module Transmitter compliance eye masks
ExpressCard - Host System Transmitter Path Specifications

Table 11 from Section 4.2.1.3.2 of the ExpressCard Specification Release 1.0.
Table 11 Supported ExpressCard Host System Transmitter Path Measurements DPOJET Parameter Symbol Release 1.0 Measurement Clock Recovery NA
See Setup by Data Rate >> 2nd Order PLL CDR w/.707 Damping Fc: 1.0MHz - And 1st Order LPF Fc: 1.5MHz Emulates 3rd Order 3500:250 Method

VtxS VtxS_d TTxS

.262 V (min) 1.2 V (max)
.247 V (min) 183 ps (min)
ExpressCard Host System Eye Diagrams
The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 11.
Figure 10: ExpressCard Host System compliance eye masks
3 Preparing to Take Measurements

Required Equipment

The following equipment is required to take the measurements: Oscilloscope Selection: o Rev 1.1 (2.5 GT/s) The PCI-SIG recommends a minimum of 6 GHz system BW. All models in the Tektronix DPO/DSA70000 series meet this requirement. o Rev 2.0 (5 GT/s) DPO/DSA70000 12.5 GHz and above are recommended for 5GT/s and above and required for Base Specification transmitter measurements. o Rev 3.0 (8 GT/s) DPO/DSAGHz and above are recommended for 8GT/s measurements. DPOJET software (Version 2.1 or above) with PCI Express Measurements (Opt. PCE) installed. Probes See Section 3.2 for probing options. Test Fixtures o Test Fixtures for System and Add-In card testing are available from the PCI-SIG. Rev1.1 Fixtures (CLB1, CBB1) break transmitter signals out into SMA connections. Rev 2.0 Fixtures (CLB2, CBB2) break transmitter signals out into SMP connections. These fixtures are available at: http://www.pcisig.com/specifications/ordering_information/ordering_information. o Test fixtures for ExpressCard testing are available from the following URL: http://www.expresscard.org/web/site/testtools.jsp
Probing Options for Transmitter Testing
The first step is to probe the link. Use one of the following four methods to connect probes to the link.

SMA Input Connection

A. Two TCA-SMA inputs using SMA cables (Ch1) and (Ch2) The differential signal is created from the math waveform (Math1 = Ch1-Ch2). The Common mode AC measurement is also available in this configuration from the common mode waveform (Ch1+Ch3)/2. This probing technique requires breaking the link and terminating into a 50 /side termination of the oscilloscope. While in this mode, the PCI Express SerDes will transmit the compliance test pattern. Ch-Ch de-skew is required using this technique because two channels are used. This configuration does not compensate for cable loss in the SMA cables. The measurement reference plane is at the input of the TCA-SMA connectors on the oscilloscope. One P7300SMA series differential active probe (Ch1) The differential signal is measured across the termination resistors inside the P7300SMA series probe. This probing technique requires breaking the link. While in this mode, the PCI Express SerDes will transmit the compliance test pattern. Matched cables are provided with the probe to avoid introducing deskew into the system. Only one channel of the oscilloscope is used. The P7300SMA provides a calibrated system at the Test Fixture attachment point, eliminating the need to compensate for cable loss associated with the probe configuration A.

SMA Pseudo-differential

SMA Input Differential Probe

ECB pad connection

C. Two active probes (Ch1) and (Ch2) The differential signal is created from the math waveform (Math1 = Ch1-Ch2). The Common mode AC/DC measurements are available in this configuration from the common mode waveform (Ch1+Ch3)/2. This probing technique can be used for either a live link that is transmitting data, or a link that has terminated into a dummy load. In both cases, the singleended signals should be probed as close as possible to the termination resistors on both sides with the shortest ground connection possible. Ch-Ch deskew is required using this technique because two channels are used. One P7300 or P7500 series Differential probe (Ch1) The differential signal is measured directly across the termination resistors. This probing technique can be used for either a live link that is transmitting data, or a link that is terminated into a dummy load. In both cases, the signals should be probed as close as possible to the termination resistors. De-skew is not necessary because a single channel of the oscilloscope is used. If using a P7500 TriMode Probe, common mode voltage measurements can be made directly with the probe.

Dual Port Connection

E. Dual Port For Rev 2.0 System testing (Described in Section 2.4), the Dual Port method is used to capture differential Data and RefClk. Direct SMA input can be used (where RefClk=Math1=Ch1-Ch2 and Data=Math2=Ch3-Ch4); or Two P7313SMA probes can be used (where RefClk = Ch1 and Data = Ch2).

Running the Test

The following is a step-by-step procedure on how to run a test in the DPOJET PCI Express Setup Library. 1. From the DPO/DSA Analysis Menu, Select PCI Express. Allow DPOJET to load. 2. From the File Menu, Select Recall Setup and navigate to the DPOJET PCIE Setup Library
3. Recall the desired file from the Setup Library
4. Press the Single button on the instrument front panel. The screen should look similar to the following image. Adjust Vertical Scale to take full advantage of the A/D range of the oscilloscope enter channel De-Skew values as needed. The Horizontal Scale is set to capture 1 Million UI (106 bits) as required by the specifications.
5. Press the Single Button in DPOJET (Jitter and Eye Analysis Tools) Menu. The end result should look similar to the following screenshot. Pass/Fail results are viewed by expanding the measurement results using the + icon next to each measurement.

UI (Unit Interval) MOI

Definition: UI (Unit Interval) is defined in the base specification Rev2.0. This measurement is done using the PCIeUI. The Result panel would display the Unit interval values Test Definition Notes from the Specification: The specified UI is equivalent to a tolerance of 300 ppm for each Refclk source. Period does not account for SSC induced variations. Limits: Refer to Table 2 thru Table 11 for specified limits on the UI measurement. Test Procedure: Ensure that PCIe UI is selected in the Jitter and Eye diagram Analysis Tools >> Select menu. Set the following parameters Configure >> Edges >> Auto Configure >> Filter >> Low pass - 198kHz Configure >> Global >> off

Measurement Algorithm:

Methods of Implementation The Unit interval measurement calculates the duration of a cycle as defined by a start and a stop edge. Edges are defined by polarity, threshold, and hysteresis. The application calculates clock period measurement using the following equation:

Where: P

is the clock period.
T is the VRefMid crossing time for the selected polarity.
TX Differential Pk-Pk Output Voltage MOI
Definition: (Differential Output Pk-Pk Voltage) is defined in the base specification Rev 2.0. This measurement is done using PCIe T-Tx-Diff-PP. The Result panel would display the Mean , Maximum and Minimum differential output pk-pk voltage. Test Definition Notes from the Specification:
VTX DIFFp p = 2 | VTX D + VTX D |
Measured on individual bits, first bit from a sequence in which all bits have same polarity, over specified number of UIs. The voltage measurement is referenced to the centre of each UI. Limits: Refer to Table 2 thru Table 11 for specified limits on the Test Procedure: Ensure that PCIe T-Tx-Diff-PP is selected in the Jitter and Eye diagram Analysis Tools >> Select menu. Select the Jitter and Eye diagram Analysis Tools >> Configure from the panel and set the Configure >> Bit configuration >> Bit Type >> Transition Bit (Which is selected by default) as shown in the Figure 7.

measurement

Figure 7: Configure selection Panel for PCIe T-Tx-Diff-PP measurement Select Configure >> Clock Recovery >> Constant Clock Mean method. Measurement Algorithm: Differential Peak Voltage Measurement: The Differential Peak Voltage measurement returns two times the larger of the Min or Max statistic of the differential voltage waveform.

V DIFF PK = 2 Max ( Max ( v DIFF (i )); Min( v DIFF (i )))
Where: i is the index of all waveform values
v DIFF is the differential voltage signal

TX De-Emphasis Ratio

Definition: VTX-DE-RATIO(De-Emphasized Differential Output Voltage (Ratio)) is defined in the base specification. This measurement uses PCIe T/nT ratio measurement. Test Definition Notes from the Specification:
This is the ratio of the VTX-DIFFp-p of the second and the following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition. Limits: Refer to Table 2 thru Table 11 for specified limits on the Measurement Algorithm:
The De-emphasis Ratio measurement reports the amplitude ratio between transition and non-transition bits. The measurement calculates the ratios of all non-transition eye voltages (2nd and subsequent eye voltages after one edge but before the next) to their nearest preceding transition eye voltage (1st eye
Methods of Implementation voltage succeeding an edge). In the accompanying diagram, it is the ratio of the Black voltages to the Blue voltages. The results are given in dB.
The application calculates the T/nT Ratio using the following equations:

following a rising edge.

following a falling edge. Where: vEYEHITRAN is the High voltage at the interpolated midpoint of the first unit interval following a positive transition. vEYELOTRAN is the Low voltage at the interpolated midpoint of the first unit interval following a negative transition. vEYEHINTRAN is the High voltage at the interpolated midpoint of all unit intervals except the first following a positive transition. vEYELONTRAN is the Low voltage at the interpolated midpoint of all unit intervals except the first following a negative transition. m is the index for all non-transition UIs. n is the index for the nearest transition UI preceding the UI specified by m. In a time trend plot of the measurement results, there is one measurement for each non-transition bit in the waveform (that is the black arrows in the diagram). NOTE. PCIe T/nT Ratio measurement uses Brick Wall filter.
TX Minimum Pulse Width MOI
Definition: TMIN-PULSE (Instantaneous lone pulse width measurement) is defined in the base specification Rev2.0. This measurement is done using the PCIe Tmin-Pulse. The Result panel would display the minimum pulse width results. Test Definition Notes from the Specification: TMIN-PULSE (Instantaneous lone pulse width measurement) is measured from transition center to the next transition center, and that the transition centers will not always occur at the differential zero crossing point. In particular, transitions from a de-emphasized level to a full level will have a center point offset from the differential zero crossing. Limits: Refer to Table 2 thru Table 11 for specified limits on the TMIN-PULSE measurement Test Procedure: Ensure that PCIe Tmin-Pulse is selected in the Jitter and Eye diagram Analysis Tools >> Select menu. Set the following parameters Configure >> Clock Recovery >> Constant Clock Recovery Mean Configure >> General >>Off Configure >> Global >> Off

Measurement Algorithm: Tmin-Pulse (minimum single pulse width TMin-Pulse) is measured from one transition center to the next. The application calculates TMin-Pulse using the following equation:
Where: TMin-Pulse is the minimum pulse width T is the transition center
TX Rise/Fall Time Mismatch MOI
Definition: TRF-MISMATCH (Rise time, Fall time mismatch) is defined in the base specification. This measurement is done using PCIe T-RF-Mismch. The Result panel would display the Mean , Maximum and Minimum Rise time, Fall time mismatch values. Limits: Refer to Table 2 thru Table 11 for TRF-MISMATCH measurement. Test Procedure: Ensure that PCIe T-RF-Mismch is selected in Jitter and Eye diagram Analysis Tools >> Select menu is selected. Set the following parameters Configure >> Clock Recovery >> Constant Clock Recovery Mean Configure >> Filter >> No filter Configure >> General >>Off Configure >> Global >> Population
Measurement Algorithm: PCIe T-RF-Mismch (Rise and Fall Time mismatch measurement) is the mismatch between Rise time (TRise) and Fall time(TFall). The application calculates this measurement using the following equation:
Where: TMismatch is the rise and fall time mismatch TRise is the rise time TFall is the fall time

Minimum TX Eye Width MOI

Definition:
TTX EYE (Minimum TX Eye Width) is defined in the base specification. See Section 4.7.2 of PCI
EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 for the Gen2 definition for both 3.5dB and 6dB De-emphasis. The eye diagrams defined in this section represent the compliance eye diagrams that must be met for both the add-in card and a system board interfacing with such an add-in card. A sample size of 106 UI is assumed for the measurement.
TTX EYE is defined to be the Jitter Eye Opening.
Test Definition Notes from the Specification: - The maximum Transmitter jitter can be derived as TTXMAX JITTER = 1 TTX EYE - Specified at the measurement point into a timing and voltage compliance test load as shown in the base specification and measured over the specified number of UIs. Also refer to the transmitter compliance eye diagram shown in the base specification. Limits: Refer to Table 2 thru Table 11 on the TTX EYE measurement. Test Procedure: Ensure that the measurement PCI T-TXA is selected in the Jitter and Eye diagram Analysis Tools >> Select menu. Configure the measurement by setting the following parameters. Configure >> Clock Recovery Mean method Configure >> General >> off. Measurement Algorithm: The measured minimum horizontal eye opening at the zero reference level as shown in the eye diagram below.

TEYE WIDTH = UI AVG TIE Pk Pk

Where:

UI AVG is the average UI TIE Pk Pk is the Peak-Peak TIE
Figure 10: Add-in Card Transmitter Path Compliance Eye Diagram
Where TtxA is the Eye width, VtxA is the full scale peak to peak voltage and VtxA_d is the De-emphasized peak to peak voltage.
Figure 11: Configure Panel
TX Median-to-Max Jitter MOI
TTX EYEMEDIAN to MAXJITTER (maximum time between the jitter median and maximum deviation from the
median.).A step response Band pass filter is being used to remove the low frequency jitter as specified in Rev2.0 of the base specification. Limits: Refer to Table 2 thru Table 11 for TTX EYEMEDIAN to MAXJITTER measurement. Test Procedure: Ensure that PCIe Med-Mx Jitter is selected in Jitter and Eye diagram Analysis Tools >> Select menu is selected. Set the following parameters Configure >> Edges >> Signal Type >> Data Configure >> Clock Recovery >> Constant Clock Recovery Mean Configure >> Filter >> Brick Wall Filter
Configure >> General >>Off Configure >> Global >> Population Measurement Algorithm: The measured time difference between a data edge and a recovered clock edge.
tie(n) = t R DAT (n) t DAT (n)
t DAT is the original data edge t R DAT is the recovered data edge (for example, the recovered clock edge corresponding to the UI boundary of t DAT )
n is the index of all edges in the waveform Med_Tie= median (tie (n)) Where: Med_Tie is the Median of the tie measured. TTx-EYEMEDIAN-to MAXJitter = Abs (Med_Tie Maximum deviation of tie (n) from the Med_Tie)